Display device and electronic device

Abstract

Provided is a display device having a novel configuration. The display device has a first layer and a second layer positioned on the first layer. The first layer has a drive circuit region. The second layer has a pixel array. The pixel array has a plurality of pixel regions. The drive circuit region has a control circuit unit and a plurality of local driver circuits. Each of the plurality of local driver circuits corresponds to one of the plurality of pixel regions. The local driver circuit has the function of outputting a drive signal that drives the plurality of pixels included in the corresponding pixel region. The control circuit has the function of comparing the resolution data for an inputted image signal with aspect ratio data for a pixel array to determine a first region in which display is performed and a second region in which display is not performed, and outputting a control signal for stopping output of the drive signal to the local driver circuit corresponding to the second region.

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] There is a demand for display devices that can be used for XR (Extended Reality), such as VR (Virtual Reality) and AR (Augmented Reality). Specifically, to enhance the sense of realism and immersion, such display devices are required to have high resolution and excellent color reproducibility.

[0004] Examples of display devices that can be applied to the display include liquid crystal display devices, and light-emitting devices equipped with light-emitting devices such as organic electroluminescence (EL) devices and light-emitting diodes (LEDs: Light Emitting Diodes). Patent Document 1 discloses a high-pixel, high-definition display device equipped with a light-emitting device that includes an organic EL device. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 220278 Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, XR devices require display devices with high display quality. Additionally, it is desirable for display devices for XR devices to have a high drive frequency in order to enhance the sense of realism and immersion. However, as the drive frequency increases, the input time per frame decreases, which may reduce the amount of data that can be input to the display device within one frame. Furthermore, maintaining a high drive frequency for display may increase power consumption.

[0007] An object of one embodiment of the present invention is to provide a display device with high display quality, a display device with reduced power consumption, or a novel display device.

[0008] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0009] One embodiment of the present invention is a display device having a first layer and a second layer located above the first layer, the first layer having a drive circuit region, the second layer having a pixel array having a plurality of pixel regions, the drive circuit region having a control circuit unit and a plurality of local driver circuits, one of the plurality of local driver circuits corresponding to any one of the plurality of pixel regions, the local driver circuit having a function of outputting a drive signal to drive a plurality of pixels included in the corresponding pixel region, and the control circuit unit having a function of comparing resolution data of an input image signal with aspect ratio data of the pixel array to determine a first region for displaying and a second region for not displaying, and outputting a control signal to the local driver circuit corresponding to the second region for stopping output of the drive signal.

[0010] In one embodiment of the present invention, the display device preferably has a driver circuit region located inside the pixel array when viewed from above, and a part of the plurality of pixel regions does not overlap with the driver circuit region when viewed from above.

[0011] In one aspect of the present invention, a display device is preferred in which each of a plurality of pixel regions has a plurality of wirings, the plurality of pixels are arranged in a matrix in the plurality of pixel regions, the plurality of wirings are arranged in each row of the plurality of pixels arranged in the matrix, one of the plurality of wirings is electrically connected to a pixel arranged in the same row, and each of the plurality of wirings has a contact portion, and the contact portion is arranged inside the pixel or between adjacent pixels.

[0012] In one embodiment of the present invention, a display device is preferred in which a pixel included in each of the plurality of pixel regions has a light-emitting device using an organic EL and a first transistor, the control circuit unit and the plurality of local driver circuits have second transistors, the first transistor has a metal oxide in a channel formation region, and the second transistor has silicon in a channel formation region.

[0013] One embodiment of the present invention is an electronic device including any one of the above display devices and a housing.

[0014] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices or may include semiconductor devices.

[0015] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0016] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0017] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0018] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0019] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0020] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0021] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can sometimes be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," and "region having a resistance value" can sometimes be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0022] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a gate capacitance of a transistor, etc. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0023] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0024] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Furthermore, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0025] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0026] In addition, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0027] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0028] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0029] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive or negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0030] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0031] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0032] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0033] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0034] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0035] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0036] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in defect level density in the semiconductor, a decrease in carrier mobility, or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0037] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals for passing a current in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0038] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, or a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0039] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0040] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0041] In this specification and the like, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification and the like, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (for example, a color filter) to realize a full-color display device.

[0042] Light-emitting devices can be broadly divided into single-structure and tandem-structure devices. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, two or more light-emitting layers may be selected so that the emission colors of the respective light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the entire light-emitting device emits white light can be obtained. The same applies to light-emitting devices having three or more light-emitting layers.

[0043] A tandem-structured device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light, light from the light-emitting layers of the multiple light-emitting units may be combined to obtain white light. The configuration for obtaining white light is the same as that of the single-structured device. In a tandem-structured device, it is preferable to provide an intermediate layer such as a charge-generating layer between the multiple light-emitting units.

[0044] Furthermore, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If you want to keep power consumption low, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields.

[0045] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0046] According to one embodiment of the present invention, a display device with high display quality, a display device with reduced power consumption, or a novel display device can be provided.

[0047] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0048] FIG. 1 is a diagram illustrating an example of the configuration of a display device. 2A and 2B are diagrams illustrating an example of the configuration of a display device. 3A and 3B are diagrams illustrating an example of the configuration of a display device. 4A and 4B are diagrams illustrating an example of the configuration of a display device. FIG. 5 is a diagram illustrating an example of the operation of the display device. 6A to 6D are diagrams illustrating an example of the configuration of a display device. FIG. 7 is a cross-sectional view showing a configuration example of a display device. FIG. 8A is a schematic top view showing an example of the configuration of a circuit layer included in a display device, and FIG. 8B is a schematic top view showing an example of the configuration of the display device. FIG. 9A is a perspective view that schematically shows an example of the configuration of a display device, and FIG. 9B is a schematic cross-sectional view that shows the example of the configuration of the display device. FIG. 10A is a perspective view that schematically shows an example of the configuration of a display device, and FIG. 10B is a schematic cross-sectional view that shows the example of the configuration of the display device. FIG. 11A is a perspective view that schematically shows an example of the configuration of a display device, and FIG. 11B is a cross-sectional view that schematically shows the example of the configuration of the display device. 12A to 12C are diagrams illustrating electrical connections between pixels and wirings included in a display device. 13A and 13B are schematic top views showing configuration examples of a display device. 14A and 14B are schematic top views showing configuration examples of a display device. FIG. 15 is a schematic top view showing an example of the configuration of a display device. FIG. 16 is a schematic top view showing an example of the configuration of a display device. FIG. 17 is a cross-sectional view showing a configuration example of a display device. 18A and 18B are cross-sectional schematic views showing configuration examples of a display device. 19A and 19B are cross-sectional views showing examples of the structure of a transistor. 20A and 20B are cross-sectional views showing examples of the structure of a transistor. 21A to 21C are schematic diagrams showing configuration examples of light-emitting devices. 22A and 22B are cross-sectional schematic views showing configuration examples of a display device. 23A to 23C are cross-sectional views showing examples of the configuration of a display device. 24A to 24D are schematic cross-sectional views showing configuration examples of a display device. FIG. 25A is a diagram illustrating the classification of IGZO crystal structures, FIG. 25B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 25C is a diagram illustrating the micro-electron diffraction pattern of crystalline IGZO. 26A to 26F are diagrams showing configuration examples of electronic devices. 27A and 27B are diagrams showing configuration examples of a display module. 28A and 28B are diagrams showing configuration examples of electronic devices. 29A to 29C are diagrams showing configuration examples of electronic devices. 30A to 30D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0049] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0050] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0051] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0052] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0053] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0054] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0055] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0056] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0057] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0058] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0059] 1 is a block diagram illustrating a display device according to one embodiment of the present invention. The display device 100 shown in FIG. 1 includes a control circuit portion CNP, a driver circuit region DRV, a pixel array ALP, and a memory portion MEM. Although not shown in FIG. 1, the driver circuit region DRV is provided in a layer different from the layer in which the pixel array ALP is provided.

[0060] The drive circuit region DRV has a plurality of local driver circuits LD. In FIG. 1, local driver circuits LD[1] to LD[n] (n is a natural number of 2 or more) are illustrated as an example. The pixel array ALP has a plurality of pixel regions ARA. In FIG. 1, pixel regions ARA[1] to ARA[n] (n is a natural number of 2 or more) are illustrated as an example. One of the plurality of local driver circuits LD corresponds to one of the plurality of pixel regions ARA. The local driver circuit LD outputs a drive signal GL DR ,SL DR It has the function of outputting the drive signal GL DR is a signal to be applied to the gate line, for example. DR is, for example, a signal to be applied to a signal line. The memory unit MEM is a memory unit provided in the display device 100, and is preferably a non-volatile memory.

[0061] The control circuit unit CNP has a controller CON and a voltage generating circuit PG. The control circuit unit CNP may be provided in the drive circuit region DRV. Input signals such as image signals DATA are input to the control circuit unit CNP from the outside.

[0062] The controller CON has, for example, a function of processing signals input from outside the display device 100. Examples of the signals include the above-mentioned image signal DATA, as well as a vertical synchronization signal, a horizontal synchronization signal, and an address signal including a destination for displaying based on the image signal DATA.

[0063] For example, the voltage generation circuit PG functions as a circuit that generates a power supply voltage for driving circuits included in the drive circuit area DRV (such as a source driver circuit and a gate driver circuit, which will be described later). The voltage generation circuit PG may also have a function of generating a voltage to be supplied to pixels included in the pixel area ARA, which will be described later.

[0064] The control circuit unit CNP transmits image signals DATA[1] to DATA[n] and control signals EN[1] to EN[n]. The image signals DATA[1] to DATA[n] and control signals EN[1] to EN[n] are transmitted to the selected local driver circuit LD by selecting the local driver circuit LD included in the drive circuit area DRV in accordance with the address signal. Note that, since a plurality of local driver circuits LD are provided in the drive circuit area DRV, the control circuit unit CNP may be configured to transmit image signals, etc., to the plurality of local driver circuits LD simultaneously in parallel.

[0065] In addition, the control circuit unit CNP receives the aspect ratio data M of the pixel array ALP from the memory unit MEM. RESO The aspect ratio data M RESO is data relating to the aspect ratio of an image that can be displayed when all pixels of the pixel array ALP are driven and displayed, and is data relating to the aspect ratio of, for example, QVGA (320 x 240), VGA (640 x 480), etc. The control circuit unit CNP uses the aspect ratio data M RESO and the resolution data of the image signal DATA, and a drive signal GL DR ,SL DR The local driver circuit LD has a function of outputting a control signal IDS (IDS[1] to IDS[n]) for stopping the output of the image signal DATA and a control signal STBY (STBY[1] to STBY[n]) to the local driver circuit LD. The resolution data of the image signal DATA is data that indicates the number of pixels in the vertical and horizontal directions of the image.

[0066] The control signal STBY is the aspect ratio data M RESOThe control signal STBY is a signal for stopping the function of the local driver circuit LD corresponding to a pixel area ARA where no display based on the image signal DATA is performed because the resolution data of the image signal DATA does not match the aspect ratio of the pixel array ALP. In this case, the data mismatch refers to a mismatch between the aspect ratio of the pixel array ALP and the ratio of the number of vertical to horizontal pixels. The control signal STBY is a signal for stopping the function of the local driver circuit LD by stopping the supply of power supply voltage to analog circuits (e.g., amplifier circuits) in the local driver circuit LD and putting the local driver circuit LD into a standby state.

[0067] The control signal IDS is a signal for stopping updating of the image signal DATA or reducing the update frequency in the local driver circuit LD corresponding to the pixel area ARA where there is no display update based on the image signal DATA. The control signal IDS is a signal for performing clock gating or changing the frequency of the clock signal when the image signal DATA is the same in consecutive frame periods, thereby stopping updating of the image signal DATA or reducing the update frequency.

[0068] Each of the multiple local driver circuits LD has the function of driving pixels included in multiple pixel areas ARA. That is, for example, each of the multiple local driver circuits LD has a source driver circuit and a gate driver circuit. Because there are multiple local driver circuits LD, it is possible to selectively control the pixel area ARA to be driven for each local driver circuit LD. The local driver circuit LD outputs drive signals GL to drive multiple pixels included in the corresponding pixel area ARA in accordance with image signals DATA[1] to DATA[n], control signals IDS[1] to IDS[n], control signals STBY[1] to STBY[n], and control signals EN[1] to EN[n]. DR ,SL DR Output.

[0069] The pixel array ALP has a plurality of pixel areas ARA. Pixel areas ARA[1] to ARA[n] are shown in Fig. 1 as an example. Each pixel area ARA has a pixel PIX connected to a gate line and a signal line.

[0070] The display device 100 described in this embodiment can divide the pixel array ALP into multiple pixel regions ARA, and drive each pixel region ARA in parallel using a corresponding local driver circuit LD. When rewriting part of an image on the display unit of the display device 100, only the necessary local driver circuits LD can be driven to drive the pixels included in the pixel region ARA displaying that part of the image. In this case, only the pixels included in the necessary pixel region ARA are driven, and the local driver circuits LD corresponding to the pixel regions ARA that do not need to be driven are put into a dormant state, thereby reducing power consumption. The dormant state can be a state in which the frequency is controlled by a clock signal based on a control signal IDS, or a state in which the supply of power supply voltage to an analog circuit is controlled based on a control signal STBY.

[0071] 2A and 2B will explain the control signal STBY and control signal IDS shown in Fig. 1. The control signal STBY stops the function of the local driver circuit LD by setting the voltage supplied to an amplifier circuit such as an amplifier circuit included in the local driver circuit LD to L level. The control signal IDS stops updating of the image signal DATA by stopping updating of data in a source register that holds the image signal DATA included in the local driver circuit LD.

[0072] In Figure 2A, the voltage supplied to the amplifier circuit is V AMP and the voltage V AMP 10 shows a timing chart in which the function of the local driver circuit LD is stopped by setting the level of the local driver circuit LD to L.

[0073] At time T01 in FIG. 2A, the control signals STBY and IDS are set to H level to stop the function of the local driver circuit LD. That is, clock gating is performed, the supply of power supply voltage is stopped, and the local driver circuit LD is set to a standby state. In the amplifier circuit of the local driver circuit LD, the voltage V AMP The voltage V supplied to the amplifier circuit in the local driver circuit LD decreases and becomes L level. AMP Since the change in voltage V is gradual, it is effective in contributing to low power consumption when the function of the local driver circuit LD is stopped for a long period of time. Conversely, when the function of the local driver circuit LD is stopped for a short period of time, the voltage V AMP The time of change must be taken into account.

[0074] At time T02 in FIG. 2A, the control signal STBY is set to L level to restore the function of the local driver circuit LD. AMP rises and becomes H level. At time T03 in Fig. 2A, the control signal IDS is set to L level to resume updating of the image signal DATA by the local driver circuit LD.

[0075] In Figure 2B, the voltage V AMP 10 shows a timing chart in the case where the local driver circuit LD stops updating of the image signal DATA by setting the signal DATA to H level.

[0076] At time T01 in FIG. 2B, the control signal IDS is set to H level to stop the local driver circuit LD from updating the image signal DATA. In other words, clock gating is performed. At this time, the voltage V AMP does not decrease and remains at H level. Therefore, the amplifier circuit in the local driver circuit LD continues to operate. Power consumption can be reduced by the amount that the clock signal is stopped.

[0077] At time T02 in FIG. 2B, the control signal IDS is set to L level in order to restore the function of updating the image signal DATA by the local driver circuit LD.

[0078] Fig. 3A illustrates an example of the local driver circuit LD shown in Fig. 1. The local driver circuit LD includes, as an example, an interface circuit IF, a source logic circuit SLO, a source driver circuit SD, a gate driver circuit GD, and a gate level shifter circuit GDLS.

[0079] The interface circuit IF is a communication circuit such as an I2C (Inter-Integrated Circuit). The source logic circuit SLO has a register for holding the image signal DATA. The source logic circuit SLO can stop the function of the logic circuit for updating the image signal DATA by the control signal IDS described above. The gate driver circuit GD is a circuit for generating pulse signals to be output to the gate lines, and the gate level shifter circuit GDLS amplifies the pulse signals generated by the gate driver circuit GD and outputs them as drive signals GL DR This is a circuit that outputs

[0080] The source driver circuit SD can stop the function of the local driver circuit LD by the control signal STBY described above. The source driver circuit SD includes, as an example, a latch circuit LAT, a source level shifter circuit SDLS, a pass transistor logic circuit PTL, an amplifier circuit AMP, and a demultiplexer circuit DMX, as shown in FIG. 3B.

[0081] The latch circuit LAT has the function of holding the image signal DATA output by the source logic circuit SLO. The source level shifter circuit SDLS is a circuit that amplifies and outputs the image signal DATA. The pass transistor logic circuit PTL is a circuit that generates a voltage according to the image signal DATA. The amplifier circuit AMP is a circuit that outputs the voltage V AMPThe demultiplexer circuit DMX controls whether or not the function is stopped depending on the image signal DATA. DR This is a circuit that outputs

[0082] 4A and 4B, a display module including the above-described display device 100 will be described.

[0083] 4A shows a perspective view of the display module 100M. The display module 100M includes the display device 100 and an FPC 1290.

[0084] The display module 100M includes a substrate FS and a substrate BS. The display module 100M includes a pixel array ALP that functions as a display unit. The pixel array ALP is an area of ​​the display module 100M that displays an image.

[0085] 4B is a perspective view showing a schematic configuration provided on the substrate BS side. A pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL are provided on the substrate BS. The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is provided on the wiring layer LINL. The pixel layer PXAL overlaps a region including a drive circuit region DRV and a region LIA, which will be described later.

[0086] The circuit layer SICL has a substrate BS, a drive circuit region DRV, and a region LIA.

[0087] The substrate BS can be, for example, a semiconductor substrate (e.g., a single-crystal substrate) made of silicon or germanium. In addition to semiconductor substrates, the substrate BS can also be, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic resin. Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device 100 includes heat treatment, it is preferable to select a material with high heat resistance for the substrate BS. Furthermore, the substrate FS may be any light-transmitting substrate, such as a glass substrate, a quartz substrate, or a light-transmitting film.

[0088] In this embodiment, the substrate BS is described as a semiconductor substrate made of silicon or the like. Therefore, the transistors included in the driver circuit region can be transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors).

[0089] The drive circuit region DRV and the region LIA are provided on a substrate BS.

[0090] The drive circuit region DRV has, as an example, a local driver circuit LD for driving pixels included in a pixel layer PXAL, which will be described later.

[0091] As an example, wiring is provided in the region LIA. The wiring included in the region LIA may be electrically connected to wiring included in the wiring layer LINL. In this case, the display device 100 may be configured so that the circuit included in the drive circuit region DRV and the circuit included in the pixel layer PXAL are electrically connected by the wiring included in the region LIA and the wiring included in the wiring layer LINL. The display device 100 may be configured so that the circuit included in the drive circuit region DRV and the wiring or circuit included in the region LIA are electrically connected via the wiring included in the wiring layer LINL.

[0092] Furthermore, the region LIA may include, for example, a functional circuit such as a GPU (Graphics Processing Unit). If the display device 100 includes a touch panel, the region LIA may include a sensor controller that controls a touch sensor included in the touch panel. If a light-emitting device using an organic EL is used as the display element of the display device 100, the region LIA may include an EL correction circuit. If a liquid crystal element is used as the display element of the display device 100, the region LIA may include a gamma correction circuit.

[0093] The wiring layer LINL is provided on the circuit layer SICL.

[0094] The wiring layer LINL is provided with wiring, for example, and the wiring included in the wiring layer LINL functions as wiring that electrically connects, for example, a drive circuit included in the drive circuit region DRV provided below and a circuit included in the pixel layer PXAL provided above.

[0095] The pixel layer PXAL has, for example, a plurality of pixel regions ARA that constitute the pixel array ALP described in Fig. 1. Each pixel region ARA has a plurality of pixels PIX. The plurality of pixels PIX may be arranged in a matrix in the pixel layer PXAL.

[0096] Each of the multiple pixels PIX can express one or more colors. In particular, the multiple colors can be, for example, three colors: red (R), green (G), and blue (B). Alternatively, the multiple colors can be, for example, red (R), green (G), and blue (B) plus at least one color selected from cyan, magenta, yellow, and white. Each pixel expressing a different color is called a sub-pixel, and when white is expressed by multiple sub-pixels of different colors, the multiple sub-pixels are sometimes collectively referred to as a pixel. For convenience, in this specification and other descriptions, sub-pixels will be referred to as pixels.

[0097] The pixels PIX may be arranged in a stripe pattern, with pixels representing different colors. Alternatively, various arrangement methods such as a delta pattern or a pentile pattern may be used.

[0098] The display module 100M can be configured such that a drive circuit region DRV is stacked below the pixel layer PXAL. The pixels PIX can be arranged at high density, which can significantly increase the resolution of the display unit.

[0099] Because such a display module 100M has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays or eyeglass-type AR devices. For example, even in a configuration in which the display unit of the display module 100M is viewed through lenses, the display module 100M has an extremely high-resolution display device 100, so even if the display unit is enlarged with the lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 100M is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0100] FIG. 5 illustrates, with reference to a flowchart, how the local driver circuit LD is controlled by the control signal STBY in the display device 100 described above.

[0101] First, in step S01, the display device 100 calculates the aspect ratio data M of the pixel array ALP. RESO In the display device 100, the aspect ratio data M stored in the memory unit MEM is acquired. RESO is read out to the control circuit unit CNP.

[0102] Next, in step S02, the resolution data of the image signal DATA is acquired in the display device 100. In the display device 100, the resolution data of the image signal DATA is read out to the control circuit unit CNP.

[0103] Next, in step S03, the display device 100 calculates the aspect ratio data M of the pixel array ALP. RESO is compared with the resolution data of the image signal DATA. This comparison is to determine whether the aspect ratio of the resolution data of the image signal DATA differs from that of the image signal DATA when the resolution data of the image signal DATA is displayed on the display device 100.

[0104] Next, in step S04, the display device 100 calculates the aspect ratio data M of the pixel array ALP. RESO and the resolution data of the image signal DATA to determine whether they match.

[0105] For example, if the resolution data of the image signal DATA is VGA (640×480), the aspect ratio is 4:3, and the aspect ratio is the aspect ratio data M of the pixel array ALP. RESO (for example, 4:3) (see FIG. 6A for example). Alternatively, if the resolution data of the image signal DATA is the Japanese high-definition TV (1920×1080), the aspect ratio is 16:9, and the aspect ratio is the aspect ratio data M of the pixel array ALP.RESO (for example, 4:3) (see, for example, FIG. 6B). In the former case, the aspect ratio data M RESO When the resolution data of the image signal DATA is compared with the resolution data of the image signal DATA, the two match, and in the latter case, they do not match.

[0106] If there is a match in step S04, the control circuit unit CNP outputs control signals and the like to each local driver circuit LD to perform display based on the image signal DATA in step S05. In the example shown in Fig. 6A, since the aspect ratios match, the image is enlarged and displayed as shown in Fig. 6C.

[0107] If there is no match in step S04, then in step S06, it is determined whether there is a local driver circuit LD whose function can be disabled. For example, in the example shown in FIG. 6B, since the aspect ratios do not match, the region ERA can be disabled in the pixel array ALP shown in FIG. 6D. In this case, it is determined whether there is a pixel region ARA and local driver circuit LD corresponding to the region ERA. If the region ERA is small and the corresponding pixel region ARA and local driver circuit LD cannot be disabled, then, as in step S05, the control circuit unit CNP outputs control signals and the like to each local driver circuit LD to perform display based on the image signal DATA.

[0108] In step S07, if the pixel area ARA and the local driver circuit LD corresponding to the area ERA can be disabled in step S06, a control signal STBY is output to the local driver circuit LD, so that the pixel area ARA corresponding to the local driver circuit LD can be an area where display based on the image signal DATA is not performed.

[0109] In step S08, control signals and the like for performing display based on the image signal DATA are output to the local driver circuits LD other than the local driver circuit LD that output the control signal STBY in step S07. In the example shown in Fig. 6B, since the aspect ratios do not match, the top and bottom of the pixel array ALP become areas ERA as shown in Fig. 6D, but since the functions of the corresponding local driver circuits LD are stopped, low power consumption is achieved.

[0110] In steps S05 and S08, the image signal DATA and the control signal or the control signal STBY are supplied to each local driver circuit LD, thereby enabling display in each pixel area ARA (step S09).

[0111] By configuring the display device 100 described in this embodiment, the pixel array ALP of the display device 100 can be divided into multiple pixel regions ARA, and each pixel region ARA can be driven in parallel by a corresponding local driver circuit LD. When rewriting a portion of an image on the display unit of the display device 100, only the necessary local driver circuits LD can be driven to drive the pixels included in the pixel region ARA displaying that portion of the image. In other words, the pixels included in each pixel region ARA of the display unit of the display device 100 can be driven independently. In this case, only the pixels included in the necessary pixel region ARA are driven, and the local driver circuits LD corresponding to the pixel regions ARA that do not need to be driven are put into a dormant state, thereby reducing power consumption. Furthermore, by dividing the pixel array ALP of the display device 100 into multiple pixel regions ARA, and driving each pixel region ARA in parallel and independently by the respective local driver circuits LD, the time required to rewrite an image displayed on the display unit of the display device 100 (e.g., the time per frame) can be shortened. Furthermore, by dividing the pixel array ALP and driving each pixel area ARA using a corresponding local driver circuit LD, the driving load on the divided unit (each pixel area ARA) is reduced, making it easier to increase the operating speed and reduce power consumption. Furthermore, by dividing the pixel array ALP, the divided units (each pixel area ARA) can be driven at the same timing, making it possible to set a longer image write time for one frame compared to when the pixel array ALP is not divided. For example, by dividing the pixel array ALP so that the multiple gate wirings extending through the pixel array ALP are divided into four, the image write time can ideally be set to 1 / 4 of the time required when the pixel array ALP is not divided, or approximately that time, and the remaining time (3 / 4 of the time required when the pixel array ALP is not divided, or approximately that time) can be used for the write time. Therefore, the image write time can be extended.

[0112] (Embodiment 2) In this embodiment, the display device 100 described in the first embodiment will be described.

[0113] 7 is a cross-sectional view of the display device 100. The display device 100 includes a pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL. Each component shown in FIG. 7 corresponds to each component described in FIG. 3.

[0114] The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is provided on the wiring layer LINL. The pixel layer PXAL overlaps a region including a drive circuit region DRV and a region LIA, which will be described later.

[0115] The circuit layer SICL has a substrate BS, a drive circuit region DRV, and a region LIA.

[0116] Fig. 8A is an example of a top view of the display device 100, showing only the circuit layer SICL. The display device 100 shown in Fig. 8A has, as an example, a configuration in which a drive circuit region DRV is surrounded by a region LIA.

[0117] In FIG. 8A, the drive circuit region DRV includes, for example, a plurality of local driver circuits LD, a controller CON, and a voltage generating circuit PG.

[0118] As an example, each of the multiple local driver circuits LD has a function of driving a pixel included in the pixel layer PXAL. For example, consider a case in which the pixel array ALP included in the pixel layer PXAL in the display device 100 is divided into regions with m rows and n columns (m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1). In this case, the number of multiple local driver circuits included in the drive circuit region DRV is m×n.

[0119] 8A shows, as an example, the local driver circuit LD[1,1], the local driver circuit LD[1,2], the local driver circuit LD[2,1], the local driver circuit LD[2,2], the local driver circuit LD[m-1,1], the local driver circuit LD[m-1,2], the local driver circuit LD[m,1], the local driver circuit LD[m,2], the local driver circuit LD[1,n-1], the local driver circuit LD[1,n], the local driver circuit LD[2,n-1], the local driver circuit LD[2,n], the local driver circuit LD[m-1,n-1], the local driver circuit LD[m-1,n], the local driver circuit LD[m,n-1], and the local driver circuit LD[m,n].

[0120] 8B shows pixel regions when the pixel array ALP included in the pixel layer PXAL is divided into regions of m rows and n columns. FIG. 8B is a top view of the display device 100, and shows only the drive circuit region DRV and the pixel array ALP. In particular, in FIG. 8B, the drive circuit region DRV is indicated by a solid line, and the pixel array ALP is indicated by a dashed line. As shown in FIG. 8B, in the top view, the position of the drive circuit region DRV overlaps the inside of the pixel array ALP. In addition, in FIG. 8B, the pixel array ALP is divided into pixel regions ARA[1,1] to ARA[m,n], as an example. In addition, in Figure 8B, as an example, the symbols for pixel area ARA[1,1], pixel area ARA[2,1], pixel area ARA[m-1,1], pixel area ARA[m,1], pixel area ARA[1,n], pixel area ARA[2,n], pixel area ARA[m-1,n], and pixel area ARA[m,n] are excerpted and shown.

[0121] As an example, if it is desired to divide the pixel array ALP into 32 regions, m = 4 and n = 8 can be applied to FIGS. 8A and 8B. Incidentally, if the resolution of the display device 100 is 8K4K, the number of pixels is 4320 pixels × 7680 pixels. Furthermore, if the sub-pixels of the display device 100 are of three colors, red (R), green (G), and blue (B), the total number of sub-pixels is 4320 × 7680 × 3. Here, if the pixel array of the display device 100 with an 8K4K resolution is divided into 32 regions, the number of pixels per region is 1080 pixels × 960 pixels. Furthermore, if the sub-pixels of the display device 100 are of three colors, red (R), green (G), and blue (B), the number of sub-pixels per region is 1080 × 960 × 3.

[0122] 8B, as an example, the local driver circuit LD[1,1] drives the pixels included in the pixel region ARA[1,1], and the local driver circuit LD[2,1] drives the pixels included in the pixel region ARA[2,1]. The local driver circuit LD[m-1,1] drives the pixels included in the pixel region ARA[m-1,1], and the local driver circuit LD[m,1] drives the pixels included in the pixel region ARA[m,1]. The local driver circuit LD[1,n] drives the pixels included in the pixel region ARA[1,n], and the local driver circuit LD[2,n] drives the pixels included in the pixel region ARA[2,n]. The local driver circuit LD[m-1,n] drives the pixels included in the pixel region ARA[m-1,n], and the local driver circuit LD[m,n] drives the pixels included in the pixel region ARA[m,n]. That is, although not shown in Fig. 8B, the local driver circuit LD[i,j] located in the i-th row and j-th column (i is an integer between 1 and m, and j is an integer between 1 and n) drives the pixels included in the pixel area ARA[i,j]. Note that in Fig. 8B, as an example, the correspondence between the pixel area ARA and the local driver circuit LD that drives the pixels included in that pixel area ARA is shown by a thick arrow.

[0123] As shown in Fig. 8B, when the position of the drive circuit region DRV overlaps the inside of the pixel array ALP in top view, the wiring (e.g., source wiring, gate wiring, constant voltage line, etc.) electrically connecting the pixels of the pixel region ARA and the local driver circuit LD is provided as shown in Fig. 9A, for example. In other words, the display device of the present invention is configured so that the wiring electrically connecting the local driver circuit LD and the pixel region ARA corresponding to the local driver circuit LD is routed in the wiring layer LINL.

[0124] 9A, the wiring group GLS[1,1] functions as, for example, a plurality of gate wirings that electrically connect a plurality of pixels included in the pixel region ARA[1,1] to the gate driver circuit included in the local driver circuit LD[1,1]. The wiring group SLS[1,1] functions as, for example, a plurality of source wirings that electrically connect a plurality of pixels included in the pixel region ARA[1,1] to the source driver circuit included in the local driver circuit LD[1,1]. The wiring group GLS[2,1] functions as, for example, a plurality of gate wirings that electrically connect a plurality of pixels included in the pixel region ARA[2,1] to the gate driver circuit included in the local driver circuit LD[2,1]. The wiring group SLS[1,2] functions as, for example, a plurality of source wirings that electrically connect a plurality of pixels included in the pixel region ARA[1,2] to the source driver circuit included in the local driver circuit LD[1,2].

[0125] 9A, consider a case where each of pixel regions ARA[1,1] to ARA[m,n] has, as an example, a plurality of pixels arranged in a matrix of s rows and t columns (s is an integer greater than or equal to 1, and t is an integer greater than or equal to 1). In this case, as an example, each of wiring groups GLS[1,1] and GLS[2,1] has s gate wirings, and each of wiring groups SLS[1,1] and SLS[1,2] has t source wirings. In addition, in Figure 9A, wiring GL[1,1]_1, wiring GL[1,1]_2, and wiring GL[1,1]_s are selected and illustrated as wirings included in the wiring group GLS[1,1], wiring GL[2,1]_1, wiring GL[2,1]_2, and wiring GL[2,1]_s are selected and illustrated as wirings included in the wiring group GLS[2,1], wiring SL[1,1]_1, wiring SL[1,1]_2, and wiring SL[1,1]_t are selected and illustrated as wirings included in the wiring group SLS[1,1], and wiring SL[1,2]_1, wiring SL[1,2]_2, and wiring SL[1,2]_t are selected and illustrated as wirings included in the wiring group SLS[1,2].

[0126] Although not shown, the wiring layer LINL may be provided with wiring other than the gate wiring and the source wiring. For example, the wiring layer LINL may be provided with wiring for applying a constant voltage from the voltage generating circuit PG included in the circuit layer SICL to the pixels included in the pixel array ALP.

[0127] The wiring layer LINL may have a configuration including a plurality of layers. Specifically, for example, as shown in FIG. 9B, the wiring layer LINL may have a configuration in which different wirings are superimposed.

[0128] 9B shows, as an example, a cross-sectional view of a circuit layer SICL, a wiring layer LINL, and a pixel layer PXAL stacked together. Note that in the pixel layer PXAL of FIG. 9B, only the pixel regions ARA[1,1], ARA[2,2], and ARA[3,3] are shown, each of which is shown as a block diagram. Also, in FIG. 9B, the circuit layer SICL includes a local driver circuit LD[1,1] and a local driver circuit LD[2,2], each of which includes a transistor 300.

[0129] 9B, one of the source and drain of the transistor 300 in the local driver circuit LD[1,1] is electrically connected to the pixel region ARA[1,1] via a wiring GL[1,1]_1 (wiring SL[1,1]_1). Also, one of the source and drain of the transistor 300 in the local driver circuit LD[2,2] is electrically connected to the pixel region ARA[2,2] via a wiring GL[2,2]_1 (wiring SL[2,2]_1). Also, FIG. 9B shows a configuration in which the pixel region ARA[3,3] and a wiring GL[3,3]_1 (wiring SL[3,3]_1) are electrically connected.

[0130] For example, during design, depending on the positional relationship of the wiring electrically connecting the local driver circuit LD and the pixel area ARA corresponding to the local driver circuit LD, the wiring may overlap. In this case, as shown in FIG. 9B, by providing the overlapping wiring on different layers, the local driver circuit LD can be electrically connected to the pixel area ARA corresponding to the local driver circuit LD without physical contact between the different wiring. For example, FIG. 9B shows a configuration in which the wiring electrically connecting the pixel area ARA[1,1] and the local driver circuit LD[1,1] and the wiring electrically connecting the pixel area ARA[2,2] and the local driver circuit LD[2,2] are routed so as not to physically contact each other. Also, for example, FIG. 9B shows a configuration in which the wiring electrically connecting the pixel area ARA[2,2] and the local driver circuit LD[2,2] and the wiring electrically connected to the pixel area ARA[3,3] are routed so as not to physically contact each other.

[0131] Furthermore, in order to suppress signal delays and / or to suppress increases in power consumption due to parasitic resistance, etc., it is preferable that the wiring (gate wiring, source wiring, etc.) for transmitting signals from the local driver circuit LD to the pixels in the pixel area ARA be short. For this reason, it is preferable that the wiring electrically connecting the local driver circuit LD and the pixel area ARA in the display device 100 be designed to be short. One example of a design for this purpose is to design the contact portion of the wiring between the pixel area ARA and the wiring layer LINL to be in an optimal position for each pixel area ARA.

[0132] Furthermore, in Figures 9A and 9B, a configuration has been described in which the drive circuit region DRV of the circuit layer SICL and the pixel region ARA of the pixel layer PXAL are electrically connected via wiring in the wiring layer LINL. However, a display device of one embodiment of the present invention may also be configured such that the drive circuit region DRV of the circuit layer SICL and the pixel region ARA of the pixel layer PXAL are electrically connected via wiring in the region LIA in addition to the wiring in the wiring layer LINL.

[0133] For example, as shown in FIG. 10A , the wiring GL[1,1]_1 (wiring SL[1,1]_1) electrically connected between the local driver circuit LD[1,1] and the pixel region ARA[1,1] included in the display device 100 may be a wiring that electrically connects from one of the source or drain of the transistor 300 to the pixel region ARA[1,1] in the following order: wiring in the wiring layer LINL, wiring included in the region LIA (wiring depicted by a thick dotted line), and wiring in the wiring layer LINL again. A cross-sectional view of the display device 100 in this case is also shown in FIG. 10B . For example, the display device 100 in FIG. 10B is configured such that the path of the wiring GL[1,1]_1 (wiring SL[1,1]_1) electrically connected between the local driver circuit LD[1,1] and the pixel region ARA[1,1] in the drive circuit region DRV passes through a low-resistance region 314c provided on the substrate BS in the region LIA of the circuit layer SICL. When the substrate BS is a semiconductor substrate made of silicon, the low resistance region 314c can be formed by doping with an element that provides conductivity.

[0134] 11A, the wiring GL[1,1]_1 (wiring SL[1,1]_1) electrically connected between the local driver circuit LD[1,1] and the pixel region ARA[1,1] included in the display device 100 may be a wiring that electrically connects one of the source or drain of the transistor 300 to the pixel region ARA[1,1] in the following order: wiring included in the region LIA (wiring drawn with a thick dotted line); and wiring in the wiring layer LINL. A cross-sectional view of the display device 100 in this case is shown in FIG. 11B. For example, the display device 100 in FIG. 11B has a low-resistance region 314c in which one of the source or drain of the transistor 300 is formed to extend into the region LIA. The display device 100 is configured to electrically connect the local driver circuit LD[1,1] in the drive circuit region DRV and the pixel region ARA[1,1] via the low-resistance region 314c, wiring included in the wiring layer LINL, and the like.

[0135] Here, the position of the contact portion of the wiring between the pixel region ARA and the wiring layer LINL will be described. FIG. 12A is a schematic diagram illustrating, as an example, the pixel region ARA and multiple pixels PIX included in the pixel region ARA. Note that, as an example, the multiple pixels PIX are arranged in a matrix in the pixel region ARA. Also, FIG. 12A illustrates, as an example, a configuration in which each pixel PIX includes a transistor Tr, and other circuit elements are not illustrated. Also, as an example, in the pixel region ARA of FIG. 12A, a wiring group SLS (wiring SL_1, wiring SL_2, wiring SL_3) extends in the X direction. Note that, although FIG. 12A illustrates three wirings included in the wiring group SLS, the number of wirings may be one, two, or four or more. Also, the wiring group GLS and the like are not illustrated. Also, in this specification and the like, the X direction may be referred to as the row direction, and the Y direction may be referred to as the column direction.

[0136] 12A, the contact portion of the wiring between the pixel region ARA and the wiring layer LINL is located, for example, at the end of the pixel array ALP. In FIG. 12A, the contact portion of the wiring between the pixel region ARA and the wiring layer LINL is designated as the contact portion CNT. In this case, the local driver circuit LD is preferably located in the positive X direction relative to the pixel region ARA. Conversely, if the local driver circuit LD is located in the negative X direction relative to the pixel region ARA, the length of the wiring between the pixel region ARA and the local driver circuit LD corresponding to the pixel region ARA becomes longer, which may result in signal delays being more likely to occur and / or increased power consumption due to parasitic resistance, etc.

[0137] Furthermore, the positions of the contact portions of the wiring between the pixel region ARA and the wiring layer LINL may be provided so as to be included inside the pixels PIX, for example, as shown in Fig. 12B. In this case, it is preferable that the local driver circuit LD is located in the positive or negative Y direction with respect to the pixel region ARA. Note that, in Fig. 12B, the contact portions CNT are provided inside the pixels PIX of different columns for each wiring included in the wiring group SLS, but the contact portions CNT may also be provided inside the pixels PIX of the same column for each wiring included in the wiring group SLS.

[0138] Furthermore, although FIG. 12B shows an example in which the contact portion CNT is provided inside the pixel PIX, the contact portion CNT may be provided outside the pixel PIX (between adjacent pixels PIX) as shown in FIG. 12C.

[0139] In this specification and the like, the inside of the pixel PIX can be, for example, a region overlapping with the light-emitting region of a light-emitting device (light-emitting device 150a to light-emitting device 150c described later) included in the pixel PIX, and the outside of the pixel PIX can be, for example, the outside of this region. The inside of the pixel PIX can be, for example, a region overlapping with an EL layer (EL layer 141a to EL layer 141c described later) included in the pixel PIX, and the outside of the pixel PIX can be, for example, the outside of this region. The inside of the pixel PIX can be, for example, a region overlapping with an opening of an insulator (opening of the insulator 112 reaching a lower electrode included in the pixel PIX) (the opening of the conductor 121a to conductor 121c described later), and the outside of the pixel PIX can be, for example, the outside of this region. The inside of the pixel PIX can be, for example, a region overlapping with a lower electrode (conductor 121a to conductor 121c described later) included in the pixel PIX, and the outside of the pixel PIX can be, for example, the outside of this region.

[0140] In this specification and the like, the boundary between the inside and outside of a pixel PIX may be described as being included within the pixel PIX, and depending on the situation, the boundary between the inside and outside of a pixel PIX may be described as being included outside of the pixel PIX.

[0141] Furthermore, depending on the positional relationship between the pixel region ARA and the local driver circuit LD, the positions of the plurality of contact portions CNT may be a combination of the cases shown in Figures 12A to 12C. That is, the positions of the plurality of contact portions CNT may be configured such that some of them are located at the edge of the pixel region ARA, another part is located inside the pixel PIX, and the rest is located outside the pixel PIX.

[0142] As shown in Figures 7, 8A, and 8B, by configuring the display device 100, the pixel array ALP of the display device 100 can be divided into pixel areas ARA[1,1] to ARA[m,n], and each pixel area ARA can be driven in parallel by a local driver circuit LD[1,1] to a local driver circuit LD[m,n].

[0143] 7, 8A, and 8B, by arranging the local driver circuit LD relatively centrally in the circuit layer SICL, when an image is displayed on the display unit of the display device 100, it is possible to reduce the difference in the time required for input of the image data signals given to each pixel in different pixel areas ARA. Similarly, it is possible to reduce the difference in the time required for input of signals in different pixel areas ARA, not only for data signals but also for pixel selection signals transmitted to the pixel areas ARA. In other words, it is possible to suppress delays in signals transmitted from the drive circuit area DRV to each pixel area ARA.

[0144] Note that the display device according to one embodiment of the present invention is not limited to the configuration of the above-described display device 100. The display device according to one embodiment of the present invention may have a modified configuration of the above-described display device 100 depending on the situation.

[0145] For example, the display device 100 described above has been described as including one drive circuit region DRV in the circuit layer SICL, but the circuit layer SICL may include two or more drive circuit regions DRV. The display device 100 in Fig. 13A is a schematic top view illustrating an example configuration in which the circuit layer SICL of the display device 100 includes two or more drive circuit regions DRV.

[0146] The display device 100 of Fig. 13A is configured such that a driving circuit region DRV is provided in a portion of the overlapping region of the pixel regions ARA that are contained within a range of 2 rows and n columns of the pixel array ALP. Specifically, in the display device 100 of Fig. 13A, a driving circuit region DRV[1] is provided in a portion of the overlapping region of the pixel regions ARA[1,1] to ARA[2,n], and a driving circuit region DRV[m / 2] is provided in a portion of the overlapping region of the pixel regions ARA[m-1,1] to ARA[m,n]. In other words, the circuit layer SICL is provided with m / 2 driving circuit regions DRV (driving circuit regions DRV[1] to DRV[m / 2]). Note that the number of columns m shown in Fig. 13A is an even number.

[0147] 13A illustrates the pixel regions ARA[1,1], ARA[2,1], ARA[m-1,1], ARA[m,1], ARA[1,n], ARA[2,n], ARA[m-1,n], and ARA[m,n] as the pixel regions ARA. Also, in FIG. 13A, the drive circuit regions DRV[1] and DRV[m / 2] are illustrated as the drive circuit regions DRV. 13A shows an excerpt of the local driver circuits LD, including a local driver circuit LD[1,1], a local driver circuit LD[2,1], a local driver circuit LD[1,2], a local driver circuit LD[2,2], a local driver circuit LD[m-1,1], a local driver circuit LD[m,1], a local driver circuit LD[m-1,2], a local driver circuit LD[m,2], a local driver circuit LD[1,n-1], a local driver circuit LD[2,n-1], a local driver circuit LD[1,n], a local driver circuit LD[2,n], a local driver circuit LD[m-1,n-1], a local driver circuit LD[m,n-1], a local driver circuit LD[m-1,n], and a local driver circuit LD[m,n].

[0148] In addition, in the display device 100 of Figure 13A, a controller CON and a voltage generation circuit PG are illustrated in the center of each of the drive circuit areas DRV[1] to DRV[m / 2], but the positions and shapes of the controller CON and voltage generation circuit PG provided in the drive circuit areas DRV[1] to DRV[m / 2] are not particularly limited.

[0149] 13A is configured such that the pixels included in each of a plurality of pixel regions ARA contained in a range of 2 rows and n columns of the pixel array ALP are driven by a local driver circuit LD included in one drive circuit region DRV, but the range of the pixel region in the pixel array ALP corresponding to one drive circuit region DRV may be a range of 1 to m rows and n columns, or a range of m rows and 1 to n columns. Specifically, the range of the pixel region in the pixel array ALP corresponding to one drive circuit region DRV may be, for example, a range of 3 rows and n columns, or a range of m rows and 2 columns.

[0150] Furthermore, although m, which indicates the number of rows, is an even number in the display device 100 of Fig. 13A, m may be an odd number. In this case, as an example of the configuration of the display device 100 of Fig. 13A, the entire pixel array ALP may be divided into a plurality of ranges of 2 rows and n columns and one range of 1 row and n columns, and a plurality of drive circuit regions DRV may be provided so that one drive circuit region DRV corresponds to each range.

[0151] 13A is configured to drive the pixels included in each of a plurality of pixel regions ARA contained in a range of 2 rows and n columns of the pixel array ALP by a local driver circuit LD included in one drive circuit region DRV, but the range of the pixel region in the pixel array ALP corresponding to one drive circuit region DRV may be a range of 1 to m rows and 1 to n columns. Specifically, for example, as shown in FIG. 13B, one range may be divided into 2 rows i a As a column, pixels in a plurality of pixel areas ARA included in one range may be driven by one driving circuit area DRV. a Each of n=i a ×p, m is an integer equal to or greater than 1 that satisfies 2×q. In this case, p×q driving circuit regions DRV (driving circuit regions DRV[1] to DRV[p×q]) are provided in the circuit layer SICL.

[0152] In FIG. 13B, the pixel area ARA includes the pixel area ARA[1,1], the pixel area ARA[2,1], the pixel area ARA[m-1,1], the pixel area ARA[m,1], and the pixel area ARA[1,i a ] and pixel area ARA[2,i a ] and pixel area ARA[m-1,i a ] and pixel area ARA[m,i a ] and pixel area ARA[1,ni a +1] and pixel area ARA[2,ni a +1] and the pixel area ARA[m-1,ni a +1] and pixel area ARA[m,ni a 13B excerpts the pixel regions ARA[1,n], ARA[2,n], ARA[m-1,n], and ARA[m,n] from the drive circuit region DRV, and excerpts the pixel regions ARA[1], ARA[p], ARA[p×q-p+1], and ARA[p×q] from the drive circuit region DRV. 13B excerpts the local driver circuit LD[1,1], ARA[2,1], ARA[m-1,1], ARA[m,1], and ARA[1,i a ] and the local driver circuit LD[2,i a ] and local driver circuit LD[m-1,i a ] and local driver circuit LD[m,i a ] and the local driver circuit LD[1,ni a +1] and the local driver circuit LD[2,ni a +1] and local driver circuit LD[m-1,ni a +1] and the local driver circuit LD[m,ni a 10 shows an excerpt of local driver circuits LD[1,n], LD[2,n], LD[m-1,n], and LD[m,n].

[0153] 13B, the drive circuit regions DRV[1] to DRV[p×q] do not include a controller CON and a voltage generating circuit PG, but the drive circuit regions DRV[1] to DRV[p×q] may include a controller CON and a voltage generating circuit PG. The positions and shapes of the controller CON and the voltage generating circuit PG provided in the drive circuit regions DRV[1] to DRV[p×q] are not particularly limited.

[0154] 8B, 13A, 13B, and the like, the drive circuit region DRV does not overlap the edge of the region including all of the pixel regions ARA[1,1] to ARA[m,n] of the pixel array ALP. However, a configuration in which a portion of the drive circuit region DRV overlaps a portion of the edge of the pixel array ALP may also be used. Specifically, for example, as shown in FIG. 14A, the display device 100 may be configured so that one drive circuit region DRV crosses the pixel array ALP in the column direction in a top view. Therefore, a portion of the edge of the region including all of the pixel regions ARA[1,1] to ARA[m,n] of the pixel array ALP overlaps the drive circuit region DRV (this also includes the case in which a portion of the edge of the pixel array ALP overlaps a portion of the edge of the drive circuit region DRV, as shown in FIG. 14A).

[0155] In this case, local driver circuits LD[1,1] to LD[m,n] are arranged in a matrix of m rows and n columns in the drive circuit region DRV, similar to the drive circuit region DRV shown in FIG. 8B.

[0156] In addition, in Figure 14A, the pixel area ARA is illustrated by selecting pixel area ARA[1,1], pixel area ARA[2,1], pixel area ARA[m-1,1], pixel area ARA[m,1], pixel area ARA[1,2], pixel area ARA[2,2], pixel area ARA[m-1,2], pixel area ARA[m,2], pixel area ARA[1,n-1], pixel area ARA[2,n-1], pixel area ARA[m-1,n-1], pixel area ARA[m,n-1], pixel area ARA[1,n], pixel area ARA[2,n], pixel area ARA[m-1,n], and pixel area ARA[m,n]. 14A shows an excerpt of the local driver circuits LD, including a local driver circuit LD[1,1], a local driver circuit LD[2,1], a local driver circuit LD[m-1,1], a local driver circuit LD[m,1], a local driver circuit LD[1,2], a local driver circuit LD[2,2], a local driver circuit LD[m-1,2], a local driver circuit LD[m,2], a local driver circuit LD[1,n-1], a local driver circuit LD[2,n-1], a local driver circuit LD[m-1,n-1], a local driver circuit LD[m,n-1], a local driver circuit LD[1,n], a local driver circuit LD[2,n], a local driver circuit LD[m-1,n], and a local driver circuit LD[m,n].

[0157] Furthermore, in the display device 100 of Figure 14A, the controller CON and the voltage generating circuit PG are illustrated in the central part of the drive circuit region DRV, but the positions and shapes of the controller CON and the voltage generating circuit PG provided in the drive circuit region DRV are not particularly limited.

[0158] 14A is configured such that one drive circuit region DRV is provided across the pixel array ALP, the display device 100 may also be configured such that a plurality of drive circuit regions DRV are provided across the pixel array ALP. Specifically, for example, as shown in FIG. 14B, one range may be divided into m rows i bAs a column, pixels in a plurality of pixel areas ARA included in one range may be driven by one drive circuit area DRV. b Each of n=i b ×r is an integer equal to or greater than 1. In this case, the circuit layer SICL is provided with r driving circuit regions DRV (driving circuit regions DRV[1] to DRV[r]).

[0159] In FIG. 14B, the pixel area ARA includes a pixel area ARA[1,1], a pixel area ARA[2,1], a pixel area ARA[m-1,1], a pixel area ARA[m,1], and a pixel area ARA[1,i b ] and pixel area ARA[2,i b ] and pixel area ARA[m-1,i b ] and pixel area ARA[m,i b ] and pixel area ARA[1,ni b +1] and pixel area ARA[2,ni b +1] and the pixel area ARA[m-1,ni b +1] and pixel area ARA[m,ni b 14B excerpts the pixel regions ARA[1,n], ARA[2,n], ARA[m-1,n], and ARA[m,n]. Also, in FIG. 14B, the drive circuit regions DRV[1] and DRV[r] are excerpted as the drive circuit regions DRV. Also, in FIG. 14B, the local driver circuits LD[1,1], LD[2,1], LD[m-1,1], LD[m,1], and LD[1,i b ] and the local driver circuit LD[2,i b ] and local driver circuit LD[m-1,i b ] and local driver circuit LD[m,i b ] and the local driver circuit LD[1,ni b +1] and the local driver circuit LD[2,ni b +1] and local driver circuit LD[m-1,nib +1] and the local driver circuit LD[m,ni b 10 shows an excerpt of local driver circuits LD[1,n], LD[2,n], LD[m-1,n], and LD[m,n].

[0160] 14B, the drive circuit regions DRV[1] to DRV[r] do not include a controller CON and a voltage generating circuit PG, but the drive circuit regions DRV[1] to DRV[r] may include a controller CON and a voltage generating circuit PG. The positions and shapes of the controller CON and the voltage generating circuit PG provided in the drive circuit regions DRV[1] to DRV[r] are not particularly limited.

[0161] The display device 100 in FIG. 14B includes the pixel array ALP in the mth row i b Although the display device 100 is configured such that the pixels included in each of the plurality of pixel regions ARA contained within the range of a column are driven by a local driver circuit LD included in one drive circuit region DRV, the ranges of pixel regions in the pixel array ALP corresponding to each of the plurality of drive circuit regions DRV may be different from each other. For example, when the number n of columns of the pixel array ALP is odd, the display device 100 may be configured such that the entire pixel array ALP is divided into a plurality of ranges of m rows and 2 columns and one range of m rows and 1 column, and multiple drive circuit regions DRV are provided so that one drive circuit region DRV corresponds to each range.

[0162] 14A shows a configuration in which both opposing ends of the pixel array ALP overlap part of an end of the drive circuit region DRV, but a configuration in which one of the opposing ends of the pixel array ALP overlaps part of an end of the drive circuit region DRV may also be used. Specifically, for example, as shown in FIG. 15, a configuration in which one of the opposing ends of the pixel array ALP overlaps part of an end of one drive circuit region DRV may also be used.

[0163] Furthermore, a display device according to one embodiment of the present invention may be obtained by appropriately combining the configuration examples of the display device 100 described above. As an example, the configuration example of the display device 100 in FIG. 16 may be combined with the configuration example of the display device 100 in FIG. 15, as in the display device 100 in FIG. 16. In the display device 100 in FIG. 16, when viewed from above, the circuit layer SICL has a drive circuit region DRVa overlapping one of the opposing ends of the pixel array ALP, and a drive circuit region DRVb overlapping a partial region inside the pixel array ALP. Specifically, in the display device 100 in FIG. 16, the drive circuit region DRVa overlaps the pixel regions ARA[1,1] to ARA[i c , n], and the driving circuit region DRVb drives the pixels in the pixel region ARA[i c +1,1] to the pixel area ARA[m,n] are driven. c can be an integer between 1 and m-1 inclusive.

[0164] In FIG. 16, the pixel area ARA includes a pixel area ARA[1,1], a pixel area ARA[2,1], and a pixel area ARA[i c ,1] and pixel area ARA[i c +1,1], pixel area ARA[m,1], pixel area ARA[1,2], pixel area ARA[2,2], and pixel area ARA[i c , 2], pixel area ARA[1, n-1], pixel area ARA[2, n-1], pixel area ARA[i c ,n-1], pixel area ARA[1,n], pixel area ARA[2,n], and pixel area ARA[i c ,n] and pixel area ARA[i c 16, the local driver circuits LD are selected from the local driver circuit LD[1,1], the local driver circuit LD[2,1], and the local driver circuit LD[i c,1], local driver circuit LD[1,2], local driver circuit LD[2,2], and local driver circuit LD[i c ,2], local driver circuit LD[1,n-1], local driver circuit LD[2,n-1], and local driver circuit LD[i c ,n-1], local driver circuit LD[1,n], local driver circuit LD[2,n], and local driver circuit LD[i c ,n] and local driver circuit LD[i c +1,1] and the local driver circuit LD[i c +1,2], local driver circuit LD[m,1], local driver circuit LD[m,2], and local driver circuit LD[i c +1,n-1] and local driver circuit LD[i c 10, the local driver circuit LD[m,n-1], the local driver circuit LD[m,n-1], and the local driver circuit LD[m,n] are selectively illustrated.

[0165] 16, the drive circuit area DRVa and the drive circuit area DRVb do not include a controller CON and a voltage generating circuit PG, but the drive circuit area DRVa and the drive circuit area DRVb may each include a controller CON and a voltage generating circuit PG. The positions and shapes of the controller CON and the voltage generating circuit PG provided in the drive circuit area DRVa and the drive circuit area DRVb are not particularly limited.

[0166] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0167] (Embodiment 3) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0168] <Example of display device configuration> 17 is a cross-sectional view illustrating an example of a display device according to one embodiment of the present invention. For example, a display device 100 illustrated in FIG. 17 has a structure in which a pixel circuit, a driver circuit, and the like are provided over a substrate 310.

[0169] The substrate 310 corresponds to, for example, the substrate BS described in the above embodiment, and therefore, the substrate 310 can be made of a material that can be applied to the substrate BS.

[0170] In this embodiment, the substrate 310 will be described as a semiconductor substrate made of silicon or the like.

[0171] The display device 100 includes a transistor 300, a transistor 500, and light-emitting devices 150a to 150c on a substrate 310.

[0172] The transistor 300 is provided over a substrate 310 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. Therefore, the transistor 300 is a transistor (a Si transistor) whose channel formation region contains silicon. Note that although FIG. 17 illustrates a structure in which one of the source and drain regions of the transistor 300 is electrically connected to the conductors 330 to 366 (described later) through the conductor 328 (described later), the electrical connection structure of the semiconductor device of one embodiment of the present invention is not limited thereto. For example, the semiconductor device of one embodiment of the present invention may have a structure in which the other of the source and drain of the transistor 300 is electrically connected to the conductors 330 to 366 through the conductor 328, or a structure in which the gate of the transistor 300 is electrically connected to the conductors 330 to 366 through the conductor 328.

[0173] The transistor 300 can be made into a fin type by, for example, configuring the top surface and the side surfaces in the channel width direction of the semiconductor region 313 to be covered with a conductor 316 via an insulator 315 that functions as a gate insulating film. By configuring the transistor 300 as a fin type, the effective channel width can be increased, and the on-state characteristics of the transistor 300 can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-state characteristics of the transistor 300 can be improved.

[0174] Note that the transistor 300 may be either a p-channel transistor or an n-channel transistor. Alternatively, a plurality of transistors 300 may be provided, and both p-channel and n-channel transistors may be used.

[0175] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0176] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0177] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0178] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed by using, for example, a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa isolation method, or the like.

[0179] 17 is just an example, and the structure of the transistor 300 is not limited thereto, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of a fin structure.

[0180] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side to cover the transistor 300 shown in FIG.

[0181] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0182] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0183] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0184] The insulator 324 is preferably a barrier insulating film that prevents diffusion of water, hydrogen, impurities, and the like from the substrate 310 or the transistor 300 to a region above the insulator 324 (e.g., a region where the transistor 500, the light-emitting devices 150a to 150c, and the like are provided). Therefore, the insulator 324 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., through which the impurities are less likely to permeate). Depending on the situation, the insulator 324 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms (i.e., through which the impurities are less likely to permeate). Alternatively, the insulator 324 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like).

[0185] An example of a film having a barrier property against hydrogen is silicon nitride formed by a chemical vapor deposition (CVD) method. Here, diffusion of hydrogen into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0186] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0187] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0188] Furthermore, conductors 328, 330, etc., which connect to a light-emitting device or the like provided above the insulator 326, are embedded in the insulators 320, 322, 324, and 326. The conductors 328, 330, etc., function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification, the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0189] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0190] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 17 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0191] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against impurities such as hydrogen and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulators 352 and 354 function as interlayer insulating films and planarizing films. The conductor 356 preferably includes a conductor having a barrier property against impurities such as hydrogen and water. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, thereby suppressing diffusion of hydrogen from the transistor 300 to the transistor 500.

[0192] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0193] In addition, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order on the insulator 354 and the conductor 356.

[0194] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0195] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, it is preferable to use an insulator that has a barrier property against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 362 and / or the insulator 364 can be made of a material that can be used for the insulator 324.

[0196] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0197] An insulator 512 is provided over the insulator 364 and the conductor 366. A substance that has a barrier property against oxygen and hydrogen is preferably used for the insulator 512. The insulator 512 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0198] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0199] For example, the insulator 512 can be made of the same material as the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance generated between wirings can be reduced. For example, the insulator 512 can be made of a silicon oxide film, a silicon oxynitride film, or the like.

[0200] Transistor 500, which is an OS transistor, is, for example, provided over an insulator 512.

[0201] The circuit layer SICL can be configured to be laminated with the wiring layer LINL and the pixel layer PXAL by a bonding process or the like. For example, as shown in FIG. 18A, the circuit layer SICL and the wiring layer LINL can be bonded together by connecting them with microbumps 23 or the like. The microbumps 23 can directly connect electrodes (not shown) provided on the circuit layer SICL and the wiring layer LINL by TSV (Through Silicon Via). In this case, the transistors included in the pixel layer PXAL can also be Si transistors. Furthermore, the microbumps 23 may be configured to be provided between the wiring layer LINL and the pixel layer PXAL, as shown in FIG. 18B, for example.

[0202] The transistor 500 will now be described in detail. 19A and 19B show an example of the structure of the OS transistor 500. Note that FIG. 19A is a cross-sectional view of the OS transistor in the channel length direction, and FIG. 19B is a cross-sectional view of the OS transistor in the channel width direction.

[0203] As shown in FIGS. 19A and 19B, an insulator 514 and an insulator 516 are formed on the insulator 512.

[0204] The insulator 514 is preferably a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 310 or a region where circuit elements and the like below the insulator 512 are provided to the region where the transistor 500 is provided. Therefore, the insulator 514 can be made of silicon nitride formed by a CVD method, for example.

[0205] The insulator 516 can be made of, for example, the same material as the insulator 512 .

[0206] As shown in FIGS. 19A and 19B, the transistor 500 includes an insulator 516 on an insulator 514, a conductor 503 (conductors 503a and 503b) disposed so as to be embedded in the insulators 514 and 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and an oxide 572a on the oxide 572b. conductor 542b on oxide 530b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping part of oxide 530b, and insulator 544 arranged on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 571b. 19A and 19B , insulator 552 contacts the upper surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and upper surface of oxide 530b, the side surface of conductor 542, the side surface of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. Furthermore, the upper surface of conductor 560 is disposed so as to be at approximately the same height as the upper surfaces of insulator 554, insulator 550, insulator 552, and insulator 580. Furthermore, insulator 574 contacts at least a portion of the upper surface of conductor 560, insulator 552, insulator 550, insulator 554, and insulator 580.

[0207] Openings reaching the oxide 530b are provided in the insulator 580 and the insulator 544. The insulator 552, the insulator 550, the insulator 554, and the conductor 560 are disposed in the openings. In addition, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b in the channel length direction of the transistor 500. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0208] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b.

[0209] Note that although the transistor 500 has a structure in which the oxide 530 has a two-layer structure of the oxide 530a and the oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a structure in which the oxide 530 has a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, the oxide 530a and the oxide 530b can each have a stacked structure.

[0210] The conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode. The insulators 552, 550, and 554 function as first gate insulators, and the insulators 522 and 524 function as second gate insulators. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 542a functions as either a source or a drain, and the conductor 542b functions as the other. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0211] FIG. 20A shows an enlarged view of the vicinity of the channel formation region in FIG. 19A. When oxygen is supplied to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 20A, the oxide 530b includes a region 530bc that functions as the channel formation region of the transistor 500, and regions 530ba and 530bb that are provided on either side of the region 530bc and function as source and drain regions. The region 530bc at least partially overlaps with the conductor 560. In other words, the region 530bc is located in the region between the conductor 542a and the conductor 542b. The region 530ba overlaps with the conductor 542a, and the region 530bb overlaps with the conductor 542b.

[0212] The region 530bc, which functions as a channel formation region, has a smaller oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V) than the regions 530ba and 530bb. O The region 530bc is a high-resistance region with a low carrier concentration due to its low oxygen vacancy or low impurity concentration. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.

[0213] A transistor using a metal oxide has impurities or oxygen vacancies (VO ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible.

[0214] The regions 530ba and 530bb that function as source and drain regions have oxygen vacancies (V O ) or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, resulting in an increased carrier concentration and low resistance. That is, the regions 530ba and 530bb are n-type regions with a higher carrier concentration and lower resistance than the region 530bc.

[0215] Here, the carrier concentration of the region 530bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 530bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0216] A region having a carrier concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc may be formed between region 530bc and regions 530ba or 530bb. That is, this region functions as a junction region between region 530bc and regions 530ba or 530bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 530ba and 530bb and equal to or higher than those of region 530bc.

[0217] 20A shows an example in which the regions 530ba, 530bb, and 530bc are formed in the oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 530b but also in the oxide 530a.

[0218] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than gradually varying from region to region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0219] In the transistor 500, the oxide 530 including the channel formation region (the oxide 530a and the oxide 530b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0220] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0221] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0222] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0223] In this way, by disposing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a into the oxide 530b.

[0224] Furthermore, since the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Because the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0225] The oxide 530b preferably has crystallinity, and it is particularly preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 530b.

[0226] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., oxygen vacancies (V O ) is a metal oxide with little crystallinity. In particular, by subjecting the formed metal oxide to heat treatment at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize, the CAAC-OS can be made to have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0227] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0228] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy is converted into a defect where hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0229] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies across the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0230] Therefore, in the oxide semiconductor, the region 530bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 530ba and 530bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 530ba and 530bb.

[0231] Therefore, in this embodiment, in a state where the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 530bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0232] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 530bc. The V of the region 530bc can be activated by the action of the plasma, microwaves, etc. O H is split off, hydrogen H is removed from the region 530bc, and oxygen vacancy V Ocan be compensated with oxygen. O H → H + V O This reaction occurs, and the hydrogen concentration in the region 530bc can be reduced. O H can be reduced to lower the carrier concentration.

[0233] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 542a and 542b and do not reach the regions 530ba and 530bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 571 and 580 that cover the oxide 530b and the conductor 542. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0234] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this manner, oxygen can be efficiently injected into the region 530bc. Furthermore, by arranging the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, injection of more oxygen than necessary into the region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed during formation of the insulating film that becomes the insulator 550.

[0235] The oxygen implanted into the region 530bc can be in various forms, such as oxygen atoms, oxygen molecules, or oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 530bc preferably takes one or more of the above forms, and oxygen radicals are particularly preferred. This can improve the film quality of the insulators 552 and 550, thereby improving the reliability of the transistor 500.

[0236] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 530bc. O By removing H, the region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 530ba and 530bb, which function as source and drain regions, can be prevented, maintaining the n-type state of the regions before microwave treatment. This suppresses fluctuations in the electrical characteristics of the transistor 500 and reduces variations in the electrical characteristics of the transistor 500 within the substrate surface.

[0237] By adopting the above-described structure, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0238] 19B, in a cross-sectional view of the transistor 500 in the channel width direction, a curved surface may be formed between the side surface of the oxide 530b and the top surface of the oxide 530b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0239] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 530b with the insulators 552, 550, and 554, and the conductor 560.

[0240] The oxide 530 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0241] The oxide 530b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 530b. This can reduce the extraction of oxygen from the oxide 530b even during heat treatment, making the transistor 500 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0242] Here, the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0243] Specifically, when the oxide 530a and the oxide 530b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-M-Zn oxide, the oxide 530a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0244] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 530b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0245] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0246] 19B , by providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530, indium contained in the oxide 530 may be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. This results in an atomic ratio near the surface of the oxide 530 that is close to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 530, particularly the oxide 530b, can improve the field-effect mobility of the transistor 500.

[0247] The oxide 530a and the oxide 530b have the above-described structure, which can reduce the defect state density at the interface between the oxide 530a and the oxide 530b. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve a large on-state current and high frequency characteristics.

[0248] At least one of the insulators 512, 514, 544, 571, 574, 576, and 581 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 is preferably made of an insulating material that suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that suppresses diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., through which the above oxygen is less likely to permeate).

[0249] For the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use an insulator that has the function of suppressing diffusion of oxygen and impurities such as water and hydrogen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a high hydrogen barrier property, is preferably used for the insulators 512, 544, and 576. Furthermore, it is preferable to use aluminum oxide or magnesium oxide, which has a high ability to capture and fix hydrogen, for the insulators 514, 571, 574, and 581. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 500 from an interlayer insulating film disposed outside the insulator 581. Alternatively, oxygen contained in the insulator 524 and the like can be prevented from diffusing toward the substrate through the insulators 512 and 514. Alternatively, oxygen contained in the insulator 580 and the like can be prevented from diffusing upward from the transistor 500 through the insulator 574. In this way, the transistor 500 is preferably surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of preventing the diffusion of impurities such as water and hydrogen and oxygen.

[0250] Here, it is preferable to use an oxide having an amorphous structure as the insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a highly reliable transistor 500 and semiconductor device can be manufactured with excellent characteristics.

[0251] Furthermore, the insulators 512, 514, 544, 571, 574, 576, and 581 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0252] The insulators 512, 514, 544, 571, 574, 576, and 581 can be formed by, for example, a sputtering method. Sputtering does not require the use of hydrogen-containing molecules in a film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 512, 514, 544, 571, 574, 576, and 581. Note that the film formation method is not limited to sputtering, and a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may also be used as appropriate.

[0253] It may also be desirable to reduce the resistivity of insulators 512, 544, and 576. For example, it may be desirable to reduce the resistivity of insulators 512, 544, and 576 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 512, 544, and 576 may be able to reduce charge-up of the conductors 503, 542, and 560 during treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0254] The insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 516, 580, and 581.

[0255] For example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarizing film, or the like.

[0256] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. In addition, a part of the conductor 503 may be embedded in the insulator 514.

[0257] The conductor 503 includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and sidewall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the top of the conductor 503b is approximately the same as the height of the top of the conductor 503a and the height of the top of the insulator 516.

[0258] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0259] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 503a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 503a may be made of titanium nitride.

[0260] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0261] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the Vth of the transistor 500 and reduce its off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0262] Note that if the oxide 530 is highly pure and intrinsic, and impurities are removed from the oxide 530 as much as possible, it may be possible to make the transistor 500 normally off (to make the threshold voltage of the transistor 500 higher than 0 V) ​​without applying a potential to the conductor 503 and / or the conductor 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that the same potential is applied to them.

[0263] The electrical resistivity of the conductor 503 is designed taking into consideration the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of the impurities into the oxide 530.

[0264] Note that the conductor 503 is preferably larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in FIG. 19B , the conductor 503 preferably extends to an area outside the channel width direction ends of the oxides 530a and 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, the conductor 503 and the conductor 560 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560, which functions as the first gate electrode, and the electric field of the conductor 503, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0265] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0266] By configuring the transistor 500 as a normally-off transistor and having the above-described S-channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 500 can also be considered to have a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By configuring the transistor 500 as an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulating film can be the entire bulk of the oxide 530. In other words, by configuring the transistor 500 as an S-channel structure, a GAA structure, or an LGAA structure, the entire bulk can be used as a carrier path, making it a so-called bulk-flow type. The bulk-flow type transistor structure can increase the current density flowing through the transistor, which is expected to improve the on-state current or field-effect mobility of the transistor.

[0267] 19B, the conductor 503 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 503. Furthermore, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0268] Note that although the conductor 503 in the transistor 500 has a stacked structure of the conductor 503a and the conductor 503b, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0269] Insulator 522 and insulator 524 function as gate insulators.

[0270] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0271] The insulator 522 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 to the substrate and diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, the insulator 522 can suppress diffusion of impurities such as hydrogen into the transistor 500 and suppress generation of oxygen vacancies in the oxide 530. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0272] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 522 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0273] The insulator 522 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 522 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0274] The insulator 524 in contact with the oxide 530 can be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0275] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0276] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0277] The insulators 522 and 524 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 524 may be formed in an island shape overlapping the oxide 530a. In this case, the insulator 544 is configured to contact the side surface of the insulator 524 and the top surface of the insulator 522.

[0278] The conductor 542a and the conductor 542b are provided in contact with the top surface of the oxide 530b. The conductor 542a and the conductor 542b function as a source electrode and a drain electrode of the transistor 500, respectively.

[0279] As the conductor 542 (conductor 542a and conductor 542b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0280] Note that hydrogen contained in the oxide 530b and the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductors 542a and 542b, hydrogen contained in the oxide 530b and the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen may bond with nitrogen contained in the conductor 542a or the conductor 542b. In other words, hydrogen contained in the oxide 530b and the like may be absorbed by the conductor 542a or the conductor 542b.

[0281] Furthermore, it is preferable that no curved surface be formed between the side surface of the conductor 542 and the top surface of the conductor 542. The conductor 542 without such a curved surface can increase the cross-sectional area of ​​the conductor 542 in the cross section in the channel width direction. This can increase the conductivity of the conductor 542 and the on-state current of the transistor 500.

[0282] The insulator 571a is provided in contact with the top surface of the conductor 542a, and the insulator 571b is provided in contact with the top surface of the conductor 542b. The insulator 571 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing oxygen diffusion. For example, the insulator 571 preferably has a function of suppressing oxygen diffusion more than the insulator 580. The insulator 571 may be, for example, a nitride containing silicon, such as silicon nitride. The insulator 571 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 571 may be an insulator of a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 is preferable because hydrogen can be more effectively captured or fixed. This enables the manufacture of a highly reliable transistor 500 and a semiconductor device with favorable characteristics.

[0283] The insulator 544 is provided to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has the function of capturing and fixing hydrogen. In this case, the insulator 544 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 544 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0284] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulator 524 and the insulator 580 can be prevented from diffusing into the conductor 542. This can prevent the conductor 542 from being directly oxidized by the oxygen contained in the insulator 524 and the insulator 580, which increases the resistivity and reduces the on-state current.

[0285] The insulator 552 functions as part of the gate insulator. The insulator 552 is preferably a barrier insulating film against oxygen. Any of the insulators that can be used for the insulator 574 described above can be used as the insulator 552. The insulator 552 can be an insulator containing one or both of an oxide of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 contains at least oxygen and aluminum.

[0286] As shown in FIG. 19B, the insulator 552 is provided in contact with the top surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the top surface of the insulator 522. That is, the regions of the oxide 530a, the oxide 530b, and the insulator 524 that overlap with the conductor 560 are covered with the insulator 552 in the cross section in the channel width direction. This allows the insulator 552, which has oxygen barrier properties, to block oxygen from being released from the oxides 530a and 530b during heat treatment or the like. This reduces the formation of oxygen vacancies (Vo) in the oxides 530a and 530b. This reduces the oxygen vacancies (Vo) and V formed in the region 530bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be improved.

[0287] Conversely, even if the insulator 580, the insulator 550, or the like contains excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 530a and the oxide 530b. Therefore, the region 530bc can prevent the regions 530ba and 530bb from being excessively oxidized, which would cause a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0288] 19A , the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 544, the insulator 571, and the insulator 580. This reduces the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. This reduces the on-state current or field-effect mobility of the transistor 500.

[0289] The insulator 552, together with the insulator 554, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 552 preferably has a small thickness. The thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 552 only needs to have at least a region with the above-described thickness. The thickness of the insulator 552 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 552 only needs to have at least a region with a thickness thinner than the insulator 550.

[0290] To deposit the insulator 552 to a thin thickness as described above, it is preferable to use the ALD method. The ALD method alternately introduces a first source gas (also called a precursor, precursor, or metal precursor) and a second source gas (also called a reactant, reactant, oxidizer, or non-metal precursor) for the reaction into a chamber, and then repeats the introduction of these source gases to deposit the film. ALD methods include thermal ALD, in which the reaction between the precursor and the reactant is carried out using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses plasma-excited reactants. The PEALD method may be preferable because it utilizes plasma, which allows film deposition at lower temperatures.

[0291] The ALD method utilizes the self-regulating property of atoms and can deposit atoms one layer at a time, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, etc. Therefore, the insulator 552 can be formed with good coverage on the side surfaces of an opening formed in the insulator 580 or the like and with the thin film thickness described above.

[0292] Some precursors used in ALD contain carbon and other impurities. Therefore, films formed by ALD may contain more carbon and other impurities than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0293] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. The insulator 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 550 is an insulator containing at least oxygen and silicon.

[0294] As with the insulator 524, the insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 550 preferably has a lower limit of 1 nm or 0.5 nm and an upper limit of 15 nm or 20 nm. The above-mentioned lower and upper limits can be combined. For example, the thickness of the insulator 550 is preferably 0.5 nm or more and 20 nm or less, and more preferably 1 nm or more and 15 nm or less. In this case, the insulator 550 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0295] 19A and 19B show a configuration in which the insulator 550 is a single layer, but the present invention is not limited to this and the insulator 550 may have a laminated structure of two or more layers. For example, as shown in Fig. 20B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0296] As shown in FIG. 20B , when the insulator 550 has a two-layer stacked structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator that suppresses oxygen diffusion. This structure can suppress the diffusion of oxygen contained in the insulator 550a into the conductor 560. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 530. It can also suppress oxidation of the conductor 560 due to the oxygen contained in the insulator 550a. For example, the insulator 550a may be formed using a material that can be used for the insulator 550 described above, and the insulator 550b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b contains at least oxygen and hafnium. The thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned thickness in at least a portion.

[0297] When silicon oxide, silicon oxynitride, or the like is used for the insulator 550a, the insulator 550b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a layered structure of the insulators 550a and 550b, a layered structure that is thermally stable and has a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 550 to be increased.

[0298] The insulator 554 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 554. This can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. The insulator 554 can be any of the insulators that can be used for the insulator 576. For example, silicon nitride formed by a PEALD method can be used as the insulator 554. In this case, the insulator 554 contains at least nitrogen and silicon.

[0299] The insulator 554 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 550 from diffusing into the conductor 560.

[0300] The insulator 554, together with the insulator 552, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 554 preferably has a small thickness. The thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 554 only needs to have at least a region with the above-described thickness. The thickness of the insulator 554 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 554 only needs to have at least a region with a thickness thinner than the insulator 550.

[0301] The conductor 560 functions as a first gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed over the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. As shown in FIGS. 19A and 19B, the height of the top surface of the conductor 560 roughly coincides with the height of the top of the insulator 550. Note that although the conductor 560 is shown as having a two-layer structure of the conductor 560a and the conductor 560b in FIGS. 19A and 19B, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers other than the two-layer structure.

[0302] The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0303] Furthermore, since conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of conductor 560b caused by oxygen contained in insulator 550. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0304] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b can have a layered structure. Specifically, for example, the conductor 560b can have a layered structure of titanium or titanium nitride and the above conductive material.

[0305] Furthermore, in the transistor 500, the conductor 560 is formed in a self-aligned manner so as to fill an opening formed in the insulator 580 or the like. By forming the conductor 560 in this manner, the conductor 560 can be reliably placed in the region between the conductor 542a and the conductor 542b without alignment.

[0306] 19B , in the channel width direction of the transistor 500, the height of the bottom surface of the conductor 560 in a region where the conductor 560 does not overlap with the oxide 530b is preferably lower than the height of the bottom surface of the oxide 530b when the bottom surface of the insulator 522 is used as the reference. When the conductor 560, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can be easily applied to the entire channel formation region of the oxide 530b. Therefore, the on-state current of the transistor 500 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of conductor 560 and the height of the bottom surface of oxide 530b in the region where oxide 530a and oxide 530b do not overlap with conductor 560, relative to the bottom surface of insulator 522, is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and is preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0307] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are to be provided. The top surface of the insulator 580 may be planarized.

[0308] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 580 is preferably formed using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0309] The concentration of impurities such as water and hydrogen is preferably reduced in the insulator 580. For example, the insulator 580 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0310] The insulator 574 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. The insulator 574 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 574 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 574 contains at least oxygen and aluminum. By providing the insulator 574, which is in contact with the insulator 580 and has a function of capturing impurities such as hydrogen, in the region between the insulators 512 and 581, the insulator 574 can capture impurities such as hydrogen contained in the insulator 580 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 574 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 500 and semiconductor device with excellent characteristics.

[0311] The insulator 576 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is disposed over the insulator 574. The insulator 576 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 576 may be formed using silicon nitride deposited by a sputtering method. A high-density silicon nitride film can be formed by depositing the insulator 576 by a sputtering method. Alternatively, the insulator 576 may be formed by stacking a silicon nitride film deposited by a PEALD method or a CVD method on the silicon nitride film deposited by a sputtering method.

[0312] One of the first and second terminals of the transistor 500 is electrically connected to a conductor 540a that functions as a plug, and the other of the first and second terminals of the transistor 500 is electrically connected to a conductor 540b. Note that the conductors 540a, 540b, and the like may function as wiring for electrically connecting to an upper light-emitting device 150 or the like. In the case of the display device 100 of FIG. 17, the conductors 540a, 540b, and the like may also function as wiring for electrically connecting to a transistor 300 or the like. Note that in this specification and the like, the conductors 540a and 540b will be collectively referred to as conductors 540.

[0313] For example, conductor 540a is provided in a region overlapping with conductor 542a. Specifically, in the region overlapping with conductor 542a, openings are formed in insulators 571a, 544, 580, 574, 576, and 581 shown in FIG. 19A , and conductor 540a is provided inside the openings. For example, conductor 540b is provided in a region overlapping with conductor 542b. Specifically, in the region overlapping with conductor 542b, openings are formed in insulators 571b, 544, 580, 574, 576, and 581 shown in FIG. 19A , and conductor 540b is provided inside the openings.

[0314] 19A, an insulator 541a may be provided as an insulator having a barrier property against impurities between the conductor 540a and a side surface of the opening in a region overlapping with the conductor 542a. Similarly, an insulator 541b may be provided as an insulator having a barrier property against impurities between the conductor 540b and a side surface of the opening in a region overlapping with the conductor 542b. Note that in this specification and the like, the insulators 541a and 541b are collectively referred to as the insulator 541.

[0315] The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0316] Furthermore, when the conductor 540 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the insulators 574, 576, 581, 580, 544, and the first conductor disposed near the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 576 from being mixed into the oxide 530 through the conductors 540a and 540b.

[0317] The insulators 541a and 541b may be a barrier insulating film that can be used for the insulator 544, etc. For example, the insulators 541a and 541b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 541a and 541b are provided in contact with the insulators 574, 576, and 571, and thus can prevent impurities such as water and hydrogen contained in the insulator 580 from entering the oxide 530 through the conductors 540a and 540b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0318] When insulators 541a and 541b are formed into a layered structure as shown in FIG. 19A, it is preferable that the first insulator in contact with the inner wall of an opening such as insulator 580 and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0319] For example, aluminum oxide formed by the ALD method can be used as the first insulator, and silicon nitride formed by the PEALD method can be used as the second insulator. With this structure, oxidation of the conductor 540 can be suppressed and hydrogen contamination of the conductor 540 can be reduced.

[0320] Although the transistor 500 has a structure in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are stacked, the present invention is not limited to this. For example, the insulator 541 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, the transistor 500 has a structure in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, but the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or a stacked structure of three or more layers.

[0321] Note that the structure of the transistor included in the semiconductor device of one embodiment of the present invention is not limited to the structure of the transistor 500 illustrated in Figures 19A and 19B. The structure of the transistor included in the semiconductor device of one embodiment of the present invention may be changed depending on the situation.

[0322] Above the transistor 500, an insulator 111 is provided.

[0323] The insulator 111 is preferably an insulator that has a function of suppressing diffusion of oxygen and impurities such as water and hydrogen, and examples thereof include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulator 111. Furthermore, for example, aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen, is preferably used for the insulator 111.

[0324] A highly flat film is preferably used as the insulator 111. In this case, the insulator 111 can be made of an organic material such as an acrylic resin or polyimide.

[0325] Above the insulator 111, light emitting devices 150a to 150c are provided.

[0326] Here, light emitting devices 150a to 150c will be described.

[0327] Conductors 121a to 121c functioning as pixel electrodes of the light-emitting devices 150a to 150c, respectively, are provided on the insulator 111. Note that in FIG. 17, there are regions on the insulator 111 where the conductors 121a to 121c are not provided.

[0328] The conductors 121a to 121c can be formed, for example, by forming a conductive film over the insulator 111 and performing a patterning process, an etching process, or the like on the conductive film.

[0329] The conductors 121a to 121c function as anodes of the light emitting devices 150a, 150b, and 150c included in the display device 100, respectively, as an example.

[0330] The conductors 121a to 121c can be made of, for example, indium tin oxide (sometimes referred to as ITO).

[0331] Furthermore, each of the conductors 121a to 121c may have a stacked structure of two or more layers instead of a single layer. For example, a conductor with high reflectivity to visible light may be used as the first-layer conductor, and a conductor with high light transmittance may be used as the top-layer conductor. Examples of conductors with high reflectivity to visible light include silver, aluminum, and an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film). Examples of conductors with high light transmittance include the above-mentioned indium tin oxide. Examples of the conductors 121a to 121c include a stacked film of aluminum sandwiched between a pair of titanium films (a stacked film of Ti, Al, and Ti in this order), a stacked film of silver sandwiched between a pair of indium tin oxide films (a stacked film of ITO, Ag, and ITO in this order), etc.

[0332] The insulator 112 is provided over the insulator 111, the conductor 121a, the conductor 121b, and the conductor 121c. Note that in Figure 17, there are regions over the conductor 121a, the conductor 121b, and the conductor 121c where the insulator 112 is not provided. For example, an insulating film to be the insulator 112 is formed over the insulator 111 and the conductors 121a to 121c, and the insulating film is patterned by photolithography or the like to form openings that reach the conductors 121a to 121c in regions of the insulating film that overlap with the conductors 121a to 121c. This allows the insulator 112 to be provided.

[0333] For example, an insulating inorganic film can be used as the insulator 112. Examples of the insulating inorganic film that can be used include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride.

[0334] An organic film having an insulating layer may also be used as the insulator 112. Examples of organic films that can be used for the insulator 112 include polyimide.

[0335] Furthermore, the insulator 112 may have a multi-layer structure. Specifically, for example, the insulator 112 may have a multi-layer structure in which the first layer is the organic film described above and the second layer is the inorganic film described above.

[0336] An EL layer 141a is provided over the insulator 112 and the conductor 121a. An EL layer 141b is provided over the insulator 112 and the conductor 121b. An EL layer 141c is provided over the insulator 112 and the conductor 121c. In FIG. 17, there is a region on the insulator 112 where the EL layers 141a to 141c are not provided.

[0337] Preferably, the EL layers 141a to 141c each have a light-emitting layer that emits light of a different color. For example, the EL layer 141a may have a light-emitting layer that emits blue (B) light, the EL layer 141b may have a light-emitting layer that emits green (G), and the EL layer 141c may have a light-emitting layer that emits red (R). In this way, the display device 100 may have a structure (SBS structure) in which different light-emitting layers for each color are formed on multiple pixel electrodes (conductors 121a to 121c).

[0338] The combination of colors emitted by the light-emitting layers included in each of the EL layers 141a to 141c is not limited to the above, and may also be colors such as cyan, magenta, yellow, etc. Although the above example shows three colors, the number of colors emitted by the light-emitting device 150 included in the display device 100 may be two colors, or four or more colors.

[0339] The EL layer 141a, the EL layer 141b, and the EL layer 141c may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0340] In addition, the EL layer 141a, the EL layer 141b, and the EL layer 141c can be formed by a method such as a vapor deposition method (vacuum vapor deposition method, etc.), a coating method (dip coating method, die coating method, bar coating method, spin coating method, spray coating method, etc.), a printing method (inkjet method, screen (stencil printing) method, offset (lithographic printing) method, flexography (relief printing) method, gravure method, microcontact method, etc.).

[0341] When applying the above-mentioned coating method, printing method, or other film formation method, it is possible to use high molecular weight compounds (oligomers, dendrimers, polymers, etc.), medium molecular weight compounds (compounds in the intermediate range between low molecular weight and high molecular weight: molecular weight 400 to 4000), inorganic compounds (quantum dot materials, etc.), etc. As quantum dot materials, colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, etc. can be used.

[0342] For example, light emitting devices 150a to 150c in FIG. 17 can be configured with multiple layers such as layer 4420, light emitting layer 4411, and layer 4430, as in light emitting device 150 shown in FIG. 21A.

[0343] The layer 4420 can have, for example, a layer containing a substance with a high electron injecting property (electron injecting layer) and a layer containing a substance with a high electron transporting property (electron transporting layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with a high hole injecting property (hole injecting layer) and a layer containing a substance with a high hole transporting property (hole transporting layer).

[0344] A structure having layer 4420, light-emitting layer 4411, and layer 4430 provided between a pair of electrodes (conductor 121 and conductor 122 described later) can function as a single light-emitting unit, and in this specification, the structure of Figure 21A is called a single structure.

[0345] Note that a configuration in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 as shown in FIG. 21B is also a variation of the single structure.

[0346] A laminate having multiple layers such as layer 4420, light-emitting layer 4411, and layer 4430 may be referred to as a light-emitting unit. Multiple light-emitting units may be connected in series via an intermediate layer (charge generation layer). Specifically, as shown in FIG. 21C , multiple light-emitting units, such as light-emitting unit 4400a and light-emitting unit 4400b, may be connected in series via an intermediate layer (charge generation layer) 4440. In this specification, such a structure is referred to as a tandem structure. In this specification, the tandem structure may also be referred to as a stack structure. By forming a light-emitting device in a tandem structure, a light-emitting device capable of emitting light with high brightness can be obtained. By forming a light-emitting device in a tandem structure, improvements in the light-emitting efficiency and lifespan of the light-emitting device can be expected. When the light-emitting device 150 of the display device 100 of FIG. 17 has a tandem structure, the EL layer 141 can be configured to include, for example, layer 4420, light-emitting layer 4411, and layer 4430 of light-emitting unit 4400a, intermediate layer 4440, and layer 4420, light-emitting layer 4412, and layer 4430 of light-emitting unit 4400b.

[0347] Furthermore, when comparing the above-described single structure and tandem structure with the previously described SBS structure, power consumption decreases in the order of the SBS structure, the tandem structure, and the single structure. If you want to keep power consumption low, the SBS structure is preferable. On the other hand, the single structure and tandem structure are preferable because their manufacturing processes are easier than those of the SBS structure, allowing for lower manufacturing costs or higher manufacturing yields.

[0348] The light-emitting device 150 can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 141. Furthermore, the color purity can be further improved by providing the light-emitting device 150 with a microcavity structure.

[0349] A light-emitting device that emits white light preferably has a structure in which the light-emitting layer contains two or more light-emitting materials. To obtain white light emission, it is sufficient to select two or more light-emitting materials whose emission colors are complementary to each other.

[0350] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0351] 17, a gap is provided between two EL layers between light-emitting devices of different colors. In this manner, it is preferable that the EL layers 141a, 141b, and 141c are provided so as not to be in contact with each other. This makes it possible to effectively prevent current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This allows for increased contrast and a display device with high display quality to be realized.

[0352] The EL layers 141a to 141c can be formed by a method using photolithography. For example, an EL film to become the EL layers 141a to 141c is formed on the insulator 111 and the conductor 121, and then the EL film is patterned by photolithography to form the EL layers 141a to 141c. Alternatively, the conductor 122 may be formed on the EL film, and then the EL film, including the conductor 122, may be patterned by photolithography to form the EL layers 141a to 141c. In this case, the EL layers 141a to 141c have the same structure. Therefore, when it is desired to perform color display with the display device 100 formed using this formation method, the light-emitting devices 150a to 150c, which include the EL layers 141a to 141c, respectively, can be configured as light-emitting devices that emit white light, and the display device 100 can be configured to emit light from the light-emitting devices to the outside through a colored layer (color filter).

[0353] The EL layers 141a to 141c are formed by first depositing an EL film that will become the EL layer 141a on the insulator 111 and the conductor 121, and then forming the EL layer 141a by photolithography. The EL layers 141b and 141c are then formed in predetermined regions using a similar procedure. By using this method, the EL layers 141a to 141c can each have a different configuration, allowing the display device 100 to have an SBS structure.

[0354] Furthermore, the above-described method can shorten the distance between pixels. This allows the number of pixels included in the display unit to be increased, thereby increasing the resolution of the display device. For example, the distance between pixels is preferably 5 μm or less, and more preferably 1 μm or less.

[0355] The EL layers 141a to 141c may be formed by a method other than photolithography, such as nanoimprinting or lift-off. Alternatively, island-shaped thin films may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0356] A conductor 122 is provided on the insulator 112, the EL layer 141a, the EL layer 141b, and the EL layer 141c.

[0357] The conductor 122 functions as, for example, a common electrode for each of the light-emitting devices 150a to 150c. In order to emit light from the light-emitting device 150 upward from the display device 100, the conductor 122 preferably includes a light-transmitting conductive material.

[0358] The conductor 122 is preferably a material that is highly conductive and has light-transmitting and light-reflecting properties (sometimes called a semi-transparent / semi-reflective electrode). For example, an alloy of silver and magnesium, or indium tin oxide can be used as the conductor 122.

[0359] The insulator 113 functions as, for example, a passivation film that protects the light-emitting devices 150a, 150b, and 150c. Therefore, the insulator 113 is preferably made of a material that prevents the intrusion of water and the like. For example, the insulator 113 may be made of a material that can be used for the insulator 111. Specifically, aluminum oxide, silicon nitride, silicon nitride oxide, or the like may be used.

[0360] A resin layer 161 is provided on the insulator 113. Furthermore, a substrate 102 is provided on the resin layer 161.

[0361] For example, a light-transmitting substrate is preferably used as the substrate 102. By using a light-transmitting substrate for the substrate 102, light emitted from the light-emitting device 150a, the light-emitting device 150b, and the light-emitting device 150c can be emitted upward from the substrate 102.

[0362] As described above, by configuring the display device 100 of FIG. 17, it is possible to realize a display device having a resolution of preferably 1000 ppi or more, more preferably 3000 ppi or more, and even more preferably 5000 ppi or more.

[0363] <Example of sealing structure for display device> Next, a sealing structure for the light emitting devices 150a to 150c that can be applied to the display device 100 of FIG. 17 will be described.

[0364] Fig. 22A is a cross-sectional view showing an example of a sealing structure applicable to the display device 100 of Fig. 17. Specifically, Fig. 22A illustrates an end portion of the pixel array ALP of the display device 100 of Fig. 17 and elements provided around the end portion. Fig. 22A also illustrates an excerpt of only a portion of the pixel layer PXAL of the display device 100. Specifically, Fig. 22A illustrates the insulator 111, a plug connected to the transistor 500, and insulators, conductors, light-emitting devices 150a to 150c, and the like, positioned above the insulator 111.

[0365] 22A, an adhesive layer 164 is provided at or around an end of the pixel array ALP. Specifically, the display device 100 is configured such that the insulator 112 and the substrate 102 are bonded together with the adhesive layer 164 interposed therebetween.

[0366] The adhesive layer 164 is preferably made of a material that suppresses the permeation of impurities such as moisture. By using such a material for the adhesive layer 164, the reliability of the display device 100 can be improved.

[0367] A structure in which the insulator 112 and the substrate 102 are bonded together via the resin layer 161 using the adhesive layer 164 is sometimes called a solid sealing structure. In addition, in the solid sealing structure, if the resin layer 161 has the function of bonding the insulator 112 and the substrate 102 together, similar to the adhesive layer 164, the adhesive layer 164 does not necessarily have to be provided.

[0368] On the other hand, a structure in which the insulator 112 and the substrate 102 are bonded together using the adhesive layer 164 and filled with an inert gas instead of the resin layer 161 is sometimes called a hollow sealing structure (not shown). Examples of the inert gas include nitrogen and argon.

[0369] 22A, two or more adhesive layers may be stacked. For example, as shown in FIG. 22B, an adhesive layer 165 may be further provided inside adhesive layer 164 (between adhesive layer 164 and resin layer 161). By stacking two or more adhesive layers, the permeation of impurities such as moisture can be further suppressed, thereby further improving the reliability of display device 100.

[0370] A desiccant may be mixed into the adhesive layer 165. This allows the desiccant to adsorb moisture contained in the adhesive layer 164, the resin layer 161 formed inside the adhesive layer 165, the insulator, the conductor, the EL layer, and the like, thereby improving the reliability of the display device 100.

[0371] Furthermore, although the display device 100 in FIG. 22B has a solid sealing structure, it may also have a hollow sealing structure.

[0372] 22A and 22B, an inert liquid may be filled in place of the resin layer 161. Examples of the inert liquid include a fluorine-based inert liquid.

[0373] <Modifications of the display device> However, one embodiment of the present invention is not limited to the above-described structure, and the above-described structure can be modified as appropriate depending on the situation. Modifications of the display device 100 in FIG. 17 will be described below with reference to FIGS. 23A to 24D. Note that FIGS. 23A to 24D illustrate only a portion of the pixel layer PXAL of the display device 100. Specifically, each of FIGS. 23A to 24D illustrates the insulator 111, a plug connected to the transistor 500, insulators positioned above the insulator 111, conductors, light-emitting devices 150a to 150c, and the like.

[0374] For example, the display device 100 may be configured so that the light-emitting device 150 emits light of two colors. Alternatively, the display device 100 may be configured so that the light-emitting device 150 emits light of four or more colors (not shown).

[0375] 23A, the display device 100 may have an EL layer 142 formed on the EL layers 141a to 141c and on the insulator 112. Specifically, in the case where the EL layers 141a to 141c in FIG. 23A include the layer 4430 and the light-emitting layer 4411 shown in FIG. 21A, the EL layer 142 may include the layer 4420 shown in FIG. 21A. In this case, the layer 4420 included in the EL layer 142 functions as a common layer for the light-emitting devices 150a to 150c. Similarly, for example, in FIG. 23B, if the EL layers 141a to 141c are configured to include the layer 4430 and the light-emitting layer 4411, the EL layer 142 can be configured to include the layer 4420, so that the layer 4420 included in the EL layer 142 functions as a common layer in each of the light-emitting devices 150a to 150c. Furthermore, for example, in FIG. 23C, when the EL layers 141a to 141c are configured to include the layer 4430, the light-emitting layer 4412, and the layer 4420 of the light-emitting unit 4400b shown in FIG. 21A, the intermediate layer 4440, and the layer 4430 and the light-emitting layer 4411 of the light-emitting unit 4400a, the EL layer 142 is configured to include the layer 4420 of the light-emitting unit 4400a, so that the layer 4420 of the light-emitting unit 4400a included in the EL layer 142 functions as a common layer in each of the light-emitting devices 150a to 150c.

[0376] Furthermore, for example, as described above, the configuration of the display device 100 may be such that the insulator 112 has a multi-layer structure in which the first layer is an insulator made of an organic material and the second layer is an insulator made of an inorganic material. Fig. 23B shows, as an example, a cross-sectional view of a portion of the display device 100 in which the insulator 112 has a multi-layer structure including the insulators 112a and 112b, in which the insulator 112a is an insulator made of an organic material and the insulator 112b is an insulator made of an inorganic material.

[0377] The organic material may be, for example, polyimide, and the inorganic material may be a material that can be used for the insulator 112 provided in the display device 100 of FIG.

[0378] Furthermore, for example, in the configuration of display device 100, insulator 113 may have a stacked structure of two or more layers instead of a single layer. Insulator 113 may have a three-layer stacked structure, for example, in which an inorganic insulator is used as a first layer, an organic insulator is used as a second layer, and an inorganic insulator is used as a third layer. Fig. 23C shows a cross-sectional view of a portion of display device 100 in which insulator 113 has a multi-layer structure including insulators 113a, 113b, and 113c, in which insulator 113a is an inorganic insulator, insulator 113b is an organic insulator, and insulator 113c is an inorganic insulator.

[0379] Furthermore, for example, the display device 100 may be configured such that each of the EL layers 141a to 141c has a microcavity structure (a microresonator structure). The microcavity structure refers to a structure in which, for example, a light-transmitting and light-reflective conductive material is used for the conductor 122 that is the upper electrode (common electrode), a light-reflective conductive material is used for the conductor 121 that is the lower electrode (pixel electrode), and the distance between the lower surface of the light-emitting layer and the upper surface of the lower electrode, that is, the film thickness of the layer 4430 in FIG. 21A, is set to a thickness corresponding to the wavelength of the color of light emitted by the light-emitting layer included in the EL layer 141.

[0380] For example, light reflected by the lower electrode and returning (reflected light) significantly interferes with light directly incident on the upper electrode from the light-emitting layer (incident light). Therefore, it is preferable to adjust the optical distance between the lower electrode and the light-emitting layer to (2n-1)λ / 4 (where n is a natural number greater than or equal to 1, and λ is the wavelength of the emitted light to be amplified). By adjusting this optical distance, the phases of the reflected light and incident light, each of which has a wavelength λ, can be matched, thereby further amplifying the light emitted from the light-emitting layer. On the other hand, if the reflected light and incident light have a wavelength other than λ, they will no longer match in phase, resulting in attenuation without resonance.

[0381] In the above configuration, the EL layer may have a structure having multiple light-emitting layers or a structure having a single light-emitting layer. Furthermore, for example, in combination with the above-described tandem light-emitting device configuration, a single light-emitting device may have multiple EL layers sandwiching a charge-generating layer therebetween, and each EL layer may have a single or multiple light-emitting layers.

[0382] The microcavity structure makes it possible to increase the light emission intensity of a specific wavelength in the front direction, thereby reducing power consumption. In particular, in the case of XR devices such as VR and AR, light from the light-emitting device is often incident on the eyes of the user wearing the device in the front direction, so it can be said that providing a microcavity structure in the display device of XR devices is preferable. In addition, in the case of a display device that displays images using four sub-pixels of red, yellow, green, and blue, in addition to the brightness improvement effect of yellow emission, the ability to apply a microcavity structure tailored to the wavelength of each color to all sub-pixels can result in a display device with good characteristics.

[0383] FIG. 24A shows a cross-sectional view of a portion of the display device 100 having a microcavity structure, as an example. When the light-emitting device 150a has a light-emitting layer that emits blue (B), the light-emitting device 150b has a light-emitting layer that emits green (G), and the light-emitting device 150c has a light-emitting layer that emits red (R), the thicknesses of the EL layers 141a, 141b, and 141c are preferably increased in this order, as shown in FIG. 24A. Specifically, the thicknesses of the layers 4430 included in the EL layers 141a, 141b, and 141c may be determined according to the color of the light emitted by each of the light-emitting layers. In this case, the layer 4430 included in the EL layer 141a is the thinnest, and the layer 4430 included in the EL layer 141c is the thickest.

[0384] 24B shows, as an example, a configuration in which colored layers 162a, 162b, and 162c are provided between the resin layer 161 and the substrate 102. The colored layers 162a to 162c can be formed on the substrate 102. In addition, when the light-emitting device 150a has a light-emitting layer that emits blue (B), the light-emitting device 150b has a light-emitting layer that emits green (G), and the light-emitting device 150c has a light-emitting layer that emits red (R), the colored layer 162a is blue, the colored layer 162b is green, and the colored layer 162c is red.

[0385] 24B can be constructed by bonding a substrate 102 provided with colored layers 162a to 162c to a substrate 310 on which light-emitting devices 150a to 150c have been formed, via a resin layer 161. The bonding is preferably performed so that the light-emitting device 150a and the colored layer 162a overlap, the light-emitting device 150b and the colored layer 162b overlap, and the light-emitting device 150c and the colored layer 162c overlap. By providing the colored layers 162a to 162c in the display device 100, for example, light emitted by the light-emitting device 150b does not exit above the substrate 102 via the colored layer 162a or the colored layer 162c, but exits above the substrate 102 via the colored layer 162b. In other words, since it is possible to block light from the light-emitting device 150 of the display device 100 in an oblique direction (the direction of the elevation angle when the top surface of the substrate 102 is considered to be a horizontal plane), it is possible to reduce the dependency of the display device 100 on the viewing angle, and it is possible to prevent a decrease in the display quality of the image displayed on the display device 100 when viewed from an oblique angle.

[0386] The colored layers 162a to 162c formed on the substrate 102 may be covered with a resin called an overcoat layer. Specifically, the display device 100 may be stacked in the order of the resin layer 161, the overcoat layer, the colored layers 162a to 162c, and the substrate 102 (not shown). Examples of resins used for the overcoat layer include thermosetting materials that are translucent and based on acrylic resin or epoxy resin.

[0387] Furthermore, for example, a black matrix (not shown) may be included in addition to the colored layers as part of the configuration of the display device 100. By providing a black matrix between the colored layers 162a and 162b, between the colored layers 162b and 162c, and between the colored layers 162c and 162a, it is possible to more effectively block light from the light-emitting device 150 of the display device 100 in an oblique direction (the direction of the elevation angle when the top surface of the substrate 102 is taken as a horizontal plane), thereby more effectively preventing a decrease in the display quality of an image displayed on the display device 100 when the image is viewed obliquely.

[0388] 24B, when the display device has a colored layer, the light-emitting devices 150a to 150c included in the display device may all be light-emitting devices that emit white light (not shown). The light-emitting devices may have, for example, a single structure or a tandem structure.

[0389] Furthermore, for example, the display device 100 may be configured without the insulator 112 formed over the conductors 121a to 121c. FIG. 24C shows a configuration example in which the insulator 112 is not provided in the display device 100 of FIG. 17 or the like. Furthermore, for example, the display device 100 may be configured such that the conductors 121a to 121c are embedded in the insulator 111. FIG. 24D shows a configuration example in which the conductors 121a to 121c are embedded in the insulator 111. Note that, for example, this configuration may be achieved by forming openings in the insulator 111 for embedding the conductors 121a to 121c, then depositing conductive films to become the conductors 121a to 121c, and then performing chemical mechanical polishing (CMP) until the insulator 111 is exposed.

[0390] Furthermore, in the above-described configuration of the display device 100, the conductors 121a to 121c are used as anodes and the conductor 122 is used as a cathode, but the display device 100 may be configured so that the conductors 121a to 121c are used as cathodes and the conductor 122 is used as an anode. That is, in the manufacturing process described above, the stacking order of the hole injection layer, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer included in the EL layers 141a to 141c and the EL layer 142 may be reversed.

[0391] The insulators, conductors, semiconductors, and the like disclosed in this specification can be formed by PVD (Physical Vapor Deposition) or CVD. Examples of PVD include sputtering, resistance heating evaporation, electron beam evaporation, and PLD. Examples of CVD include plasma CVD and thermal CVD. Examples of thermal CVD include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD.

[0392] The thermal CVD method is a film formation method that does not use plasma, and therefore has the advantage that defects caused by plasma damage are not generated.

[0393] In the thermal CVD method, a source gas and an oxidant are simultaneously fed into a chamber, the chamber is kept at atmospheric pressure or reduced pressure, and the reaction occurs near or on a substrate, resulting in deposition on the substrate, thereby forming a film.

[0394] Alternatively, the ALD method may be used to deposit a film by sequentially introducing source gases into a chamber under atmospheric or reduced pressure and repeating this gas introduction sequence. For example, two or more source gases may be sequentially supplied to the chamber by switching between switching valves (also called high-speed valves). To prevent mixing of the multiple source gases, an inert gas (e.g., argon or nitrogen) may be introduced simultaneously with or after the first source gas, followed by the second source gas. When an inert gas is introduced simultaneously, the inert gas acts as a carrier gas, and may also be introduced simultaneously with the introduction of the second source gas. Alternatively, instead of introducing an inert gas, the first source gas may be evacuated by vacuum evacuation before the second source gas is introduced. The first source gas adsorbs onto the substrate surface to form a first thin layer, which then reacts with the second source gas introduced later, forming a thin film. Repeating this gas introduction sequence multiple times until the desired thickness is achieved allows for the formation of a thin film with excellent step coverage. The thickness of the thin film can be adjusted by changing the number of times the gas introduction sequence is repeated, allowing for precise film thickness adjustment, making this method suitable for fabricating fine FETs.

[0395] Thermal CVD methods such as MOCVD and ALD can form various films such as metal films, semiconductor films, and inorganic insulating films disclosed in the embodiments described above. For example, when forming an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. Furthermore, the combinations are not limited to these, and triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

[0396] For example, when forming a hafnium oxide film using a film deposition system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide or hafnium amide such as tetrakisdimethylamidohafnium (TDMAH, Hf[N(CH3)2]4)), and ozone (O3) as an oxidizer. Other materials include tetrakis(ethylmethylamido)hafnium.

[0397] For example, when forming an aluminum oxide film using a film formation system that uses ALD, two types of gases are used: a source gas made by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA, Al(CH3)3)), and H2O as an oxidizer. Other materials include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0398] For example, when forming a silicon oxide film using a film formation apparatus that uses ALD, hexachlorodisilane is adsorbed onto the surface to be filmed, and radicals of oxidizing gas (O2, dinitrogen monoxide) are supplied to react with the adsorbed material.

[0399] For example, when forming a tungsten film using an ALD deposition system, WF6 gas and B2H6 gas are introduced in sequence and repeatedly to form an initial tungsten film, and then WF6 gas and H2 gas are introduced in sequence and repeatedly to form the tungsten film. Note that SiH4 gas may be used instead of B2H6 gas.

[0400] For example, when forming an In-Ga-Zn-O film as an oxide semiconductor film using an ALD film formation apparatus, a precursor (generally referred to as a precursor, metal precursor, etc.) and an oxidant (generally referred to as a reactant, non-metal precursor, etc.) are sequentially and repeatedly introduced to form the film. Specifically, for example, an In-O layer is formed by introducing precursor gas In(CH3)3 and oxidant gas O3, followed by introducing precursor gas Ga(CH3)3 and oxidant gas O3 to form a GaO layer, and then introducing precursor gas Zn(CH3)2 and oxidant gas O3 to form a ZnO layer. Note that the order of these layers is not limited to this example. Mixed oxide layers such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer may also be formed using these gases. Note that, instead of O3 gas, HO gas obtained by bubbling water with an inert gas such as Ar may be used, but it is preferable to use O3 gas, which does not contain H. In addition, In(C2H5)3 gas may be used instead of In(CH3)3 gas, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas, and Zn(CH3)2 gas may be used instead of Ga(CH3)3 gas.

[0401] The screen ratio (aspect ratio) of the display portion of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 3:4, 16:9, and 16:10.

[0402] The shape of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can have various shapes such as a rectangular shape, a polygonal shape (for example, an octagonal shape), a circular shape, and an elliptical shape.

[0403] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0404] (Fourth embodiment) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0405] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0406] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 25A. Fig. 25A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0407] As shown in FIG. 25A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0408] The structure within the bold frame in Figure 25A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0409] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 25B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." (The horizontal axis represents 2θ [deg.], and the vertical axis represents intensity in arbitrary units (au).) The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 25B may be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 25B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 25B is 500 nm.

[0410] As shown in Figure 25B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 25B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0411] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 25C. Figure 25C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 25C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0412] As shown in FIG. 25C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0413] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from those shown in FIG. 25A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0414] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0415] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0416] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0417] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0418] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0419] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0420] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0421] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0422] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the formation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0423] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0424] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0425] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0426] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0427] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0428] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0429] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0430] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0431] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0432] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0433] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0434] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0435] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0436] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0437] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0438] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0439] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0440] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0441] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17atoms / cm 3 The following applies.

[0442] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0443] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0444] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0445] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0446] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0447] (Embodiment 5) In this embodiment, an example of a head-mounted display to which a display device is applied will be described as an example of an electronic device of one embodiment of the present invention.

[0448] 26A and 26B show the appearance of the head mounted display 8300.

[0449] The head mounted display 8300 includes a housing 8301, a display portion 8302, operation buttons 8303, and a band-shaped fixture 8304.

[0450] The operation button 8303 has a function of a power button, etc. The head mounted display 8300 may have a button in addition to the operation button 8303.

[0451] 26C, a lens 8305 may be provided between the display unit 8302 and the user's eyes. The lens 8305 allows the user to view an enlarged image of the display unit 8302, enhancing the sense of realism. In this case, as shown in FIG. 26C, a dial 8306 may be provided to change the position of the lens for diopter adjustment.

[0452] The display device of one embodiment of the present invention can be applied to the display portion 8302. The display device of one embodiment of the present invention has extremely high resolution; therefore, even when an image is enlarged using the lens 8305 as in FIG. 26C , pixels are not visible to a user, and more realistic images can be displayed.

[0453] 26A to 26C show an example in which one display unit 8302 is included. With such a configuration, the number of components can be reduced.

[0454] The display portion 8302 can display two images, one for the right eye and one for the left eye, side by side in two regions, left and right, respectively, thereby enabling display of a stereoscopic image using binocular parallax.

[0455] Alternatively, a single image that can be viewed with both eyes may be displayed across the entire area of ​​the display unit 8302. This allows a panoramic image to be displayed across both ends of the field of view, thereby enhancing the sense of reality.

[0456] Here, the head mounted display 8300 preferably has a mechanism for changing the curvature of the display portion 8302 to an appropriate value depending on the size of the user's head, the position of the user's eyes, etc. For example, the user may adjust the curvature of the display portion 8302 by operating a dial 8307 for adjusting the curvature of the display portion 8302. Alternatively, the housing 8301 may be provided with a sensor (for example, a camera, a contact sensor, a non-contact sensor, etc.) that detects the size of the user's head, the position of the user's eyes, etc., and the head mounted display 8300 may have a mechanism for adjusting the curvature of the display portion 8302 based on detection data from the sensor.

[0457] When the lens 8305 is used, it is preferable to provide a mechanism for adjusting the position and angle of the lens 8305 in synchronization with the curvature of the display portion 8302. Alternatively, the dial 8306 may have a function for adjusting the angle of the lens.

[0458] 26E and 26F show an example including a driver 8308 that controls the curvature of the display unit 8302. The driver 8308 is fixed to at least a part of the display unit 8302. The driver 8308 has a function of deforming the display unit 8302 by deforming or moving the part fixed to the display unit 8302.

[0459] 26E is a schematic diagram showing a case where a user 8310 with a relatively large head size is wearing housing 8301. At this time, the shape of display unit 8302 is adjusted by drive unit 8308 so that the curvature is relatively small (the radius of curvature is large).

[0460] On the other hand, Fig. 26F shows a case where a user 8311, whose head is smaller than that of the user 8310, is wearing the housing 8301. Furthermore, the distance between the eyes of the user 8311 is narrower than that of the user 8310. In this case, the shape of the display unit 8302 is adjusted by the driving unit 8308 so that the curvature of the display unit 8302 is large (the radius of curvature is small). In Fig. 26F, the position and shape of the display unit 8302 in Fig. 26E are indicated by dashed lines.

[0461] In this way, the head mounted display 8300 has a mechanism for adjusting the curvature of the display portion 8302, and can provide an optimal display to various users, regardless of age or gender.

[0462] Furthermore, by changing the curvature of the display portion 8302 depending on the content displayed on the display portion 8302, a high sense of realism can be given to the user. For example, a trembling motion can be expressed by vibrating the curvature of the display portion 8302. In this way, various effects can be produced according to the scene in the content, and a new experience can be provided to the user. Furthermore, by linking the display portion 8302 with a vibration module provided in the housing 8301, a more realistic display can be achieved.

[0463] Note that the head mounted display 8300 may have two display units 8302 as shown in FIG. 26D.

[0464] By having two display units 8302, the user can view one display unit per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax. Furthermore, the display unit 8302 is curved in an arc shape roughly centered on the user's eye. This allows the distance from the user's eye to the display surface of the display unit to be constant, allowing the user to view more natural images. Furthermore, even if the brightness and chromaticity of light from the display unit change depending on the viewing angle, this effect can be substantially ignored because the user's eyes are positioned in the normal direction to the display surface of the display unit, allowing for the display of more realistic images.

[0465] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0466] (Sixth embodiment) In this embodiment, a display module that can be manufactured using the display device of one embodiment of the present invention will be described.

[0467] A display module 6000 shown in FIG. 27A has a display device 6006 connected by an FPC 6005, a frame 6009, a printed circuit board 6010, and a battery 6011 between an upper cover 6001 and a lower cover 6002.

[0468] For example, a display device manufactured using one embodiment of the present invention can be used as the display device 6006. The display device 6006 can provide a display module with extremely low power consumption.

[0469] The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be changed appropriately to match the size of the display device 6006.

[0470] The display device 6006 may have a function as a touch panel.

[0471] The frame 6009 may have a function of protecting the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, and the like.

[0472] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, a battery control circuit, and the like.

[0473] FIG. 27B is a cross-sectional schematic diagram of a display module 6000 equipped with an optical touch sensor.

[0474] The display module 6000 has a light emitting section 6015 and a light receiving section 6016 provided on a printed circuit board 6010. The display module 6000 also has a pair of light guiding sections (light guiding section 6017a, light guiding section 6017b) in an area surrounded by an upper cover 6001 and a lower cover 6002.

[0475] The display device 6006 is provided so as to overlap the printed circuit board 6010 and the battery 6011 with the frame 6009 interposed therebetween. The display device 6006 and the frame 6009 are fixed to the light guide portions 6017a and 6017b.

[0476] Light 6018 emitted from light-emitting unit 6015 passes through light-guiding unit 6017a, passes through the upper part of display device 6006, and reaches light-receiving unit 6016 through light-guiding unit 6017b. When light 6018 is blocked by a detectable object such as a finger or a stylus, a touch operation can be detected.

[0477] A plurality of light-emitting units 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light-receiving units 6016 are provided at positions facing the light-emitting units 6015. This makes it possible to obtain information about the position where a touch operation is performed.

[0478] The light-emitting unit 6015 may be a light source such as an LED element, and it is particularly preferable to use a light source that emits infrared light. The light-receiving unit 6016 may be a photoelectric element that receives the light emitted by the light-emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode that can receive infrared light may be used.

[0479] The light guiding portions 6017a and 6017b that transmit light 6018 allow the light emitting portion 6015 and the light receiving portion 6016 to be disposed below the display device 6006, thereby preventing external light from reaching the light receiving portion 6016 and causing the touch sensor to malfunction. In particular, using a resin that absorbs visible light and transmits infrared light can more effectively prevent the touch sensor from malfunctioning.

[0480] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0481] (Embodiment 7) In this embodiment, examples of electronic devices to which the display device of one embodiment of the present invention can be applied will be described.

[0482] Electronic device 6500 shown in FIG. 28A is a portable information terminal that can be used as a smartphone.

[0483] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0484] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0485] FIG. 28B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0486] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0487] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0488] A part of the display panel 6511 is folded back in an area outside the display unit 6502. An FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is also connected to a terminal provided on a printed circuit board 6517.

[0489] For example, a flexible display panel can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, it is possible to mount a large-capacity battery 6518 while suppressing the thickness of the electronic device. In addition, by folding back a part of the display panel 6511 and arranging a connection part with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0490] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0491] (Embodiment 8) In this embodiment, electronic devices including a display device manufactured using one embodiment of the present invention will be described.

[0492] The electronic devices exemplified below each include a display device according to one embodiment of the present invention in a display portion. Therefore, the electronic devices can achieve high resolution. Furthermore, the electronic devices can also have both high resolution and a large screen.

[0493] One embodiment of the present invention includes a display device and at least one of an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

[0494] The electronic device of one embodiment of the present invention may include a secondary battery, and it is preferable that the secondary battery can be charged using contactless power transmission.

[0495] Examples of secondary batteries include lithium ion secondary batteries such as lithium polymer batteries (lithium ion polymer batteries) that use a gel electrolyte, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0496] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0497] The display portion of the electronic device of one embodiment of the present invention can display images with a resolution of, for example, full high definition, 4K2K, 8K4K, 16K8K, or higher.

[0498] Examples of electronic devices include electronic devices with relatively large screens such as television devices, notebook personal computers, monitor devices, digital signage, pachinko machines, and game machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0499] An electronic device to which one embodiment of the present invention is applied can be incorporated along a flat or curved surface of an inner or outer wall of a building such as a house or a building, or the interior or exterior of a car or the like.

[0500] FIG. 29A is a diagram showing the appearance of the camera 8000 with the viewfinder 8100 attached.

[0501] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, etc. The camera 8000 also has a detachable lens 8006 attached thereto.

[0502] The camera 8000 may have the lens 8006 and the housing integrated together.

[0503] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display unit 8002 that functions as a touch panel.

[0504] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as a strobe device and the like.

[0505] The finder 8100 includes a housing 8101, a display portion 8102, a button 8103, and the like.

[0506] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display unit 8102.

[0507] The button 8103 has a function such as a power button.

[0508] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the camera 8000 may have a built-in finder.

[0509] 29B shows the appearance of an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.

[0510] The display device described in any of the above embodiments can be applied to the information terminal 5900, so that high-quality images can be displayed in the display portion 5902.

[0511] 29C is a diagram showing the appearance of a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0512] Furthermore, the video images of the portable game machine 5200 can be output by a display device such as a television device, a display for a personal computer, a game display, or a head-mounted display.

[0513] By applying the display device described in the above embodiment to the portable game console 5200, a high-quality image can be displayed in the display portion 5202. In addition, a low-power portable game console 5200 can be realized. Furthermore, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0514] FIG. 30A is a diagram showing the appearance of the head mounted display 8200.

[0515] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, and a cable 8205. The mounting portion 8201 has a built-in battery 8206.

[0516] A cable 8205 supplies power from a battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like, and can display received video information on a display portion 8204. The main body 8203 also includes a camera, and can use information on the movement of the user's eyeballs or eyelids as an input means.

[0517] The wearing unit 8201 may have a function of recognizing the line of sight by providing a plurality of electrodes at positions that come into contact with the user, the electrodes being capable of detecting a current that flows in association with the movement of the user's eyeballs or eyelids. The wearing unit 8201 may also have a function of monitoring the user's pulse rate based on the current that flows through the electrodes. The wearing unit 8201 may also have various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may also have a function of displaying biometric information of the user on the display unit 8204, a function of changing an image displayed on the display unit 8204 in accordance with the movement of the user's head, and the like.

[0518] The display device of one embodiment of the present invention can be applied to the display portion 8204.

[0519] 30B, 30C, and 30D are diagrams showing the appearance of a head mounted display 8300. The head mounted display 8300 includes a housing 8301, a display portion 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0520] A user can view the display on the display portion 8302 through the lens 8305. Note that it is preferable to arrange the display portion 8302 in a curved manner because the user can feel a high sense of presence. In addition, by viewing different images displayed in different regions of the display portion 8302 through the lens 8305, it is possible to perform 3D display using parallax. Note that the present invention is not limited to a configuration in which one display portion 8302 is provided, and two display portions 8302 may be provided, with one display portion being provided for each eye of the user.

[0521] Note that the display device of one embodiment of the present invention can be applied to the display portion 8302. The display device including the semiconductor device of one embodiment of the present invention has extremely high definition, and therefore, even when an image is enlarged using the lens 8305 as in FIG. 30D , pixels are not visible to a user, and a more realistic image can be displayed.

[0522] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. [Explanation of symbols]

[0523] ALP: pixel array, AMP: amplifier circuit, ARA: pixel area, CNP: control circuit section, CON: controller, DATA: image signal, DRV: drive circuit area, LD: local driver circuit, MEM: memory section, PG: voltage generation circuit

Claims

1. a first layer and a second layer located above the first layer, the first layer has a drive circuit region; the second layer has a pixel array; the pixel array has a plurality of pixel regions; the drive circuit region includes a control circuit section and a plurality of local driver circuits; one of the plurality of local driver circuits corresponds to one of the plurality of pixel areas; the local driver circuit has a function of outputting a drive signal for driving a plurality of pixels included in the corresponding pixel region; The control circuit unit has the function of determining a first area in which display is to be performed and a second area in which display is not to be performed by comparing resolution data of an input image signal with aspect ratio data of the pixel array, and outputting a control signal to the local driver circuit corresponding to the second area to stop output of a drive signal.

2. In claim 1, the drive circuit region is located inside the pixel array in a top view, a plurality of pixel regions that are arranged in a plane parallel to each other and that face each other;

3. In claim 1 or claim 2, each of the plurality of pixel regions has a plurality of wirings; In the plurality of pixel regions, the plurality of pixels are arranged in a matrix, the plurality of wirings are located for each row of the plurality of pixels arranged in the matrix, one of the plurality of wirings is electrically connected to the pixels located in the same row; Each of the plurality of wirings has a contact portion, The contact portion is located inside the pixel or between adjacent pixels.

4. In any one of claims 1 to 3, the pixel included in each of the plurality of pixel regions has a light-emitting device using an organic EL and a first transistor; the control circuitry and the local driver circuits each have a second transistor; the first transistor has a metal oxide in a channel formation region; The second transistor has silicon in a channel formation region.

5. 5. An electronic device comprising: the display device according to claim 1; and a housing.

Images