Gate time calculation program, gate time calculation method, and gate time calculation device for sampling circuit

Abstract

To provide a gate time calculation program, gate time calculation method and gate time calculation device of a sampling circuit which can secure the calculation time and shorten the response time.SOLUTION: A gate time calculation program of a sampling circuit 20 causes a processor 44 to execute the steps of: acquiring the target response time being the target value of the response time until the change in the input signal input to the sampling circuit 20 is reflected as the change in the output signal of an arithmetic circuit 30 that executes arithmetic processing based on the sampling result; and calculating the gate time being the length of the period during which the input signal is sampled in the sampling circuit 20 on the basis of the target response time.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a gate time calculation program, a gate time calculation method, and a gate time calculation device for a sampling circuit. [Background technology]

[0002] BACKGROUND ART Conventionally, there is known a transmitter that adjusts the gate time of a frequency conversion circuit that samples a vibration signal related to a physical quantity of a process and converts the sampled vibration signal into a frequency signal (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-122399 Summary of the Invention [Problem to be solved by the invention]

[0004] The transmitter described in Patent Document 1 monitors fluctuations in the output of a physical quantity conversion circuit, which calculates a signal related to a physical quantity from a frequency signal, and controls the gate time of the frequency conversion circuit to reduce fluctuations in the output signal of the physical quantity conversion circuit. However, no consideration is given to shortening the response time it takes for the output signal of the physical quantity conversion circuit to change in response to a change in the physical quantity corresponding to the vibration signal input to the frequency conversion circuit. Furthermore, no consideration is given to ensuring sufficient processing time for the calculation in the physical quantity conversion circuit. It is necessary to ensure sufficient processing time for the calculation circuit and to shorten the response time.

[0005] The present disclosure has been made in consideration of the above points, and aims to provide a gate time calculation program, a gate time calculation method, and a gate time calculation device for a sampling circuit that can ensure calculation time and shorten response time. [Means for solving the problem]

[0006] (1) In some embodiments, a gate time calculation program for a sampling circuit causes a processor to acquire a target response time, which is a target value for the response time until a change in an input signal input to a sampling circuit is reflected as a change in an output signal of an arithmetic circuit that executes arithmetic processing based on the sampling results in the sampling circuit, and calculate a gate time, which is the length of the period during which the input signal is sampled in the sampling circuit, based on the target response time.

[0007] (2) In the gate time calculation program for a sampling circuit described in (1) above, the response time may be a time from when the input signal changes until a ratio of a rate of change of the output signal to a rate of change of the input signal becomes greater than a response threshold. The gate time calculation program for a sampling circuit may cause the processor to calculate the gate time so that the sum of the product of the gate time and the response threshold and the processing time of the arithmetic circuit is equal to or less than the target response time.

[0008] By calculating the gate time based on the target response time, it is possible to ensure the processing time for calculations in a device or equipment that includes a sampling circuit and to reduce the response time.

[0009] (3) The gate time calculation program for the sampling circuit described in (1) or (2) above may cause the processor to acquire a required processing time, which is the processing time required for the sampling circuit to process the input signal and generate the output signal, and calculate the gate time based on the target response time and the required processing time.

[0010] By calculating the gate time based on the required processing time, the demands on the hardware performance of the arithmetic circuit are reduced, which results in a reduction in the cost of the arithmetic circuit or a reduction in the power consumption of the arithmetic circuit.

[0011] (4) In the program for calculating the gate time of a sampling circuit described in (3) above, the time from the end of a period in which the input signal is sampled in the sampling circuit until the start of the next period may be shorter than the required processing time.

[0012] If the idle time between the end of a sampling period and the start of the next sampling period is shorter than the processing time of the arithmetic circuit, the processing time of the arithmetic circuit is limited by the gate time. Therefore, it is useful to calculate the gate time based on the required processing time.

[0013] (5) The gate time calculation program for a sampling circuit described in any one of (1) to (4) above may cause the processor to calculate the gate time so that the processing time of the sampling circuit becomes a maximum value.

[0014] By maximizing the processing time of the arithmetic circuit 30, the processing load on the arithmetic circuit 30 can be minimized.

[0015] (6) In some embodiments, a method for calculating a gate time of a sampling circuit includes a processor obtaining a target response time, which is a target value of the response time until a change in an input signal input to the sampling circuit is reflected as a change in an output signal of an arithmetic circuit that performs arithmetic processing based on the sampling result in the sampling circuit; and the processor calculating, based on the target response time, a gate time, which is the length of a period during which the input signal is sampled in the sampling circuit.

[0016] (7) A gate time calculation device according to some embodiments executes the gate time calculation program according to any one of (1) to (5) above. [Effects of the Invention]

[0017] According to the gate time calculation program, gate time calculation method, and gate time calculation device for a sampling circuit according to the present disclosure, it is possible to ensure calculation time and reduce response time. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 10 is a block diagram showing the configuration of a transmitter according to a comparative example. [Figure 2] FIG. 2 is a block diagram illustrating a configuration example of a transmitter according to an embodiment of the present disclosure. [Figure 3] 1 is a time chart showing an example of the correspondence between a change over time in a physical quantity detected by a sensor, a period during which sampling is performed by a sampling circuit, a period during which calculation is performed by a calculation circuit, and a change over time in the output of the calculation circuit; [Figure 4] 10 is a graph showing an example of the relationship between the gate time of a sampling circuit and the processing time that can be secured by an arithmetic circuit when a target response time is satisfied. [Figure 5] 10 is a flowchart illustrating an example of a procedure for calculating a gate time of a sampling circuit. DETAILED DESCRIPTION OF THE INVENTION

[0019] (Comparative Example) As shown in FIG. 1 , a device 90 according to the comparative example includes a sensor 91, a sampling circuit 92, and an arithmetic circuit 93. The sensor 91 detects a physical quantity and inputs a signal corresponding to the detection result of the physical quantity to the sampling circuit 92. The sampling circuit 92 samples the signal input from the sensor 91 during a period whose length is specified by a gate time, and outputs the sampling result to the arithmetic circuit 93. The gate time is the length of the period during which the sampling circuit 92 opens the gate of an element such as a transistor to acquire an input signal from the sensor 10 and performs sampling. The arithmetic circuit 93 performs arithmetic processing based on the sampling result input from the sampling circuit 92, and outputs the arithmetic result corresponding to the physical quantity detected by the sensor 91 as an output signal.

[0020] The sampling circuit 92 accepts a gate time setting. In the comparative example, the gate time is set by a user inputting it into the sampling circuit 92 or by inputting an initial value held by the arithmetic circuit 93 into the sampling circuit 92. However, when a target value for the response time required for the signal input from the sensor 91 to the sampling circuit 92 to be reflected in the output of the arithmetic circuit 93 is set in the device 90, the response time may exceed the target value depending on the length of the gate time. Furthermore, depending on the length of the gate time, it may be necessary to increase the operating clock of the arithmetic circuit 93. In this case, the cost or power consumption of the arithmetic circuit 93 increases.

[0021] Therefore, the present disclosure describes a gate time calculation program, a gate time calculation method, and a gate time calculation device 40 (see FIG. 2) for a sampling circuit 20 (see FIG. 2) that can ensure calculation time and shorten response time in equipment such as a transmitter 1 (see FIG. 2).

[0022] (Transmitter 1 configuration example) As shown in FIG. 2, a transmitter 1 according to an embodiment of the present disclosure includes a sensor 10, a sampling circuit 20, an arithmetic circuit 30, and a gate time calculation device 40.

[0023] The transmitter 1 may be replaced with various other devices or apparatuses such as a field device. The gate time calculation device 40 may be incorporated as a device into the transmitter 1 or a field device. The function of the gate time calculation device 40 may be incorporated into the transmitter 1 or a field device.

[0024] The sensor 10 detects a physical quantity and outputs a signal corresponding to the detection result of the physical quantity. The sensor 10 may include, for example, a pressure sensor that detects a differential pressure or a pressure as the physical quantity. The sensor 10 may include, for example, a temperature sensor that detects a temperature as the physical quantity. The sensor 10 is not limited to these examples and may be configured to detect various other physical quantities. The sensor 10 may output various types of signals, such as an electrical signal such as a current signal or a voltage signal, or an optical signal, as a signal corresponding to the detected physical quantity. The sensor 10 may output the detection result of the physical quantity not only as a signal, but also in various other forms.

[0025] The sampling circuit 20 samples the input signal. The input signal is a signal input from the sensor 10 during a sampling period that lasts for a gate time. The gate time is the length of a period during which the sampling circuit 20 opens the gate of an element such as a transistor, acquires the input signal from the sensor 10, and performs sampling. The sampling circuit 20 may integrate or average the input signal input from the sensor 10 during the sampling period. The sampling circuit 20 may sample the input signal input from the sensor 10 by performing various processes other than arithmetic processes such as integration or averaging of the input signal input from the sensor 10 during the sampling period.

[0026] The sampling circuit 20 accepts the setting of the gate time. The gate time may be set by being input to the sampling circuit 20 from a gate time calculation device 40, which will be described later. The gate time may also be set by a user inputting the gate time calculated by the gate time calculation device 40 to the sampling circuit 20. The gate time may also be set by inputting an initial value held by the arithmetic circuit 30 to the sampling circuit 20.

[0027] The sampling circuit 20 converts the sampling result of the input signal input from the sensor 10 into a signal in a format that can be processed by the arithmetic circuit 30, or into data or information in a format that can be processed by the arithmetic circuit 30, and outputs it to the arithmetic circuit 30. The sampling result is a signal, data, or information generated as a result of the sampling circuit 20 sampling the input signal.

[0028] The arithmetic circuit 30 acquires sampling results such as signals, data, or information from the sampling circuit 20, performs arithmetic processing based on the sampling results, and outputs the arithmetic results as an output signal. The output signal is a signal corresponding to a physical quantity detected by the sensor 10. The output signal may be an electrical signal such as a current signal or a voltage signal, or a signal of various types such as an optical signal. The output signal may include a communication signal. The output signal may include a current signal of 4 mA to 20 mA. The output signal may include a contact signal.

[0029] The arithmetic circuit 30 may be configured to include a processor such as a CPU (Central Processing Unit) or a dedicated circuit such as an FPGA (Field Programmable Gate Array). The arithmetic circuit 30 may be configured to execute a program including arithmetic processing procedures. The arithmetic circuit 30 may include a memory unit. The memory unit may store various information used in the operation of the arithmetic circuit 30, or a program including arithmetic processing procedures. The memory unit may function as a work memory for the arithmetic circuit 30. The memory unit may be configured, for example, as a semiconductor memory. The memory unit may be configured integrally with the arithmetic circuit 30 or may be configured separately.

[0030] The arithmetic circuit 30 performs arithmetic processing for a predetermined time. The time required for the arithmetic circuit 30 to perform arithmetic processing is also referred to as the processing time of the arithmetic circuit 30. The processing time is determined according to the hardware performance of the arithmetic circuit 30. For example, the lower the hardware performance of the arithmetic circuit 30, the longer the processing time may be. The processing time may also be determined according to the number of operating clocks input to the arithmetic circuit 30. For example, the lower the number of operating clocks, the longer the processing time may be. The higher the number of operating clocks input to the arithmetic circuit 30, the greater the power consumption of the arithmetic circuit 30. In other words, the power consumption of the arithmetic circuit 30 may increase in order to shorten the processing time.

[0031] The gate time calculation device 40 calculates the gate time to be set in the sampling circuit 20. The gate time calculation device 40 may or may not be included in the transmitter 1. The gate time calculation device 40 may be connected to the sampling circuit 20 when it is necessary to set a gate time in the sampling circuit 20, and may set the calculated gate time in the sampling circuit 20. The gate time calculation device 40 may not be connected to the sampling circuit 20. If the gate time calculation device 40 is not connected to the sampling circuit 20, it may notify the user who sets the gate time in the transmitter 1 of the calculation result of the gate time. The user of the transmitter 1 may set the result of the gate time calculated by the gate time calculation device 40 in the sampling circuit 20.

[0032] The gate time calculation device 40 includes an acquisition unit 42, a calculation unit 44, and an output unit 46.

[0033] The calculation unit 44 may be configured to include, for example, a processor such as a CPU or a dedicated circuit such as an FPGA. The calculation unit 44 may be configured to execute programs that realize various functions of the gate time calculation device 40. The calculation unit 44 may include a storage unit. The storage unit may store various information used in the operation of the calculation unit 44, or programs for realizing the functions of the gate time calculation device 40. The storage unit may function as a work memory for the calculation unit 44. The storage unit may be configured, for example, as a semiconductor memory. The storage unit may be configured integrally with the calculation unit 44 or may be configured separately.

[0034] The acquisition unit 42 and the output unit 46 may include, for example, a communication interface for communicating with an external device via a wired or wireless connection.

[0035] The acquisition unit 42 may include an input device that accepts input from a user. The input device may include, for example, a keyboard or physical keys, or a pointing device such as a touch panel, a touch sensor, or a mouse.

[0036] The output unit 46 may include a display device. The display device may include various displays such as a liquid crystal display, etc. The output unit 46 may also include an audio output device such as a speaker.

[0037] (Example of operation of the sensor 10, sampling circuit 20, and arithmetic circuit 30) The transmitter 1 inputs the result of detecting a physical quantity by the sensor 10 as an input signal to the sampling circuit 20, samples the input signal by the sampling circuit 20, processes the sampling result by the arithmetic circuit 30, and outputs an output signal corresponding to the physical quantity. In other words, the transmitter 1 outputs the detection result of the physical quantity by the sensor 10 as an output signal.

[0038] 3, an input signal corresponding to the detection result of a physical quantity in the sensor 10 is sampled by the sampling circuit 20 and processed by the arithmetic circuit 30, and is reflected in an output signal from the arithmetic circuit 30. In FIG. 3, it is assumed that the magnitudes of the input signal and the output signal vary between 0% and 100%.

[0039] The sampling circuit 20 acquires an input signal corresponding to a physical quantity detected by the sensor 10 from the sensor 10. The sampling circuit 20 samples the input signal acquired from the sensor 10 and outputs the sampling result to the arithmetic circuit 30 at the end of each sampling period. In Fig. 3, three sampling periods are represented as SP1, SP2, and SP3. The length of one sampling period, i.e., the gate time, is represented as Tgt.

[0040] The arithmetic circuit 30 performs arithmetic processing on the sampling results in one sampling period, and outputs the arithmetic result as an output signal when the arithmetic processing is completed. In Fig. 3, the period during which arithmetic processing is performed on the sampling results in the first sampling period (SP1) is represented as CP1. The period during which arithmetic processing is performed on the sampling results in the second sampling period (SP2) is represented as CP2. The length of one arithmetic processing is represented in Tex.

[0041] As shown in Figure 3, after the input signal changes, the output signal of the arithmetic circuit 30 may change in multiple stages. When the ratio of the rate of change of the output signal to the rate of change of the input signal becomes greater than a predetermined threshold, it is determined that the change in the input signal has been reflected in the output signal. The time from when the input signal changes until the change in the input signal is reflected in the output signal is also called the response time. In other words, the response time is the time from when the input signal changes until the ratio of the rate of change of the output signal to the rate of change of the input signal becomes greater than a predetermined threshold.

[0042] The predetermined threshold used to determine whether a change in the input signal is reflected in the output signal is also referred to as a response threshold. In other words, the response threshold is a value that is compared with the ratio of the rate of change of the output signal to the rate of change of the input signal to determine whether a change in the input signal is reflected in the output signal. The response threshold may be set to, for example, 63%, which may be used as a time constant based on a natural logarithm value. The response threshold may be set to, for example, 90%, which may be used as a value for determining whether a pulse signal rises or falls.

[0043] As shown in Figure 3, when the input signal changes from 100% to 0%, the rate of change of the input signal is 100%. For example, if the response threshold is set to 63% based on the natural logarithm, it is determined that the change in the input signal is reflected in the output signal when the output signal changes from 100% to less than 37%. On the vertical axis of the graph representing the output signal in the timing chart of Figure 3, the value determined as the comparison target of the output signal based on the response threshold is indicated by TH. The response threshold is 100% - TH.

[0044] 3, the response time is represented by Tres, which is calculated as the sum of the length of the period after the input signal changes from 100% to 0% in the sampling period (SP1), the length of the second sampling period (SP2), and the processing time (CP2) of the sampling result in the arithmetic circuit 30.

[0045] Here, it is assumed that a target response time is set as a specification of the transmitter 1. The target response time is a time set as an upper limit of the response time. In other words, when a target response time is set as a specification of the transmitter 1, the sampling circuit 20 and the arithmetic circuit 30 must be operated so that the response time is equal to or less than the target response time.

[0046] It is assumed that the sampling circuit 20 outputs the average value of the input signal input during the sampling period as the sampling result to the arithmetic circuit 30. The following cases (a) to (g) are assumed to be cases in which the response time is maximum in the timing chart of FIG. (a) The input signal changes from 100% to 0% at 37% (Tgt × 0.37) of the time from the start of the first sampling period (SP1). (b) The sampling circuit 20 calculates the average value of the input signal during the first sampling period (SP1) as 37%, and outputs 37% as the sampling result at the end of SP1. (c) After the processing time has elapsed since the arithmetic circuit 30 acquired the sampling result from the sampling circuit 20, 37% is output as an output signal corresponding to the processing result. (d) Since the output signal has only changed by 63% of the 100% change rate of the input signal (only changing from 100% to 37%), it is determined that the change in the input signal has not yet been reflected in the output signal. (e) The sampling circuit 20 outputs 0% as the sampling result at the end of the second sampling period (SP2). (f) After the processing time has elapsed since the arithmetic circuit 30 acquired the sampling result from the sampling circuit 20, 0% is output as the output signal corresponding to the processing result. (g) Since the output signal has changed by 100% (changed from 100% to 0%) relative to the 100% change rate of the input signal, it is determined that the change in the input signal has been reflected in the output signal.

[0047] The response time in the cases (a) to (g) described above is calculated as the sum (Tgt×1.63+Tex) of the length of the period after the input signal changes from 100% to 0% in the sampling period (SP1) (Tgt×0.63), the gate time (Tgt) which is the length of the second sampling period (SP2), and the processing time (Tex) of the arithmetic circuit 30. Since this response time is the maximum, the range of the response time (Tres) is expressed by the following inequality (1). Tres≦Tgt×1.63+Tex (1)

[0048] In addition, the processing time of the arithmetic circuit 30 must be equal to or shorter than the gate time (Tgt), which is the length of one sampling period, so that the processing of the arithmetic circuit 30 executed for each sampling period is completed within the sampling period. Therefore, the following inequality (2) must be satisfied. Tex≦Tgt (2)

[0049] The above inequality (1) holds when the response threshold is set to 63%. When the response threshold is represented by Rth, inequality (1) can be rewritten as the following inequality (1a): Tres≦Tgt×(1+Rth)+Tex (1a)

[0050] When the response threshold is represented by Rth, the relationship represented by TH=1−Rth holds between the threshold TH of the output of the arithmetic circuit 30 illustrated in FIG. 3 and Rth.

[0051] Assume that a target response time is set as a specification for transmitter 1. In this case, the gate time, which is the length of the sampling period, must be set within the constraints of the above-mentioned inequalities (1) or (1a) and (2) so that the response time is equal to or less than the target response time. Specifically, under the constraints of the above-mentioned inequalities (1) and (2), the range of the gate time is determined by the following inequality (3). Tgt≧Tres / 2.63 (3) Furthermore, under the constraints of the above inequalities (1a) and (2), the range of the gate time is determined by the following inequality (3a). Tgt≧Tres / (2+Rth) (3a)

[0052] A required processing time for the arithmetic circuit 30 may be further set as a specification of the transmitter 1. The required processing time is a time secured as the minimum time required for processing the arithmetic circuit 30. For example, when the processing speed of the arithmetic circuit 30 is limited by constraints such as the clock count or power consumption of the arithmetic circuit 30, the time required to process the sampling results and output an output signal at the limited processing speed is set as the required processing time.

[0053] When the required processing time is set, the gate time is set so that the processing time of the arithmetic circuit 30 is equal to or greater than the required processing time. If the required processing time is shorter than the lower limit Tres / 2.63 determined by the above-mentioned inequality (3) or the lower limit Tres / (2+Rth) determined by the inequality (3a), the lower limit of the gate time becomes the lower limit determined by the above-mentioned inequality (3) or (3a). On the other hand, if the required processing time is longer than the lower limit Tres / 2.63 determined by the above-mentioned inequality (3) or the lower limit Tres / (2+Rth) determined by the inequality (3a), the lower limit of the gate time becomes the required processing time. If the required processing time falls within the gate time, the processing time (Tex) of the arithmetic circuit 30 and the gate time (Tgt) may be set to be equal.

[0054] (Example of operation of gate time calculation device 40) As described above, when a target response time is set as a specification of the transmitter 1, it is necessary to appropriately set the gate time of the sampling circuit 20. The gate time calculation device 40 according to this embodiment calculates a predetermined gate time to be set in the sampling circuit 20 based on the target response time.

[0055] <Constraints based on target response time> First, the gate time must be set to be longer than the processing time of the arithmetic circuit 30. Therefore, the following constraint A is set. Constraint A: Tgt ≧ Tex

[0056] In addition, the response time must be equal to or less than the target response time. Here, the target response time is represented by Tres_t. Also, the response threshold is set to 63%. In this case, the following constraint B is set. Constraint B: Tres_t≧Tres=Tex+Tgt×1.63 Constraint B is transformed into the following constraint B'. Constraint B':Tex≦Tres_t-Tgt×1.63

[0057] The calculation unit 44 of the gate time calculation device 40 calculates the gate time so as to satisfy both the constraint condition A and the constraint condition B' described above. For example, assuming that the relationship between the gate time and the processing time of the arithmetic circuit 30 is expressed as shown in the graph in FIG. 4, the procedure for calculating the optimal value of the gate time will be described. In the graph in FIG. 4, the horizontal axis represents the gate time (Tgt), and the vertical axis represents the processing time (Tex) of the arithmetic circuit 30. Furthermore, in the graph in FIG. 4, it is assumed that the target response time is set to 90 msec (milliseconds).

[0058] The upper limit boundary of the processing time of the arithmetic circuit 30 based on constraint A is represented by a graph of Tex = Tgt. On the other hand, the upper limit boundary of the processing time of the arithmetic circuit 30 based on constraint B' is represented by a graph of Tex = Tres_t - Tgt × 1.63. Note that when the response threshold is represented by Rth, the upper limit boundary of the processing time of the arithmetic circuit 30 based on constraint B' is represented by a graph of Tex = Tres_t - Tgt × (1 + Rth).

[0059] In other words, the calculation unit 44 may calculate the gate time so that the sum of the product of the gate time and the response threshold (Tgt×Rth), the gate time (Tgt), and the processing time (Tex) of the arithmetic circuit 30 is less than or equal to the target response time (Tres_t).

[0060] <Constraints Based on Required Processing Time of the Arithmetic Circuit 30> Based on the performance of the arithmetic circuit 30, the required processing time is determined as the lower limit of the time required for the arithmetic circuit 30 to process the measurement values ​​input from the sampling circuit 20. Therefore, the gate time must be set so that the processing time of the arithmetic circuit 30 is equal to or greater than the required processing time. In other words, the gate time must be calculated based on the required processing time of the arithmetic circuit 30 in addition to the target response time.

[0061] 4, the required processing time is represented by a dashed line extending along the horizontal axis. The gate time must be set within the hatched area surrounded by the line representing the required processing time and the lines representing the upper boundaries of the processing time of the arithmetic circuit 30 based on each of constraints A and B'. In other words, the calculation unit 44 of the gate time calculation device 40 must calculate the gate time so that both constraints A and B' are satisfied and the processing time of the arithmetic circuit 30 is equal to or greater than the required processing time.

[0062] Here, the longer the processing time of the arithmetic circuit 30, the more the processing load of the arithmetic circuit 30 can be reduced. If setting the gate time so that the processing time of the arithmetic circuit 30 is at its maximum value is optimal for the operation of the transmitter 1, the optimal value of the gate time will be equal to the maximum value of the processing time of the arithmetic circuit 30. By setting the processing time of the arithmetic circuit 30 to its maximum value, the processing load of the arithmetic circuit 30 can be minimized.

[0063] If the gate time when the processing time of the arithmetic circuit 30 reaches its maximum value is the optimal gate time, the intersection of the graph of Tex = Tgt and the graph of Tex = Tres_t - Tgt × 1.63 in FIG. 4 is the optimal gate time. Specifically, the optimal gate time is calculated as Tres_t / 2.63. In the graph of FIG. 4, Tres_t = 90 msec, so the optimal gate time is calculated as 90 / 2.63 = 34.2 msec. When the response threshold is represented by Rth, the optimal gate time is calculated as Tres_t / (2 + Rth).

[0064] <Gate time output calculated based on constraints> The gate time calculation device 40 outputs the gate time calculated by the calculation unit 44 as described above from the output unit 46. The output unit 46 may output the calculation result of the gate time to the sampling circuit 20 to set the gate time in the sampling circuit 20. The output unit 46 may display the calculation result of the gate time to notify the user of the transmitter 1. The user of the transmitter 1 may set the gate time in the sampling circuit 20 based on the display of the calculation result of the gate time.

[0065] <Example of procedure for calculating the gate time of the sampling circuit 20> The calculation section 44 of the gate time calculation device 40 may execute a gate time calculation method for the sampling circuit 20, including the example procedure of the flowchart illustrated in Fig. 5. The gate time calculation method may be realized as a gate time calculation program executed by a processor constituting the calculation section 44. The gate time calculation program may be stored in a non-transitory computer-readable medium.

[0066] The calculation unit 44 acquires the target response time of the transmitter 1 and the required processing time of the arithmetic circuit 30 by the acquisition unit 42 (step S1).

[0067] The calculation unit 44 calculates the gate time of the sampling circuit 20 so that the constraint conditions determined based on the target response time and the required processing time are satisfied (step S2). The calculation unit 44 may calculate the gate time within a range in which the constraint conditions are satisfied, or may calculate the gate time so that the processing time of the arithmetic circuit 30 becomes the maximum value.

[0068] The calculation unit 44 outputs the calculation result of the gate time via the output unit 46 (step S3). The output unit 46 may output the calculation result of the gate time to the sampling circuit 20, or may notify the user of the transmitter 1. After executing the procedure of step S3, the calculation unit 44 ends the execution of the procedure of the flowchart in FIG. 5.

[0069] (Small summary) As described above, according to the gate time calculation device 40 and the gate time calculation method and gate time calculation program for the sampling circuit 20 of this embodiment, the gate time is calculated based on the target response time. Calculating the gate time based on the target response time ensures that the processing time for calculations is sufficient and that the response time is reduced in a device or equipment such as the transmitter 1 that includes the sampling circuit 20. Calculating the gate time based on the required processing time also reduces the requirements for the hardware performance of the arithmetic circuit 30. As a result, the cost of the arithmetic circuit 30 can be reduced, or the power consumption of the arithmetic circuit 30 can be reduced.

[0070] In the transmitter 1 according to this embodiment, if an increase and a decrease in the input signal occur during one sampling period, the increase and decrease in the input signal cancel each other out in the sampling result, and the change in the input signal is not reflected in the output signal. Therefore, the sampling circuit 20 according to this embodiment may be applied when the frequency of the input signal change is ½ or less per sampling period.

[0071] If there is a vacant period between the end of one sampling period and the start of the next sampling period, part of the processing of the arithmetic circuit 30 may be executed during the vacant period. In this case, the gate time (Tgt) may be calculated based on the time obtained by subtracting the length of the vacant period from the processing time (Tex) of the arithmetic circuit 30. Specifically, constraint A (Tgt≧Tex) may be converted to the following constraint A'. Constraint A': Tgt≧Tex-(length of free time)

[0072] If the length of the idle time is longer than the processing time of the arithmetic circuit 30, constraint A effectively disappears. Therefore, the gate time calculation method or gate time calculation program described above may be applied on the assumption that the idle time is shorter than the required processing time. Furthermore, the gate time calculation method or gate time calculation program described above is useful for setting the gate time in the sampling circuit 20, in which the sampling period is set so that the idle time is zero or almost non-existent. In other words, if the length of the idle time from the end of one sampling period to the start of the next sampling period is shorter than the processing time of the arithmetic circuit 30, the processing time of the arithmetic circuit 30 is constrained by the gate time. Therefore, calculating the gate time based on the required processing time becomes useful.

[0073] The gate time calculation device 40 may include a tool for setting the gate time in the sampling circuit 20. The gate time calculation device 40 may include a general-purpose PC (Personal Computer), a mobile terminal, or the like.

[0074] The above describes an embodiment of the present disclosure with reference to the drawings, but the specific configuration is not limited to this embodiment, and various modifications are also included within the scope that does not deviate from the spirit of the present disclosure. [Explanation of symbols]

[0075] 1 transmitter 10 sensors 20 Sampling Circuit 30 Arithmetic circuit 40 Gate time calculation device (42: acquisition unit, 44: calculation unit, 46: output unit)

Claims

1. acquiring a target response time, which is a target value of the response time from when a change in an input signal input to a sampling circuit is reflected as a change in an output signal of an arithmetic circuit that executes arithmetic processing based on the sampling result in the sampling circuit; calculating a gate time, which is the length of a period for sampling the input signal in the sampling circuit, based on the target response time; A program for calculating the gate time of a sampling circuit, which causes a processor to execute the program.

2. the response time is a time from when the input signal changes until when a ratio of a rate of change of the output signal to a rate of change of the input signal becomes greater than a response threshold; 2. The gate time calculation program for a sampling circuit according to claim 1, which causes the processor to calculate the gate time so that the sum of the product of the gate time and the response threshold and the gate time and the processing time of the arithmetic circuit is equal to or less than the target response time.

3. acquiring a required processing time, which is a processing time required to process the input signal in the sampling circuit and generate the output signal; calculating the gate time based on the target response time and the required processing time; 2. The sampling circuit gate time calculation program according to claim 1, which causes the processor to execute the following:

4. 4. The sampling circuit gate time calculation program according to claim 3, wherein the time from the end of a period in which the input signal is sampled in the sampling circuit to the start of the next period is shorter than the required processing time.

5. 5. The sampling circuit gate time calculation program according to claim 1, which causes the processor to calculate the gate time so that the processing time of the sampling circuit is maximized.

6. a processor acquiring a target response time, which is a target value of a response time from a change in an input signal input to a sampling circuit to a change in an output signal of an arithmetic circuit that executes arithmetic processing based on a sampling result in the sampling circuit; the processor calculates a gate time, which is the length of a period for sampling the input signal in the sampling circuit, based on the target response time; A method for calculating a gate time of a sampling circuit, comprising:

7. A gate time calculation device that executes the gate time calculation program according to any one of claims 1 to 4.

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