capacitor

Abstract

The capacitor (1A) includes an insulating substrate (10) having a main surface (10a), a capacitance-forming portion (20) provided on the main surface (10a), and first and second external connection wiring connected to the capacitance-forming portion (20). The capacitance-forming portion (20) includes a conductive porous metal body (21) connected to the first external connection wiring, a dielectric film (22) covering the surface of the porous metal body (21), and a conductive film (23) covering the dielectric film (22) and connected to the second external connection wiring. The second external connection wiring includes a conductive plated portion (50) provided on the outer periphery (20a) of the capacitance-forming portion (20) and a conductive intervening film (40) interposed between the capacitance-forming portion (20) and the plated portion (50). The capacitance-forming portion (20) is sealed by the insulating substrate (10) and the plated portion (50).

Description

[Technical Field]

[0001] The present invention relates to a capacitor. [Background technology]

[0002] For example, International Publication No. 2018 / 092722 (Patent Document 1) discloses a capacitor having a capacitance-forming portion formed by a metal porous body, a dielectric film covering the surface of the metal porous body, and a conductive film covering the dielectric film. In this capacitor, the capacitance-forming portion is sealed with a conductive plating portion. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 092722 Summary of the Invention [Problem to be solved by the invention]

[0004] In the capacitor disclosed in Patent Document 1, the plating solution used to form the plating portion may remain in multiple tiny spaces within the capacitance-forming portion. In this case, the plating solution may expand due to thermal loads applied during capacitor manufacturing or after mounting, causing blisters, which may apply stress to the capacitance-forming portion and cause cracks in the dielectric film. Furthermore, contact of the plating solution residue with the porous metal body may cause the porous metal body to dissolve.

[0005] If cracks form in the dielectric film or the porous metal body dissolves in this way, a short circuit will occur in the capacitance forming portion, resulting in a deterioration in the function of the capacitor.

[0006] Therefore, the present invention has been made to solve the above-mentioned problems, and aims to improve the reliability after mounting in a capacitor having a capacitance forming portion consisting of a metal porous body, a dielectric film, and a conductive film, and a plated portion that seals it. [Means for solving the problem]

[0007] A capacitor according to the present invention includes an insulating substrate having a main surface, a capacitance-forming portion provided on the main surface, and first and second external connection wirings connected to the capacitance-forming portion. The capacitance-forming portion includes a conductive porous metal body connected to the first external connection wiring, a dielectric film covering the surface of the porous metal body, and a conductive film covering the dielectric film and connected to the second external connection wiring. The second external connection wiring includes a conductive plated portion provided on the outer periphery of the capacitance-forming portion and a conductive intervening film interposed between the capacitance-forming portion and the plated portion. The capacitance-forming portion is sealed by the insulating substrate and the plated portion. [Effects of the Invention]

[0008] According to the present invention, it is possible to improve the reliability after mounting in a capacitor having a capacitance forming portion made of a metal porous body, a dielectric film, and a conductive film, and a plated portion that seals it. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic front view of a capacitor according to a first embodiment. [Figure 2] FIG. 2 is a schematic bottom view of the capacitor shown in FIG. [Figure 3] FIG. 3 is a schematic cross-sectional view of the capacitor shown in FIG. [Figure 4] FIG. 4 is an enlarged cross-sectional view of a main part of the capacitor shown in FIG. [Figure 5] FIG. 10 is an enlarged cross-sectional view of a main part for explaining an example of a distance measurement method. [Figure 6] 3 is a flowchart showing a method for manufacturing a capacitor according to the first embodiment. FIG. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a state after step S4 of the manufacturing flow shown in FIG. 6 is completed. [Figure 8] FIG. 7 is a schematic cross-sectional view for explaining step S5 of the manufacturing flow shown in FIG. 6. [Figure 9] FIG. 7 is a schematic cross-sectional view for explaining step S6 of the manufacturing flow shown in FIG. 6. [Figure 10] FIG. 7 is a schematic cross-sectional view for explaining step S7 of the manufacturing flow shown in FIG. 6. [Figure 11] FIG. 7 is a schematic cross-sectional view for explaining step S8 of the manufacturing flow shown in FIG. 6. [Figure 12] FIG. 7 is a schematic cross-sectional view for explaining step S9 of the manufacturing flow shown in FIG. 6. [Figure 13] FIG. 10 is a schematic cross-sectional view of a capacitor according to a first modified example. [Figure 14] FIG. 10 is a schematic cross-sectional view of a capacitor according to a second modified example. [Figure 15] FIG. 10 is a schematic cross-sectional view of a capacitor according to a second embodiment. [Figure 16] FIG. 16 is an enlarged cross-sectional view of a main part of the capacitor shown in FIG. [Figure 17] FIG. 10 is a flowchart showing a method for manufacturing a capacitor according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the embodiments described below, identical or common parts are designated by the same reference numerals in the drawings, and their description will not be repeated. In addition, in the embodiments described below, the terms "anode" and "cathode" are used for the sake of convenience, but the electrical polarity of the capacitor in the embodiments described below is not uniquely determined by these terms, and the electrical polarity is determined appropriately according to the environment in which the capacitor is used.

[0011] (Embodiment 1) FIG. 1 is a schematic front view of a capacitor according to embodiment 1. FIG. 2 is a schematic bottom view of the capacitor as viewed from the direction of arrow II shown in FIG. 1. FIG. 3 is a schematic cross-sectional view of the capacitor taken along line III-III shown in FIG. 2. FIG. 4 is an enlarged cross-sectional view of a main portion of region IV of the capacitor shown in FIG. 3. FIG. 5 is an enlarged cross-sectional view of a main portion for explaining an example of a distance measurement method. First, the configuration of a capacitor 1A according to this embodiment will be described with reference to FIGS. 1 to 5. The region shown in FIG. 5 is the same as the region shown in FIG. 4.

[0012] As shown in Figures 1 to 4, capacitor 1A has a flat, approximately rectangular parallelepiped outer shape, with its bottom surface configured as a mounting surface for a wiring board or the like. Capacitor 1A mainly comprises an insulating substrate 10, a capacitance-forming portion 20, and a plated portion 50. Capacitor 1A is provided so as to face insulating substrate 10. Capacitor 20 is located inside capacitor 1A by being sealed by insulating substrate 10 and the plated portion 50 provided on insulating substrate 10.

[0013] The insulating substrate 10 is provided with a first via conductor 13 and a first bump 16. The first via conductor 13 and the first bump 16 constitute one of a pair of external connection wirings for electrically connecting the capacitance forming portion 20 located inside the capacitor 1A to an external circuit. More specifically, the pair of external connection wirings includes a first external connection wiring as an anode and a second external connection wiring as a cathode. The first external connection wiring is constituted by the first via conductor 13 and the first bump 16. The second external connection wiring is constituted by a plated portion 50 and the like, which will be described in detail later.

[0014] The insulating substrate 10 is a flat plate-shaped member having a first main surface 10a as a main surface and a second main surface 10b located on the opposite side of the first main surface 10a. An electrically insulating substrate is preferably used as the insulating substrate 10, and a substrate primarily composed of an inorganic material is preferably used. More specifically, the insulating substrate 10 may be a substrate primarily composed of any of Si, Al2O3, ZrO2, BN, Si3N4, AlN, MgO, Mg2SiO4, BaTiO3, SrTiO3, and CaTiO3.

[0015] The thickness and size of the insulating substrate 10 are not particularly limited, but it is preferable to use an alumina substrate that is rectangular in plan view, for example, with a thickness of 5 μm or more and 75 μm or less and a side length of 500 μm or more and 2000 μm or less.

[0016] A first through hole 11 is provided in the insulating substrate 10. The first through hole 11 penetrates the insulating substrate 10 so as to reach from the first main surface 10a to the second main surface 10b. The first through hole 11 is filled with a first via conductor 13. The shape of the first via conductor 13 is, for example, approximately cylindrical.

[0017] The first via conductor 13 constitutes a part of the above-mentioned first external connection wiring. When viewed along the normal direction of the first main surface 10a of the insulating substrate 10, the first via conductor 13 is provided within the region in which the capacitance forming portion 20 is arranged.

[0018] The first via conductors 13 can be made of various wiring materials, but are preferably made of a metal material with particularly high electrical conductivity. The material of the first via conductors 13 can be a metal material primarily made of, for example, Ni, Ag, Cu, Au, Pt, Mo, or W. The material of the first via conductors 13 can be changed as appropriate depending on the mounting environment of the capacitor 1A according to this embodiment. In this embodiment, the first via conductors 13 are made of Ni.

[0019] The axial length and size of first via conductor 13 are not particularly limited and are set appropriately depending on the thickness and size of insulating substrate 10. Here, the axial length of first via conductor 13 is preferably, for example, 5 μm or more and 75 μm or less, and the diameter is preferably, for example, 15 μm or more and 150 μm or less. In this embodiment, first via conductor 13 is made of Ni and has an axial length of 75 μm and a diameter of 150 μm.

[0020] A first bump 16 is provided on the second main surface 10b of the insulating substrate 10 so as to cover the first via conductor 13. The first bump 16 serves to mount the capacitor 1A on a wiring board or the like and also serves as a bonding material for electrically connecting the capacitance forming portion 20 of the capacitor 1A to an external circuit. The first bump 16 is provided so as to protrude from the second main surface 10b of the insulating substrate 10. The shape of the first bump 16 is approximately hemispherical. The first bump 16 constitutes a part of the above-mentioned first external connection wiring.

[0021] The first bump 16 can be made of various wiring materials, but is preferably made of a metal material with particularly high electrical conductivity. The material of the first bump 16 can be, for example, a metal material containing any of Ni, Ag, Cu, Au, and Sn as the main component. In this embodiment, the first bump 16 is made of Au.

[0022] The size of the first bump 16 is not particularly limited, and is set appropriately depending on the size of the first via conductor 13 .

[0023] 3, the capacitance forming portion 20 is provided on the first main surface 10a of the insulating substrate 10. The capacitance forming portion 20 includes a conductive porous metal body 21 having a plurality of fine pores therein, a dielectric film 22 covering the surface of the porous metal body 21, and a conductive film 23 further covering the surface of the dielectric film 22.

[0024] Porous metal body 21 is connected to first via conductor 13. Porous metal body 21 has a plurality of fine pores formed therein, at least some of which are not closed by porous metal body 21 itself, and preferably most or all of the fine pores formed therein are not closed by porous metal body 21 itself. Such porous metal body 21 is made of, for example, a sintered body of metal particles.

[0025] The porous metal body 21 can be made of various conductive metal materials, but is preferably made of a metal material containing as its main component any of Ni, Mo, W, Al, Ti, Ta, Nb, Cu, Pt, Au, and Ag. The porous metal body 21 may also be made of an alloy material containing as its main component two or more selected from these metal materials.

[0026] The thickness and size of the porous metal body 21 are not particularly limited, and the size is set appropriately depending on the size of the insulating substrate 10. In this embodiment, the porous metal body 21 is made of Ni and has a thickness of 200 μm.

[0027] The porous metal body 21 is preferably made of a sintered body of metal particles. In this case, the metal particles may have various shapes, such as spherical, oval, flat, plate-like, or needle-like. The particle size of the metal particles is not particularly limited, but the average particle size is preferably 600 nm or less, and more preferably 20 nm to 500 nm.

[0028] As described above, the dielectric film 22 covers the surface of the porous metal body 21. More specifically, the dielectric film 22 not only covers the surface of the porous metal body 21 in the portion located on the outermost side of the capacitance forming portion 20, but also covers the surface of the porous metal body 21 in the portion located inside the capacitance forming portion 20, which is defined by the above-mentioned fine pores that are not closed by the porous metal body itself. Furthermore, the dielectric film 22 covers the side surfaces of the insulating substrate 10 and the edge portion of the second main surface 10b.

[0029] The dielectric film 22 can be made of various insulating materials, for example, AlO x , SiO x , HfO x , TiO x , TaO x , ZrO x , SiAlO x , HfAlO x , ZrAlO x , AlTiO x , SrTiO x , HfSiO x , ZrSiO x , TiZrO x , TiZrWO x , BaTiO x , PbTiO x , BaSrTiO x , BaCaTiO x Metal oxides such as AlN x , SiN x , AlScN x Metal nitrides such as AlO x N y , SiO x N y , HfO x N y , SiC x O y N z Among them, AlO x (e.g. Al2O3), SiO x (e.g. SiO2), HfO x , TiO x , SiAlO x , HfAlO x , ZrAlO x , HfSiO x and ZrSiO xIt is preferable that the dielectric film 22 is made of any one of the above. Note that the above chemical formula simply indicates the composition of the material and does not limit the composition. In other words, x, y, and z attached to O, N, and C may be any value greater than 0, and the abundance ratio of each element, including metal elements, is arbitrary. Furthermore, the dielectric film 22 may be made of a laminated film consisting of multiple dielectric layers made of different materials.

[0030] The dielectric film 22 can be preferably formed by a gas phase method such as a vacuum deposition method, a chemical vapor deposition (CVD) method, a sputtering method, an atomic layer deposition (ALD) method, a pulsed laser deposition (PLD) method, or a method using a supercritical fluid, and is particularly preferably formed by an ALD method.

[0031] The thickness of the dielectric film 22 is not particularly limited, but is preferably 3 nm to 100 nm, and more preferably 5 nm to 50 nm. In this embodiment, the dielectric film 22 is made of AlSiO and has a thickness of approximately 20 nm.

[0032] As described above, the conductive film 23 covers the surface of the dielectric film 22. More specifically, the conductive film 23 not only covers the surface of the dielectric film 22 in the portion located on the outermost side of the capacitance forming portion 20, but also covers the surface of the dielectric film 22 in the portion located inside the capacitance forming portion 20. Furthermore, the conductive film 23 covers the surface of the dielectric film 22 in the portion covering the side surface of the insulating substrate 10 and the surface of the dielectric film 22 in the portion covering the surface of the edge of the second main surface 10b.

[0033] The conductive film 23 can be made of various conductive materials, including metal materials whose main component is any of Ni, Cu, Ru, Al, W, Ti, Ag, Au, Zn, Ta, and Nb; alloy materials whose main components are two or more selected from these metal materials; metal nitrides such as TiN, TiAlN, TiSiN, TaN, NbN, and WN; metal oxynitrides such as TiON and TiAlON; conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)), polypyrrole, and polyaniline; and conductive oxide films such as RuO2, ZnO, (Zn,Al)O, and NiO.

[0034] The conductive film 23 can be preferably formed by CVD, ALD, PLD, plating, bias sputtering, sol-gel, a method using conductive polymer filling, or a method using supercritical fluid, and is particularly preferably formed by ALD. The conductive film 23 may also be configured as a laminated film consisting of multiple conductive layers made of different materials. In this case, a film can be formed by the ALD method and then another film can be formed by another method.

[0035] The thickness of the conductive film 23 is not particularly limited, but is preferably 3 nm or more, and more preferably 10 nm or more. In this embodiment, the conductive film 23 is made of TiN and has a thickness of approximately 25 nm.

[0036] 3 and 4, the outer periphery 20a of the capacitance forming portion 20 is covered with a conductive intervening film 40. More specifically, the intervening film 40 includes an outer portion 41 that does not penetrate into the internal space of the capacitance forming portion 20 and is located between the conductive film 23 and the plating portion 50, which defines the outer periphery 20a of the capacitance forming portion 20. As a result, the intervening film 40 is interposed between the capacitance forming portion 20 and the plating portion 50. Here, the "outer periphery of the capacitance forming portion" refers to the portion that surrounds the outside of the capacitance forming portion, and does not limit the shape of the capacitance forming portion to, for example, a cylindrical or spherical shape.

[0037] The intervening film 40 further includes an inner portion 42 positioned to extend into the internal space of the capacitance forming portion 20 .

[0038] By configuring the intervening film 40 in this way, it is possible to effectively prevent short circuits from occurring in the capacitance forming portion 20, the details of which will be described later.

[0039] In the thickness direction of the intervening film 40, it is preferable that the distance (see distance d1 in Figure 4) between the part of the outer portion 41 of the intervening film 40 that is in contact with the plated portion 50 and the outer periphery 20a of the capacitance forming portion 20 is 100 nm or more.

[0040] On the other hand, the distance in the thickness direction of the intervening film 40 between the part of the inner portion 42 of the intervening film 40 that penetrates deepest into the internal space of the capacitance forming portion 20 and the outer periphery 20a of the capacitance forming portion 20 (see distance d2 in FIG. 4) is preferably 15 μm or less. If this distance is considerably large, the film stress generated in the intervening film 40 will be large, which may cause the capacitance forming portion 20 to peel off from the insulating substrate 10.

[0041] The intervening film 40 can be made of various conductive materials, including metal materials primarily composed of any of Ni, Cu, Ru, Al, W, Ti, Ag, Au, Zn, Ta, and Nb, alloy materials primarily composed of two or more selected from these metal materials, metal nitrides such as TiN, TiAlN, TiSiN, TaN, NbN, and WN, metal oxynitrides such as TiON and TiAlON, conductive polymers such as PEDOT (poly(3,4-ethylenedioxythiophene)), polypyrrole, and polyaniline, and conductive oxide films such as RuO2, ZnO, (Zn,Al)O, and NiO. In this embodiment, the intervening film 40 is made of Cu.

[0042] The intervening film 40 can be preferably formed by a CVD method, an ALD method, a PLD method, a bias sputtering method, a sol-gel method, a method using conductive polymer filling, or a method using a supercritical fluid, and is particularly preferably formed by a CVD method.

[0043] The distances d1 and d2 are measured, for example, by observing a cross section perpendicular to the extending direction of the first main surface 10a of the insulating substrate 10 using a scanning ion microscope (SIM). A method for measuring the distance d1 will be described below with reference to Fig. 5. The distance d2 can be measured using a method similar to the method for measuring the distance d1.

[0044] When capacitor 1A is viewed from above, the longitudinal direction of capacitor 1A is Lx, the lateral direction is Ly, and the thickness direction of capacitor 1A (i.e., the normal direction to first main surface 10a) is Lz. First, capacitor 1A is polished so that the Lx-Lz cross section of capacitor 1A at the center in the Ly direction is exposed. The polishing is performed so that the exposed cross section is located within an error range of ±100 μm in the Ly direction from the center position.

[0045] Next, a portion of the exposed cross section near the outer periphery 20a of the capacitance forming portion 20 is observed using an SIM at a magnification of 50,000. The observation range of the cross section in the Lz direction is within a range of ±50 μm from the center position of the cross section in the Lz direction.

[0046] Next, in the observation range of the cross section, the distance between the portion of the outer portion 41 of the intervening film 40 that is in contact with the plating portion 50 and the outer peripheral portion 20a of the capacitance forming portion 20 in the thickness direction of the intervening film 40 is measured at 10 locations equally spaced in the Lz direction. When measuring at these 10 locations, the distance between adjacent measurement locations in the Lz direction should be 200 nm or more.

[0047] Next, of the 10 measured values ​​thus obtained, the maximum and second largest values, and the minimum and second smallest values ​​are excluded, and the average of the six measured values ​​is calculated. The average calculated in this manner becomes the distance d1 described above. Here, in Figure 5, three of the distances measured at these 10 locations are illustrated as line segment lengths da, db, and dc.

[0048] Although the measurement points described above are determined based on SIM images, the length measurement may be performed based on an image at a magnification of 200,000 times using a transmission electron microscope (TEM).

[0049] As shown in FIGS. 1 to 3, the plating portion 50 is provided on the outer peripheral portion 20a of the capacitance forming portion 20. As a result, the capacitance forming portion 20 is sealed by the insulating substrate 10 and the plating portion 50. The plating portion 50 defines an outer surface 50a located on the opposite side of the capacitance forming portion 20 from the insulating substrate 10. More specifically, the plating portion 50 is located so as to cover the upper and side surfaces of the capacitance forming portion 20, which is provided to face the first main surface 10a of the insulating substrate 10. As described above, the intervening film 40 is interposed between the capacitance forming portion 20 and the plating portion 50.

[0050] Plated portion 50 is also provided on the side surface of insulating substrate 10 and on part of second main surface 10b. More specifically, plated portion 50 is provided so as to cover most of the surface of conductive film 23 located on the side surface of insulating substrate 10 and on the surface of the edge of second main surface 10b. Capacitor 1A according to this embodiment is configured so that capacitance forming portion 20 can be electrically connected from plated portion 50 in a ring-shaped portion formed along the edge of second main surface 10b of insulating substrate 10.

[0051] That is, in this embodiment, the above-mentioned first bump 16 and the plating portion 50 formed in a ring shape along the edge of the second main surface 10b of the insulating substrate 10 define the bottom surface of the capacitor 1A, and this bottom surface is configured as a mounting surface for a wiring board, etc.

[0052] The plated portion 50 can be made of various conductive materials, but is preferably made of a metal material with particularly high electrical conductivity. The material of the plated portion 50 can be, for example, a metal material primarily made of any of Ni, Ag, Cu, Au, Pt, Mo, and W. In this embodiment, the plated portion 50 is made of Cu. The plated portion 50 can be formed by various plating methods.

[0053] The thickness and size of plating portion 50 are not particularly limited, and the size is set appropriately depending on the size of insulating substrate 10. Here, plating portion 50 preferably has a thickness of, for example, 0.5 μm or more and 50 μm or less, and its size is preferably such that it covers the entire first main surface 10a of insulating substrate 10.

[0054] The second external connection wiring, which is the other of the pair of external connection wirings for electrically connecting the capacitance forming portion 20 to an external circuit, is composed of the intervening film 40 and the plating portion 50 described above.

[0055] With the above configuration, in capacitor 1A according to this embodiment, electrical extraction of capacitance forming portion 20, which is made up of conductive porous metal body 21, dielectric film 22, and conductive film 23, is achieved by a pair of external connection wirings. More specifically, in capacitor 1A, first external connection wiring includes first via conductor 13 and first bump 16, and porous metal body 21 of capacitance forming portion 20 is connected to first via conductor 13. In addition, in capacitor 1A, second external connection wiring includes intervening film 40 and plating portion 50, and conductive film 23 of capacitance forming portion 20 is connected to plating portion 50 via intervening film 40.

[0056] Fig. 6 is a flow diagram showing a method for manufacturing a capacitor according to this embodiment. Figs. 7 to 12 are schematic cross-sectional views illustrating each step of the manufacturing flow shown in Fig. 6. Next, an example of a specific manufacturing method for manufacturing the capacitor 1A according to this embodiment described above will be described with reference to Figs. 6 to 12.

[0057] To manufacture the capacitor 1A according to this embodiment, first, in step S1, a green sheet is produced, as shown in Fig. 6. Specifically, Al2O3 powder and glass powder are weighed, and then these Al2O3 powder and glass powder are mixed with an organic solvent such as toluene or ethanol and a binder such as polyvinyl butyral. This mixture is then formed into a sheet, thereby producing a green sheet that will serve as the base for the insulating substrate.

[0058] Next, in step S2, first through holes are formed in the green sheet as shown in Fig. 6. Specifically, first through holes 11 are provided at predetermined positions in the green sheet, and the first through holes 11 will be filled later with first via conductors 13, which are part of the anodes.

[0059] Here, the method for forming the first through holes 11 is not particularly limited, but for example, the first through holes 11 can be formed by irradiating the green sheet with laser light. Additionally, the first through holes 11 may also be formed by processing using a mechanical puncher or sandblasting.

[0060] 6, in step S3, first via conductors are formed in the green sheet with the first through holes formed therein. Specifically, a conductive paste is applied to the green sheet so as to fill the first through holes 11.

[0061] Here, the method for applying the conductive paste is not particularly limited, but for example, a screen printing method can be used.

[0062] Next, in step S4, the green sheet coated with the conductive paste is fired, as shown in Fig. 6. The firing of the green sheet is carried out, for example, in an air atmosphere at a temperature of 700°C to 1000°C.

[0063] By going through the steps S1 to S4 described above, an insulating substrate as shown in FIG. 7 is obtained.

[0064] Although the above description has been given using an example in which the green sheet and the conductive paste are fired simultaneously, first via conductors 13 may be provided after firing an insulating substrate that does not have first through holes or the like. In this case, first through holes 11 may be provided in the fired insulating substrate by, for example, sandblasting, wet etching, dry etching, or the like, and then conductive paste may be applied and fired. Alternatively, first via conductors 13 may be formed by sputtering, vapor deposition, plating, or the like.

[0065] Next, in step S5, a porous metal body is formed as shown in Figures 6 and 8. In detail, a porous metal body 21 is formed on the first main surface 10a of the insulating substrate 10 as shown in Figure 8.

[0066] More specifically, conductive metal particles, an organic solvent such as terpineol, and an ethyl cellulose varnish are weighed and mixed, and a conductive paste is prepared from the mixture using a rolling mill. The conductive paste thus prepared is applied to the first main surface 10a of the insulating substrate 10 and dried.

[0067] At this time, the conductive paste is applied in multiple layers to a predetermined thickness on the first main surface 10a. The conductive paste is applied so as to have a rectangular pattern shape in plan view as a whole. Each layer of conductive paste applied on the first main surface 10a becomes the above-mentioned porous metal body 21.

[0068] Next, insulating substrate 10 after the conductive paste is applied is degreased, and then the conductive paste is fired in a reducing atmosphere, for example, a mixture of nitrogen and hydrogen, at a temperature of 400° C. to 900° C. As a result, adjacent metal particles contained in the conductive paste form necks, resulting in the formation of porous metal body 21.

[0069] The atmosphere during firing is preferably a reducing atmosphere as described above, but it may be set to an atmosphere below the equilibrium oxygen partial pressure of the metal selected as the main component of the metal porous body 21 .

[0070] Next, in step S6, a dielectric film is formed as shown in Figure 6 and Figure 9. In detail, as shown in Figure 9, a dielectric film 22 is formed so as to cover the first main surface 10a, the side surfaces, and the edge portion of the second main surface 10b of the insulating substrate 10, and the surface of the metal porous body 21.

[0071] Although there is no particular limitation on the method for forming the dielectric film 22, the ALD method is preferably used. The ALD method allows the raw materials for the dielectric film 22 to be supplied as gas, making it possible to select the material and adjust the film thickness at the atomic layer level.

[0072] When the dielectric film 22 is formed by the ALD method, it is preferable to use a source gas that has a high vapor pressure, is easy to gasify, has high thermal stability, and is highly reactive. x When forming a film, it is preferable to use TMA (trimethylaluminum) as a raw material. x When forming a film, it is preferable to use TDMAS (trisdimethylaminosilane) as a raw material. In this embodiment, the dielectric film 22 made of AlSiO is formed using the ALD method.

[0073] The dielectric film 22 is formed under temperature conditions of, for example, 150° C. or higher and 400° C. or lower, although this varies depending on the film formation method and film formation material.

[0074] 6 and 10, a conductive film is formed in step S7. More specifically, a conductive film 23 is formed so as to cover the dielectric film 22 formed in step S6.

[0075] The method for forming the conductive film 23 is not particularly limited, but preferably the ALD method is used. The ALD method allows the raw materials for the conductive film 23 to be supplied as gas, making it possible to select the material and adjust the film thickness at the atomic layer level. The conductive film 23 is formed at a temperature of 150° C. or higher and 600° C. or lower, for example, although this varies depending on the film formation method and film formation material. In this embodiment, the conductive film 23 made of TiN is formed using the ALD method.

[0076] By going through steps S5 to S7 described above, a capacitance forming portion 20 consisting of a conductive metal porous body 21, a dielectric film 22 and a conductive film 23 is formed on the first main surface 10a of the insulating substrate 10, as shown in Figure 10.

[0077] 6 and 11, an intervening film is formed in step S8. Specifically, the intervening film 40 is formed so as to cover the surface of the conductive film 23 in a portion that defines the outer periphery 20a of the capacitance forming portion 20 and to be positioned within the space inside the capacitance forming portion 20.

[0078] Although there are no particular limitations on the method for forming the intervening film 40, the CVD method is preferably used. In this embodiment, the intervening film 40 made of Cu is formed using the CVD method.

[0079] 6 and 12, a plated portion is formed in step S9. Specifically, plated portion 50 is formed on first main surface 10a of insulating substrate 10 on which capacitance forming portion 20 is provided, so as to cover capacitance forming portion 20. Plated portion 50 is also formed so as to cover the surface of conductive film 23 in a portion located on the side surface of insulating substrate 10 and most of the surface of conductive film 23 in a portion located on the edge of second main surface 10b. Plated portion 50 is formed by any of various plating methods, such as electrolytic plating.

[0080] By forming the plating portion 50 in this manner, the capacitance-forming portion 20 is sealed by the insulating substrate 10 and the plating portion 50. As a result, it is possible to prevent moisture from entering the capacitance-forming portion 20 from the outside, and moisture resistance can be ensured. In addition, the capacitance-forming portion 20 is covered by the plating portion 50, and the capacitance-forming portion 20 is also physically protected by the plating portion 50.

[0081] Next, in step S10, first bumps are formed on the insulating substrate as shown in Fig. 6. Specifically, first bumps 16 are formed on second main surface 10b of insulating substrate 10 so as to cover first via conductors 13 provided in insulating substrate 10 as shown in Fig. 3.

[0082] The first bumps 16 can be formed by, for example, electrolytic plating. In this case, the portions other than the vicinity of the portions where the first via conductors 13 are exposed are covered with an ultraviolet-curable resin film as a mask (not shown), and electrolytic plating is performed in this state, thereby forming the first bumps 16 so as to protrude from the second main surface 10b. After the electrolytic plating is completed, the ultraviolet-curable resin film as a mask is removed.

[0083] The method of forming the first bumps 16 is not limited to the above-mentioned method using electrolytic plating, but may also be a combination of a screen printing method using a conductive paste, an inkjet method, a dispenser method, or the like, and firing. Furthermore, the formation of the first bumps 16 may be performed after firing the green sheet (step S4) described above.

[0084] By going through the steps S1 to S10 described above, the capacitor 1A according to the first embodiment is manufactured.

[0085] In a capacitor including a capacitance forming portion 20 and a plating portion 50 that seals it, such as capacitor 1A according to the present embodiment, there is a risk that the plating solution used to form plating portion 50 may remain in the multiple minute spaces provided inside capacitance forming portion 20. If the plating solution remains in the spaces inside capacitance forming portion 20 in this way, the function of capacitor 1A may be impaired.

[0086] In this regard, in capacitor 1A according to this embodiment, as described above, conductive intervening film 40 is interposed between capacitance forming portion 20 and plating portion 50. This allows plating portion 50 to be configured to be out of contact with capacitance forming portion 20.

[0087] By configuring it in this manner, when forming the plating portion 50 during the manufacturing process of the capacitor 1A, the intervening film 40 acts as a physical obstacle, effectively preventing the plating solution from entering the internal space of the capacitance forming portion 20.

[0088] This prevents the capacitance forming portion 20 from peeling off from the insulating substrate 10 due to the plating solution remaining in the space inside the capacitance forming portion 20, or prevents the metal porous body 21 from dissolving, which could cause a short circuit in the capacitance forming portion 20. As a result, the loss of the capacitor's function due to such a short circuit is suppressed, and the capacitor 1A can be made to have improved reliability after mounting.

[0089] Therefore, by using capacitor 1A according to this embodiment, the reliability after mounting is improved in a capacitor having a capacitance forming portion consisting of a metal porous body, a dielectric film, and a conductive film, and a plated portion that seals it.

[0090] Furthermore, in capacitor 1A according to this embodiment, as described above, intervening film 40 includes not only outer portion 41 that does not penetrate into the internal space of capacitance forming portion 20 and is located between outer peripheral portion 20a of capacitance forming portion 20 and plating portion 50, but also inner portion 42 that penetrates into the internal space of capacitance forming portion 20. This more effectively prevents the plating solution from penetrating into the internal space of capacitance forming portion 20 described above.

[0091] Furthermore, in capacitor 1A according to the present embodiment, as described above, it is preferable that the distance in the thickness direction of intervening film 40 between the portion of outer portion 41 of intervening film 40 that is in contact with plating portion 50 and outer periphery 20a of capacitance forming portion 20 be 100 nm or more. By configuring in this manner, it is possible to more reliably prevent the plating solution from entering the internal space of capacitance forming portion 20 described above.

[0092] Furthermore, in capacitor 1A according to this embodiment, as described above, it is preferable that the distance in the thickness direction of intervening film 40 between the portion of inner portion 42 of intervening film 40 that penetrates deepest into the internal space of capacitance forming portion 20 and outer periphery 20a of capacitance forming portion 20 is 15 μm or less. By configuring in this manner, peeling of capacitance forming portion 20 from insulating substrate 10 due to film stress generated in intervening film 40 is more reliably suppressed, resulting in a capacitor with improved reliability after mounting.

[0093] In the capacitor 1A according to the present embodiment described above, an example has been given in which the capacitance forming portion 20 is electrically led out from the plating portion 50 that is formed in a ring shape along the edge of the second main surface 10b of the insulating substrate 10, but the capacitance forming portion 20 may be electrically led out from the outer surface 50a of the plating portion 50, or from the plating portion 50 that defines the side surface of the capacitor 1A.

[0094] In this way, by providing a plating portion 50 that seals the capacitance forming portion 20, as in the capacitor 1A of this embodiment, it is possible to dramatically improve the freedom in setting the direction in which the electrical extraction of the capacitance forming portion 20 is conducted.

[0095] (First Modification) 13 is a schematic cross-sectional view of a capacitor according to the first modification example. A capacitor 1A1 according to the first modification example based on the above-described first embodiment will now be described with reference to FIG.

[0096] As shown in FIG. 13, capacitor 1A1 according to the first modification differs from capacitor 1A according to the first embodiment described above in the configurations of dielectric film 22, conductive film 23, and plating portion 50.

[0097] More specifically, in capacitor 1A1 according to this modification, dielectric film 22, conductive film 23, and plating portion 50 are not provided on either the side surface or second main surface 10b of insulating substrate 10.

[0098] Therefore, in capacitor 1A1, capacitance forming portion 20 is electrically connected from first bump 16 and outer surface 50a of plating portion 50. Alternatively, capacitance forming portion 20 may be electrically connected from first bump 16 and plating portion 50 that defines the side surface of capacitor 1A1. That is, in capacitor 1A1, the bottom and top surfaces of capacitor 1A1 are configured as mounting surfaces for a wiring board or the like, or alternatively, the bottom and side surfaces of capacitor 1A1 are configured as mounting surfaces for a wiring board or the like.

[0099] Even when configured in this manner, the same effects as those described in the first embodiment can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a metal porous body, a dielectric film, and a conductive film, and a plated portion that seals it.

[0100] The capacitor 1A1 according to the first modified example can be manufactured basically in accordance with the manufacturing method of the capacitor 1A according to the first embodiment described above.

[0101] (Second Modification) 14 is a schematic cross-sectional view of a capacitor according to the second modification example. A capacitor 1A2 according to the second modification example based on the first embodiment will now be described with reference to FIG.

[0102] As shown in FIG. 14, a capacitor 1A2 according to the second modification is different from the capacitor 1A according to the first embodiment described above in the configurations of the capacitance forming portion 20 and the second external connection wiring.

[0103] More specifically, in the capacitor 1A2 according to this modification, a through-hole 20c is provided in the capacitance forming portion 20. The through-hole 20c penetrates the capacitance forming portion 20 so as to reach from one end to the other end in the height direction of the capacitance forming portion 20.

[0104] The through hole 20c is filled with a plated portion 50. An intervening film 40 is interposed between the plated portion 50 that is filled in the through hole 20c and the capacitance forming portion 20 that defines the through hole 20c.

[0105] Furthermore, in the capacitor 1A2 according to this modified example, the second external connection wiring includes, in addition to the intervening film 40 and the plated portion 50 described above, a second via conductor 14 and a second bump 17 provided on the insulating substrate 10.

[0106] More specifically, when capacitor 1A2 is viewed from above, insulating substrate 10 has a second through hole 12 in a portion that overlaps with plated portion 50 embedded in through hole 20c. Second through hole 12 penetrates insulating substrate 10 so as to reach second main surface 10b from first main surface 10a.

[0107] The second through hole 12 is filled with a second via conductor 14. The shape of the second via conductor 14 is, for example, a substantially cylindrical shape. The material, shape, etc. of the second via conductor 14 are configured similarly to the first via conductor 13 described above, for example.

[0108] Second bumps 17 are provided on the second main surface 10b of the insulating substrate 10 so as to cover the second via conductors 14. The second bumps 17 are provided so as to protrude from the second main surface 10b of the insulating substrate 10. The shape of the second bumps 17 is generally semispherical. The material, shape, etc. of the second bumps 17 are configured similarly to those of the first bumps 16 described above, for example.

[0109] That is, in this modified example, first bump 16 and second bump 17 define the bottom surface of capacitor 1A2, and this bottom surface is configured as a mounting surface for a wiring board or the like.

[0110] Even when configured in this manner, the same effects as those described in the first embodiment can be obtained, and the reliability after mounting can be improved in a capacitor having a capacitance forming portion consisting of a metal porous body, a dielectric film, and a conductive film, and a plated portion that seals it.

[0111] The capacitor 1A2 according to the second modification can be manufactured basically in accordance with the manufacturing method of the capacitor 1A according to the first embodiment described above.

[0112] As an example, the second through hole is formed simultaneously with the above-described step S2 (forming the first through hole). The second via conductor is formed simultaneously with step S3 (forming the first via conductor). After step S7 and before step S8 (after forming the conductive film and before forming the intervening film), a through hole is provided in the capacitance-forming portion. In step S8, the intervening film is formed so as to cover the portion of the capacitance-forming portion that defines the through hole. In step S9, plating portion 50 is formed so as to fill through hole 20c as well.

[0113] By manufacturing the capacitor 1A2 in the manner described above, as described above, the intervening film 40 is also interposed between the plating portion 50 embedded in the through hole 20c and the capacitance forming portion 20 that defines the through hole 20c.

[0114] (Embodiment 2) Fig. 15 is a schematic cross-sectional view of a capacitor according to embodiment 2. Fig. 16 is an enlarged cross-sectional view of a main part of region XVI of the capacitor shown in Fig. 15. Hereinafter, a capacitor 1B according to this embodiment will be described with reference to Figs. 15 and 16.

[0115] As shown in FIGS. 15 and 16, capacitor 1B according to this embodiment differs from capacitor 1A according to the first embodiment described above in the configuration of capacitance forming portion 20.

[0116] More specifically, in the capacitor 1B according to this embodiment, the capacitance forming portion 20 further includes a water-repellent film 24. As will be described in detail later, depending on the electrical properties of the water-repellent film 24, the water-repellent film 24 may cover only the portion of the conductive film 23 that defines the internal space of the capacitance forming portion 20, or may additionally cover the portion of the conductive film 23 that defines the outer periphery 20a of the capacitance forming portion 20. In this embodiment, the insulating water-repellent film 24 covers only the portion of the conductive film 23 that defines the internal space of the capacitance forming portion 20.

[0117] The water-repellent film 24 may be made of an insulating material or a conductive material. When an insulating water-repellent film 24 is used, the water-repellent film 24 may be made of a material such as a silane coupling agent or an organic fluorine compound. When a conductive water-repellent film 24 is used, the water-repellent film 24 may be made of a material such as a fluoride compound. In this embodiment, an insulating water-repellent film 24 made of a silane coupling agent is used.

[0118] The method for forming the water-repellent film 24 is not particularly limited, but is preferably formed by an impregnation method. The thickness of the water-repellent film 24 is not particularly limited, but is preferably 10 nm or more and 1 μm or less.

[0119] When the capacitance forming portion 20 includes the water-repellent film 24 in this manner, the distance in the thickness direction of the intervening film 40 between the portion of the outer portion 41 of the intervening film 40 that is in contact with the plating portion 50 and the outer peripheral portion 20a of the capacitance forming portion 20 (see distance d1 in FIG. 4 ) may be configured to be smaller than the distance when the capacitance forming portion 20 does not include the water-repellent film 24, as in the capacitor 1A according to the first embodiment described above. This is because the water-repellent film 24, like the intervening film 40, has the function of suppressing the intrusion of the plating solution into the internal space of the capacitance forming portion 20. Therefore, in this embodiment, the distance is preferably 50 nm or more.

[0120] Fig. 17 is a flow diagram showing a method for manufacturing the capacitor according to embodiment 2. Next, with reference to Fig. 17, an example of a specific method for manufacturing the capacitor 1B according to the present embodiment described above will be described.

[0121] 17, the manufacturing method of capacitor 1B is largely similar to the manufacturing method of capacitor 1A. Therefore, in the following, a description of the steps in the manufacturing method of capacitor 1B that are common to the manufacturing method of capacitor 1A will be omitted, and only the steps that are different from the manufacturing method of capacitor 1A will be described.

[0122] 17, after the conductive film is formed in step S8, a water-repellent film is formed in step S8B. More specifically, an insulating water-repellent film 24 is formed so as to cover only the portion of the conductive film 23 that defines the internal space of the capacitance forming portion 20.

[0123] Here, when the water-repellent film 24 has insulating properties, it is preferable that the water-repellent film 24 is formed so as not to cover the conductive film 23 in the portion that defines the outer periphery 20a of the capacitance forming portion 20. The conductive film 23, the water-repellent film 24, and the conductive intervening film 40 are stacked in this order to form a so-called MIM (Metal Insulator Metal) structure, which prevents an unintended capacitance forming portion from being formed in the capacitor 1B.

[0124] Therefore, in step S8B, it is preferable to form the water-repellent film 24 after applying a mask to the conductive film 23 in the portion that defines the outer periphery 20a of the capacitance forming portion 20, or to form the water-repellent film 24 while controlling the penetration depth of the water-repellent film 24 to a desired depth. This makes it possible to form the insulating water-repellent film 24 so as to cover only the portion of the conductive film 23 that defines the internal space of the capacitance forming portion 20.

[0125] The capacitor 1B of this embodiment configured in this manner also achieves the same effects as those described in the first embodiment above, and improves reliability after mounting in a capacitor having a capacitance forming portion consisting of a metal porous body, a dielectric film, and a conductive film, and a plated portion that seals it.

[0126] Furthermore, when configured in this manner, when forming the plating portion 50 during the manufacturing process of the capacitor 1B, not only can the intervening film 40 act as a physical obstacle to prevent the plating solution from penetrating into the internal space of the capacitance forming portion 20, but the water-repellent properties of the water-repellent film 24 can also prevent the plating solution from penetrating.

[0127] In the above-described embodiment, the capacitance forming portion 20 is described as including an insulating water-repellent film 24, but as described above, the water-repellent film 24 may be conductive.

[0128] In this case, the water-repellent film 24 may be formed so as to cover not only the conductive film 23 in the portion that defines the internal space of the capacitance forming portion 20, but also the conductive film 23 in the portion that defines the outer periphery 20a of the capacitance forming portion 20. This is because, if the water-repellent film 24 is conductive, an unintended capacitance forming portion as described above will not be formed in the capacitor 1B.

[0129] (Addendum) The characteristic configurations of the capacitors disclosed in the above-described embodiments and their modifications can be summarized as follows.

[0130] [Appendix 1] an insulating substrate having a main surface; a capacitance forming portion provided on the main surface; a first external connection wiring and a second external connection wiring connected to the capacitance forming portion; the capacitance forming portion includes a conductive metal porous body connected to the first external connection wiring, a dielectric film covering a surface of the metal porous body, and a conductive film covering the dielectric film and connected to the second external connection wiring, the second external connection wiring includes a conductive plating portion provided on the outer periphery of the capacitance forming portion, and a conductive intervening film interposed between the capacitance forming portion and the plating portion, The capacitance forming portion is sealed by the insulating substrate and the plating portion.

[0131] [Appendix 2] A capacitor as described in Appendix 1, wherein the intervening film includes an inner portion that extends into the internal space of the capacitance forming portion, and an outer portion that does not extend into the internal space of the capacitance forming portion and is located between the outer periphery of the capacitance forming portion and the plating portion.

[0132] [Appendix 3] A capacitor as described in Appendix 2, wherein the distance in the thickness direction of the intervening film between the part of the inner part of the intervening film that penetrates deepest into the internal space of the capacitance forming portion and the outer periphery of the capacitance forming portion is 15 μm or less.

[0133] [Appendix 4] A capacitor described in Appendix 2 or 3, wherein the distance in the thickness direction of the intervening film between the portion of the outer part of the intervening film that is in contact with the plated portion and the outer periphery of the capacitance forming portion is 100 nm or more.

[0134] [Appendix 5] the capacitance forming portion further includes an insulating water-repellent film, 4. The capacitor according to claim 2, wherein the water-repellent film covers only a portion of the conductive film that defines the internal space of the capacitance forming portion.

[0135] [Appendix 6] the capacitance forming portion further includes a conductive water-repellent film, 4. The capacitor according to claim 2, wherein the water-repellent film covers at least a portion of the conductive film that defines the internal space of the capacitance forming portion.

[0136] [Appendix 7] A capacitor described in Appendix 5 or 6, wherein the distance in the thickness direction of the intervening film between the portion of the outer part of the intervening film that is in contact with the plating portion and the outer periphery of the capacitance forming portion is 50 nm or more.

[0137] (Other forms, etc.) The shape, configuration, size, number, material, etc. of each part shown in the above-described embodiment of the present invention can be changed in various ways without departing from the spirit of the present invention.

[0138] Furthermore, the characteristic configurations shown in the above-described embodiments of the present invention can naturally be combined with each other within the scope permitted in light of the spirit of the present invention.

[0139] As such, the above-described embodiments disclosed herein are illustrative in all respects and are not restrictive. The technical scope of the present invention is defined by the claims, and includes all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0140] 1A, 1A1, 1A2, 1B capacitor, 10 insulating substrate, 10a first main surface, 10b second main surface, 11 first through hole, 12 second through hole, 13 first via conductor, 14 second via conductor, 16 first bump, 17 second bump, 20 capacitance forming portion, 20a outer peripheral portion, 20c through hole, 21 metal porous body, 22 dielectric film, 23 conductive film, 24 water-repellent film, 40 intervening film, 41 outer portion, 42 inner portion, 50 plated portion, 50a outer surface.

Claims

1. an insulating substrate having a main surface; a capacitance forming portion provided on the main surface; a first external connection wiring and a second external connection wiring connected to the capacitance forming portion; the capacitance forming portion includes a conductive metal porous body connected to the first external connection wiring, a dielectric film covering a surface of the metal porous body, and a conductive film covering the dielectric film and connected to the second external connection wiring; the second external connection wiring includes a conductive plating portion provided on an outer periphery of the capacitance forming portion, and a conductive intervening film interposed between the capacitance forming portion and the plating portion, the capacitance forming portion is sealed by the insulating substrate and the plating portion, the intervening film includes an inner portion located in the space inside the capacitance forming portion, and an outer portion located between the outer periphery of the capacitance forming portion and the plating portion without entering the space inside the capacitance forming portion, the capacitance forming portion further includes an insulating water-repellent film, A capacitor, wherein the water-repellent film covers only a portion of the conductive film that defines the internal space of the capacitance forming portion.

2. The capacitor described in claim 1, wherein the distance in the thickness direction of the intervening film between the part of the inner portion of the intervening film that penetrates deepest into the internal space of the capacitance forming portion and the outer periphery of the capacitance forming portion is 15 μm or less.

3. 2. The capacitor according to claim 1, wherein the distance in the thickness direction of the intervening film between the portion of the outer portion of the intervening film that is in contact with the plating portion and the outer periphery of the capacitance forming portion is 50 nm or more.

4. 4. The capacitor according to claim 3, wherein the distance in the thickness direction of the intervening film between the portion of the outer portion of the intervening film that is in contact with the plating portion and the outer periphery of the capacitance forming portion is 100 nm or more.

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