Semiconductor Devices

Abstract

To provide a semiconductor device capable of suppressing signal delay and performing product-sum operation in parallel.SOLUTION: A semiconductor device comprises first through fourth registers, an adder, a multiplier, a selector and a first storage section. The first register has an output terminal electrically connected to an input terminal of the second register, and the second register has an output terminal electrically connected to a first input terminal of the multiplier. The multiplier has an output terminal electrically connected to a first input terminal of the adder, and the adder has an output terminal electrically connected to an input terminal of the third register. The third register has an output terminal electrically connected to a first input terminal of the selector, and the selector has an output terminal electrically connected to an input terminal of the fourth register, and the first storage section is electrically connected to a second input terminal of the multiplier. The first storage section has a function to read out first data matched with a context signal inputted to the first storage section and input the same to the second input terminal of the multiplier.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to an arithmetic circuit, a semiconductor device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] Currently, active development is underway on integrated circuits that mimic the workings of the human brain. These integrated circuits incorporate the workings of the brain as electronic circuits, and have circuits that correspond to the "neurons" and "synapses" of the human brain. For this reason, such integrated circuits are sometimes called "neuromorphic," "brain-morphic," or "brain-inspired." These integrated circuits have a non-von Neumann architecture, and are expected to be able to perform parallel processing with significantly less power consumption than von Neumann architectures, which consume more power as processing speed increases.

[0004] An information processing model that mimics a neural network with "neurons" and "synapses" is called an artificial neural network (ANN). By using an artificial neural network, it is possible to make inferences with accuracy comparable to or even exceeding that of humans. In a neural network, the main operation is the weighted sum of neuron outputs, i.e., the sum-of-products operation.

[0005] Since optimal values ​​such as the depth of the hierarchy and the number of neuron elements of the artificial neural network vary depending on the problem that the artificial neural network is intended to address, it is preferable to construct an artificial neural network that is suited to the problem. For example, Patent Document 1 discloses a semiconductor device that has programmable logic elements and switches between conductive and non-conductive states between circuits according to multiple contexts, thereby performing product-sum operations with a circuit scale suited to the desired artificial neural network. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2018-110386 Summary of the Invention [Problem to be solved by the invention]

[0007] In recent years, there has been a great deal of development in artificial intelligence, and the "inference" (sometimes called "cognition") performed by artificial intelligence is derived from the results of calculations in artificial neural networks. In order for artificial intelligence to solve complex problems, it is necessary to increase the scale of the artificial neural network. In other words, it is necessary to take measures such as deepening the layers of the artificial neural network or increasing the number of neuron elements contained in each layer.

[0008] When implementing a product-sum operation circuit as an operation of an artificial neural network, it is preferable to arrange the product-sum operation circuit with a high degree of parallelism. On the other hand, as the scale of the artificial neural network increases, the number of parallel product-sum operation circuits also increases. In this case, the wiring distance in the circuit layout may become long depending on the arrangement of the input terminals and output terminals of the parallel product-sum operation circuits, the buffer memory for storing the operation results, etc. As the wiring distance becomes longer, the parasitic resistance of the wiring and the parasitic capacitance with other surrounding wiring or elements also increase, which may delay the signal transmitted through the wiring and reduce the operating speed of the product-sum operation circuit.

[0009] An object of one embodiment of the present invention is to provide a novel arithmetic circuit. Alternatively, an object of one embodiment of the present invention is to provide a semiconductor device that includes the above arithmetic circuit, thereby suppressing signal delay and capable of performing product-sum operations in parallel.

[0010] Another object of one embodiment of the present invention is to provide a novel semiconductor device or an electronic device including the semiconductor device.

[0011] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0012] (1) One aspect of the present invention is an arithmetic circuit including a first register, a second register, a third register, a fourth register, an adder, a multiplier, a selector, and a first storage unit. An output terminal of the first register is electrically connected to an input terminal of the second register, and the output terminal of the second register is electrically connected to a first input terminal of the multiplier. An output terminal of the multiplier is electrically connected to a first input terminal of the adder, an output terminal of the adder is electrically connected to an input terminal of the third register, an output terminal of the third register is electrically connected to a first input terminal of the selector, and an output terminal of the selector is electrically connected to an input terminal of the fourth register. The first storage unit is electrically connected to a second input terminal of the multiplier, and has a function of reading out first data corresponding to a context signal input to the first storage unit and inputting the first data to the second input terminal of the multiplier.

[0013] (2) Another embodiment of the present invention is a semiconductor device including a first arithmetic circuit and a second arithmetic circuit. The second arithmetic circuit has the same circuit configuration as the first arithmetic circuit. The first arithmetic circuit includes a first storage unit, a first register, a second register, a third register, a first terminal, a second terminal, a third terminal, and a fourth terminal. In the first arithmetic circuit, an input terminal of the first register is electrically connected to the first terminal, an output terminal of the first register is electrically connected to an input terminal of the second register and the second terminal, and an output terminal of the third register is electrically connected to the fourth terminal. The first arithmetic circuit has a function of reading first data corresponding to the context signal from the first storage unit when a context signal is input to the first storage unit. The first arithmetic circuit also has a function of holding second data input to the first terminal in the first register or the second register. The first arithmetic circuit has a function of multiplying the first data by the second data held in the second register to generate third data, a function of adding the third data and fourth data input from the third terminal to generate sum data, and a function of holding the sum data in the third register. The first arithmetic circuit has a function of outputting the second data held in the first register to the second terminal and inputting it to the first terminal of the second arithmetic circuit, and a function of outputting the sum data held in the third register to the fourth terminal and inputting the sum data as the fourth data to the third terminal of the second arithmetic circuit.

[0014] (3) Alternatively, according to one embodiment of the present invention, the circuit configuration of (2) may further include an input register and a second storage unit. The second storage unit is electrically connected to an input terminal of the input register. The second storage unit has a function of reading out second data and inputting the second data from an output terminal of the input register to a first terminal of the first arithmetic circuit via the input register.

[0015] (4) Alternatively, one aspect of the present invention may include a third arithmetic circuit having the same circuit configuration as the first arithmetic circuit in the configuration (3), and each of the first arithmetic circuit and the third arithmetic circuit may include a selector, a fourth register, a fifth terminal, and a sixth terminal. In each of the first arithmetic circuit and the third arithmetic circuit, a first input terminal of the selector is electrically connected to an output terminal of the third register, a second input terminal of the selector is electrically connected to the fifth terminal, an output terminal of the selector is electrically connected to an input terminal of the fourth register, the output terminal of the fourth register is electrically connected to the sixth terminal, and the fifth terminal of the first arithmetic circuit is electrically connected to the sixth terminal of the third arithmetic circuit.

[0016] (5) Alternatively, in one embodiment of the present invention, the configuration (4) may further include a circuit that performs an activation function calculation on data output from the sixth terminal of the first arithmetic circuit or the third arithmetic circuit, and stores the result of the calculation in a second storage unit.

[0017] (6) Alternatively, according to one embodiment of the present invention, in the configurations (2) to (5) above, a plurality of first switches and a plurality of second switches may be provided, wherein the second terminal of the first arithmetic circuit is electrically connected to the first terminal of the second arithmetic circuit via the plurality of first switches, and the third terminal of the first arithmetic circuit is electrically connected to the fourth terminal of the second arithmetic circuit via the plurality of second switches.

[0018] (7) Another embodiment of the present invention is an electronic device including the semiconductor device according to any one of (2) to (6) above and a housing, wherein the electronic device has a function of performing neural network calculations using the semiconductor device.

[0019] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, or an electronic component in which a chip is housed in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. are themselves semiconductor devices and may include semiconductor devices.

[0020] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0021] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0022] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0023] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0024] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0025] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0026] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element, wiring, or the like having a resistance value higher than 0 Ω. Therefore, in this specification and the like, a "resistance element" is intended to include wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can be replaced with terms such as "resistance," "load," or "region having a resistance value," and conversely, the terms "resistance," "load," or "region having a resistance value" can be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0027] Furthermore, in this specification, the term "capacitive element" can refer to, for example, a circuit element having a capacitance value greater than 0 F, a region of wiring having a capacitance value, parasitic capacitance, or the gate capacitance of a transistor. Therefore, in this specification, the term "capacitive element" includes not only a circuit element including a pair of electrodes and a dielectric between the electrodes, but also a parasitic capacitance appearing between wiring and one of the source or drain of a transistor and the gate, and the like. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can be replaced with terms such as "capacitance," and conversely, the term "capacitance" can be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," or "pair of regions." The capacitance value can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0028] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain are interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0029] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0030] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0031] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0032] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positive carriers move and is expressed as a positive current amount. In other words, the direction in which negative carriers move is opposite to the direction of current and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive / negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0033] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0034] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "insulator located on the upper surface of a conductor" can be rephrased as "insulator located on the lower surface of a conductor" by rotating the orientation of the drawing 180 degrees.

[0035] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0036] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0037] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0038] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0039] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in defect level density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (including water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0040] In this specification and the like, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific one as long as it can control a current.

[0041] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0042] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0043] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0044] According to one embodiment of the present invention, a novel arithmetic circuit can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device including the arithmetic circuit can be provided in which signal delay can be suppressed and product-sum operations can be performed in parallel.

[0045] According to one embodiment of the present invention, a novel semiconductor device or the like can be provided. Alternatively, according to one embodiment of the present invention, an electronic device including the semiconductor device can be provided.

[0046] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0047] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 2] FIG. 2 is a block diagram showing an example of the configuration of a semiconductor device. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 4] FIG. 4 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 5] FIG. 5 is a block diagram showing an example of the configuration of a circuit included in the semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a CNN. [Figure 7] FIG. 7 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 8]FIG. 8 is a timing chart showing an example of the operation of the semiconductor device. [Figure 9] FIG. 9A is a diagram for explaining filter values ​​included in a filter, and FIG. 9B is a block diagram showing the filter values ​​read into the arithmetic circuit. [Figure 10] FIG. 10A is a diagram illustrating pixel data included in image data, and FIG. 10B is a diagram illustrating pixel data input to an arithmetic circuit. [Figure 11] FIG. 11 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 12] 12A and 12B are diagrams for explaining pixel data input to the arithmetic circuit. [Figure 13] FIG. 13 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 14] FIG. 14 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 15] FIG. 15 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 16] FIG. 16 is a diagram for explaining pixel data input to the arithmetic circuit. [Figure 17] FIG. 17 is a diagram illustrating the calculation results output from the calculation circuit. [Figure 18] FIG. 18 is a diagram illustrating image data (feature map) in which only characteristic parts are extracted by a filter. [Figure 19] 19A and 19B are block diagrams showing examples of the configuration of circuits included in a semiconductor device. [Figure 20] FIG. 20 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 21] FIG. 21 is a timing chart showing an example of the operation of the semiconductor device. [Figure 22] 22A and 22B are diagrams for explaining pixel data input to the arithmetic circuit. [Figure 23] FIG. 23 is a diagram illustrating the filter value read out to the arithmetic circuit. [Figure 24] 24A to 24C are diagrams for explaining the calculation results output from the calculation circuit. [Figure 25] FIG. 25 is a block diagram showing an example of the configuration of a circuit included in a semiconductor device. [Figure 26] FIG. 26 is a diagram for explaining neuron signals input to the arithmetic circuit and weighting coefficients read out to the arithmetic circuit. [Figure 27] 27A to 27C are circuit diagrams showing examples of the configuration of a memory cell included in a memory circuit. [Figure 28] FIG. 28 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 29] FIG. 29 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 30] 30A to 30C are cross-sectional views showing examples of the structure of a transistor. [Figure 31] 31A and 31B are cross-sectional views showing examples of the structure of a transistor. [Figure 32] FIG. 32 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 33] 33A and 33B are cross-sectional views showing examples of the structure of a transistor. [Figure 34] FIG. 34 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 35] FIG. 35A is a top view showing an example of the configuration of a capacitor, and FIGS. 35B and 35C are cross-sectional perspective views showing the example of the configuration of a capacitor. [Figure 36] FIG. 36A is a top view showing an example of the configuration of a capacitor, FIG. 36B is a cross-sectional view showing the example of the configuration of a capacitor, and FIG. 36C is a cross-sectional perspective view showing the example of the configuration of a capacitor. [Figure 37] FIG. 37A is a diagram illustrating the classification of IGZO crystal structures, FIG. 37B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 37C is a diagram illustrating the micro-electron diffraction pattern of crystalline IGZO. [Figure 38]FIG. 38A is a perspective view showing an example of a semiconductor wafer, FIG. 38B is a perspective view showing an example of a chip, and FIGS. 38C and 38D are perspective views showing an example of an electronic component. [Figure 39] FIG. 39 is a perspective view showing an example of an electronic device. [Figure 40] 40A to 40C are perspective views showing an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0048] In an artificial neural network (hereafter referred to as a neural network), the strength of synaptic connections can be changed by providing existing information to the neural network. This process of providing existing information to a neural network and determining connection strengths is sometimes called "learning."

[0049] Furthermore, by providing some information to a neural network that has undergone "learning" (with connection strengths determined), new information can be output based on the connection strengths. In this way, the process of outputting new information based on the provided information and connection strengths in a neural network is sometimes called "inference" or "cognition."

[0050] Neural network models include, for example, Hopfield and hierarchical types. In particular, neural networks with multi-layer structures are sometimes called "deep neural networks" (DNNs), and machine learning using deep neural networks is sometimes called "deep learning."

[0051] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when a metal oxide is referred to as an OS FET or an OS transistor, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0052] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0053] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0054] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0055] Note that the content described in the embodiments refers to the content described in each embodiment (or example) using various figures, or the content described using text in the specification.

[0056] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0057] The embodiments described in this specification will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0058] In this specification, when the same symbol is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as “_1”, “[n]”, or “[m,n]” may be added to the symbol.

[0059] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0060] (Embodiment 1) In this embodiment, a configuration of a digital arithmetic circuit, which is a semiconductor device of one embodiment of the present invention, will be described.

[0061] 1 is a block diagram showing an example configuration of a calculation device 100. The calculation device 100 includes a control circuit CTLR, a MAC (Multiply-Accumulate) array MAR, a memory unit MEMD, and circuits AF[1] to AF[v] (v is an integer equal to or greater than 2).

[0062] As an example, the MAC array MAR has a plurality of arithmetic circuits MA, and the arithmetic circuits MA are arranged in a u x v matrix (u is an integer equal to or greater than 2) in the MAC array MAR. That is, the MAC array MAR has u x v arithmetic circuits MA. In FIG. 1, symbols [, ] are used to indicate the positions at which the arithmetic circuits MA are arranged. For example, the arithmetic circuit MA located in row 1, column 1 is written as arithmetic circuit MA[1,1], and the arithmetic circuit MA located in row u, column v is written as arithmetic circuit MA[u,v].

[0063] The arithmetic circuit MA has, for example, a MAC function. Specifically, the arithmetic circuit MA has a function of performing a product-sum operation between first data (e.g., w[1] to w[m], where m is a positive integer) and second data (e.g., x[1] to x[m]). Note that, for example, the first data can be one of multiplier data or multiplicand data, and the second data can be the other of the multiplier data or multiplicand data. Furthermore, for example, when performing an operation on a hierarchical neural network in the arithmetic device 100, the first data can be a weight coefficient and the second data can be a value of an output signal of a neuron, thereby calculating the product-sum of the weight coefficient and the value of the output signal of a neuron.

[0064] The MAC array MAR also has a plurality of programmable switches PR and a plurality of programmable switches PC. In Fig. 1, one of the plurality of programmable switches PR is electrically connected to one of the plurality of arithmetic circuits MA, and one of the plurality of programmable switches PC is electrically connected to one of the plurality of arithmetic circuits MA. Therefore, in Fig. 1, as with the arithmetic circuits MA, the symbols for the programmable switches PR and PC are marked with [, ] to indicate their positions.

[0065] The number of wirings electrically connected between the arithmetic circuit MA and the programmable switch PR may be one or more. The number of wirings electrically connected between the arithmetic circuit MA and the programmable switch PC may be one or more. In other words, the number of wirings electrically connecting the programmable switch PR and the programmable switch PC to the arithmetic circuit MA can be determined depending on the number of terminals of the arithmetic circuit MA.

[0066] The programmable switches PR[1,1] through PR[1,v] located in the first row of the MAC array MAR are electrically connected in series. Similarly, the programmable switches PR[2,1] through PR[2,v] located in the second row of the MAC array MAR are electrically connected in series, and the programmable switches PR[u,1] through PR[u,v] located in the u-th row of the MAC array MAR are electrically connected in series.

[0067] Furthermore, the programmable switches PC[1,1] through PC[u,1] located in the first column of the MAC array MAR are electrically connected in series. Similarly, the programmable switches PC[1,2] through PC[u,2] located in the second column of the MAC array MAR are electrically connected in series, and the programmable switches PC[1,v] through PC[u,v] located in the v-th column of the MAC array MAR are electrically connected in series.

[0068] For example, the programmable switches PR[1,1] to PR[u,1] are electrically connected to wirings XL[1] to XL[u], respectively. Also, the programmable switches PC[u,1] to PC[u,v] are electrically connected to wirings YL[1] to YL[v], respectively.

[0069] For example, each of the wirings XL[1] to XL[u] is electrically connected to the memory unit MEMD via a plurality of registers RG. Also, for example, each of the wirings YL[1] to YL[v] is electrically connected to the memory unit MEMD.

[0070] The memory unit MEMD has a function of holding, for example, second data to be input to the MAC array MAR via the wirings XL[1] to XL[u] in order to execute a multiply-and-accumulate operation between the first data and the second data in the MAC array MAR, and also has a function of holding, for example, the result of the multiply-and-accumulate operation between the first data and the second data sent from the MAC array MAR via the wirings YL[1] to YL[v].

[0071] A plurality of registers RG electrically connected to the wirings XL[1] to XL[u], respectively, are provided to perform pipeline processing in the arithmetic device 100. Specifically, for example, in FIG. 1, the plurality of registers RG are provided with registers RG[1,1] to RG[1,p] (p is an integer equal to or greater than 1) on the wiring XL[1] between the programmable switch PR[1,1] of the MAC array MAR and the memory unit MEMD. Note that, among the registers RG[1,1] to RG[1,p], the input terminal and the output terminal of the adjacent registers RG are electrically connected, and the input terminal of the register RG[1,1] is electrically connected to the memory unit MEMD, and the output terminal of the register RG[1,p] is electrically connected to the programmable switch PR[1,1].

[0072] Similarly, registers RG[2,1] to RG[2,p] are provided on the wiring XL[2] between the programmable switch PR[2,1] of the MAC array MAR and the memory unit MEMD. The input terminals and output terminals of the registers RG[2,1] to RG[2,p] are electrically connected to each other in the adjacent registers RG. The input terminal of the register RG[2,1] is electrically connected to the memory unit MEMD, and the output terminal of the register RG[2,p] is electrically connected to the programmable switch PR[2,1]. The wiring XL[u] between the programmable switch PR[u,1] of the MAC array MAR and the memory unit MEMD is provided with registers RG[u,1] to RG[u,p]. In addition, the input terminals and output terminals of adjacent registers RG from register RG[u,1] to register RG[u,p] are electrically connected, and the input terminal of register RG[u,1] is electrically connected to the memory unit MEMD, and the output terminal of register RG[u,p] is electrically connected to the programmable switch PR[u,1].

[0073] As an example, the register RG has a function of temporarily holding data (for example, digital data, or in some cases, an electric potential) provided to the input terminal of the register RG when a pulse voltage is provided as a clock signal provided to the register RG. Furthermore, as an example, the register RG has a function of outputting the data held in the register RG to the output terminal of the register RG. In this specification, the register RG is assumed to temporarily hold the data provided to the input terminal of the register RG and output first data to the output terminal of the register RG when a high-level electric potential is provided as a clock signal. Therefore, the register RG functions as an input register for transmitting the first data to the MAC array MAR.

[0074] The clock signal may be, for example, a signal sent over a line CKL, which will be described later.

[0075] The register RG preferably holds, for example, 8-bit data, more preferably 16-bit data, and even more preferably 32-bit or more data.

[0076] Incidentally, for example, the registers RG[1,1] through RG[1,p] between the programmable switch PR[1,1] and the memory unit MEMD may be replaced with a single shift register. Similarly, for example, the registers RG[2,1] through RG[2,p] between the programmable switch PR[2,1] and the memory unit MEMD may also be replaced with a single shift register, and the registers RG[u,1] through RG[u,p] between the programmable switch PR[u,1] and the memory unit MEMD may also be replaced with a single shift register.

[0077] As described above, data transmission from the memory unit MEMD to the MAC array MAR can be pipelined by electrically connecting multiple registers RG in series between the memory unit MEMD and the MAC array MAR as shown in Figure 1. Furthermore, connecting multiple registers RG in series can suppress delays in signals for transmitting data that are caused by parasitic resistance and parasitic capacitance.

[0078] The control circuit CTLR is electrically connected to the MAC array MAR. The control circuit CTLR and the MAC array MAR are electrically connected to a wiring CKL.

[0079] The wiring CKL functions as, for example, a wiring that supplies a clock signal. The clock signal may be, for example, a pulse voltage.

[0080] The control circuit CTLR has, as an example, a function to control the arithmetic circuits MA[1,1] to MA[u,v] included in the MAC array MAR. Specifically, for example, the control circuit CTLR has a function to send a selection signal for writing data to a memory unit (corresponding to a memory unit OSM, etc., described later) included in the arithmetic circuit MA, and a function to send the data. Also, for example, the control circuit CTLR has a function to send a signal for controlling a register (such as a register RG2 to a register RG4, described later) included in the arithmetic circuit MA. The control circuit CTLR may also have a function to generate a different clock signal based on a clock signal from the wiring CKL.

[0081] The circuits AF[1] to AF[v] are electrically connected to the wirings YL[1] to YL[v], respectively. The circuits AF[1] to AF[v] are electrically connected to the memory unit MEMD, respectively.

[0082] Each of the circuits AF[1] to AF[v] can be a function circuit that outputs an activation function value using the results of product-sum operations sent from the wirings YL[1] to YL[v]. The activation function can be, for example, a step function, a ReLU function, a sigmoid function, a tanh function, or the like.

[0083] Each of the circuits AF[1] to AF[v] may be a circuit that performs pooling, such as maximum pooling, average pooling, or Lp pooling.

[0084] Furthermore, each of the circuits AF[1] to AF[v] may be a circuit having a function circuit that outputs the value of an activation function, a circuit that performs pooling processing, or the like.

[0085] That is, by using the arithmetic device 100, it is possible to perform calculations of a hierarchical neural network, calculations of a convolutional neural network (CNN), and the like.

[0086] One embodiment of the present invention is not limited to the semiconductor device illustrated in Fig. 1. In one embodiment of the present invention, the semiconductor device illustrated in Fig. 1 may be modified depending on the situation. For example, like the arithmetic device 100A illustrated in Fig. 2, the arithmetic device 100 illustrated in Fig. 1 may not include the circuits AF[1] to AF[v].

[0087] <Configuration example of arithmetic circuit MA> Next, an example of the configuration of the arithmetic circuit MA will be described.

[0088] 3 is a block diagram showing an example of the arithmetic circuit MA. The arithmetic circuit MA includes, for example, a register RG1, a register RG2, a register RG3, a register RG4, a multiplier MP, an adder AD, a selector SLC, and a storage unit OSM.

[0089] Moreover, the arithmetic circuit MA shown in FIG. 3 has, as an example, a terminal SI, a terminal SO, a terminal MI, a terminal MO, a terminal AI, and a terminal AO.

[0090] Register RG1 has a terminal IT1 corresponding to an input terminal and a terminal OT1 corresponding to an output terminal. Register RG2 has a terminal IT2 corresponding to an input terminal, a terminal OT2 corresponding to an output terminal, and a terminal CT2 corresponding to an enable input terminal. Register RG3 has a terminal IT3 corresponding to an input terminal, a terminal OT3 corresponding to an output terminal, and a terminal CT3 corresponding to an enable input terminal. Register RG4 has a terminal IT4 corresponding to an input terminal and a terminal OT4 corresponding to an output terminal. Although not shown in FIG. 3, each of registers RG1 to RG4 is electrically connected to a line CKL and receives a clock signal from the line CKL.

[0091] The multiplier MP has a terminal WI corresponding to a first input terminal, a terminal XI corresponding to a second input terminal, and a terminal ZO corresponding to an output terminal, while the adder AD has a terminal FT corresponding to a first input terminal, a terminal ST corresponding to a second input terminal, and a terminal TT corresponding to an output terminal.

[0092] The terminal IT1 of the register RG1 is electrically connected to the terminal SI, the terminal OT1 of the register RG1 is electrically connected to the terminal IT2 and the terminal SO of the register RG2, the terminal OT2 of the register RG2 is electrically connected to the terminal XI of the multiplier MP, and the terminal CT2 of the register RG2 is electrically connected to the line SLT.

[0093] The storage unit OSM is electrically connected to the wiring CF, the wiring WDT, and the wiring CTX, and is also electrically connected to the terminal WI of the multiplier MP.

[0094] The terminal ZO of the multiplier MP is electrically connected to the terminal FT of the adder AD, and the terminal ST of the adder AD is electrically connected to the terminal AI.

[0095] The terminal IT3 of the register RG3 is electrically connected to the terminal TT of the adder AD, the terminal OT3 of the register RG3 is electrically connected to the terminal AO and the first input terminal of the selector SLC, and the terminal CT3 of the register RG3 is electrically connected to the line URST.

[0096] A terminal IT4 of the register RG4 is electrically connected to the output terminal of the selector SLC, and a terminal OT4 of the register RG4 is electrically connected to the terminal MO.

[0097] A second input terminal of the selector SLC is electrically connected to the terminal MI, and a control terminal of the selector SLC is electrically connected to the line SEL.

[0098] As an example, register RG1 has a function of temporarily holding data (which may be digital data, or may be an electric potential) given to terminal IT1 when a pulse voltage is given as a clock signal. In this specification, register RG1 temporarily holds the data given to the input terminal of register RG1 when a potential change occurs as a clock signal, for example, from a low-level electric potential to a high-level electric potential, and outputs the data from the output terminal of register RG1. As an example, register RG1 has a function of outputting the data held in register RG1 to terminal OT1.

[0099] As an example, the register RG2 stores data (which can be digital data, for example) that is provided to the terminal IT2 when an enable signal is provided to the terminal CT2 that is an enable input terminal and a pulse voltage is provided as a clock signal. In this specification, the register RG2 temporarily stores the data that is provided to the input terminal of the register RG2 when, for example, a high-level potential is input to the enable input terminal and a potential change occurs from a low-level potential to a high-level potential as a clock signal. As an example, the register RG2 has a function of outputting the data that is stored in the register RG2 to the terminal OT2.

[0100] Furthermore, when a low-level potential is input to the terminal CT2 of the register RG2, even if a potential change occurs from a low-level potential to a high-level potential as a clock signal, the register RG2 does not hold the data input to the terminal IT2. However, even when a low-level potential is input to the terminal CT2 of the register RG2, the data held in the register RG2 is still output.

[0101] For example, the line SLT functions as a line that supplies an enable signal to the register RG2.

[0102] The potential applied by the line CKL of the register RG1 changes, for example, from a low level potential to a high level potential, thereby holding the data input to the terminal IT1 and transmitting the data from the terminal OT1 of the register RG1 to the terminal IT2 of the register RG2. Also, when a high level potential is applied to the line SLT, the potential applied by the line CKL of the register RG2 changes, for example, from a low level potential to a high level potential, thereby holding the data input to the terminal IT2 of the register RG2 and transmitting the data from the terminal OT2 of the register RG2 to the terminal XI of the multiplier MP.

[0103] The storage unit OSM has a function of holding, for example, data according to a context. Here, the data according to a context can be, for example, first data used in the calculation of the multiplier MP. The storage unit OSM has a function of acquiring a context signal from the wiring CTX, selecting a data set according to the context signal, and inputting a plurality of first data to the terminals WI of the multiplier MP. Note that the context signal may be a digital signal or an analog signal.

[0104] Furthermore, the storage unit OSM has a function of acquiring a write signal from the wiring WDT and writing configuration data sent from the wiring CF to a context corresponding to the write signal.

[0105] The context signal, write signal, and configuration data can be supplied from, for example, a control circuit CTLR. In this case, the lines CTX, WDT, and CF may be electrically connected to the control circuit CTLR.

[0106] The multiplier MP has a function of multiplying, for example, first data input to a terminal WI by second data input to a terminal XI, and outputting the result of the multiplication (hereinafter referred to as multiplied data) to a terminal ZO. For example, when w is input to the terminal WI as the first data and x is input to the terminal XI as the second data, w×x is output as multiplied data to the terminal ZO of the multiplier MP.

[0107] The adder AD has the function of adding, for example, the multiplication data input to the terminal ZO and the data input to the terminal ST, and outputting the result of the addition (hereinafter referred to as the addition data) to the terminal TT.

[0108] For example, register RG3 has a function of temporarily holding the addition data given to terminal IT3 when an enable signal is given to terminal CT3, which is an enable input terminal, and a pulse voltage is given as a clock signal. In this specification, register RG3 temporarily holds the data given to the input terminal of register RG3 when, for example, a high-level potential is input to the enable input terminal and a potential change occurs from a low-level potential to a high-level potential as a clock signal. For example, register RG3 has a function of outputting the data held in register RG3 to terminal OT3.

[0109] Furthermore, when a low-level potential is input to the terminal CT3 of the register RG3, even if a potential change occurs from low to high as a clock signal, the register RG3 does not hold the data input to the terminal IT3. However, even when a low-level potential is input to the terminal CT3 of the register RG3, the data held in the register RG3 is still output.

[0110] For example, the line URST functions as a line that supplies an enable signal to the register RG3.

[0111] The selector SLC has a function of establishing a conductive state between one of the first input terminal or the second input terminal and the output terminal, and establishing a non-conductive state between the other of the first input terminal or the second input terminal and the output terminal. Whether the selector SLC selects the first input terminal or the second input terminal that is established a conductive state with the output terminal is determined by the potential of the line SEL input to the control terminal. Here, as an example, when a high-level potential is input to the control terminal, the selector SLC establishes a conductive state between the first input terminal and the output terminal, and when a low-level potential is input to the control terminal, the selector SLC establishes a conductive state between the second input terminal and the output terminal.

[0112] In the selector SLC, when the first input terminal and the output terminal are in a conductive state and the second input terminal and the output terminal are in a non-conductive state, the addition data from the terminal OT3 of the register RG3 is input to the terminal IT4 of the register RG4. Alternatively, when the second input terminal and the output terminal of the selector SLC are in a conductive state and the first input terminal and the output terminal are in a non-conductive state, the data from the terminal MI is input to the terminal IT4 of the register RG4.

[0113] The line SEL functions, for example, as a line that supplies a signal for controlling the selector SLC.

[0114] As an example, the register RG4 stores data (for example, digital data) provided to the terminal IT4 when a pulse voltage is provided as a clock signal. In this specification, the register RG4 temporarily stores the data provided to the input terminal of the register RG4 when, for example, a potential change occurs from a low level potential to a high level potential as a clock signal. As an example, the register RG4 has a function of outputting the data stored in the register RG4 to the terminal OT4.

[0115] <Programmable switch configuration> Next, the programmable switches PR and PC will be described with reference to FIGS.

[0116] The programmable switches PR[s,1] to PR[s,v] (not shown in Figures 1 and 2) located on the sth row (s is an integer greater than or equal to 1 and less than or equal to u) have the function of controlling the conductive and non-conductive states of the arithmetic circuits MA[s,1] to MA[s,v], respectively.

[0117] For example, the programmable switch PR can have the circuit configuration shown in Fig. 4. Fig. 4 illustrates not only configuration examples of the programmable switch PR[s,g] (g is an integer greater than 1 and less than v-1) and the programmable switch PR[s,h] (h is an integer greater than g and less than v), but also the arithmetic circuit MA[s,g] and the arithmetic circuit MA[s,h].

[0118] FIG. 4 also shows terminals SI, SO, AI, and AO as terminals that the arithmetic circuit MA[s,g] and the arithmetic circuit MA[s,h] have, respectively.

[0119] The programmable switches PR[s,g] and PR[s,h] are electrically connected to a plurality of wirings SL. The programmable switches PR[s,g] and PR[s,h] are also electrically connected to a plurality of wirings ALX.

[0120] The plurality of wirings SL and the plurality of wirings ALX are, for example, wirings extending in the row direction of the MAC array MAR.

[0121] The plurality of wirings SL are electrically connected to the wiring XL[s]. Although the plurality of wirings XL[s] are illustrated in FIG. 4, the wiring XL[s] may be a single wiring and may be electrically connected to one of the plurality of wirings SL.

[0122] 4 shows a configuration in which the programmable switch PR[s,g] includes a plurality of switches SW_SI[s,g], a plurality of switches SW_SO[s,g], a plurality of switches SW_AIX[s,g], and a plurality of switches SW_AOX[s,g], and the programmable switch PR[s,h] includes a plurality of switches SW_SI[s,h], a plurality of switches SW_SO[s,h], a plurality of switches SW_AIX[s,h], and a plurality of switches SW_AOX[s,h].

[0123] The terminal SI of the arithmetic circuit MA[s,g] is electrically connected to a first terminal of each of the multiple switches SW_SI[s,g], and a second terminal of one of the multiple switches SW_SI[s,g] is electrically connected to one of the multiple wirings SL. The terminal SO of the arithmetic circuit MA[s,g] is electrically connected to a first terminal of each of the multiple switches SW_SO[s,g], and a second terminal of one of the multiple switches SW_SO[s,g] is electrically connected to one of the multiple wirings SL. The terminal AI of the arithmetic circuit MA[s,g] is electrically connected to a first terminal of each of the multiple switches SW_AIX[s,g], and a second terminal of one of the multiple switches SW_AIX[s,g] is electrically connected to one of the multiple wirings ALX. The terminal AO of the arithmetic circuit MA[s,g] is electrically connected to a first terminal of each of the multiple switches SW_AOX[s,g], and a second terminal of one of the multiple switches SW_AOX[s,g] is electrically connected to one of the multiple wirings ALX.

[0124] The terminal SI of the arithmetic circuit MA[s,h] is electrically connected to a first terminal of each of the multiple switches SW_SI[s,h], and a second terminal of one of the multiple switches SW_SI[s,h] is electrically connected to one of the multiple wirings SL. The terminal SO of the arithmetic circuit MA[s,h] is electrically connected to a first terminal of each of the multiple switches SW_SO[s,h], and a second terminal of one of the multiple switches SW_SO[s,h] is electrically connected to one of the multiple wirings SL. The terminal AI of the arithmetic circuit MA[s,h] is electrically connected to a first terminal of each of the multiple switches SW_AIX[s,h], and a second terminal of one of the multiple switches SW_AIX[s,h] is electrically connected to one of the multiple wirings ALX. The terminal AO of the arithmetic circuit MA[s,h] is electrically connected to a first terminal of each of the multiple switches SW_AOX[s,h], and a second terminal of one of the multiple switches SW_AOX[s,h] is electrically connected to one of the multiple wirings ALX.

[0125] For example, to establish electrical continuity between terminal SO of arithmetic circuit MA[s,g] and terminal SI of arithmetic circuit MA[s,h], one of the multiple wirings SL is selected, and the switches SW_SO[s,g] and SW_SI[s,h] directly connected to that wiring are each turned on, and the remaining multiple switches SW_SO[s,g] and SW_SI[s,h] are each turned off.

[0126] Like the programmable switch PR, the programmable switches PC[1,t] to PC[u,t] (not shown in Figures 1 and 2) located in the t-th column (t is an integer greater than or equal to 1 and less than or equal to v) have the function of controlling the conductive and non-conductive states of each of the arithmetic circuits MA[1,t] to MA[u,t], respectively.

[0127] For example, the programmable switch PC can have the circuit configuration shown in Fig. 5. Fig. 5 illustrates not only configuration examples of the programmable switch PC[e,t] (e is an integer greater than 1 and less than u-1) and the programmable switch PC[f,t] (f is an integer greater than e and less than u), but also the arithmetic circuit MA[e,t] and the arithmetic circuit MA[f,t].

[0128] FIG. 5 also illustrates terminals AI, AO, MI, and MO as terminals that the arithmetic circuit MA[e,t] and the arithmetic circuit MA[f,t] have, respectively.

[0129] The programmable switches PC[e,t] and PC[f,t] are electrically connected to a plurality of wirings ML and a plurality of wirings ALY.

[0130] The plurality of wirings ML and the plurality of wirings ALY are, for example, wirings that extend in the column direction of the MAC array MAR.

[0131] Furthermore, the multiple wirings ML are electrically connected to the wiring YL[t]. Although multiple wirings YL[t] are illustrated in Fig. 5, the wiring YL[t] may be a single wiring that is electrically connected to one of the multiple wirings ML.

[0132] 5 shows a configuration in which the programmable switch PC[e,t] includes a plurality of switches SW_MI[e,t], a plurality of switches SW_MO[e,t], a plurality of switches SW_AIY[e,t], and a plurality of switches SW_AOY[e,t], and the programmable switch PC[f,t] includes a plurality of switches SW_MI[f,t], a plurality of switches SW_MO[f,t], a plurality of switches SW_AIY[f,t], and a plurality of switches SW_AOY[f,t].

[0133] The terminal MI of the arithmetic circuit MA[e,t] is electrically connected to a first terminal of each of the multiple switches SW_MI[e,t], and a second terminal of one of the multiple switches SW_MI[e,t] is electrically connected to one of the multiple wirings ML. The terminal MO of the arithmetic circuit MA[e,t] is electrically connected to a first terminal of each of the multiple switches SW_MO[e,t], and a second terminal of one of the multiple switches SW_MO[e,t] is electrically connected to one of the multiple wirings ML. The terminal AI of the arithmetic circuit MA[e,t] is electrically connected to a first terminal of each of the multiple switches SW_AIY[e,t], and a second terminal of one of the multiple switches SW_AIY[e,t] is electrically connected to one of the multiple wirings ALY. The terminal AO of the arithmetic circuit MA[e,t] is electrically connected to a first terminal of each of the multiple switches SW_AOY[e,t], and a second terminal of one of the multiple switches SW_AOY[e,t] is electrically connected to one of the multiple wirings ALY.

[0134] The terminal MI of the arithmetic circuit MA[f,t] is electrically connected to a first terminal of each of the multiple switches SW_MI[f,t], and a second terminal of each of the multiple switches SW_MI[f,t] is electrically connected to a first terminal of each of the multiple wires ML. The terminal MO of the arithmetic circuit MA[f,t] is electrically connected to a first terminal of each of the multiple switches SW_MO[f,t], and a second terminal of each of the multiple switches SW_MO[f,t] is electrically connected to a first terminal of each of the multiple wires ML. The terminal AI of the arithmetic circuit MA[f,t] is electrically connected to a first terminal of each of the multiple switches SW_AIY[f,t], and a second terminal of each of the multiple switches SW_AIY[f,t] is electrically connected to a first terminal of each of the multiple wires ALY. The terminal AO of the arithmetic circuit MA[f,t] is electrically connected to a first terminal of each of the multiple switches SW_AOY[f,t], and a second terminal of each of the multiple switches SW_AOY[f,t] is electrically connected to a first terminal of each of the multiple wires ALY.

[0135] For example, to establish electrical continuity between the terminal MO of the arithmetic circuit MA[e,t] and the terminal MI of the arithmetic circuit MA[f,t], one of the multiple wirings ML is selected, and the switches SW_MO[e,t] and SW_MI[f,t] directly connected to that wiring are turned on, while the remaining multiple switches SW_MO[e,t] and SW_MI[f,t] are turned off. Furthermore, to establish electrical continuity between the terminal AO of the arithmetic circuit MA[e,t] and the terminal AI of the arithmetic circuit MA[f,t], one of the multiple wirings ALY is selected, and the switches SW_AOY[e,t] and SW_SI[f,t] directly connected to that wiring are turned on, while the remaining multiple switches SW_AOY[e,t] and SW_AIY[f,t] are turned off.

[0136] 4 shows a configuration in which the programmable switch PR is electrically connected to the terminals SI, SO, AI, and AO of the arithmetic circuit MA, and FIG. 5 shows a configuration in which the programmable switch PC is electrically connected to the terminals AI, AO, MI, and MO of the arithmetic circuit MA, but one embodiment of the present invention is not limited to this. For example, the arithmetic device 100 may be configured such that the programmable switch PR is electrically connected to not only the terminals SI, SO, AI, and AO, but also the terminals MI and MO, or such that the programmable switch PC is electrically connected to not only the terminals AI, AO, MI, and MO, but also the terminals SI and SO.

[0137] The MAC array MAR can change the scale of circuits involved in the sum-of-products operation by using the programmable switches PR[1,1] through PR[u,v] and the programmable switches PC[1,1] through PC[u,v]. For example, when performing the sum-of-products operation using the MAC array MAR, if the operation is sufficient with only the arithmetic circuits MA[1,t] through MA[u,t], the programmable switches PR[1,t] through PR[u,t] and the programmable switches PC[1,t] through PC[u,t] can be turned on, and the other programmable switches can be turned off.

[0138] <How it works> Next, a description will be given of an example of the operation of the arithmetic device 100. Note that in this operation method, an example of the operation in the calculation of a convolutional neural network (CNN) will be described.

[0139] CNN is a computational model used to extract features from images, etc. Figure 6 shows an example of the configuration of a CNN. The CNN is composed of a convolutional layer CL, a pooling layer PL, and a fully connected layer FCL. In this operation method, for example, image data IPD read from the memory unit MEMD is input to the MAC array MAR, and feature extraction is performed.

[0140] The convolution layer CL has the function of performing convolution processing on image data. The convolution processing is performed by repeatedly performing product-sum operations on a portion of the image data and the filter value of the weight filter. The convolution in the convolution layer CL extracts image features.

[0141] One or more weight filters can be used in the convolution process. When multiple weight filters are used, it is possible to extract multiple features contained in the image data. FIG. 6 shows filters fil1, fil2, and fil3 as multiple weight filters. Although FIG. 6 shows three filters, the number of filters used in the convolution process may be one, two, or four or more. FIG. 6 shows an example in which image data input to the convolution layer CL is subjected to filtering using filters fil1, fil2, and fil3, and image data D1, D2, and D3 are generated.

[0142] The convolved image data D1, D2, and D3 may be subjected to an operation using, for example, an activation function. As an example of the activation function, ReLU (Rectified Linear Units) or the like can be used. ReLU is a function that outputs "0" when the input value is negative and outputs the input value as is when the input value is "0" or greater. Alternatively, a sigmoid function, a tanh function, or the like can be used as another activation function.

[0143] Regardless of whether or not an activation function is used, the image data D1, D2, and D3 are output to, for example, a pooling layer PL. The pooling layer PL has a function of performing pooling on the image data input from the convolutional layer CL. Pooling is a process of dividing the image data into multiple regions, extracting predetermined data for each region, and arranging it in a new matrix. Pooling reduces the image data while retaining the features extracted by the convolutional layer CL. Note that, for pooling, max pooling, average pooling, Lp pooling, etc. can be used.

[0144] The CNN extracts features by, for example, the above-mentioned convolution process, pooling process, etc. The CNN may have multiple convolution layers CL and / or multiple pooling layers PL. In FIG. 6, as an example, z layers (where z is an integer equal to or greater than 1) of layers L each consisting of a convolution layer CL and a pooling layer PL are provided (layers L1 to L2). z ), the convolution process and pooling process are performed z times. In this case, feature extraction can be performed in each layer L, enabling more advanced feature extraction. z The other layers L are omitted.

[0145] The fully connected layer FCL includes, for example, layers L1 to L z The fully connected layer FCL has a function of judging an image using image data obtained through the above. The fully connected layer FCL has a configuration in which all nodes in a layer are connected to all nodes in the next layer. In other words, the fully connected layer FCL performs calculations using a fully connected neural network (FNN). The image data output from the convolution layer CL or pooling layer PL is a two-dimensional feature map, which is expanded into one dimension when input to the fully connected layer FCL. Then, the image data OPD obtained by inference using the fully connected layer FCL is output.

[0146] <<Convolutional Layer CL Operation 1>> Here, we will explain a method of computing the convolutional layer CL using the computing device 100. Note that, as an example, the computing circuits MA included in the MAC array MAR of the computing device 100 are arranged in a matrix of 9 rows and 10 columns. In other words, the MAC array MAR used in this operating method includes computing circuits MA[1,1] to MA[9,10].

[0147] In addition, the MAC array MAR in this operation method has a circuit configuration as shown in Figure 7, using programmable switches PR and programmable switches PC. Specifically, in an arithmetic circuit MA included in one row of the MAC array MAR, the programmable switch PR is set so that the terminal SO of the arithmetic circuit MA is in a conductive state with the terminal SI of the adjacent arithmetic circuit MA. For example, the programmable switch PR[1,1] and the programmable switch PR[1,2] are set so that the terminal SO of the arithmetic circuit MA[1,1] is in a conductive state with the terminal SI of the arithmetic circuit MA[1,2], and the programmable switch PR[1,2] and the programmable switch PR[1,3] are set so that the terminal SO of the arithmetic circuit MA[1,2] is in a conductive state with the terminal SI of the arithmetic circuit MA[1,3]. Note that the wiring XL[1] is in a conductive state with the terminal SI of the arithmetic circuit MA[1,1] via the programmable switch PR[1,1]. In this manner, in this operating method, it is assumed that the programmable switches PR are set so that the arithmetic circuits MA are serially connected to each other and brought into a conductive state in each row of the MAC array MAR.

[0148] In addition, in the MAC array MAR in this operation method, specifically, in the arithmetic circuit MA included in one column of the MAC array MAR, the programmable switch PC is set so that the terminal AO of the arithmetic circuit MA is in a conductive state with the terminal AI of the adjacent arithmetic circuit MA. For example, the programmable switch PC[1,1] and the programmable switch PC[2,1] are set so that the terminal AO of the arithmetic circuit MA[1,1] is in a conductive state with the terminal AI of the arithmetic circuit MA[2,1]. Note that the wiring YL[1] is in a conductive state with the terminal AO of the arithmetic circuit MA[9,1] via the programmable switch PC[9,1]. In this way, in this operation method, it is assumed that the programmable switch PC is set so that the arithmetic circuits MA in each column of the MAC array MAR are in a conductive state in series.

[0149] 8 is a timing chart showing changes in data input to terminals SI, SO, XI, WI, AI (terminal ST), TT, and AO of the arithmetic circuit MA[2,1] from time T1 to time T9 and at times around those times. Also shown in FIG. 8 are changes in the potentials of lines CKL, SLT, SEL, and URST. Note that "high" in FIG. 8 represents a high-level potential, and "low" represents a low-level potential.

[0150] In this operation method, it is assumed that a high level potential is always input to the line SLT, and therefore the register RG2 is in an enabled state during this operation method.

[0151] In this operation method, the line SEL is always supplied with a low-level potential, so that the selector SLC always maintains a non-conductive state between the first input terminal and the output terminal, and a conductive state between the second input terminal and the output terminal.

[0152] The calculation method performed in the MAC array MAR will be explained below with reference to the timing chart of FIG.

[0153] [Step 0: Initialization] First, an initialization operation is performed in the arithmetic device 100. Specifically, before time T1, it is preferable that initialization data be input to the terminals SI, SO, XT, WT, AI (terminal ST), TT, and AO of each of the arithmetic circuits MA[1,1] to MA[9,10] (not shown in FIG. 8). The initialization data can be, for example, data with a value of "0." Furthermore, the potential of the wiring URST is changed from a low-level potential to a high-level potential, and the potential of the terminal AO is adjusted to an appropriate value by the register RG3. At this time, it is preferable that the potential of the terminal AO be, for example, a potential corresponding to the value of "0."

[0154] [Step 1: Read filter value] After step 0 and before time T1, in each of the arithmetic circuits MA[1,1] to MA[9,10] of the MAC array MAR of the arithmetic device 100, a filter value is read from the storage unit OSM. Specifically, a context signal is supplied from the wiring CTX, and data corresponding to the desired context, i.e., a filter value, is read from the storage unit OSM. Here, as an example, the filter fil is stored in the storage unit OSM of each of the arithmetic circuits MA[1,t] to MA[9,t] located in the t-th column (here, t is an integer between 1 and 10). t The filter value of the filter fil is read. t For example, let us consider a 3-row, 3-column matrix shown in FIG. 9A, and the filter fil t is a matrix element that contains fil t [1,1] to fil t For example, the storage unit OSM of the arithmetic circuit MA[1,t] has fil t [1,1] is read, and the memory unit OSM of the arithmetic circuit MA[2,t] is fil t [1,2] is read, and the memory unit OSM of the arithmetic circuit MA[3,t] is fil t [1,3] is read, and the memory unit OSM of the arithmetic circuit MA[4,t] is fil t [2,1] is read, and the memory unit OSM of the arithmetic circuit MA[5,t] is fil t [2,2] is read, and the memory unit OSM of the arithmetic circuit MA[6,t] is fil t [2,3] is read, and the memory unit OSM of the arithmetic circuit MA[7,t] is fil t [3,1] is read, and the memory unit OSM of the arithmetic circuit MA[8,t] is fil t [3,2] is read, and the memory unit OSM of the arithmetic circuit MA[9,t] is fil t Let's read [3,3].

[0155] Therefore, as shown in FIG. 9B, the arithmetic circuit MA of the MAC array MAR has filters fil1 to fil2 in the first to tenth columns, respectively. 10 is read out.

[0156] In each of the arithmetic circuits MA[1,1] to MA[9,10], the filter value read from the storage unit OSM is input to the terminal WI of the multiplier MP.

[0157] [Step 2: Input image data] Next, the operation of inputting image data IPD to the MAC array MAR will be described.

[0158] As an example, the image data IPD here is assumed to be composed of multiple pixel data pix[1,1] to pixel data pix[m,n] in m rows and n columns (where m and n are integers greater than or equal to 1), as shown in Figure 10A.

[0159] The image data IPD is read from the storage unit MEMD of the arithmetic device 100, for example.

[0160] Incidentally, the arithmetic circuits MA of the MAC array MAR are arranged in a matrix of 9 rows and 10 columns, so that the registers RG[1,p] through RG[9,p] are electrically connected to the MAC array MAR. Also, the registers RG[s,1] through RG[s,p] are electrically connected to the s-th row (here, s is an integer between 1 and 9) of the MAC array MAR. In other words, when pixel data pix read out from the memory unit MEMD is input to the arithmetic circuit MA[s,1] of the MAC array MAR, it passes through the registers RG[s,1] through RG[s,p].

[0161] Registers RG[s,1] to RG[s,p] sequentially transmit multiple pixel data pix read out from the memory unit MEMD to the wiring CKL each time a potential change, for example from a low-level potential to a high-level potential, is input as a clock signal.

[0162] FIG. 10B is a block diagram showing pixel data pix that is held in each of registers RG[1, p] to RG[9, p] and input to the MAC array MAR between time T1 and time T9.

[0163] 10B shows that at time T1, a potential change from low to high occurs on the line CKL, pixel data pix[1,1] is stored in each of registers RG[1,p] to RG[3,p], and the pixel data pix[1,1] is input to the terminal SI of each of arithmetic circuits MA[1,1] to MA[3,1]. Also, for example, FIG. 10B shows that at time T2, a potential change from low to high occurs on the line CKL, pixel data pix[1,2] is stored in each of registers RG[1,p] to RG[3,p], and the pixel data pix[1,2] is input to the terminal SI of each of arithmetic circuits MA[1,1] to MA[3,1]. Also, for example, Figure 10B shows that at time T3, a potential change from low level potential to high level potential occurs on wiring CKL, pixel data pix[1,3] is stored in each of registers RG[1,p] to RG[3,p], and pixel data pix[1,3] is input to terminals SI of arithmetic circuits MA[1,1] to MA[1,3].

[0164] Also, for example, Figure 10B shows that at time T4, a potential change from low level potential to high level potential occurs on wiring CKL, pixel data pix[1,4] is stored in each of registers RG[1,p] to RG[3,p], the pixel data pix[1,4] is input to terminals SI of each of arithmetic circuits MA[1,1] to MA[3,1], pixel data pix[2,1] is stored in each of registers RG[4,p] to RG[6,p], and the pixel data pix[2,1] is input to terminals SI of arithmetic circuits MA[4,1] to MA[6,1].

[0165] Also, for example, Figure 10B shows that at time T7, a potential change from low to high occurs on wiring CKL, pixel data pix[1,7] is stored in each of registers RG[1,p] to RG[3,p], the pixel data pix[1,7] is input to terminal SI of each of arithmetic circuits MA[1,1] to MA[3,1], pixel data pix[2,4] is stored in registers RG[4,p] to RG[6,p], the pixel data pix[2,4] is input to terminal SI of each of arithmetic circuits MA[4,1] to MA[6,1], pixel data pix[3,1] is stored in register RG[7,p], and the pixel data pix[3,1] is input to terminal SI of arithmetic circuit MA[7,1].

[0166] As described above, pixel data pix[1,1] to pix[1,n] are sequentially input to the arithmetic circuits MA[1,1] to MA[3,1] each time a potential change from low to high occurs as a clock signal on the wiring CKL. Also, pixel data pix[2,1] to pix[2,n] are sequentially input to the arithmetic circuits MA[4,1] to MA[6,1] after three potential changes from low to high occur as a clock signal on the wiring CKL after data is input to the arithmetic circuits MA[1,1] to MA[3,1]. In addition, after data is input to the arithmetic circuits MA[4,1] to MA[6,1], three potential changes from low-level potential to high-level potential occur as a clock signal on the wiring CKL, and then pixel data pix[3,1] to pix[3,n] are sequentially input to the arithmetic circuits MA[7,1] to MA[9,1].

[0167] Note that after pixel data pix[1,n] is input to arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[4,1] through pixel data pix[4,n] may be sequentially input. Similarly, after pixel data pix[2,n] is input to arithmetic circuits MA[4,1] through MA[6,1], pixel data pix[5,1] through pixel data pix[5,n] may be sequentially input, and after pixel data pix[3,n] is input to arithmetic circuits MA[7,1] through MA[9,1], pixel data pix[6,1] through pixel data pix[6,n] may be sequentially input. In this way, after one row of pixel data pix is ​​input to arithmetic circuits MA[1,1] through MA[9,1], pixel data pix of the next row may be input, allowing for continuous arithmetic processing.

[0168] Note that, as will be described in detail later, in FIG. 10B, pixel data pix enclosed by dotted lines (for example, pixel pix[1,1] stored in register RG[2,p] and register RG[3,p] at time T1 and input to arithmetic circuits MA[2,1] and MA[3,1], respectively) is data not used in the CNN calculations. Therefore, when performing calculations in the MAC array MAR, only data of pixels pix enclosed by solid lines may be input to the MAC array MAR. However, when actually configuring a calculation device, it may be easier to configure the calculation device by transmitting pixels pix enclosed by dotted lines as dummy data together with pixels pix enclosed by black lines, rather than by inputting only data of pixels pix enclosed by solid lines to the MAC array MAR.

[0169] The pixel data pix is ​​input to the MAC array MAR through the filters fil1 to fil2. 10 This can be applied only when the filter fil1 to the filter fil2 are 3 rows and 3 columns. 10If the matrix is ​​other than 3 rows and 3 columns, the method of inputting pixel data pix to the MAC array MAR described above must be changed. For example, if the filter read into the arithmetic circuit MA of the MAC array MAR has a rows and b columns (a is an integer greater than or equal to 1, and b is an integer greater than or equal to 1), the MAC array MAR to which pixel data pix is ​​input from the register RG should have a × b rows (i.e., the number of rows in the arithmetic circuit MA of the MAC array MAR should be a × b). Also, the pixel data pix can be input to the MAC array MAR in groups of a rows, with a difference of a clock signals. For example, if the filter read into the arithmetic circuit MA of the MAC array MAR has 2 rows and 3 columns, the pixel data and timing input from the register RG to the MAC array MAR should be as shown in Figure 11.

[0170] Next, with reference to Figure 3, consider the case where pixel data pix is ​​input to terminal SI of arithmetic circuit MA. The pixel data pix input to terminal SI of arithmetic circuit MA is input to terminal IT1 of register RG1 included in arithmetic circuit MA. When the clock signal, for example, changes from low-level potential to high-level potential, register RG1 holds the pixel data pix input to terminal IT1 and outputs the pixel data pix from terminal OT1.

[0171] The register RG1 is electrically connected to the wiring CKL, and thus can output pixel data pix to the terminal OT1 in synchronization with the register RG external to the MAC array MAR. The pixel data pix output from the terminal OT1 is also input to the terminal SO of the arithmetic circuit MA, and the terminal SO of the arithmetic circuit MA is electrically connected to the terminal SI of the adjacent arithmetic circuit MA. Therefore, the arithmetic circuits MA included in one row of the MAC array MAR can be regarded as serially connected registers, with the terminal SI serving as the input terminal and the terminal SO serving as the output terminal. Therefore, the arithmetic circuits MA included in one row of the MAC array MAR can sequentially transmit pixel data pix in response to a clock signal, just like the register RG external to the MAC array MAR. For example, the pixel data pix sequentially transmitted to the registers RG[s,1] through RG[s,p] are subsequently sequentially transmitted to the arithmetic circuits MA[s,1] through MA[s,v] (v=10 in this example) of the MAC array MAR.

[0172] In this operation method, it is assumed that a high level potential is always applied to the terminal CT2 of the register RG2, that is, a high level potential is always applied to the line SLT.

[0173] The pixel data pix output from the terminal OT1 of the register RG1 is input to the terminal IT2 of the register RG2. The register RG2 is electrically connected to the line CKL, so that the pixel data pix can be output to the terminal OT2 in synchronization with the register RG and the register RG1 external to the MAC array MAR described above. Therefore, the register RG2 holds the pixel data pix input to the terminal IT2 and outputs the pixel data pix to the terminal OT2. The pixel data pix output to the terminal OT2 is input to the terminal XI of the multiplier MP.

[0174] That is, the pixel data pix input to the terminal IT1 of the register RG1 is output to the terminal OT2 of the register RG2 when the potential changes from low level potential to high level potential twice as the clock signal input to the line CKL.

[0175] [Step 3: Multiply and accumulate the filter value and pixel data pix] In step 2, pixel data pix is ​​input to the arithmetic circuit MA, whereby the arithmetic circuit MA multiplies the pixel data pix by the filter value read out from the storage unit OSM of the arithmetic circuit MA.

[0176] [Time T1] 12A is a block diagram illustrating, as an example, data output to terminals AO of some arithmetic circuits MA of the MAC array MAR at time T1. Note that in FIG. 12A, only registers RG[1,p] through RG[5,p] and arithmetic circuits MA[1,1] through MA[5,1] are selectively illustrated.

[0177] At time T1, pixel data is input to the MAC array MAR from each of registers RG[1,p] to RG[9,p]. Note that at time T1, pixel data pix[1,1] is input to arithmetic circuits MA[1,1] to MA[3,1], and pixel data is not input to arithmetic circuits MA[4,1] to MA[9,1]. Therefore, in Figure 12A, BLK is shown, indicating that no pixel data is input to arithmetic circuits MA[4,1] to MA[9,1].

[0178] Furthermore, pixel data pix[1,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] to MA[3,1].

[0179] At time T1, no operation results have been generated in any of the arithmetic circuits MA of the MAC array MAR. Therefore, in Fig. 12A, BLK is shown at the terminals AO of the arithmetic circuits MA[1,1] to MA[9,1], indicating that no operation results have been output.

[0180] [Time T2] 12B is a block diagram illustrating, as an example, data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR at time T2. Note that, in FIG. 12B, only registers RG[1,p] through RG[5,p], arithmetic circuits MA[1,1] through MA[5,1], and arithmetic circuits MA[1,3] through MA[5,3] are selectively illustrated.

[0181] At time T2, pixel data pix[1,2] is output from registers RG[1,p] through RG[3,p], and pixel data is not input from arithmetic circuits MA[4,1] through MA[9,1]. Furthermore, as described above, the arithmetic circuits MA of the MAC array MAR also function as registers, so at time T2, pixel data pix[1,1] is output from the terminals SO of each of the arithmetic circuits MA[1,1] through MA[3,1]. Furthermore, pixel data pix is ​​not output from the terminals SO of each of the arithmetic circuits MA[4,1] through MA[9,1].

[0182] At this time, pixel data pix[1,1] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Also, pixel data pix[1,2] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] to MA[3,1].

[0183] Furthermore, pixel data pix[1,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,2] to MA[3,2].

[0184] At time T2, no operation results have been generated in any of the operation circuits MA of the MAC array MAR. Therefore, in Fig. 12B, as in Fig. 12A, BLK is shown at the terminals AO of the operation circuits MA[1,1] to MA[9,1], indicating that no operation results have been output.

[0185] [Time T3] Next, consider the operation of the MAC array MAR at time T3. Fig. 13 is a block diagram illustrating, as an example, data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR at time T3. Note that Fig. 13 only illustrates registers RG[1,p] through RG[5,p], arithmetic circuits MA[1,1] through MA[5,1], arithmetic circuits MA[1,2] through MA[5,2], and arithmetic circuits MA[1,3] through MA[5,3].

[0186] At time T3, pixel data pix[1,3] is input from registers RG[1,p] to RG[3,p] to arithmetic circuits MA[1,1] to MA[3,1], and pixel data is not input to arithmetic circuits MA[4,1] to MA[9,1]. As described above, the arithmetic circuits MA of the MAC array MAR also function as registers. Therefore, at time T3, pixel data pix[1,2] is output from the terminal SO of each of the arithmetic circuits MA[1,1] to MA[3,1], and pixel data pix[1,1] is output from the terminal SO of each of the arithmetic circuits MA[1,2] to MA[3,2]. Furthermore, pixel data pix is ​​not output from the terminal SO of each of the arithmetic circuits MA[4,1] to MA[9,1] and the arithmetic circuits MA[4,2] to MA[9,2].

[0187] At this time, pixel data pix[1,2] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Also, pixel data pix[1,3] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] to MA[3,1].

[0188] The pixel data pix[1,1] is input to the terminal IT2 of the register RG2 of each of the arithmetic circuits MA[1,2] to MA[3,2]. The pixel data pix[1,2] is input to the terminal IT1 of the register RG1 of each of the arithmetic circuits MA[1,2] to MA[3,2].

[0189] Furthermore, pixel data pix[1,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,3] to MA[3,3].

[0190] Furthermore, pixel data pix[1,1] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,1] is input to terminal XI of multiplier MP.

[0191] Here, the operations performed by the arithmetic circuits MA[1,1] to MA[9,1] will be described.

[0192] In the arithmetic circuit MA[1,1], fil1[1,1] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, fil1[1,1] x pix[1,1] is output to the terminal ZO of the multiplier MP, and input to the terminal FT of the adder AD. Also, it is assumed that a value of "0" is input to the terminal ST of the adder AD. As a result, fil1[1,1] x pix[1,1] is output to the terminal TT of the adder AD. In this operation example, F1 [1,1] [1] = fil1[1,1] × pix[1,1]. F1 [1,1] [1] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,1].

[0193] In addition, in the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP receives fil1[1,2] as a filter value, and the terminal XI of the multiplier MP receives pixel pix[1,1]. As a result, fil1[1,2] x pix[1,1] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. Also, as an example, a value of "0" is input to the terminal ST of the adder AD. As a result, fil1[1,2] x pix[1,1] is output to the terminal TT of the adder AD. However, since this calculation result is not used in the CNN calculation, it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[2,1].

[0194] In the arithmetic circuit MA[3,1], the filter value fil1[1,3] is input to the terminal WI of the multiplier MP, and the pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, fil1[1,3] x pix[1,1] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. Also, as an example, a value of "0" is input to the terminal ST of the adder AD. As a result, fil1[1,3] x pix[1,1] is output to the terminal TT of the adder AD. However, as with the previous arithmetic circuit MA[2,1], this calculation result is not used in the CNN calculation, so it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,1].

[0195] In the arithmetic circuits MA[4,1] to MA[9,1], pixel data pix is ​​not input to the terminal XI of the multiplier MP, so no arithmetic is performed.

[0196] [Time T4] Next, consider the operation of the MAC array MAR at time T4. Fig. 14 is a block diagram illustrating, as an example, data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR at time T4. Note that Fig. 14 only illustrates registers RG[1,p] through RG[5,p], arithmetic circuits MA[1,1] through MA[5,1], arithmetic circuits MA[1,2] through MA[5,2], and arithmetic circuits MA[1,3] through MA[5,3].

[0197] In this operation method, it is assumed that a high-level potential is always applied to the terminal CT3 of the register RG3 of each of the arithmetic circuits MA[1,1] to MA[9,10], i.e., a high-level potential is always applied to the wiring URST.

[0198] In the arithmetic circuit MA[1,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs a signal from the terminal OT3 to the terminal F1 [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,1], and in addition, the terminal AO of the arithmetic circuit MA[1,1] and the terminal AI of the arithmetic circuit MA[2,1] are in a conductive state. [1,1] [1] is input to the terminal AI of the arithmetic circuit MA[2,1].

[0199] Similarly, in each of the arithmetic circuits MA[2,1] and MA[3,1], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from low to high as a clock signal. Because the terminal OT3 of the register RG3 in the arithmetic circuit MA[2,1] is in a state of conduction with the terminal AI of the arithmetic circuit MA[3,1] via the terminal AO of the arithmetic circuit MA[2,1], the result FD of the operation performed in the arithmetic circuit MA[2,1] is input to the terminal AI of the circuit MA[3,1]. Also, because the terminal OT3 of the register RG3 in the arithmetic circuit MA[3,1] is in a state of conduction with the terminal AI of the arithmetic circuit MA[4,1] via the terminal AO of the arithmetic circuit MA[3,1], the result FD of the operation performed in the arithmetic circuit MA[3,1] is input to the terminal AI of the circuit MA[4,1].

[0200] At time T4, pixel data pix[1,4] is input from registers RG[1,p] to RG[3,p] to arithmetic circuits MA[1,1] to MA[3,1], pixel data pix[2,1] is input from registers RG[4,p] to RG[6,p] to arithmetic circuits MA[4,1] to MA[6,1], and no pixel data is input to arithmetic circuits MA[7,1] to MA[9,1]. As described above, the arithmetic circuits MA of the MAC array MAR also function as registers, so at time T4, pixel data pix[1,3] is output from the terminal SO of each of the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[1,2] is output from the terminal SO of each of the arithmetic circuits MA[1,2] through MA[3,2], and pixel data pix[1,1] is output from the terminal SO of each of the arithmetic circuits MA[1,3] through MA[3,3]. Furthermore, pixel data pix is ​​not output from the terminal SO of each of the arithmetic circuits MA[4,1] through MA[9,1], the arithmetic circuits MA[4,2] through MA[9,2], and the arithmetic circuits MA[4,3] through MA[9,3].

[0201] At this time, pixel data pix[1,3] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Also, pixel data pix[1,4] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] to MA[3,1].

[0202] Furthermore, pixel data pix[1,2] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,2] to MA[3,2]. Furthermore, pixel data pix[1,3] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,2] to MA[3,2].

[0203] Furthermore, pixel data pix[1,1] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,3] to MA[3,3]. Furthermore, pixel data pix[1,2] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,3] to MA[3,3].

[0204] Furthermore, pixel data pix[2,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,1] to MA[6,1].

[0205] Furthermore, pixel data pix[1,2] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,2] is input to terminal XI of multiplier MP.

[0206] Furthermore, pixel data pix[1,1] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,2] to MA[3,2]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,1] is input to terminal XI of multiplier MP.

[0207] Here, the operations performed by the arithmetic circuits MA[1,1] to MA[9,1] and the arithmetic circuits MA[1,2] to MA[9,2] will be described.

[0208] In the arithmetic circuit MA[1,1], fil1[1,1] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, fil1[1,1] x pix[1,2] is output to the terminal ZO of the multiplier MP, and input to the terminal FT of the adder AD. Also, it is assumed that a value of "0" is input to the terminal ST of the adder AD. As a result, fil1[1,1] x pix[1,2] is output to the terminal TT of the adder AD. In this operation example, F1 [1,2] [1] = fil1[1,1] × pix[1,2]. F1 [1,2] [1] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,1].

[0209] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP receives the filter value fil1[1,2], and the terminal XI of the multiplier MP receives the pixel pix[1,2]. As a result, the terminal ZO of the multiplier MP receives the output fil1[1,2]×pix[1,2], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives the output F1 [1,1] The value of [1] is input. This causes F1 to be input to the terminal TT of the adder AD. [1,1] [1] + fil1[1,1] × pix[1,2] is output. In this example, F1 [1,1] [2]=F1 [1,1] [1] + fil1[1,1] × pix[1,2]. F1 [1,1] [2] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[2,1].

[0210] In addition, in the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP receives fil1[1,3] as a filter value, and the terminal XI of the multiplier MP receives pixel pix[1,1]. As a result, fil1[1,3] x pix[1,2] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. In addition, the terminal ST of the adder AD receives the FD output from the terminal AO of the arithmetic circuit MA[2,1]. However, since this calculation result is not used in the CNN calculation, it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,1].

[0211] In addition, in the arithmetic circuit MA[1,2], fil2[1,1] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, fil2[1,1] x pix[1,1] is output to the terminal ZO of the multiplier MP, and input to the terminal FT of the adder AD. Also, it is assumed that a value of "0" is input to the terminal ST of the adder AD. As a result, fil2[1,1] x pix[1,1] is output to the terminal TT of the adder AD. In this operation example, F2 [1,1] [1] = fil2[1,1] × pix[1,1]. F2 [1,1] [1] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,2].

[0212] In addition, in the arithmetic circuit MA[2,2], the terminal WI of the multiplier MP receives fil2[1,2] as a filter value, and the terminal XI of the multiplier MP receives pixel pix[1,1]. As a result, fil2[1,2] x pix[1,1] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. Also, as an example, a value of "0" is input to the terminal ST of the adder AD. As a result, fil2[1,2] x pix[1,1] is output to the terminal TT of the adder AD. However, since this calculation result is not used in the CNN calculation, it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[2,2].

[0213] In addition, in the arithmetic circuit MA[3,2], the filter value fil2[1,3] is input to the terminal WI of the multiplier MP, and the pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, fil2[1,3] x pix[1,1] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. Also, as an example, a value of "0" is input to the terminal ST of the adder AD. As a result, fil2[1,3] x pix[1,1] is output to the terminal TT of the adder AD. However, as with the previous arithmetic circuit MA[2,2], this calculation result is not used in the CNN calculation, so it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,2].

[0214] In the arithmetic circuits MA[4,1] to MA[9,1] and the arithmetic circuits MA[4,2] to MA[9,2], pixel data pix is ​​not input to the terminal XI of the multiplier MP, so no calculation is performed.

[0215] [Time T5] Next, consider the operation of the MAC array MAR at time T5. Fig. 15 is a block diagram illustrating, as an example, data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR at time T5. Note that Fig. 15 only illustrates registers RG[1,p] through RG[5,p], arithmetic circuits MA[1,1] through MA[5,1], arithmetic circuits MA[1,2] through MA[5,2], and arithmetic circuits MA[1,3] through MA[5,3].

[0216] In the arithmetic circuit MA[1,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs a signal from the terminal OT3 to the terminal F1 [1,2] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,1], and in addition, the terminal AO of the arithmetic circuit MA[1,1] and the terminal AI of the arithmetic circuit MA[2,1] are in a conductive state.[1,2] [1] is input to the terminal AI of the arithmetic circuit MA[2,1]. Similarly, in the arithmetic circuit MA[2,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F1 from the terminal OT3. [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[2,1], and in addition, the terminal AO of the arithmetic circuit MA[2,1] and the terminal AI of the arithmetic circuit MA[3,1] are in a conductive state, so F1 [1,1] [2] is input to the terminal AI of the arithmetic circuit MA[3,1].

[0217] Similarly, in each of the arithmetic circuits MA[3,1] and MA[4,1], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from low to high as a clock signal. Because the terminal OT3 of the register RG3 in the arithmetic circuit MA[3,1] is in a state of conduction with the terminal AI of the arithmetic circuit MA[4,1] via the terminal AO of the arithmetic circuit MA[3,1], the result FD of the operation performed in the arithmetic circuit MA[3,1] is input to the terminal AI of the circuit MA[4,1]. Also, because the terminal OT3 of the register RG3 in the arithmetic circuit MA[4,1] is in a state of conduction with the terminal AI of the arithmetic circuit MA[5,1] via the terminal AO of the arithmetic circuit MA[4,1], the result FD of the operation performed in the arithmetic circuit MA[4,1] is input to the terminal AI of the circuit MA[5,1].

[0218] In the arithmetic circuit MA[1,2], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs a signal from the terminal OT3 to the terminal F2 [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,2], and in addition, the terminal AO of the arithmetic circuit MA[1,2] and the terminal AI of the arithmetic circuit MA[2,2] are in a conductive state, so F2 [1,1] [1] is input to the terminal AI of the arithmetic circuit MA[2,2].

[0219] Similarly, in each of the arithmetic circuits MA[2,2] and MA[3,2], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from low to high as a clock signal. Because the terminal OT3 of the register RG3 in the arithmetic circuit MA[2,2] is in a state of conduction with the terminal AI of the arithmetic circuit MA[3,2] via the terminal AO of the arithmetic circuit MA[2,2], the result FD of the operation performed in the arithmetic circuit MA[2,2] is input to the terminal AI of the circuit MA[3,2]. Also, because the terminal OT3 of the register RG3 in the arithmetic circuit MA[3,2] is in a state of conduction with the terminal AI of the arithmetic circuit MA[4,2] via the terminal AO of the arithmetic circuit MA[3,2], the result FD of the operation performed in the arithmetic circuit MA[3,2] is input to the terminal AI of the circuit MA[4,2].

[0220] At time T5, pixel data pix[1,5] is input from registers RG[1,p] to RG[3,p] to calculation circuits MA[1,1] to MA[3,1], pixel data pix[2,2] is input from registers RG[3,p] to RG[6,p] to calculation circuits MA[4,1] to MA[6,1], and no pixel data is input to calculation circuits MA[7,1] to MA[9,1]. As described above, the arithmetic circuits MA of the MAC array MAR also function as registers, so at time T5, pixel data pix[1,4] is output from the terminal SO of each of the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[1,3] is output from the terminal SO of each of the arithmetic circuits MA[1,2] through MA[3,2], and pixel data pix[1,2] is output from the terminal SO of each of the arithmetic circuits MA[1,3] through MA[3,3]. Also, pixel data pix[2,1] is output from the terminal SO of each of the arithmetic circuits MA[4,1] through MA[6,1]. Furthermore, pixel data pix is ​​not output from the terminal SO of each of the arithmetic circuits MA[7,1] through MA[9,1], the arithmetic circuits MA[4,2] through MA[9,2], and the arithmetic circuits MA[4,3] through MA[9,3].

[0221] At this time, pixel data pix[1,4] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Also, pixel data pix[1,5] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] to MA[3,1].

[0222] Furthermore, pixel data pix[1,3] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,2] to MA[3,2]. Furthermore, pixel data pix[1,4] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,2] to MA[3,2].

[0223] Furthermore, pixel data pix[1,2] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,3] to MA[3,3]. Furthermore, pixel data pix[1,3] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,3] to MA[3,3].

[0224] Furthermore, pixel data pix[2,1] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[4,1] to MA[6,1]. Furthermore, pixel data pix[2,2] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,1] to MA[6,1].

[0225] Furthermore, pixel data pix[2,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,2] to MA[6,2].

[0226] Furthermore, pixel data pix[1,3] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,3] is input to terminal XI of multiplier MP.

[0227] Furthermore, pixel data pix[1,2] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,2] to MA[3,2]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,2] is input to terminal XI of multiplier MP.

[0228] Furthermore, pixel data pix[1,1] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,3] to MA[3,3]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,1] is input to terminal XI of multiplier MP.

[0229] Here, the operations performed by the arithmetic circuits MA[1,1] to MA[9,1], MA[1,2] to MA[9,2], and MA[1,3] to MA[9,3] will be described.

[0230] In the arithmetic circuit MA[1,1], fil1[1,1] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,3] is input to the terminal XI of the multiplier MP. As a result, fil1[1,1] x pix[1,3] is output to the terminal ZO of the multiplier MP, and input to the terminal FT of the adder AD. Also, it is assumed that a value of "0" is input to the terminal ST of the adder AD. As a result, fil1[1,1] x pix[1,3] is output to the terminal TT of the adder AD. In this operation example, F1 [1,3] [1] = fil1[1,1] × pix[1,3]. F1 [1,3] [1] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,1].

[0231] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP receives the filter value fil1[1,2], and the terminal XI of the multiplier MP receives the pixel pix[1,3]. As a result, the terminal ZO of the multiplier MP outputs fil1[1,2]×pix[1,3], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives the filter value fil1[1,2]×pix[1,3]. [1,2] The value of [1] is input. This causes F1 to be input to the terminal TT of the adder AD. [1,2] [1] + fil1[1,2] × pix[1,3] is output. In this example, F1 [1,2] [2]=F1 [1,2] [1] + fil1[1,2] × pix[1,3]. F1 [1,2] [2] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[2,1].

[0232] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP receives the filter value fil1[1,3], and the terminal XI of the multiplier MP receives the pixel pix[1,3]. As a result, the terminal ZO of the multiplier MP receives the output fil1[1,3]×pix[1,3], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives the output F1 [1,1] The value of [2] is input. This causes F1 to be input to the terminal TT of the adder AD. [1,1] [2] + fil1[1,3] × pix[1,3] is output. In this example, F1 [1,1] [3]=F1 [1,1] [2]+fil1[1,3]×pix[1,3]. F1 [1,1] [3] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,1].

[0233] In the arithmetic circuit MA[1,2], fil2[1,1] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, fil2[1,1]×pix[1,2] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. Also, it is assumed that a value of "0" is input to the terminal ST of the adder AD. As a result, fil2[1,1]×pix[1,2] is output to the terminal TT of the adder AD. In this operation example, F2 [1,2] [1] = fil2[1,1] × pix[1,2]. F2 [1,2] [1] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,2].

[0234] In the arithmetic circuit MA[2,2], the terminal WI of the multiplier MP receives fil2[1,2] as a filter value, and the terminal XI of the multiplier MP receives pixel pix[1,2]. As a result, the terminal ZO of the multiplier MP receives fil2[1,2]×pix[1,2], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives F2 [1,1] The value of [1] is input. This causes F2 to be input to the terminal TT of the adder AD. [1,1] [1] + fil2[1,2] × pix[1,2] is output. In this example, F2 [1,1] [2]=F2 [1,1] [1] + fil2[1,2] × pix[1,2]. F2 [1,1] [2] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[2,2].

[0235] In addition, in the arithmetic circuit MA[3,2], fil2[1,3] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, fil2[1,3] x pix[1,2] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. In addition, the FD output from the terminal AO of the arithmetic circuit MA[2,2] is input to the terminal ST of the adder AD. However, since this calculation result is not used in the CNN calculation, it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,2].

[0236] In the arithmetic circuit MA[1,3], fil3[1,1] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,1] is input to the terminal XI of the multiplier MP. As a result, fil3[1,1] x pix[1,1] is output to the terminal ZO of the multiplier MP, and input to the terminal FT of the adder AD. Also, it is assumed that a value of "0" is input to the terminal ST of the adder AD. As a result, fil3[1,1] x pix[1,1] is output to the terminal TT of the adder AD. In this operation example, F3 [1,1] [1] = fil3[1,1] × pix[1,1]. F3 [1,1] [1] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,3].

[0237] In addition, in the arithmetic circuit MA[2,3], the terminal WI of the multiplier MP receives fil3[1,2] as a filter value, and the terminal XI of the multiplier MP receives pixel pix[1,1]. As a result, fil3[1,2] x pix[1,1] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. Also, as an example, a value of "0" is input to the terminal ST of the adder AD. As a result, fil3[1,2] x pix[1,1] is output to the terminal TT of the adder AD. However, since this calculation result is not used in the CNN calculation, it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[2,3].

[0238] In addition, in the arithmetic circuit MA[3,3], the terminal WI of the multiplier MP receives the filter value fil3[1,3], and the terminal XI of the multiplier MP receives the pixel pix[1,1]. As a result, fil3[1,3] x pix[1,1] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. Also, as an example, a value of "0" is input to the terminal ST of the adder AD. As a result, fil3[1,3] x pix[1,1] is output to the terminal TT of the adder AD. However, as with the previous arithmetic circuit MA[2,3], this calculation result is not used in the CNN calculation, so it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,3].

[0239] In addition, in the arithmetic circuits MA[4,1] to MA[9,1], MA[4,2] to MA[9,2], and MA[4,3] to MA[9,3], pixel data pix is ​​not input to the terminal XI of the multiplier MP, so no calculations are performed.

[0240] [Time T6] Next, consider the operation of the MAC array MAR at time T6. Fig. 16 is a block diagram illustrating, as an example, data output to terminals AO and SI of some arithmetic circuits MA of the MAC array MAR at time T6. Note that Fig. 16 only illustrates registers RG[1,p] through RG[5,p], arithmetic circuits MA[1,1] through MA[5,1], arithmetic circuits MA[1,2] through MA[5,2], and arithmetic circuits MA[1,3] through MA[5,3].

[0241] In the arithmetic circuit MA[1,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs a signal from the terminal OT3 to the terminal F1 [1,3]The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,1], and in addition, the terminal AO of the arithmetic circuit MA[1,1] and the terminal AI of the arithmetic circuit MA[2,1] are in a conductive state. [1,3] [1] is input to the terminal AI of the arithmetic circuit MA[2,1]. Similarly, in the arithmetic circuit MA[2,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F1 from the terminal OT3. [1,2] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[2,1], and in addition, the terminal AO of the arithmetic circuit MA[2,1] and the terminal AI of the arithmetic circuit MA[3,1] are in a conductive state, so F1 [1,2] [2] is input to the terminal AI of the arithmetic circuit MA[3,1]. Also, in the arithmetic circuit MA[3,1], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F1 from the terminal OT3. [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[3,1], and in addition, the terminal AO of the arithmetic circuit MA[3,1] and the terminal AI of the arithmetic circuit MA[4,1] are in a conductive state. [1,1] [3] is input to the terminal AI of the arithmetic circuit MA[3,1].

[0242] Similarly, in each of the arithmetic circuits MA[4,1] and MA[5,1], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from low to high as a clock signal. Because the terminal OT3 of the register RG3 in the arithmetic circuit MA[4,1] is in a state of conduction with the terminal AI of the arithmetic circuit MA[5,1] via the terminal AO of the arithmetic circuit MA[4,1], the result FD of the operation performed in the arithmetic circuit MA[4,1] is input to the terminal AI of the circuit MA[5,1]. Also, because the terminal OT3 of the register RG3 in the arithmetic circuit MA[5,1] is in a state of conduction with the terminal AI of the arithmetic circuit MA[6,1] via the terminal AO of the arithmetic circuit MA[5,1], the result FD of the operation performed in the arithmetic circuit MA[5,1] is input to the terminal AI of the circuit MA[6,1].

[0243] In the arithmetic circuit MA[1,2], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs a signal from the terminal OT3 to the terminal F2 [1,2] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,2], and in addition, the terminal AO of the arithmetic circuit MA[1,2] and the terminal AI of the arithmetic circuit MA[2,2] are in a conductive state, so F2 [1,2] [1] is input to the terminal AI of the arithmetic circuit MA[2,2]. Similarly, in the arithmetic circuit MA[2,2], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs F2 from the terminal OT3. [1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[2,2], and in addition, the terminal AO of the arithmetic circuit MA[2,2] and the terminal AI of the arithmetic circuit MA[3,2] are in a conductive state, so F2 [1,1] [2] is input to the terminal AI of the arithmetic circuit MA[3,2].

[0244] Similarly, in each of the arithmetic circuits MA[3,2] and MA[4,2], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from low to high as a clock signal. Because the terminal OT3 of the register RG3 in the arithmetic circuit MA[3,2] is in a state of conduction with the terminal AI of the arithmetic circuit MA[4,2] via the terminal AO of the arithmetic circuit MA[3,2], the result FD of the operation performed in the arithmetic circuit MA[3,2] is input to the terminal AI of the circuit MA[4,2]. Also, because the terminal OT3 of the register RG3 in the arithmetic circuit MA[4,2] is in a state of conduction with the terminal AI of the arithmetic circuit MA[5,2] via the terminal AO of the arithmetic circuit MA[4,2], the result FD of the operation performed in the arithmetic circuit MA[4,2] is input to the terminal AI of the circuit MA[5,2].

[0245] In the arithmetic circuit MA[1,3], when a potential change occurs from a low level potential to a high level potential as a clock signal, the register RG3 outputs a clock signal from the terminals OT3 to F3.[1,1] The terminal OT3 of the register RG3 is electrically connected to the terminal AO of the arithmetic circuit MA[1,3], and in addition, the terminal AO of the arithmetic circuit MA[1,3] and the terminal AI of the arithmetic circuit MA[2,3] are in a conductive state, so F3 [1,1] [1] is input to the terminal AI of the arithmetic circuit MA[2,3].

[0246] Similarly, in each of the arithmetic circuits MA[2,3] and MA[3,3], the register RG3 outputs FD from the terminal OT3 when a potential change occurs from low to high as a clock signal. Because the terminal OT3 of the register RG3 in the arithmetic circuit MA[2,3] is in a state of conduction with the terminal AI of the arithmetic circuit MA[3,3] via the terminal AO of the arithmetic circuit MA[2,3], the result FD of the operation performed in the arithmetic circuit MA[2,3] is input to the terminal AI of the circuit MA[3,3]. Also, because the terminal OT3 of the register RG3 in the arithmetic circuit MA[3,3] is in a state of conduction with the terminal AI of the arithmetic circuit MA[4,3] via the terminal AO of the arithmetic circuit MA[3,3], the result FD of the operation performed in the arithmetic circuit MA[3,3] is input to the terminal AI of the circuit MA[4,3].

[0247] At time T6, pixel data pix[1,6] is input from registers RG[1,p] to RG[3,p] to calculation circuits MA[1,1] to MA[3,1], pixel data pix[2,3] is input from registers RG[4,p] to RG[6,p] to calculation circuits MA[4,1] to MA[6,1], and no pixel data is input to calculation circuits MA[7,1] to MA[9,1]. As described above, the arithmetic circuits MA of the MAC array MAR also function as registers, so that at time T6, pixel data pix[1,5] is output from the terminal SO of each of the arithmetic circuits MA[1,1] through MA[3,1], pixel data pix[1,4] is output from the terminal SO of each of the arithmetic circuits MA[1,2] through MA[3,2], and pixel data pix[1,3] is output from the terminal SO of each of the arithmetic circuits MA[1,3] through MA[3,3]. Also, pixel data pix[2,2] is output from the terminal SO of each of the arithmetic circuits MA[4,1] through MA[6,1], and pixel data pix[2,1] is output from the terminal SO of each of the arithmetic circuits MA[4,2] through MA[6,2]. Furthermore, pixel data pix is ​​not output from the terminals SO of the arithmetic circuits MA[7,1] to MA[9,1], the arithmetic circuits MA[4,2] to MA[9,2], and the arithmetic circuits MA[4,3] to MA[9,3].

[0248] At this time, pixel data pix[1,5] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Also, pixel data pix[1,6] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,1] to MA[3,1].

[0249] Furthermore, pixel data pix[1,4] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,2] to MA[3,2]. Furthermore, pixel data pix[1,5] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,2] to MA[3,2].

[0250] Furthermore, pixel data pix[1,3] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[1,3] to MA[3,3]. Furthermore, pixel data pix[1,4] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[1,3] to MA[3,3].

[0251] Furthermore, pixel data pix[2,2] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[4,1] to MA[6,1]. Furthermore, pixel data pix[2,3] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,1] to MA[6,1].

[0252] Furthermore, pixel data pix[2,1] is input to terminal IT2 of register RG2 of each of arithmetic circuits MA[4,2] to MA[6,2]. Furthermore, pixel data pix[2,2] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,2] to MA[6,2].

[0253] Furthermore, pixel data pix[2,1] is input to terminal IT1 of register RG1 of each of arithmetic circuits MA[4,3] to MA[6,3].

[0254] Furthermore, pixel data pix[1,4] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,1] to MA[3,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,4] is input to terminal XI of multiplier MP.

[0255] Furthermore, pixel data pix[1,3] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,2] to MA[3,2]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,3] is input to terminal XI of multiplier MP.

[0256] Furthermore, pixel data pix[1,2] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[1,3] to MA[3,3]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[1,2] is input to terminal XI of multiplier MP.

[0257] Furthermore, pixel data pix[2,1] is output from terminal OT2 of register RG2 of each of arithmetic circuits MA[4,1] to MA[6,1]. Since terminal OT2 of register RG2 is electrically connected to terminal XI of multiplier MP, pixel data pix[2,1] is input to terminal XI of multiplier MP.

[0258] Here, the operations performed by the arithmetic circuits MA[1,1] to MA[9,1], MA[1,2] to MA[9,2], and MA[1,3] to MA[9,3] will be described.

[0259] In the arithmetic circuit MA[1,1], fil1[1,1] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,4] is input to the terminal XI of the multiplier MP. As a result, fil1[1,1] x pix[1,4] is output to the terminal ZO of the multiplier MP, and input to the terminal FT of the adder AD. Also, it is assumed that a value of "0" is input to the terminal ST of the adder AD. As a result, fil1[1,1] x pix[1,4] is output to the terminal TT of the adder AD. In this operation example, F1 [1,4] [1] = fil1[1,1] × pix[1,4]. F1 [1,4] [1] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,1].

[0260] In the arithmetic circuit MA[2,1], the terminal WI of the multiplier MP receives the filter value fil1[1,2], and the terminal XI of the multiplier MP receives the pixel pix[1,4]. As a result, the terminal ZO of the multiplier MP receives the output fil1[1,2]×pix[1,4], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives the output F1 [1,3] The value of [1] is input. This causes F1 to be input to the terminal TT of the adder AD. [1,3] [1] + fil1[1,2] × pix[1,4] is output. In this example, F1 [1,3] [2]=F1 [1,3] [1] + fil1[1,2] × pix[1,4]. F1 [1,3] [2] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[2,1].

[0261] In the arithmetic circuit MA[3,1], the terminal WI of the multiplier MP receives fil1[1,3] as a filter value, and the terminal XI of the multiplier MP receives pixel pix[1,4]. As a result, the terminal ZO of the multiplier MP outputs fil1[1,3]×pix[1,4], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives fil1[1,3]×pix[1,4]. [1,2] The value of [2] is input. This causes F1 to be input to the terminal TT of the adder AD. [1,2] [2] + fil1[1,3] × pix[1,4] is output. In this example, F1 [1,2] [3]=F1 [1,2] [2]+fil1[1,3]×pix[1,4]. F1 [1,2] [3] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,1].

[0262] In the arithmetic circuit MA[4,1], the terminal WI of the multiplier MP receives the filter value fil1[2,1], and the terminal XI of the multiplier MP receives the pixel pix[2,1]. As a result, the terminal ZO of the multiplier MP receives the output fil1[2,1]×pix[2,1], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives the output F1[1,1] The value of [3] is input. This causes F1 to be input to the terminal TT of the adder AD. [1,1] [3] + fil1[2,1] × pix[2,1] is output. In this example, F1 [1,1] [4]=F1 [1,1] [3]+fil1[2,1]×pix[2,1]. F1 [1,1] [4] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[4,1].

[0263] In addition, in the arithmetic circuit MA[5,1], the terminal WI of the multiplier MP receives the filter value fil1[2,2], and the terminal XI of the multiplier MP receives the pixel pix[2,1]. As a result, the terminal ZO of the multiplier MP outputs fil1[2,2] x pix[2,1], which is then input to the terminal FT of the adder AD. In addition, the terminal ST of the adder AD receives the FD output from the terminal AO of the arithmetic circuit MA[4,1]. However, since this calculation result is not used in the CNN calculation, it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[5,1].

[0264] In the arithmetic circuit MA[1,2], fil2[1,1] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,3] is input to the terminal XI of the multiplier MP. As a result, fil2[1,1]×pix[1,3] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. Also, it is assumed that a value of "0" is input to the terminal ST of the adder AD. As a result, fil2[1,1]×pix[1,3] is output to the terminal TT of the adder AD. In this operation example, F2 [1,3] [1] = fil2[1,1] × pix[1,3]. F2 [1,3] [1] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,1].

[0265] In the arithmetic circuit MA[2,2], the terminal WI of the multiplier MP receives fil2[1,2] as a filter value, and the terminal XI of the multiplier MP receives pixel pix[1,3]. As a result, the terminal ZO of the multiplier MP receives fil2[1,2]×pix[1,3], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives F2 [1,2] The value of [1] is input. This causes F2 to be input to the terminal TT of the adder AD. [1,2] [1] + fil2[1,2] × pix[1,3] is output. In this example, F2 [1,2] [2]=F2 [1,2] [1] + fil2[1,2] × pix[1,3]. F2 [1,2] [2] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[2,2].

[0266] In the arithmetic circuit MA[3,2], the terminal WI of the multiplier MP receives the filter value fil1[1,3], and the terminal XI of the multiplier MP receives the pixel pix[1,3]. As a result, the terminal ZO of the multiplier MP receives the output fil2[1,3]×pix[1,3], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives the output F2 [1,1] The value of [2] is input. This causes F2 to be input to the terminal TT of the adder AD. [1,1] [2] + fil2[1,3] × pix[1,3] is output. In this example, F2 [1,1] [3]=F2 [1,1] [2]+fil2[1,3]×pix[1,3]. F2 [1,1] [3] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,2].

[0267] In the arithmetic circuit MA[1,3], fil3[1,1] is input as a filter value to the terminal WI of the multiplier MP, and pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, fil3[1,1]×pix[1,2] is output to the terminal ZO of the multiplier MP, and input to the terminal FT of the adder AD. Also, it is assumed that a value of "0" is input to the terminal ST of the adder AD. As a result, fil3[1,1]×pix[1,2] is output to the terminal TT of the adder AD. In this operation example, F3 [1,2] [1] = fil3[1,1] × pix[1,2]. F3 [1,2] [1] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[1,3].

[0268] In the arithmetic circuit MA[2,3], the terminal WI of the multiplier MP receives the filter value fil3[1,2], and the terminal XI of the multiplier MP receives the pixel pix[1,2]. As a result, the terminal ZO of the multiplier MP receives the output fil3[1,2]×pix[1,2], which is then input to the terminal FT of the adder AD. The terminal ST of the adder AD receives the output F3 [1,1] The value of [1] is input. This causes F3 to be input to the terminal TT of the adder AD. [1,1] [1] + fil3[1,2] × pix[1,2] is output. In this example, F3 [1,1] [2]=F3 [1,1] [1] + fil3[1,2] × pix[1,2]. F3 [1,1] [2] is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[2,3].

[0269] In addition, in the arithmetic circuit MA[3,3], the filter value fil3[1,3] is input to the terminal WI of the multiplier MP, and the pixel pix[1,2] is input to the terminal XI of the multiplier MP. As a result, fil2[1,3] x pix[1,2] is output to the terminal ZO of the multiplier MP and input to the terminal FT of the adder AD. In addition, the FD output from the terminal AO of the arithmetic circuit MA[2,3] is input to the terminal ST of the adder AD. However, since this calculation result is not used in the CNN calculation, it will be referred to as FD hereafter. This FD is input to the terminal IT3 of the register RG3 of the arithmetic circuit MA[3,3].

[0270] In addition, in the arithmetic circuits MA[6,1] to MA[9,1], the arithmetic circuits MA[4,2] to MA[9,2], and the arithmetic circuits MA[4,3] to MA[9,3], pixel data pix is ​​not input to the terminal XI of the multiplier MP, so no calculations are performed.

[0271] The above-mentioned operation is performed at a certain time (here, for example, at time T 11 Continuing until the terminal AO of the arithmetic circuit MA[9,1], F1 [1,1] [9] is output. F1 [1,1] [9] is the above-mentioned operation, F1 [1,1] [9]=fil1[1,1]×pix[1,1]+fil1[1,2]×pix[1,2]+fil1[1,3]×pix[1,3]+fil1[2,1]×pix[2,1]+fil1[2,2]×pix[2,2]+fil1[2,3]×pix[2,3]+fil1[3,1]×pix[3,1]+fil1[3,2]×pix[3,2]+fil1[3,3]×pix[3,3].

[0272] In other words, F1 [1,1] [9] is the value obtained by convolving the areas of pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3] of the image data IPD with filter fil1.

[0273] Also, at time T 11 The time when the potential of the clock signal of the wiring CKL changes from a low level potential to a high level potential once (here, for example, time T 12 In this case, the terminal AO of the arithmetic circuit MA[9,1] is connected to F1 [1,2] [9] is output. F1 [1,2] [9] is the above-mentioned operation, F1 [1,2] [9]=fil1[1,1]×pix[1,2]+fil1[1,2]×pix[1,3]+fil1[1,3]×pix[1,4]+fil1[2,1]×pix[2,2]+fil1[2,2]×pix[2,3]+fil1[2,3]×pix[2,4]+fil1[3,1]×pix[3,2]+fil1[3,2]×pix[3,3]+fil1[3,3]×pix[3,4].

[0274] In other words, F1 [1,2] [9] is the value obtained by convolving the areas of pixel data pix[1,2] to pixel data pix[1,4], pixel data pix[2,2] to pixel data pix[2,4], and pixel data pix[3,2] to pixel data pix[3,4] of the image data IPD with filter fil1.

[0275] Also, at time T 12 Now, from the terminal AO of the arithmetic circuit MA[9,2], F2 [1,1] [9] is output. F2 [1,1] [9] is the F2 [1,1] [9]=fil2[1,1]×pix[1,1]+fil2[1,2]×pix[1,2]+fil2[1,3]×pix[1,3]+fil2[2,1]×pix[2,1]+fil2[2,2]×pix[2,2]+fil2[2,3]×pix[2,3]+fil2[3,1]×pix[3,1]+fil2[3,2]×pix[3,2]+fil2[3,3]×pix[3,3].

[0276] In other words, F2 [1,1][9] is the value obtained by convolving the areas of pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3] of the image data IPD with filter fil2.

[0277] In this way, by inputting image data IPD to the MAC array MAR, the filters fil1 to fil2 are output from the arithmetic circuits MA[9,1] to MA[9,10], respectively. 10 The results of the convolution operations performed by the above operations are sequentially output. The results of the convolution operations can be shown as in FIG. 17, for example. In the MAC array MAR shown in FIG. 17, the operation circuits MA[1,1] to MA[1,9] and the operation circuits MA[9,1] to MA[9,9] are selectively shown. Also, at time T 12 to time T 20 Each of these is at time T 11 In this example, the time is defined as the time when a potential change from a low level potential to a high level potential occurs 1 to 9 times on the wiring CKL as a clock signal.

[0278] For example, at time T 18 In this case, when a potential change from a low level potential to a high level potential occurs in the wiring CKL as a clock signal, F1 is output from each of the arithmetic circuits MA[9,1] to MA[9,8] as the result of the convolution calculation performed by the filters fil1 to fil8. [1,8] [9], F2 [1,7] [9], F3 [1,6] [9], F4 [1,5] [9], F5 [1,4] [9], F6 [1,3] [9], F7 [1,2] [9], F8 [1,1] Note that the arithmetic circuits MA[9,9] and MA[9,10] do not output any calculation results because the convolution calculations have not yet been completed in the 9th and 10th columns of the MAC array MAR.

[0279] Furthermore, the convolution calculation results output from the calculation circuits MA[9,1] to MA[9,10] may be processed by the circuits AF[1] to AF

[10] using an activation function, a pooling layer, etc. Here, as an example, the filter fil t F obtained by convolution of t [1,1] [9]~F t [m-2,n-2] [9], we apply the activation function to each of them to obtain F At [1,1] ~F At [m-2,n-2] It is assumed that the following can be obtained.

[0280] where F At [1,1] ~F At [m-2,n-2] These are arranged in a matrix of m-2 rows and n-2 columns and are called image data IPD-F. t Image data IPD-F t For example, the filter fil is applied to the image data IPD. t The filter fil is obtained by performing convolution processing using the activation function and then calculating the result of the convolution processing using the activation function. t It is possible to create image data (sometimes called a feature map) that extracts only the characteristic parts that depend on the image data IPD-F. t can be expressed as shown in FIG. 18, for example.

[0281] <<Convolutional Layer CL Operation 2>> Next, we will explain a method of computing the convolutional layer CL and the pooling layer PL, which is different from the above-mentioned method, using the computing device 100. Note that, as in the above-mentioned computing method, the computing circuits MA included in the MAC array MAR of the computing device 100 are arranged in a matrix of 9 rows and 10 columns, for example.

[0282] 19A, 19B, and 20. Specifically, as shown in FIG. 19A, in an arithmetic circuit MA included in the s-th row (where s is an integer between 1 and 9) of the MAC array MAR, the programmable switch PR is set so that the terminal SO of the arithmetic circuit MA is in a conductive state with the terminal SI of the adjacent arithmetic circuit MA. For example, the programmable switches PR[s,1] and PR[s,2] are set so that the terminal SO of the arithmetic circuit MA[s,1] is in a conductive state with the terminal SI of the arithmetic circuit MA[s,2], and the programmable switches PR[s,2] and PR[s,3] are set so that the terminal SO of the arithmetic circuit MA[s,2] is in a conductive state with the terminal SI of the arithmetic circuit MA[s,3]. The wiring XL[s] is electrically connected to the terminal SI of the arithmetic circuit MA[s,1] via the programmable switch PR[s,1]. In this manner, in this operation method, the programmable switch PR is set so that the arithmetic circuits MA are electrically connected in series in each row of the MAC array MAR.

[0283] 19B, in the MAC array MAR in this operation method, in each of the arithmetic circuits MA[s,1] to MA[s,9] included in one row of the MAC array MAR, the programmable switches PC are set so that the terminal AO of one arithmetic circuit MA is electrically connected to the terminal AI of another arithmetic circuit MA, and data output from the terminal AO of one arithmetic circuit MA is input to the terminal AI of the original arithmetic circuit MA via a plurality of different arithmetic circuits MA. For example, the programmable switches PR[s,9] and PR[s,8] are set so that the terminal AO of the arithmetic circuit MA[s,9] is electrically connected to the terminal AI of the arithmetic circuit MA[s,8]. For example, the programmable switches PR[s,8] and PR[s,7] are set so that the terminal AO of the arithmetic circuit MA[s,8] is electrically connected to the terminal AI of the arithmetic circuit MA[s,7]. Furthermore, the programmable switches PR[s,1] and PR[s,9] are set so that the terminal AO of the arithmetic circuit MA[s,1] is electrically connected to the terminal AI of the arithmetic circuit MA[s,9]. That is, in this operation method, the programmable switches PR[s,1] to PR[s,9] are set in the arithmetic circuits MA of each row of the MAC array MAR so that data output from the arithmetic circuit MA circulates to other arithmetic circuits MA in the same row. Note that in this operation method, the arithmetic circuit MA[s,10] is not used, and therefore the arithmetic circuit MA[s,10] is electrically disconnected from the other arithmetic circuits MA by the programmable switch PR[s,10].

[0284] 20, in the MAC array MAR in this operation method, in an arithmetic circuit MA included in the t-th column of the MAC array MAR (where t is an integer between 1 and 10), the programmable switch PC is set so that the terminal MO of the arithmetic circuit MA is electrically connected to the terminal MI of the adjacent arithmetic circuit MA. For example, the programmable switch PC[1,t] and the programmable switch PC[2,t] are set so that the terminal MO of the arithmetic circuit MA[1,t] is electrically connected to the terminal MI of the arithmetic circuit MA[2,t]. Furthermore, the programmable switch PC[2,t] and the programmable switch PC[3,t] are set so that the terminal MO of the arithmetic circuit MA[2,t] is electrically connected to the terminal MI of the arithmetic circuit MA[3,t]. The wiring YL[t] is electrically connected to the terminal MO of the arithmetic circuit MA[9,t] via the programmable switch PC[9,t]. In this manner, in this operating method, it is assumed that the programmable switches PC are set so that the arithmetic circuits MA are serially connected to each other and are in a conductive state in each column of the MAC array MAR.

[0285] Figure 21 shows the time T 21 From time T 41 21 is a timing chart showing changes in data input to the terminals SI, SO, AI (terminal ST of the adder), AO, MO, terminals XI and WI of the multiplier MP, terminal TT of the adder, and terminal IT4 of the register RG4 of the arithmetic circuit MA[1,1] during and around the time. Also shown in FIG. 21 are changes in the potentials of the lines CKL, SLT, SEL, and URST. In FIG. 21, "high" represents a high-level potential, and "low" represents a low-level potential.

[0286] The calculation method performed in the MAC array MAR will be described below with reference to the timing chart in Fig. 21. Unless otherwise specified, the calculation method is assumed to be performed in the calculation circuits MA[1,1] to MA[1,9].

[0287] [Step 0: Initialization] First, an initialization operation is performed in the arithmetic device 100. Specifically, at time T 21 Prior to this, it is preferable that initialization data be input to the terminals SI, SO, XT, WT, AI (terminal ST), TT, and AO of each of the arithmetic circuits MA[1,1] to MA[9,10] (not shown in FIG. 21). The initialization data may be, for example, data with a value of "0." Furthermore, the potential of the wiring URST is changed from a low-level potential to a high-level potential, and the potential of the terminal AO is adjusted to an appropriate value by the register RG3. At this time, it is preferable that the potential of the terminal AO be set to, for example, a potential corresponding to the value of "0." Furthermore, when the potential of the wiring URST is a low-level potential, the potential of the wiring SEL is set to a high-level potential, and the potential of the terminal MO is adjusted to an appropriate value by the register RG4. At this time, it is preferable that the potential of the terminal MO be set to, for example, a potential corresponding to the value of "0."

[0288] [Step 1: Input image data] Next, pixel data pix of the image data IPD is input to each of the arithmetic circuits MA[1,1] to MA[9,10] of the MAC array MAR of the arithmetic device 100. Note that, as an example, the image data IPD here is assumed to be composed of a plurality of pixel data pix[1,1] to pix[m,n] in m rows and n columns, as shown in Fig. 10A, in the same manner as in the above-mentioned arithmetic method.

[0289] The image data IPD is read from the storage unit MEMD of the arithmetic device 100, for example.

[0290] As in the above-described calculation method, in this operation method, the registers RG[1,p] to RG[9,p] are electrically connected to the MAC array MAR, and pixel data pix is ​​input to the s-th row of the MAC array MAR via the registers RG[s,1] to RG[s,p].

[0291] The registers RG[s,1] to RG[s,p] sequentially transmit a plurality of pixel data pix read from the memory unit MEMD each time a potential change from a low level potential to a high level potential is input as a clock signal to the wiring CKL. Also, as described above, the arithmetic circuits MA[s,1] to MA[s,10] on the sth row have the function of a register with the terminal SI as an input terminal and the terminal SO as an output terminal, and therefore the pixel data pix sent to the register RG[s,p] are sequentially transmitted to the arithmetic circuits MA[s,1] to MA[s,10] in response to the clock signal.

[0292] In this operation method, the pixel data pix is ​​transmitted to the MAC array MAR in such a way that the same pixel data pix is ​​input to the same column of the arithmetic circuit MA at the same timing for each row, as shown in FIG. 22A. 23 22A shows the input of pixel data pix to the MAC array MAR. Specifically, for example, pixel data pix[1,1] is held by the register RG1 of each of the arithmetic circuits MA[1,2] through MA[9,2] and output to the terminal SO of each of the arithmetic circuits MA[1,2] through MA[9,2]. Similarly, pixel data pix[1,2] is held by the register RG1 of each of the arithmetic circuits MA[1,1] through MA[9,1]. Note that registers RG[1,p] through RG[9,p] external to the MAC array MAR hold pixel data pix[1,3] and input the pixel data pix[1,3] to the arithmetic circuits MA[1,1] through MA[9,1]. Note that arithmetic circuits MA[1,10] through MA[9,10] are not shown in FIG.

[0293] From the stage shown in Figure 22A, the potential of the clock signal changes six times from low level potential to high level potential, and the pixel data pix[3,3] is input to the terminals SI of the arithmetic circuits MA[1,1] to MA[9,1] as shown in Figure 22B. The time at which this happens is referred to as time T 29 Let's say.

[0294] Note that a low-level potential is input to the line SLT until the pixel data pix[1,1] is held in the registers RG1 of the arithmetic circuits MA[1,9] through MA[9,9]. In other words, during the period from when the pixel data pix[1,1] is input to the MAC array MAR until when it is held in the registers RG1 of the arithmetic circuits MA[1,1] through MA[9,9], the register RG2 does not acquire the pixel data pix from the terminal IT2.

[0295] After the pixel data pix[1,1] is stored in the register RG1 of the arithmetic circuit MA[1,9] to the arithmetic circuit MA[9,9], a high-level potential is temporarily input to the line SLT (the time at which this occurs is referred to as time T 31 At this time, a potential change from low to high occurs as a clock signal, causing the register RG2 to hold the pixel data pix[1,1] input to the terminal IT2 of the register RG2 of each of the arithmetic circuits MA[1,9] to MA[9,9], and output the pixel data pix[1,1] to the terminal OT2. After the pixel data pix[1,1] is held in the register RG2 of each of the arithmetic circuits MA[1,9] to MA[9,9], a low potential is input to the line SLT. This is done to prevent the pixel data pix[1,1] held in the register RG2 from being rewritten when a potential change from low to high occurs as a clock signal.

[0296] In the MAC array MAR, the same applies to the arithmetic circuits other than the arithmetic circuit MA[1,9] to the arithmetic circuit MA[9,9] at time T 31 At this time, a high level potential is temporarily input to the wiring SLT. 31The pixel data pix input to the terminal IT2 of the register RG2 of each of the arithmetic circuits MA[1,1] to MA[9,8] in the arithmetic circuit MA[1,1] through the arithmetic circuit MA[9,8] is held and the pixel data pix is ​​output to the terminal OT2. For example, since the pixel data pix[3,3] is input to the terminal IT2 of the register RG2 of the arithmetic circuit MA[9,1], when a high-level potential is input to the line SLT, the pixel data pix[3,3] is output to the terminal OT2.

[0297] [Step 2: Read filter values] Also, at time T 31 At this time, a filter value is read from the storage unit OSM in each of the arithmetic circuits MA[1,1] to MA[1,9] of the MAC array MAR of the arithmetic device 100. Ct In this case, the matrix is ​​one of the elements of the matrix included in fil shown in FIG. t As an example, it is assumed that a filter value corresponding to the context CTEX1 is read from each of the storage units OSM of the arithmetic circuits MA[1,1] to MA[1,10] in the first row of the MAC array MAR.

[0298] The filter value corresponding to the context CTEX1 is the value in the block indicated by the context CTEX1, which is read from the memory unit OSM of each of the arithmetic circuits MA[1,1] to MA[1,9], as shown in Fig. 23. Note that Fig. 23 also shows the filter values ​​corresponding to not only the context CTEX1 but also the contexts CTEX2 to CTEX9.

[0299] Specifically, when a signal of the context CTEX1 is given to the storage unit OSM of each of the arithmetic circuits MA[1,1] to MA[1,9], the storage unit OSM of the arithmetic circuit MA[1,9] outputs fil C1 [1,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,8]. C2[1,2] is read out and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,7]. C3 [1,3] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,6]. C4 [2,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,5]. C5 [2,2] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,4]. C6 [2,3] is read out and fil is read out from the memory part OSM of the arithmetic circuit MA[1,3]. C7 [3,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,2]. C8 [3,2] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,1]. C9 [3,3] is read out.

[0300] [Step 3: Multiplying pixel data by filter value] Next, the pixel data and filter values ​​performed by each multiplier MP in the arithmetic circuits MA[1,1] to MA[1,9] in the first row of the MAC array MAR will be described.

[0301] For example, in the arithmetic circuit MA[1,9], the terminal WI of the multiplier MP receives a filter value fil C1 [1,1] is input to the register RG2. Also, since the pixel data pix[1,1] is held in the register RG2, the pixel data pix[1,1] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP receives the pixel data pix[1,1]. C1 [1,1] x pix[1,1] is output. Also, assume that the terminal ST of the adder AD is input with data of "0" as the initial value. As a result, the terminal FT of the adder AD is input with data of "0". C1 By inputting [1,1] × pix[1,1], the terminal TT of the adder AD is C1 [1,1] x pix[1,1] is output. In this example, A1[1]=fil C1 Let [1,1] x pix[1,1]. A1[1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,9].

[0302] Also, for example, in the arithmetic circuit MA[1,1], the terminal WI of the multiplier MP receives a filter value fil C9 In addition, since the pixel data pix[3,3] is held in the register RG2, the pixel data pix[3,3] is input to the terminal XI of the multiplier MP. As a result, the terminal ZO of the multiplier MP receives the pixel data pix[3,3]. C1 [3,3] x pix[3,3] is output. Also, assume that the terminal ST of the adder AD is input with data of "0" as the initial value. As a result, the terminal FT of the adder AD is input with fil C9 By inputting [3,3] × pix[3,3], the terminal TT of the adder AD is C9 [3,3] x pix[3,3] is output. In this example, A9[1]=fil C9 Let it be [3,3] x pix[3,3]. A9[1] is input to terminal IT3 of register RG3 of arithmetic circuit MA[1,1].

[0303] The same calculations as those of the calculation circuits MA[1,9] and MA[1,1] are performed for the calculation circuits MA[1,2] through MA[1,8]. At this time, the multiplication results output from each adder AD are input to the terminal IT3 of the corresponding register RG3. The following table shows the multiplication results input to the terminal IT3 of the register RG3 of each of the calculation circuits MA[1,1] through MA[1,9]. The respective multiplication results are assumed to be A9[1], A8[1], A7[1], A6[1], A5[1], A4[1], A3[1], and A2[1].

[0304] [Table 1]

[0305] [Step 4: Switching filter values ​​and adding the calculation results] Here, when a potential change from a low level potential to a high level potential occurs as a clock signal, the register RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9] holds the addition data input to the terminal IT3 and outputs the addition data to the terminal OT3 of the register RG3 (the time at which this occurs is referred to as time T 32 As a result, as shown in FIG. 24A, A9[1], A8[1], A7[1], A6[1], A5[1], A4[1], A3[1], A2[1], and A1[1] are output from the terminals AO of the arithmetic circuits MA[1,1] to MA[1,9], respectively.

[0306] A1[1] is input to the terminal AI of the arithmetic circuit MA[1,8], A2[1] is input to the terminal AI of the arithmetic circuit MA[1,7], A3[1] is input to the terminal AI of the arithmetic circuit MA[1,6], A4[1] is input to the terminal AI of the arithmetic circuit MA[1,5], A5[1] is input to the terminal AI of the arithmetic circuit MA[1,4], A6[1] is input to the terminal AI of the arithmetic circuit MA[1,3], A7[1] is input to the terminal AI of the arithmetic circuit MA[1,2], A8[1] is input to the terminal AI of the arithmetic circuit MA[1,1], and A9[1] is input to the terminal AI of the arithmetic circuit MA[1,9].

[0307] At this time, it is assumed that in each of the arithmetic circuits MA[1,1] to MA[1,9], a filter value corresponding to the context CNTX2 shown in FIG. 23 is read from the storage unit OSM.

[0308] Specifically, the storage unit OSM of the arithmetic circuit MA[1,8] stores fil C1 [1,2] is read out and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,7]. C2 [1,3] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,6]. C3 [2,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,5]. C4 [2,2] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,4]. C5[2,3] is read out and fil is read out from the memory part OSM of the arithmetic circuit MA[1,3]. C6 [3,1] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,2]. C7 [3,2] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,1]. C8 [3,3] is read out, and fil is read out from the memory unit OSM of the arithmetic circuit MA[1,9]. C9 Assume that [1,1] is read out.

[0309] As a result, as in step 3, in each of the arithmetic circuits MA[1,1] to MA[1,9], the pixel data pix held by the register RG2 is input to the terminal XI of the multiplier MP, and the changed filter value is input to the terminal WI of the multiplier MP, so that the multiplication result of the pixel data and the filter value is output from the terminal ZO of the multiplier MP.

[0310] Furthermore, in each adder AD of the arithmetic circuits MA[1,1] to MA[1,9], the multiplication result is input to the terminal FT of the adder AD, and the data input to the terminal AI is input to the terminal ST of the adder AD. Therefore, the sum data output from the terminal TT of the adder AD is as shown in the following table. Note that the respective multiplication results are A8[2], A7[2], A6[2], A5[2], A4[2], A3[2], A2[2], A1[2], and A9[2].

[0311] [Table 2]

[0312] Then, A8[2], A7[2], A6[2], A5[2], A4[2], A3[2], A2[2], A1[2], and A9[2] are input to terminal IT3 of register RG3 of each of arithmetic circuits MA[1,1] to MA[1,9].

[0313] Here, when a potential change from low level potential to high level potential occurs as a clock signal, the registers RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9] output A8[2], A7[2], A6[2], A5[2], A4[2], A3[2], A2[2], A1[2], and A9[2] from the terminals AO of each of the arithmetic circuits MA[1,1] to MA[1,9], as shown in Figure 24B.

[0314] [Step 5: Repeat step 4] The operation of step 4 involves repeatedly holding the data input to the register RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9], outputting the data to the terminal OT3 of the register RG3, reading the corresponding filter value from the memory unit OSM of each of the arithmetic circuits MA[1,1] to MA[1,9], and adding the multiplication result of the filter value and the pixel data pix to the corresponding data. In particular, the filter values ​​read from the memory unit OSM of each of the arithmetic circuits MA[1,1] to MA[1,9] can be sequentially selected from the contexts CNTX3 to CNTX9 in FIG.

[0315] For example, in the arithmetic circuit MA[1,1], at time T 33 From time T 40 During this period, the contexts CNTX3 to CNTX9 in FIG. 23 are selected in order as filter values ​​read from the storage unit OSM. C7 [3,3], fil C6 [3,3], fil C5 [3,3], fil C4 [3,3], fil C3 [3,3], fil C2 [3,3], fil C1 The arithmetic circuit MA[1,1] outputs A7[3], A6[4], A5[5], A4[6], A3[7], A2[8], and A1[9] from the terminal AO based on the operations in each of the contexts CNTX3 to CNTX9.

[0316] From the above, time T 40 At this stage, A1[9], A9[9], A8[9], A7[9], A6[9], A5[9], A4[9], A3[9], and A2[9] are input to terminal IT3 of register RG3 of each of arithmetic circuits MA[1,1] to MA[1,9].

[0317] As an example, A1[9] is the result of the multiplication and addition operation of the filter value and the pixel data pix by the arithmetic circuits MA[1,1] to MA[1,9]. Specifically, A1[9] is calculated as follows by the above operation: A1[9]=fil C1 [1,1]×pix[1,1]+fil C1 [1,2]×pix[1,2]+fil C1 [1,3]×pix[1,3]+fil C1 [2,1]×pix[2,1]+fil C1 [2,2]×pix[2,2]+fil C1 [2,3]×pix[2,3]+fil C1 [3,1]×pix[3,1]+fil C1 [3,2]×pix[3,2]+fil C1 It becomes [3,3]×pix[3,3].

[0318] That is, A1[9] is a filter fil C1 The value is obtained by convolution with

[0319] Similarly, A9[9] is calculated as follows: A9[9]=fil C9 [3,3]×pix[3,3]+fil C9 [1,1]×pix[1,1]+fil C9 [1,2]×pix[1,2]+fil C9 [1,3]×pix[1,3]+fil C9 [2,1]×pix[2,1]+fil C9[2,2]×pix[2,2]+fil C9 [2,3]×pix[2,3]+fil C9 [3,1]×pix[3,1]+fil C9 It becomes [3,2]×pix[3,2].

[0320] That is, A9[9] filters the pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3] of the image data IPD using the filter fil C9 The value is obtained by convolution with

[0321] Therefore, like A1[9] and A9[9], each of A2[9] to A8[9] filters the pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3] of the image data IPD using the filter fil C2 or filter fil C8 The value is obtained by convolution with

[0322] [Step 6: Output the result of the multiply-and-accumulate operation] In step 6, the values ​​of the sum-of-products operation are output from the terminals MO of the arithmetic circuits MA[1,1] to MA[1,9]. 40 In this example, since a high-level potential is input to the control terminal of the selector SLC of each of the arithmetic circuits MA[1,1] to MA[1,9], the first input terminal and the output terminal are in a conductive state, and the second input terminal and the output terminal are in a non-conductive state, which causes a conductive state between the terminal OT3 of the register RG3 and the terminal IT4 of the register RG4.

[0323] At this time, a potential change from low to high occurs in the clock signal, and the data input to the terminal IT3 of the register RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9] is held and the data is output to the terminal OT3 of the register RG3. Therefore, the data is input to the terminal IT4 of the register RG4.

[0324] In other words, A1[9], A9[9], A8[9], A7[9], A6[9], A5[9], A4[9], A3[9], and A2[9] are held in the registers RG3 of each of the arithmetic circuits MA[1,1] to MA[1,9], and each data is input to the terminal IT4 of the register RG4.

[0325] Furthermore, when a potential change from a low level potential to a high level occurs as a clock signal (the time at which this occurs is called T 41 The data input to the terminal IT4 of the register RG4 is held by the register RG4 and the data is output to the terminal OT4 of the register RG4. Therefore, A1[9], A9[9], A8[9], A7[9], A6[9], A5[9], A4[9], A3[9], and A2[9] output from the register RG4 of each of the arithmetic circuits MA[1,1] to MA[1,9] are output from the terminals MO of the arithmetic circuits MA[1,1] to MA[1,9].

[0326] In step 6, a low-level potential is input to the control terminal of each selector SLC of each arithmetic circuit MA other than the arithmetic circuits MA[1,1] to MA[1,9] of the MAC array MAR. This causes a non-conductive state between the first input terminal and the output terminal, and a conductive state between the second input terminal and the output terminal. This causes a conductive state between the terminal MI of the corresponding arithmetic circuit MA and the terminal IT4 of the register RG4.

[0327] 20, the terminal MO of the arithmetic circuit MA[1,1] in the first column of the MAC array MAR is electrically connected to the terminal MI of the arithmetic circuit MA[9,1] via the arithmetic circuits MA[2,1] to MA[8,1]. Similarly, for the other columns, in the same column of the MAC array MAR, the terminal MO of the arithmetic circuit MA located in the first row is electrically connected to the terminal MI of the arithmetic circuit MA in the ninth row via the arithmetic circuits MA in the second to eighth rows.

[0328] Therefore, after A1[9], A9[9], A8[9], A7[9], A6[9], A5[9], A4[9], A3[9], and A2[9] are output from the terminals MO of each of the arithmetic circuits MA[1,1] to MA[1,9], eight potential changes from low level potential to high level potential occur as a clock signal, and as shown in Figure 24C, A1[9], A9[9], A8[9], A7[9], A6[9], A5[9], A4[9], A3[9], and A2[9] are output from the terminals MO of each of the arithmetic circuits MA[9,1] to MA[9,9].

[0329] On the other hand, in the arithmetic circuits MA other than the arithmetic circuits MA[1,1] to MA[1,9] of the MAC array MAR, a low-level potential is input to the control terminal of each selector SLC, so that there is no conduction between the first input terminal and the output terminal. Therefore, the arithmetic circuits MA other than the arithmetic circuits MA[1,1] to MA[1,9] of the MAC array MAR can output the arithmetic results such as A1[9], A9[9], A8[9], A7[9], A6[9], A5[9], A4[9], A3[9], A2[9], and the like, and can simultaneously perform arithmetic operations. Therefore, in the arithmetic circuits MA other than the first row of the MAC array MAR, convolution operations may be performed on areas of the image data IPD other than pixel data pix[1,1] to pixel data pix[1,3], pixel data pix[2,1] to pixel data pix[2,3], and pixel data pix[3,1] to pixel data pix[3,3], for example.

[0330] As shown in the timing chart of FIG. 21, during the calculation by the multiplier MP and the adder AD, specifically, at time T 30 From time T 39During this period, the pixel data pix[1,2] to pix[1,4], pixel data pix[2,2] to pix[2,4], and pixel data pix[3,2] to pix[3,4] for the next calculation may be sequentially transmitted from the registers RG[1,p] to RG[9,p] to the MAC array MAR. By performing this operation, immediately after the convolution calculations for the pixel data pix[1,1] to pix[1,3], pixel data pix[2,1] to pix[2,3], and pixel data pix[3,1] to pix[3,3] are completed, the convolution calculations for the pixel data pix[1,2] to pix[1,4], pixel data pix[2,2] to pix[2,4], and pixel data pix[3,2] to pix[3,4] can be performed in the same manner. Furthermore, by transmitting pixel data during calculation, the time spent waiting for data transfer can be reduced, thereby improving calculation efficiency.

[0331] The convolution calculation results output from the calculation circuits MA[9,1] to MA[9,10] may be processed by the circuits AF[1] to AF

[10] using activation functions, pooling layers, etc. For details of this processing, please refer to the explanation of the operation method described above.

[0332] In this operation method, as in the above-described operation method, the filter fil is applied to the image data IPD. Ct By performing convolution processing using Ct It is possible to generate image data (feature map) that extracts only the characteristic parts that depend on the

[0333] The above-described operation method can be applied not only to the convolution calculation of image data but also to the calculation of FNN.

[0334] For example, m neurons (where m is an integer equal to or greater than 1) in the (k-1)th layer N (k-1) 1 to neuron N (k-1) mFrom the kth layer, n neurons (where n is an integer greater than or equal to 1) (k) 1 to neuron N (k) n Let us consider the case where a signal is sent to the (k-1)th layer neuron N (k-1) i (where i is an integer between 1 and m) (k-1) i Let N be the neuron in the (k-1)th layer. (k-1) i and the k-th layer neuron N (k) j The weighting coefficient between (k-1) i (k) j Then, the (k-1)th layer neuron N (k-1) 1 to neuron N (k-1) m to the k-th layer neuron N (k) j The sum of the products of the signals input to and the weighting coefficients is S (k) j =Σw (k-1) i (k) j ×z (k-1) i (Σ is the sum from 1 to m for i).

[0335] Here, the kth layer neuron N (k) 1 to neuron N (k) n S for each of (k) j The method for calculating z is explained below. (k-1) i Specifically, for example, in FIG. 26, the registers RG2 of the arithmetic circuits MA[1,1] to MA[1,10] store z (k-1) 10 ~z (k-1) It holds 1.

[0336] Next, the data read from the storage units OSM of the arithmetic circuits MA[1,1] to MA[1,10] are used as weighting coefficients to set, for example, contexts CNTXF1 to CNTXF10. The contexts CNTXF1 to CNTXF10 may be set, for example, as shown in FIG. 26. In this way, z is stored in the registers RG2 of the arithmetic circuits MA[1,1] to MA[1,10]. (k-1) 10 ~z (k-1) By holding 1 and setting the weighting coefficients read from the storage unit OSM as shown in FIG. 26 to the contexts CNTXF1 to CNTXF10, it is possible to perform FNN calculations in the same way as the above-mentioned convolution calculations.

[0337] Although FIG. 26 shows the case where the number of neurons in the k-th layer is n=10, if n is not 10, the number of contexts should be set to the number of n. Also, FIG. 26 shows the case where the number of neurons in the (k-1)-th layer is m=10, but if m is smaller than 10, the number of arithmetic circuits MA used for calculation should be reduced. Also, if m is larger than 10, the neuron signal z (k-1) 1 to z (k-1) 10 When performing the sum-of-products calculation of the weighting coefficients, the signal of the neuron to be calculated next may be stored in advance in the register RG1 of each of the calculation circuits MA[1,1] to MA[1,10].

[0338] Furthermore, the operation method of the semiconductor device according to one embodiment of the present invention is not limited to the above-described method. The operation method of the semiconductor device according to one embodiment of the present invention can be changed depending on the situation. For example, the configuration of the MAC array MAR set by the programmable switches PR shown in FIG. 19B may be changed to the configuration of the MAC array MAR set by the programmable switches PR shown in FIG. 25.

[0339] 25, the programmable switches PR[s,1] to PR[s,9] are set so that the terminal AO of an arithmetic circuit MA is electrically connected to the terminal AI of the arithmetic circuit MA next to it. Note that for the arithmetic circuits MA[s,1] and MA[s,2], the programmable switches PR[s,2] and PR[s,1] are set so that the terminal AO of the arithmetic circuit MA[s,2] is electrically connected to the terminal AI of the arithmetic circuit MA[s,1], and for the arithmetic circuits MA[s,8] and MA[s,9], the programmable switches PR[s,9] and PR[s,8] are set so that the terminal AO of the arithmetic circuit MA[s,9] is electrically connected to the terminal AI of the arithmetic circuit MA[s,8].

[0340] In the configuration shown in Figure 19B, the distance between terminal AO of arithmetic circuit MA[s,1] and terminal AI of arithmetic circuit MA[s,9] is long, which may cause signal delays. However, in the configuration shown in Figure 25, the distance between arithmetic circuits MA can be shortened on average, which can suppress signal delays.

[0341] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0342] (Embodiment 2) In this embodiment, a memory circuit that can be applied to the memory unit OSM explained in the above-mentioned embodiment will be explained.

[0343] The storage unit OSM may be, for example, a register, a flip-flop, a static random access memory (SRAM), etc. Alternatively, for example, a flash memory may be used.

[0344] Furthermore, for example, a Dynamic Oxide Semiconductor Random Access Memory (DOSRAM) (registered trademark) or a Dynamic Oxide Semiconductor Random Access Memory (NOSRAM) (registered trademark) may be applied as the storage unit OSM.

[0345] 27A shows an example of the circuit configuration of a DOSRAM memory cell. The memory cell 221 includes a transistor M1 and a capacitance element CA. The transistor M1 includes a front gate (sometimes simply referred to as a gate) and a back gate.

[0346] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to the wiring BIL, a gate of the transistor M1 is connected to the wiring WOL, a back gate of the transistor M1 is connected to the wiring BGL, and a second terminal of the capacitance element CA is connected to the wiring CVL.

[0347] The transistor M1 functions as a write transistor in the memory cell 221. Note that the write transistor is preferably an OS transistor, which will be described later.

[0348] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CVL.

[0349] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying a given potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0350] Data is written and read by applying a high-level potential to the wiring WOL to turn on the transistor M1 and establish electrical continuity between the wiring BIL and the first terminal of the capacitor CA.

[0351] Specifically, data is written by applying a potential corresponding to the data to be written to the wiring BIL and writing the potential to the first terminal of the capacitor CA through the transistor M1. After the data is written, a low-level potential is applied to the wiring WOL to turn off the transistor M1, so that the potential can be held in the memory cell 221.

[0352] To read data, the wiring BIL is first precharged to an appropriate potential, for example, a potential intermediate between a low-level potential and a high-level potential, and then the wiring BIL is set to an electrically floating state. After that, a high-level potential is applied to the wiring WOL to turn on the transistor M1, thereby changing the potential of the wiring BIL. The change in the potential of the wiring BIL is determined by the potential written to the first terminal of the capacitor CA, so the data stored in the memory cell 221 can be read from the changed potential of the wiring BIL.

[0353] Furthermore, the above-described memory cell 221 is not limited to the circuit configuration shown in FIG. 27A, and the circuit configuration of the memory cell 221 may be changed as appropriate.

[0354] 27B shows an example of the circuit configuration of a NOSRAM memory cell. The memory cell 231 includes a transistor M2, a transistor M3, and a capacitance element CB. The transistor M2 includes a front gate (sometimes simply referred to as a gate) and a back gate.

[0355] The transistor M2 functions as a write transistor in the memory cell 231. Note that the write transistor is preferably an OS transistor, which will be described later.

[0356] The transistor M3 also functions as a read transistor in the memory cell 231. The read transistor is preferably an OS transistor (described later) or a transistor containing silicon in its semiconductor layer. In this operation example, the transistor M3 operates in the saturation region unless otherwise specified. That is, the gate voltage, source voltage, and drain voltage of the transistor M3 are appropriately biased to voltages within the range in which the transistor M3 operates in the saturation region.

[0357] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SOL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0358] The line WBL functions as a write bit line, the line RBL functions as a read bit line, and the line WOL functions as a word line. The line CAL functions as a line for applying a predetermined potential to the second terminal of the capacitance element CB. During data retention, it is preferable to apply a low-level potential (sometimes called a reference potential) to the line CAL, and during data writing and reading, it is preferable to apply a high-level potential to the line CAL.

[0359] The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying a given potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

[0360] Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M2, and establishing electrical continuity between the wiring WBL and the first terminal of the capacitor CB. Specifically, when the transistor M2 is on, a potential corresponding to the information to be recorded is applied to the wiring WBL, and the potential is written to the first terminal of the capacitor CB and the gate of the transistor M3. Then, a low-level potential is applied to the wiring WOL, turning off the transistor M2, thereby maintaining the potential of the first terminal of the capacitor CB and the potential of the gate of the transistor M3.

[0361] Data is read by applying a predetermined potential to the wiring SOL. The current flowing between the source and drain of the transistor M3 and the potential of the first terminal of the transistor M3 are determined by the potential of the gate of the transistor M3 and the potential of the second terminal of the transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of the transistor M3, the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3) can be read. In other words, information written in this memory cell can be read from the potential held in the first terminal of the capacitor CB (or the gate of the transistor M3).

[0362] Furthermore, the memory cell 231 described above is not limited to the circuit configuration shown in FIG. 27B, and the circuit configuration of the memory cell 231 may be changed as appropriate. For example, the wiring WBL and the wiring RBL may be combined into a single wiring BIL. An example of the circuit configuration of such a memory cell is shown in FIG. 27C. The memory cell 232 is configured such that the wiring WBL and the wiring RBL of the memory cell 231 are combined into a single wiring BIL, and the second terminal of the transistor M2 and the first terminal of the transistor M3 are connected to the wiring BIL. In other words, the memory cell 232 is configured to operate with the write bit line and the read bit line as a single wiring BIL.

[0363] As described above, DOSRAM and NOSRAM are memory devices having an OS transistor as a write transistor. The semiconductor layer of the OS transistor includes the metal oxide described in Embodiment 3. The metal oxide can be, for example, one or more materials selected from indium, element M (one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.), and zinc. In particular, when a metal oxide of indium, gallium, or zinc is contained in the semiconductor layer, the band gap of the semiconductor layer can be increased. Therefore, the off-state current of the OS transistor can be reduced.

[0364] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0365] (Embodiment 3) In this embodiment, structural examples of the semiconductor device described in the above embodiment and structural examples of a transistor that can be applied to the semiconductor device will be described.

[0366] <Configuration example of semiconductor device> 28 includes a transistor 300, a transistor 500, and a capacitor 600. Fig. 30A is a cross-sectional view of the transistor 500 in the channel length direction, Fig. 30B is a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 30C is a cross-sectional view of the transistor 300 in the channel width direction.

[0367] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has characteristics of a small off-state current and a field-effect mobility that does not change even at high temperatures. By applying the transistor 500 to a semiconductor device, such as a transistor included in the arithmetic device 100 or 100A described in the above embodiment, a semiconductor device whose operating capability does not decrease even at high temperatures can be realized. In particular, by utilizing the characteristics of a small off-state current, the transistor 500 can be applied to the transistor M1 or M2 as the transistor 500, so that a potential written to the memory cell 221, the memory cell 231, the memory cell 232, or the like can be held for a long time.

[0368] 28, for example. The transistor 500 is provided above the transistor 300, and the capacitor 600 is provided above the transistors 300 and 500. The capacitor 600 can be a capacitor included in the memory cell 231, the memory cell 232, or the like described in the above embodiment. Depending on the circuit configuration, the capacitor 600 illustrated in FIG. 28 is not necessarily provided.

[0369] The transistor 300 is provided over a substrate 311 and includes a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 311, and low-resistance regions 314a and 314b functioning as source and drain regions. Note that the transistor 300 can be applied to, for example, the transistors included in the arithmetic device 100, the arithmetic device 100A, and the like described in the above embodiments.

[0370] As the substrate 311, it is preferable to use a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0371] 30C , the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0372] The transistor 300 may be either a p-channel type or an n-channel type.

[0373] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0374] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0375] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0376] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a laminated state, and tungsten is particularly preferable in terms of heat resistance.

[0377] 28 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration and driving method. For example, when the semiconductor device is a unipolar circuit including only OS transistors (which in this specification and the like means a circuit including transistors of the same conductivity type, such as only n-channel transistors), the structure of the transistor 300 may be the same as that of the transistor 500 including an oxide semiconductor, as shown in FIG. 29. The details of the transistor 500 will be described later.

[0378] An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order to cover the transistor 300.

[0379] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0380] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0381] The insulator 322 may function as a planarizing film that flattens steps caused by the transistor 300 or the like provided thereunder. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0382] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311, the transistor 300, or the like to a region where the transistor 500 is provided.

[0383] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0384] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0385] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0386] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings. A plurality of conductors that function as plugs or wirings may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integral. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0387] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0388] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 28 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0389] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0390] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0391] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 28, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0392] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0393] A wiring layer may be provided over the insulator 364 and the conductor 366. For example, in FIG. 28, an insulator 370, an insulator 372, and an insulator 374 are stacked in this order. A conductor 376 is formed in the insulator 370, the insulator 372, and the insulator 374. The conductor 376 functions as a plug or a wiring. The conductor 376 can be formed using a material similar to that of the conductors 328 and 330.

[0394] Note that, for example, the insulator 370 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 376 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 370 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0395] A wiring layer may be provided over the insulator 374 and the conductor 376. For example, in FIG. 28 , an insulator 380, an insulator 382, ​​and an insulator 384 are stacked in this order. A conductor 386 is formed in the insulator 380, the insulator 382, ​​and the insulator 384. The conductor 386 functions as a plug or a wiring. The conductor 386 can be formed using a material similar to that of the conductors 328 and 330.

[0396] Note that, for example, the insulator 380 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 386 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 380 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0397] In the above, a wiring layer including the conductor 356, a wiring layer including the conductor 366, a wiring layer including the conductor 376, and a wiring layer including the conductor 386 have been described, but the semiconductor device according to this embodiment is not limited to this. There may be three or fewer wiring layers similar to the wiring layer including the conductor 356, or there may be five or more wiring layers similar to the wiring layer including the conductor 356.

[0398] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 384. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably formed using a substance that has a barrier property against oxygen and hydrogen.

[0399] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or a region where the transistor 300 is provided to a region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0400] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0401] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0402] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0403] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0404] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0405] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0406] Above the insulator 516 is the transistor 500 .

[0407] As shown in Figures 30A and 30B, the transistor 500 has a conductor 503 arranged so as to be embedded in the insulator 514 and the insulator 516, an insulator 520 arranged on the insulator 516 and the conductor 503, an insulator 522 arranged on the insulator 520, an insulator 524 arranged on the insulator 522, an oxide 530a arranged on the insulator 524, an oxide 530b arranged on the oxide 530a, conductors 542a and 542b arranged apart from each other on the oxide 530b, an insulator 580 arranged on the conductors 542a and 542b and having an opening formed therein overlapping with the conductors 542a and 542b, an oxide 530c arranged on the bottom and side surfaces of the opening, an insulator 550 arranged on the surface on which the oxide 530c is formed, and a conductor 560 arranged on the surface on which the insulator 550 is formed.

[0408] 30A and 30B, it is preferable that an insulator 544 be disposed between the oxide 530a, the oxide 530b, the conductor 542a, and the conductor 542b and the insulator 580. It is preferable that the conductor 560 include a conductor 560a disposed inside the insulator 550 and a conductor 560b disposed so as to be embedded inside the conductor 560a. It is preferable that an insulator 574 be disposed on the insulator 580, the conductor 560, and the insulator 550, as shown in FIGS.

[0409] In the following, the oxide 530a, the oxide 530b, and the oxide 530c may be collectively referred to as the oxide 530.

[0410] Although the transistor 500 has a three-layer structure of oxides 530a, 530b, and 530c in and around a channel formation region, one embodiment of the present invention is not limited to this structure. For example, the transistor may have a single layer of oxide 530b, a two-layer structure of oxides 530b and 530a, a two-layer structure of oxides 530b and 530c, or a stacked structure of four or more layers. Although the transistor 500 has a two-layer structure, one embodiment of the present invention is not limited to this structure. For example, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers. The transistor 500 illustrated in FIGS. 28, 30A, and 30B is merely an example, and the transistor is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration and driving method.

[0411] Here, the conductor 560 functions as the gate electrode of the transistor, and the conductors 542a and 542b function as the source and drain electrodes, respectively. As described above, the conductor 560 is formed so as to be embedded in the opening of the insulator 580 and in the region sandwiched between the conductors 542a and 542b. The arrangements of the conductors 560, 542a, and 542b are selected in a self-aligned manner with respect to the opening of the insulator 580. That is, in the transistor 500, the gate electrode can be positioned between the source and drain electrodes in a self-aligned manner. Therefore, the conductor 560 can be formed without providing an alignment margin, thereby reducing the area occupied by the transistor 500. This allows for miniaturization and high integration of semiconductor devices.

[0412] Furthermore, since the conductor 560 is formed in a self-aligned manner in the region between the conductor 542a and the conductor 542b, the conductor 560 does not have a region that overlaps with the conductor 542a or the conductor 542b. This reduces the parasitic capacitance formed between the conductor 560 and the conductor 542a and between the conductor 560 and the conductor 542b. This improves the switching speed of the transistor 500 and provides high frequency characteristics.

[0413] The conductor 560 may function as a first gate (also referred to as a top gate) electrode. The conductor 503 may function as a second gate (also referred to as a bottom gate) electrode. In this case, the threshold voltage of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the threshold voltage of the transistor 500 above 0 V and reduce the off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to when a negative potential is not applied.

[0414] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. In this way, when a potential is applied to the conductor 560 and the conductor 503, the electric field generated from the conductor 560 and the electric field generated from the conductor 503 are connected, and the channel formation region formed in the oxide 530 can be covered. In this specification and the like, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is called a surrounded channel (S-channel) structure.

[0415] The conductor 503 has a structure similar to that of the conductor 518, in which the conductor 503a is formed in contact with the inner walls of the openings of the insulators 514 and 516, and the conductor 503b is formed further inward. Note that although the transistor 500 has a structure in which the conductor 503a and the conductor 503b are stacked, one embodiment of the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0416] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, and copper atoms (the impurities are less likely to permeate). Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the oxygen is less likely to permeate). In this specification, the function of suppressing the diffusion of impurities or oxygen refers to the function of suppressing the diffusion of any one or all of the impurities and oxygen.

[0417] For example, the conductor 503a has a function of suppressing the diffusion of oxygen, so that the conductor 503b can be prevented from being oxidized and its conductivity from decreasing.

[0418] Furthermore, when the conductor 503 also functions as a wiring, it is preferable that the conductor 503b be made of a highly conductive material containing tungsten, copper, or aluminum as a main component. In this case, the conductor 503a is not necessarily provided. Note that although the conductor 503b is illustrated as a single layer, it may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the above-mentioned conductive material.

[0419] The insulators 520, 522, and 524 function as a second gate insulating film.

[0420] Here, the insulator 524 in contact with the oxide 530 preferably contains more oxygen than the oxygen required for the stoichiometric composition. In other words, the insulator 524 preferably has an excess oxygen region. By providing an insulator containing such excess oxygen in contact with the oxide 530, oxygen vacancies in the oxide 530 can be reduced, improving the reliability of the transistor 500. Note that in this specification and elsewhere, oxygen vacancies in a metal oxide are referred to as V O In addition, the region where the channel is formed in the metal oxide may contain impurities or oxygen vacancies (V O ), the electrical characteristics are likely to fluctuate and reliability may be reduced.O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereinafter referred to as V O H) to generate electrons that serve as carriers. This makes the transistor 500 more likely to have normally-on characteristics.

[0421] Specifically, it is preferable to use an oxide material from which a portion of oxygen is released by heating as an insulator having an excess oxygen region. The oxide material from which oxygen is released by heating is an oxide material from which the amount of released oxygen converted to oxygen atoms is 1.0 × 10 in TDS (Thermal Desorption Spectroscopy) analysis. 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atoms / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3.0 x 10 20 atoms / cm 3 The oxide film is one having the above properties. The surface temperature of the film during the TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0422] Alternatively, the oxide 530 may be brought into contact with the insulator having the excess oxygen region and subjected to one or more of heat treatment, microwave treatment, and RF treatment. By performing such treatment, water or hydrogen in the oxide 530 can be removed. For example, a reaction occurs in the oxide 530 that breaks the VOH bond, in other words, "V O H→V O +H" reaction occurs, resulting in dehydrogenation. Some of the generated hydrogen may combine with oxygen to form HO and be removed from the oxide 530 or the insulator near the oxide 530. Some of the hydrogen may also be diffused or captured (also called gettered) in the conductor 542a and the conductor 542b.

[0423] The microwave treatment is preferably performed using, for example, an apparatus having a power source for generating high-density plasma or an apparatus having a power source for applying RF to the substrate side. For example, high-density oxygen radicals can be generated by using an oxygen-containing gas and high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 530 or an insulator near the oxide 530 by applying RF to the substrate side. The microwave treatment is performed at a pressure of 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. The gases introduced into the microwave treatment apparatus may be, for example, oxygen and argon, with an oxygen flow ratio (O2 / (O2+Ar)) of 50% or less, preferably 10% to 30%.

[0424] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 450° C., more preferably 350° C. to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0425] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0426] When the insulator 524 has an excess oxygen region, the insulator 522 preferably has a function of suppressing the diffusion of oxygen (for example, oxygen atoms, oxygen molecules, etc.) (preferably making the oxygen less permeable).

[0427] The insulator 522 preferably has a function of suppressing diffusion of oxygen and impurities, which prevents oxygen contained in the oxide 530 from diffusing toward the insulator 520. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0428] The insulator 522 is preferably a single-layer or multi-layer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, oxide containing aluminum and hafnium (hafnium aluminate), tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Using a high-k material for the insulator that functions as the gate insulating film allows for a reduction in the gate potential during transistor operation while maintaining the physical film thickness.

[0429] In particular, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material that has the function of suppressing the diffusion of impurities and oxygen (i.e., is difficult for oxygen to permeate), is preferably used. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 and the intrusion of impurities such as hydrogen into the oxide 530 from the periphery of the transistor 500.

[0430] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the above insulators.

[0431] Furthermore, it is preferable that the insulator 520 is thermally stable. For example, silicon oxide and silicon oxynitride are suitable because they are thermally stable. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, it is possible to obtain the insulator 520 having a thermally stable layered structure with a high dielectric constant.

[0432] 30A and 30B illustrates the second gate insulating film having a three-layer stack structure including the insulators 520, 522, and 524. However, the second gate insulating film may have a single-layer, two-layer, or four or more-layer stack structure. In this case, the second gate insulating film is not limited to a stack structure made of the same material, and may have a stack structure made of different materials.

[0433] In the transistor 500, a metal oxide functioning as an oxide semiconductor is preferably used for the oxide 530 including the channel formation region. For example, a metal oxide such as In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used for the oxide 530. In particular, the In-M-Zn oxide that can be used for the oxide 530 is preferably a C-Axis Aligned Crystalline Oxide Semiconductor (CAAC-OS) or a Cloud-Aligned Composite Oxide Semiconductor (CAC-OS). Alternatively, an In-Ga oxide, an In-Zn oxide, an In oxide, or the like may be used for the oxide 530.

[0434] Furthermore, it is preferable to use a metal oxide with a low carrier concentration for the transistor 500. To lower the carrier concentration of a metal oxide, the impurity concentration in the metal oxide should be lowered to lower the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Examples of impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0435] In particular, hydrogen contained in the metal oxide reacts with oxygen that bonds with the metal atom to form water, which can cause oxygen vacancies in the metal oxide. When hydrogen enters an oxygen vacancy in the oxide 530, the oxygen vacancy and hydrogen bond to form V. O May form H. V OH functions as a donor and may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen, which is bonded to a metal atom, to generate electrons as carriers. Therefore, a transistor using a metal oxide containing a large amount of hydrogen is likely to have normally-on characteristics. Furthermore, since hydrogen in a metal oxide is easily moved by stresses such as heat and an electric field, the reliability of the transistor may be reduced if the metal oxide contains a large amount of hydrogen. In one embodiment of the present invention, V in the oxide 530 O It is preferable to reduce H as much as possible to obtain high-purity intrinsic or substantially high-purity intrinsic V. O To obtain metal oxides with sufficiently reduced H, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment), and to supply oxygen to the metal oxide to compensate for oxygen deficiencies (sometimes referred to as oxygen addition treatment). O By using a metal oxide in which impurities such as H are sufficiently reduced for the channel formation region of a transistor, stable electrical characteristics can be achieved.

[0436] Defects in which hydrogen has entered oxygen vacancies can function as donors in metal oxides. However, it is difficult to quantitatively evaluate such defects. Therefore, metal oxides are sometimes evaluated using carrier concentration rather than donor concentration. Therefore, in this specification and the like, the carrier concentration assuming a state in which no electric field is applied may be used as a parameter of metal oxides, rather than donor concentration. In other words, the "carrier concentration" described in this specification and the like may sometimes be rephrased as "donor concentration."

[0437] Therefore, when a metal oxide is used for the oxide 530, it is preferable that the hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 By using a metal oxide in which impurities such as hydrogen are sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0438] When a metal oxide is used for the oxide 530, the metal oxide has a wide band gap and is an intrinsic (also referred to as I-type) or substantially intrinsic semiconductor. The carrier concentration of the metal oxide in the channel formation region is 1×10 18 cm -3 Preferably, it is less than 1 x 10 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0439] Furthermore, when a metal oxide is used for the oxide 530, contact between the conductors 542a and 542b and the oxide 530 may cause oxygen in the oxide 530 to diffuse into the conductors 542a and 542b, resulting in oxidation of the conductors 542a and 542b. The oxidation of the conductors 542a and 542b is likely to result in a decrease in the conductivity of the conductors 542a and 542b. The diffusion of oxygen in the oxide 530 to the conductors 542a and 542b can be rephrased as the conductors 542a and 542b absorbing the oxygen in the oxide 530.

[0440] Furthermore, oxygen in the oxide 530 diffuses into the conductor 542a and the conductor 542b, which may form a heterogeneous layer between the conductor 542a and the oxide 530b and between the conductor 542b and the oxide 530b. Since the heterogeneous layer contains more oxygen than the conductor 542a and the conductor 542b, it is presumed that the heterogeneous layer has insulating properties. In this case, the three-layer structure of the conductor 542a or the conductor 542b, the heterogeneous layer, and the oxide 530b can be regarded as a three-layer structure consisting of a metal, an insulator, and a semiconductor, and may be referred to as a metal-insulator-semiconductor (MIS) structure or a diode junction structure based on the MIS structure.

[0441] Note that the above-mentioned different layer is not limited to being formed between the conductor 542a and the conductor 542b and the oxide 530b, but may be formed, for example, between the conductor 542a and the conductor 542b and the oxide 530c, between the conductor 542a and the conductor 542b and the oxide 530b, or between the conductor 542a and the conductor 542b and the oxide 530c.

[0442] The metal oxide that functions as a channel formation region in the oxide 530 preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0443] The oxide 530 has the oxide 530a below the oxide 530b, which can prevent impurities from diffusing from structures formed below the oxide 530a to the oxide 530b. Also, the oxide 530 has the oxide 530c on the oxide 530b, which can prevent impurities from diffusing from structures formed above the oxide 530c to the oxide 530b.

[0444] The oxide 530 preferably has a stacked structure of multiple oxide layers with different atomic ratios of the metal atoms. Specifically, the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M among the constituent elements in the metal oxide used for the oxide 530b. The atomic ratio of the element M to In in the metal oxide used for the oxide 530a is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. The atomic ratio of In to M in the metal oxide used for the oxide 530b is preferably greater than the atomic ratio of In to M in the metal oxide used for the oxide 530a. The oxide 530c can be the same metal oxide as that used for the oxide 530a or the oxide 530b.

[0445] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 or 1:1:0.5. Oxide 530b may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=4:2:3 or 1:1:1. Oxide 530c may be a metal oxide having an atomic ratio of In, Ga, and Zn of In:Ga:Zn=1:3:4 and an atomic ratio of Ga to Zn of Ga:Zn=2:1 or Ga:Zn=2:5. Specific examples of the oxide 530c having a layered structure include layered structures in which the atomic ratios of In, Ga, and Zn are In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:1 and In:Ga:Zn=4:2:3, layered structures in which the atomic ratios of Ga and Zn are Ga:Zn=2:5 and In:Ga:Zn=4:2:3, and layered structures in which gallium oxide and In, Ga, and Zn are In:Ga:Zn=4:2:3.

[0446] Furthermore, for example, when the atomic ratio of In to element M in the metal oxide used for oxide 530a is smaller than the atomic ratio of In to element M in the metal oxide used for oxide 530b, an In-Ga-Zn oxide having a composition in which the atomic ratio of In to Ga to Zn is In:Ga:Zn=5:1:6 or thereabouts, In:Ga:Zn=5:1:3 or thereabouts, or In:Ga:Zn=10:1:3 or thereabouts, can be used as oxide 530b.

[0447] In addition to the compositions described above, oxide 530b may be a metal oxide having a composition of In:Zn=2:1, a composition of In:Zn=5:1, a composition of In:Zn=10:1, or a composition close to any one of these.

[0448] It is preferable to combine these oxides 530a, 530b, and 530c so that the atomic ratios satisfy the above relationship. For example, it is preferable that oxides 530a and 530c are metal oxides having a composition of In:Ga:Zn=1:3:4 or a composition close to that, and oxide 530b is a metal oxide having a composition of In:Ga:Zn=4:2:3 to 4.1 or a composition close to that. Note that the above compositions refer to the atomic ratios in the oxide formed on the substrate or in the sputtering target. Furthermore, increasing the In ratio in the composition of oxide 530b is preferable because it can increase the on-state current or field-effect mobility of the transistor.

[0449] The conduction band minimum energy of the oxide 530a and the oxide 530c is preferably higher than that of the oxide 530b. In other words, the electron affinity of the oxide 530a and the oxide 530c is preferably smaller than that of the oxide 530b.

[0450] Here, the energy level of the conduction band minimum changes gradually at the junction between the oxides 530a, 530b, and 530c. In other words, the energy level of the conduction band minimum at the junction between the oxides 530a, 530b, and 530c changes continuously or forms a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layers formed at the interface between the oxides 530a and 530b and at the interface between the oxides 530b and 530c.

[0451] Specifically, when the oxide 530a and the oxide 530b, and the oxide 530b and the oxide 530c have a common element (main component) other than oxygen, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-Ga-Zn oxide, the oxide 530a and the oxide 530c may be made of an In-Ga-Zn oxide, a Ga-Zn oxide, or a gallium oxide.

[0452] In this case, the oxide 530b serves as the main carrier path. By configuring the oxide 530a and the oxide 530c as described above, the defect state density at the interface between the oxide 530a and the oxide 530b and at the interface between the oxide 530b and the oxide 530c can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can obtain a high on-state current.

[0453] Conductors 542a and 542b, which function as a source electrode and a drain electrode, are provided on oxide 530b. Conductors 542a and 542b are preferably made of a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing any of the above metal elements or an alloy combining any of the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or materials that maintain conductivity even when absorbing oxygen. Furthermore, metal nitride films such as tantalum nitride are preferred because they have barrier properties against hydrogen or oxygen.

[0454] 30A and 30B, the conductor 542a and the conductor 542b are shown as single-layer structures, but they may also have a stacked structure of two or more layers. For example, a tantalum nitride film and a tungsten film may be stacked. Alternatively, a titanium film and an aluminum film may be stacked. Alternatively, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, or a two-layer structure in which a copper film is stacked on a tungsten film may be used.

[0455] Further, there are three-layer structures in which a titanium film or titanium nitride film is laminated on the titanium film or titanium nitride film, an aluminum film or copper film is laminated on the titanium film or titanium nitride film, and a titanium film or titanium nitride film is further formed thereon, a three-layer structure in which a molybdenum film or molybdenum nitride film is laminated on the molybdenum film or molybdenum nitride film, an aluminum film or copper film is laminated on the molybdenum film or molybdenum nitride film, and a molybdenum film or molybdenum nitride film is further formed thereon, etc. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may also be used.

[0456] 30A, regions 543a and 543b may be formed as low-resistance regions at and near the interface of the oxide 530 with the conductor 542a (conductor 542b). In this case, the region 543a functions as one of the source region and the drain region, and the region 543b functions as the other of the source region and the drain region. A channel formation region is formed in the region sandwiched between the regions 543a and 543b.

[0457] By providing the conductor 542a (conductor 542b) so as to be in contact with the oxide 530, the oxygen concentration in the region 543a (region 543b) may be reduced. Also, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and components of the oxide 530 may be formed in the region 543a (region 543b). In such a case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0458] The insulator 544 is provided to cover the conductors 542a and 542b and suppresses oxidation of the conductors 542a and 542b. In this case, the insulator 544 may be provided to cover the side surface of the oxide 530 and to be in contact with the insulator 524.

[0459] The insulator 544 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, neodymium, lanthanum, magnesium, etc. Alternatively, the insulator 544 can be silicon nitride oxide, silicon nitride, or the like.

[0460] In particular, it is preferable to use, as the insulator 544, an insulator containing an oxide of either or both of aluminum and hafnium, such as aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, it is preferable because it is less likely to crystallize during heat treatment in a later process. Note that the insulator 544 is not an essential component if the conductors 542a and 542b are made of oxidation-resistant materials or if their conductivity does not decrease significantly even when they absorb oxygen. The insulator 544 may be designed appropriately depending on the desired transistor characteristics.

[0461] The insulator 544 can prevent impurities such as water and hydrogen contained in the insulator 580 from diffusing to the oxide 530b through the oxide 530c and the insulator 550. The insulator 544 can also prevent the conductor 560 from being oxidized by excess oxygen contained in the insulator 580.

[0462] The insulator 550 functions as a first gate insulating film. The insulator 550 is preferably disposed in contact with the inside (top surface and side surface) of the oxide 530c. The insulator 550 is preferably formed using an insulator that contains excess oxygen and releases oxygen by heating, similar to the insulator 524 described above.

[0463] Specifically, silicon oxide having excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having vacancies can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0464] By providing the insulator 550, which releases oxygen upon heating, in contact with the top surface of the oxide 530c, oxygen can be effectively supplied from the insulator 550 to the channel formation region of the oxide 530b through the oxide 530c. Similar to the insulator 524, the concentration of impurities such as water or hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably 1 nm to 20 nm.

[0465] Furthermore, a metal oxide may be provided between the insulator 550 and the conductor 560 to efficiently supply excess oxygen contained in the insulator 550 to the oxide 530. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. By providing a metal oxide that suppresses oxygen diffusion, the diffusion of excess oxygen from the insulator 550 to the conductor 560 is suppressed. In other words, a decrease in the amount of excess oxygen supplied to the oxide 530 can be suppressed. Furthermore, oxidation of the conductor 560 due to excess oxygen can be suppressed. As the metal oxide, a material that can be used for the insulator 544 may be used.

[0466] The insulator 550 may have a stacked structure, similar to the second gate insulating film. As transistors become smaller and more highly integrated, thinner gate insulating films can cause problems such as leakage current. Therefore, by using a stacked structure of a high-k material and a thermally stable material for the insulator that functions as the gate insulating film, it becomes possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. Furthermore, a stacked structure that is thermally stable and has a high dielectric constant can be achieved.

[0467] The conductor 560 functioning as the first gate electrode is shown as having a two-layer structure in FIGS. 30A and 30B, but may have a single-layer structure or a stacked structure of three or more layers.

[0468] The conductor 560a is preferably made of a conductive material that suppresses the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms. Alternatively, a conductive material that suppresses the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) is preferably used. The conductor 560a has the function of suppressing the diffusion of oxygen, which can suppress the oxidation of the conductor 560b due to oxygen contained in the insulator 550 and a decrease in conductivity. Examples of conductive materials that suppress the diffusion of oxygen include tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Alternatively, the conductor 560a can be made of an oxide semiconductor that can be used for the oxide 530. In this case, the conductor 560b can be formed by sputtering to reduce the electrical resistance of the conductor 560a, thereby making it a conductor. This can be referred to as an OC (Oxide Conductor) electrode.

[0469] The conductor 560b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. Since the conductor 560b also functions as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 560b may have a layered structure, such as a layered structure of titanium or titanium nitride and the above conductive material.

[0470] The insulator 580 is provided over the conductor 542a and the conductor 542b with the insulator 544 interposed therebetween. The insulator 580 preferably has an excess oxygen region. For example, the insulator 580 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having voids, or a resin. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. Silicon oxide and silicon oxide having voids are particularly preferred because they allow for easy formation of excess oxygen regions in a later step.

[0471] The insulator 580 preferably has an excess oxygen region. By providing the insulator 580, from which oxygen is released by heating, in contact with the oxide 530c, oxygen in the insulator 580 can be efficiently supplied to the oxide 530 through the oxide 530c. Note that the concentration of impurities such as water or hydrogen in the insulator 580 is preferably reduced.

[0472] The opening of the insulator 580 is formed to overlap the region between the conductor 542a and the conductor 542b, so that the conductor 560 is formed to be embedded in the opening of the insulator 580 and the region sandwiched between the conductor 542a and the conductor 542b.

[0473] When miniaturizing semiconductor devices, it is necessary to shorten the gate length, but it is also necessary to prevent the conductivity of the conductor 560 from decreasing. If the film thickness of the conductor 560 is increased to achieve this, the conductor 560 may have a shape with a high aspect ratio. In this embodiment, the conductor 560 is provided so as to be embedded in the opening of the insulator 580. Therefore, even if the conductor 560 has a shape with a high aspect ratio, the conductor 560 can be formed without collapsing during the process.

[0474] The insulator 574 is preferably provided in contact with the top surface of the insulator 580, the top surface of the conductor 560, and the top surface of the insulator 550. By forming the insulator 574 by a sputtering method, excess oxygen regions can be provided in the insulator 550 and the insulator 580. This allows oxygen to be supplied from the excess oxygen regions into the oxide 530.

[0475] For example, the insulator 574 can be a metal oxide containing one or more elements selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like.

[0476] In particular, aluminum oxide has high barrier properties and can suppress the diffusion of hydrogen and nitrogen even when it is a thin film with a thickness of 0.5 nm to 3.0 nm. Therefore, aluminum oxide formed by sputtering can function as both an oxygen source and a barrier film against impurities such as hydrogen.

[0477] An insulator 581 functioning as an interlayer film is preferably provided over the insulator 574. Like the insulator 524, the insulator 581 preferably has a reduced concentration of impurities such as water or hydrogen.

[0478] Furthermore, the conductor 540a and the conductor 540b are placed in openings formed in the insulator 581, the insulator 574, the insulator 580, and the insulator 544. The conductor 540a and the conductor 540b are provided opposite each other with the conductor 560 interposed therebetween. The conductor 540a and the conductor 540b have the same structure as the conductor 546 and the conductor 548, which will be described later.

[0479] An insulator 582 is provided over the insulator 581. The insulator 582 is preferably formed using a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be formed using a material similar to that of the insulator 514. For example, the insulator 582 is preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0480] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0481] An insulator 586 is provided over the insulator 582. The insulator 586 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator 586.

[0482] Furthermore, conductors 546, conductors 548, etc. are embedded in insulators 520, 522, 524, 544, 580, 574, 581, 582, and 586.

[0483] The conductor 546 and the conductor 548 function as a plug or a wiring that connects to the capacitor 600, the transistor 500, or the transistor 300. The conductor 546 and the conductor 548 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0484] After the transistor 500 is formed, an opening may be formed to surround the transistor 500, and an insulator with high barrier properties against hydrogen or water may be formed to cover the opening. By surrounding the transistor 500 with the insulator with high barrier properties, it is possible to prevent moisture and hydrogen from entering from the outside. Alternatively, multiple transistors 500 may be collectively surrounded by an insulator with high barrier properties against hydrogen or water. When forming an opening to surround the transistor 500, for example, it is preferable to form an opening that reaches the insulator 514 or the insulator 522 and form the insulator with high barrier properties in contact with the insulator 514 or the insulator 522, because this can serve as part of the manufacturing process of the transistor 500. For example, the insulator with high barrier properties against hydrogen or water may be made of a material similar to that of the insulator 522.

[0485] Subsequently, a capacitor 600 is provided above the transistor 500. The capacitor 600 includes a conductor 610, a conductor 620, and an insulator 630.

[0486] A conductor 612 may be provided over the conductor 546 and the conductor 548. The conductor 612 functions as a plug or a wiring connected to the transistor 500. The conductor 610 functions as an electrode of the capacitor 600. Note that the conductor 612 and the conductor 610 can be formed at the same time.

[0487] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0488] 28, the conductor 612 and the conductor 610 have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high conductivity.

[0489] The conductor 620 is provided to overlap with the conductor 610 with the insulator 630 interposed therebetween. Note that the conductor 620 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is particularly preferable. Furthermore, when the conductor 620 is formed simultaneously with other structures such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used.

[0490] An insulator 650 is provided over the conductor 620 and the insulator 630. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape underneath.

[0491] By using this structure, in a semiconductor device including a transistor having an oxide semiconductor, fluctuation in electrical characteristics can be suppressed and reliability can be improved, or miniaturization or high integration can be achieved in a semiconductor device including a transistor having an oxide semiconductor.

[0492] Next, another example of the structure of an OS transistor shown in FIGS. 28 and 29 will be described.

[0493] 31A and 31B illustrate modifications of the transistor 500 illustrated in FIGS. 30A and 30B. FIG. 31A is a cross-sectional view of the transistor 500 in the channel length direction, and FIG. 31B is a cross-sectional view of the transistor 500 in the channel width direction. Note that the structures illustrated in FIGS. 31A and 31B can also be applied to other transistors included in the semiconductor device of one embodiment of the present invention, such as the transistor 300.

[0494] 31A and 31B differs from the transistor 500 shown in FIGS. 30A and 30B in that the transistor 500 includes an insulator 402 and an insulator 404. The transistor 500 also differs from the transistor 500 shown in FIGS. 30A and 30B in that the insulator 552 is provided in contact with the side surface of the conductor 540a and the insulator 552 is provided in contact with the side surface of the conductor 540b. The transistor 500 also differs from the transistor 500 shown in FIGS. 30A and 30B in that the insulator 520 is not provided.

[0495] 31A and 31B, the insulator 402 is provided over the insulator 512. The insulator 404 is provided over the insulator 574 and the insulator 402.

[0496] 31A and 31B includes insulators 514, 516, 522, 524, 544, 580, and 574, and the insulator 404 covers these. That is, the insulator 404 is in contact with the top surface of the insulator 574, the side surface of the insulator 574, the side surface of the insulator 580, the side surface of the insulator 544, the side surface of the insulator 524, the side surface of the insulator 522, the side surface of the insulator 516, the side surface of the insulator 514, and the top surface of the insulator 402. As a result, the oxide 530 and the like are isolated from the outside by the insulators 404 and 402.

[0497] The insulators 402 and 404 preferably have a high function of suppressing diffusion of hydrogen (for example, at least one of a hydrogen atom and a hydrogen molecule) or water molecules. For example, silicon nitride or silicon nitride oxide, which are materials with high hydrogen barrier properties, are preferably used for the insulators 402 and 404. This can suppress diffusion of hydrogen and the like into the oxide 530, thereby suppressing deterioration in the characteristics of the transistor 500. Therefore, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0498] The insulator 552 is provided in contact with the insulator 581, the insulator 404, the insulator 574, the insulator 580, and the insulator 544. The insulator 552 preferably has a function of suppressing diffusion of hydrogen or water molecules. For example, the insulator 552 is preferably formed using an insulator with high hydrogen barrier properties, such as silicon nitride, aluminum oxide, or silicon nitride oxide. Silicon nitride is particularly suitable for use as the insulator 552 because it has high hydrogen barrier properties. Using a material with high hydrogen barrier properties for the insulator 552 can suppress diffusion of impurities such as water or hydrogen from the insulator 580 or the like to the oxide 530 through the conductors 540a and 540b. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b. Thus, the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0499] 32 is a cross-sectional view showing an example of the configuration of a semiconductor device when the transistor 500 and the transistor 300 have the configurations shown in FIGS. 31A and 31B. An insulator 552 is provided on the side surface of the conductor 546.

[0500] The transistor 500 shown in FIGS. 31A and 31B may have a modified configuration depending on the situation. For example, the transistor 500 shown in FIGS. 31A and 31B can be modified to the transistor shown in FIGS. 33A and 33B. FIG. 33A is a cross-sectional view of the transistor in the channel length direction, and FIG. 33B is a cross-sectional view of the transistor in the channel width direction. The transistor shown in FIGS. 33A and 33B differs from the transistor shown in FIGS. 31A and 31B in that the oxide 530c has a two-layer structure of oxides 530c1 and 530c2.

[0501] The oxide 530c1 contacts the top surface of the insulator 524, the side surface of the oxide 530a, the top surface and side surface of the oxide 530b, the side surfaces of the conductors 542a and 542b, the side surface of the insulator 544, and the side surface of the insulator 580. The oxide 530c2 contacts the insulator 550.

[0502] Oxide 530c1 can be, for example, an In-Zn oxide. Oxide 530c2 can be made of the same material as that used for oxide 530c when oxide 530c has a single-layer structure. For example, oxide 530c2 can be made of a metal oxide with an atomic ratio of In:Ga:Zn=1:3:4, Ga:Zn=2:1, or Ga:Zn=2:5.

[0503] By forming the oxide 530c as a two-layer structure of the oxide 530c1 and the oxide 530c2, the on-state current of the transistor can be increased compared to when the oxide 530c has a single-layer structure. Therefore, the transistor can be used as, for example, a power MOS transistor. The oxide 530c of the transistor having the configuration shown in FIGS. 30A and 30B can also have a two-layer structure of the oxide 530c1 and the oxide 530c2.

[0504] 33A and 33B can be applied to, for example, the transistor 300 illustrated in FIGS. 28 and 29. As described above, the transistor 300 can be applied to the semiconductor device described in the above embodiment, such as the transistor included in the arithmetic device 100 or 100A described in the above embodiment. Note that the transistors illustrated in FIGS. 33A and 33B can also be applied to transistors other than the transistor 300 and the transistor 500 included in the semiconductor device of one embodiment of the present invention.

[0505] 34 is a cross-sectional view illustrating a structural example of a semiconductor device in which the transistor 500 has the transistor structure illustrated in FIG. 30A and the transistor 300 has the transistor structure illustrated in FIG. 33A. Note that, as in FIG. 32, an insulator 552 is provided on the side surface of the conductor 546. As illustrated in FIG. 34, in the semiconductor device of one embodiment of the present invention, the transistors 300 and 500 are both OS transistors, but the transistors 300 and 500 can have different structures.

[0506] Next, a capacitive element that can be applied to the semiconductor devices of FIGS. 28, 29, 32, and 34 will be described.

[0507] Fig. 35 shows a capacitive element 600A as an example of the capacitive element 600 that can be applied to the semiconductor devices shown in Fig. 28, Fig. 29, Fig. 32, and Fig. 34. Fig. 35A is a top view of the capacitive element 600A, Fig. 35B is a perspective view showing a cross section of the capacitive element 600A taken along dashed dotted line L3-L4, and Fig. 35C is a perspective view showing a cross section of the capacitive element 600A taken along dashed dotted line W3-L4.

[0508] The conductor 610 functions as one of a pair of electrodes of the capacitor 600A, and the conductor 620 functions as the other of the pair of electrodes of the capacitor 600A. The insulator 630 functions as a dielectric sandwiched between the pair of electrodes.

[0509] The insulator 630 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, or the like, and can be formed as a stacked layer or a single layer.

[0510] In this specification, hafnium oxynitride refers to a material whose composition contains more oxygen than nitrogen, and hafnium nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0511] Furthermore, for example, a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material may be used for the insulator 630. With this configuration, the capacitive element 600A can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the insulator with high dielectric strength improves the dielectric strength, thereby suppressing electrostatic breakdown of the capacitive element 600A.

[0512] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0513] Alternatively, the insulator 630 may be a single layer or a stack of insulators containing high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO), or (Ba,Sr)TiO (BST). For example, when the insulator 630 is a stack, a three-layer stack in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially formed may be used, or a four-layer stack in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are sequentially formed may be used. Alternatively, the insulator 630 may be a compound containing hafnium and zirconium. As semiconductor devices become smaller and more highly integrated, thinner dielectrics used in gate insulators and capacitors may cause problems such as leakage current in transistors and capacitors. By using high-k materials for the gate insulator and the insulator that functions as the dielectric used in the capacitor element, it is possible to reduce the gate potential during transistor operation and ensure the capacitance of the capacitor element while maintaining the physical film thickness.

[0514] The capacitor 600 is electrically connected to the conductor 546 and the conductor 548 below the conductor 610. The conductors 546 and 548 function as plugs or wiring for connecting to other circuit elements. In addition, in FIGS. 35A to 35C, the conductors 546 and 548 are collectively referred to as the conductor 540.

[0515] Also, in order to clarify the illustration, Figure 35 omits the insulator 586 in which the conductors 546 and 548 are embedded, and the insulator 650 covering the conductor 620 and the insulator 630.

[0516] 28, 29, 32, 34, 35A, 35B, and 35C are planar capacitor elements, but the shape of the capacitor element is not limited to this. For example, the capacitor element 600 may be a cylindrical capacitor element 600B shown in FIGS. 36A to 36C.

[0517] 36A is a top view of the capacitive element 600B, FIG. 36B is a cross-sectional view of the capacitive element 600B taken along the dashed dotted line L3-L4, and FIG. 36C is a perspective view showing the cross-section of the capacitive element 600B taken along the dashed dotted line W3-L4.

[0518] In Figure 36B, the capacitor element 600B has an insulator 631 on an insulator 586 in which a conductor 540 is embedded, an insulator 651 having an opening, a conductor 610 that functions as one of a pair of electrodes, and a conductor 620 that functions as the other of the pair of electrodes.

[0519] Also, in FIG. 36C, insulator 586, insulator 650, and insulator 651 are omitted for clarity.

[0520] The insulator 631 can be formed using, for example, a material similar to that of the insulator 586.

[0521] Furthermore, a conductor 611 is embedded in the insulator 631 so as to be electrically connected to the conductor 540. The conductor 611 can be made of the same material as the conductors 330 and 518, for example.

[0522] The insulator 651 can be formed using, for example, a material similar to that of the insulator 586.

[0523] As described above, the insulator 651 has an opening that overlaps with the conductor 611.

[0524] The conductor 610 is formed on the bottom and side surfaces of the opening. That is, the conductor 621 overlaps with the conductor 611 and is electrically connected to the conductor 611.

[0525] The conductor 610 is formed by forming an opening in the insulator 651 by etching or the like, and then depositing the conductor 610 by sputtering, ALD, or the like. Thereafter, the conductor 610 deposited on the insulator 651 may be removed by chemical mechanical polishing (CMP) or the like, leaving the conductor 610 deposited in the opening.

[0526] The insulator 630 is located on the insulator 651 and on the surface on which the conductor 610 is formed. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes in the capacitor.

[0527] The conductor 620 is formed on the insulator 630 so that the opening of the insulator 651 is filled.

[0528] The insulator 650 is formed to cover the insulator 630 and the conductor 620 .

[0529] The cylindrical capacitive element 600B shown in FIG. 36 can have a higher capacitance value than the planar capacitive element 600A.

[0530] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0531] (Fourth embodiment) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0532] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0533] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 37A, which is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0534] As shown in FIG. 37A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0535] The structure within the bold frame in Figure 37A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "Amorphous" and "Crystal."

[0536] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 37B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 37B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 37B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 37B is 500 nm.

[0537] As shown in Figure 37B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 37B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0538] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). The diffraction pattern of a CAAC-IGZO film is shown in Figure 37C. Figure 37C shows a diffraction pattern observed using NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 37C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed using a probe diameter of 1 nm.

[0539] As shown in Figure 37C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0540] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 37A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0541] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0542] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0543] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0544] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0545] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0546] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0547] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0548] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0549] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0550] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0551] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0552] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0553] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0554] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0555] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0556] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0557] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0558] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0559] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0560] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0561] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0562] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0563] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm-3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0564] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0565] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0566] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0567] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0568] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon or carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated as follows: 18 atoms / cm 3 Less than or equal to 2 x 10 17atoms / cm 3 The following applies.

[0569] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0570] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0571] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0572] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0573] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0574] (Embodiment 5) This embodiment mode will describe an example of a semiconductor wafer on which the semiconductor device or the like shown in the above embodiment mode is formed, and an electronic component in which the semiconductor device is incorporated.

[0575] <Semiconductor wafer> First, an example of a semiconductor wafer on which a semiconductor device or the like is formed will be described with reference to FIG. 38A.

[0576] 38A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of wafer 4801. On the upper surface of wafer 4801, a portion where circuit portions 4802 are not present is spacing 4803, which is a region for dicing.

[0577] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0578] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes referred to as dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0579] By performing a dicing process, chips 4800a as shown in FIG. 38B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. Note that spacing 4803a is preferably made as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0580] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 38A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the apparatus for manufacturing the element.

[0581] <Electronic components> FIG. 38C shows a perspective view of electronic component 4700 and a substrate (mounting substrate 4704) on which electronic component 4700 is mounted. Electronic component 4700 shown in FIG. 38C has chip 4800a in mold 4711. Note that, as shown in FIG. 38C, chip 4800a may have a configuration in which circuit section 4802 is stacked. FIG. 38C omits a portion to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a by wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. Mounting substrate 4704 is completed by combining a plurality of such electronic components and electrically connecting them on printed circuit board 4702.

[0582] 38D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0583] The electronic component 4730 includes a semiconductor device 4710. The semiconductor device 4710 can be, for example, any of the semiconductor devices described in the above embodiments or a high bandwidth memory (HBM). The semiconductor device 4735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0584] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0585] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0586] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0587] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0588] Furthermore, in SiPs and MCMs that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the surface of a silicon interposer is highly flat, poor connections between the integrated circuit mounted on the silicon interposer and the silicon interposer are unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging), in which multiple integrated circuits are arranged horizontally on an interposer.

[0589] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0590] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. Fig. 38D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0591] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0592] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0593] (Sixth embodiment) In this embodiment, an example of an electronic device including the semiconductor device described in the above embodiment will be described. Note that Fig. 39 illustrates how each electronic device includes an electronic component 4700 including the semiconductor device.

[0594] [mobile phone] 39 is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0595] By applying the semiconductor device described in the above embodiment, the information terminal 5500 can execute applications using artificial intelligence. Examples of the applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication such as fingerprints and voiceprints.

[0596] [Wearable devices] 39 also illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, an operator 5904, a band 5905, and the like.

[0597] The wearable terminal can execute applications using artificial intelligence by applying the semiconductor device described in the above embodiment, similar to the information terminal 5500 described above. Examples of applications using artificial intelligence include an application that manages the health condition of a person wearing a wearable terminal, and a navigation system that selects and guides the user along the optimal route based on the input of a destination.

[0598] [Information terminal] 39 also shows a desktop information terminal 5300. The desktop information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0599] The desktop information terminal 5300, like the information terminal 5500 described above, can execute applications using artificial intelligence by applying the semiconductor device described in the above embodiment. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. Furthermore, the desktop information terminal 5300 can be used to develop new artificial intelligence.

[0600] In the above description, a smartphone and a desktop information terminal are shown as examples of electronic devices in Fig. 39, but information terminals other than smartphones and desktop information terminals can also be applied. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0601] [electric appliances] 39 also illustrates an electric refrigerator-freezer 5800 as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0602] The electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the semiconductor device described in the above embodiment to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and their expiration dates, a function of automatically adjusting the temperature to match the ingredients stored in the electric refrigerator-freezer 5800, and the like.

[0603] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction heating (IH) cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0604] [Game consoles] 39 also shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0605] FIG. 39 further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 39, ...

Claims

1. It has an arithmetic circuit, the arithmetic circuit has a first storage unit, a first register, a second register, a third register, a fourth register, a multiplier, an adder, a selector, a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal; an input terminal of the first register electrically connected to the first terminal; an output terminal of the first register electrically connected to an input terminal of the second register; an output terminal of the first register electrically connected to the second terminal; an output terminal of the second register electrically connected to a first input terminal of the multiplier; an output terminal of the first storage unit electrically connected to a second input terminal of the multiplier; an output terminal of the multiplier electrically connected to a first input terminal of the adder; a second input terminal of the adder electrically connected to the third terminal; an output terminal of the adder electrically connected to an input terminal of the third register; an output terminal of the third register is electrically connected to the fourth terminal; an output terminal of the third register is electrically connected to a first input terminal of the selector; a second input terminal of the selector electrically connected to the fifth terminal; an output terminal of the selector is electrically connected to an input terminal of the fourth register; an output terminal of the fourth register is electrically connected to the sixth terminal; Semiconductor device.

2. In claim 1, a circuit; The circuit comprises: The sixth terminal has a function of calculating an activation function for the data output from the sixth terminal. Semiconductor device.

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