Semiconductor Devices

Abstract

To provide a technique for suppressing characteristic variations in temperature sense diodes.SOLUTION: In a semiconductor device related to the technology disclosed in this application specification, the temperature sensing region is provided with a diffusion layer of the second conductivity type provided on the surface layer of the drift layer of the first conductivity type, a well layer of the first conductivity type provided on the surface layer of the diffusion layer and electrically connected with the anode electrode, and a cathode layer of the first conductivity type provided on the surface layer of the well layer and electrically connected with the cathode electrode.SELECTED DRAWING: Figure 14

Description

[Technical Field]

[0001] The technology disclosed in the present specification relates to a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, there is a semiconductor device in which an insulated gate bipolar transistor (IGBT) region and a region in which a temperature detection diode (temperature sensing diode) is formed are provided on a single semiconductor substrate.

[0003] Among such semiconductor devices, there is one that has a configuration in which a temperature sensing diode is formed in a Si substrate and is capable of detecting the temperature in the Si substrate with high accuracy (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-188335 Summary of the Invention [Problem to be solved by the invention]

[0005] In the semiconductor device having the above-described configuration, a parasitic bipolar transistor exists due to the temperature sensing diode and the well layer that junction-isolates the temperature sensing diode and the Si substrate.

[0006] Therefore, since the temperature sensing diode and the parasitic bipolar transistor are connected in parallel and act together, the characteristics of the temperature sensing diode may vary due to the influence of the parasitic bipolar transistor.

[0007] The technology disclosed in this specification has been made in consideration of the problems described above, and is a technology for suppressing variations in the characteristics of temperature sensing diodes. [Means for solving the problem]

[0008] A semiconductor device according to a first aspect of the technology disclosed in the present specification is a semiconductor device including a temperature detection region, a switching element region at least partially surrounding the temperature detection region in a plan view, and a signal pad region, wherein the temperature detection region is provided with a diffusion layer of a second conductivity type provided in a surface layer of a drift layer of a first conductivity type, a well layer of the first conductivity type provided in the surface layer of the diffusion layer and in contact with an anode electrode, and a cathode layer of the first conductivity type provided in the surface layer of the well layer and electrically connected to a cathode electrode, wherein the cathode layer has a higher impurity concentration than the well layer, the diffusion layer is connected to an emitter electrode; the switching element region is provided with a base layer of a second conductivity type provided on a surface layer of a semiconductor layer of a first conductivity type, a source layer of the first conductivity type partially provided on the surface layer of the base layer, a plurality of trenches provided from an upper surface of the base layer to the inside of the semiconductor layer, and a gate electrode provided in the trench and surrounded by a gate insulating film; the source layer is electrically connected to the emitter electrode, and the cathode electrode is electrically connected to the emitter electrode; The signal pad region is provided with an anode pad electrically connected to the anode electrode and a cathode pad electrically connected to the cathode electrode. [Effects of the Invention]

[0009] According to at least the first aspect of the technology disclosed in the present specification, by using a Schottky diode that operates unipolarly as the temperature sensing diode, it is possible to suppress the operation of the parasitic bipolar transistor and suppress the variation in the characteristics of the temperature sensing diode.

[0010] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description and accompanying drawings set forth below. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing an example of the configuration of an RC-IGBT, which is an example of a semiconductor device according to an embodiment. [Figure 2] FIG. 10 is a plan view showing an example of an RC-IGBT with another configuration. [Figure 3] 1 is a plan view showing an example of the configuration of an IGBT region in an RC-IGBT. FIG. [Figure 4] 1 is a cross-sectional view showing an example of the configuration of an IGBT region in an RC-IGBT. [Figure 5] 1 is a cross-sectional view showing an example of the configuration of an IGBT region in an RC-IGBT. [Figure 6] 1 is a plan view showing an example of the configuration of a diode region in an RC-IGBT. FIG. [Figure 7] 1 is a cross-sectional view showing an example of the configuration of a diode region in an RC-IGBT. [Figure 8] 1 is a cross-sectional view showing an example of the configuration of a diode region in an RC-IGBT. [Figure 9] 1 is a cross-sectional view showing an example of the configuration of a boundary region between an IGBT region and a diode region in an RC-IGBT. [Figure 10] 1 is a cross-sectional view showing an example of the configuration of a termination region in an RC-IGBT. [Figure 11] 1 is a cross-sectional view showing an example of the configuration of a termination region in an RC-IGBT. [Figure 12] FIG. 2 is a cross-sectional view showing an example of the structure of a temperature sensing diode. [Figure 13] FIG. 10 is a cross-sectional view showing another example of the structure of a temperature sensing diode. [Figure 14] 4 is a cross-sectional view showing an example of the configuration of a temperature sensing diode in a temperature detection region according to an embodiment. FIG. [Figure 15] FIG. 2 is a cross-sectional view showing an example of the configuration of a temperature sensing diode according to an embodiment. [Figure 16]FIG. 2 is a cross-sectional view showing an example of the configuration of a temperature sensing diode according to an embodiment. [Figure 17] FIG. 10 is a cross-sectional view showing another example of the configuration of a temperature sensing diode according to the embodiment. [Figure 18] 1 is a plan view showing an example of the arrangement of temperature sensing diodes in a semiconductor device; [Figure 19] 1 is a plan view showing an example of the arrangement of temperature sensing diodes in a semiconductor device; DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features will be shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0013] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0014] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0015] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0016] Furthermore, although ordinal numbers such as "first" or "second" may be used in the descriptions in this specification, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0017] Furthermore, in the description given in this specification, expressions such as "positive direction of the ... axis" or "negative direction of the ... axis" refer to the direction along the arrow of the ... axis shown in the figure as the positive direction, and the direction opposite to the arrow of the ... axis shown in the figure as the negative direction.

[0018] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0019] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude another component "C" from being interposed between A and B.

[0020] First Embodiment The semiconductor device according to this embodiment will be described below.

[0021] <Configuration of semiconductor device> In the following description, n and p indicate the conductivity types of semiconductors, with the first conductivity type being n-type and the second conductivity type being p-type. However, the first conductivity type may also be p-type and the second conductivity type may also be n-type.

[0022] Furthermore, n- indicates that the impurity concentration is lower than n, and n+ indicates that the impurity concentration is higher than n. Similarly, p- indicates that the impurity concentration is lower than p, and p+ indicates that the impurity concentration is higher than p.

[0023] In the following description, a reverse conducting IGBT (RC-IGBT) is shown as an example, but an IGBT without a diode region 20 (described later) may also be used.

[0024] Fig. 1 is a plan view showing an example of the configuration of an RC-IGBT, which is an example of a semiconductor device according to this embodiment, and Fig. 2 is a plan view showing an example of an RC-IGBT with another configuration.

[0025] 1, the IGBT region 10 and the diode region 20 are arranged side by side in a striped pattern in a plan view. This shape can also be said to be such that the IGBT region 10 and the diode region 20 partially surround each other (the sides of the entire periphery of each region on the positive side of the Y-axis and the sides on the negative side of the Y-axis are sandwiched in the Y-axis direction). Hereinafter, this configuration may be simply referred to as a "striped type."

[0026] 2, a plurality of diode regions 20a are provided spaced apart from one another in the vertical and horizontal directions, and the IGBT region 10 is provided around the diode regions 20a. Hereinafter, such a configuration may be simply referred to as an "island type."

[0027] <Overall stripe structure> 1, a semiconductor device 100 includes an IGBT region 10 and a diode region 20. The IGBT region 10 and the diode region 20 extend from one end of the semiconductor device 100 to the other end. The IGBT region 10 and the diode region 20 are alternately arranged in stripes in a direction (Y-axis direction) perpendicular to the extension direction (X-axis direction) of the IGBT region 10 and the diode region 20.

[0028] The configuration shown in FIG. 1 shows three IGBT regions 10 and two diode regions, and all diode regions 20 are sandwiched between IGBT regions 10, but the number of IGBT regions 10 and the number of diode regions 20 are not limited to this, and for example, the number of IGBT regions 10 may be three or more or three or less, and the number of diode regions 20 may be two or more or two or less.

[0029] 1 may be replaced with the formation locations of the IGBT regions 10 and the diode regions 20, or all the IGBT regions 10 may be sandwiched between the diode regions 20. In this case, as shown in FIG.

[0030] Alternatively, one IGBT region 10 and one diode region 20 may be provided adjacent to each other.

[0031] 1, a signal pad region 40 is provided adjacent to the IGBT region 10 on the negative side of the Y axis. The signal pad region 40 is a region where a control pad 41 for controlling the semiconductor device 100 is provided.

[0032] The IGBT region 10 and the diode region 20 are collectively called a cell region. A termination region 30 is provided around the combined region of the cell region and the signal pad region 40 to maintain the breakdown voltage of the semiconductor device 100.

[0033] The termination region 30 may be provided with a known breakdown voltage support structure that is appropriately selected. Examples of breakdown voltage support structures include a field limiting ring (FLR) that surrounds the cell region with a p-type termination well layer, which is a p-type semiconductor, on the first main surface side, which is the front surface side of the semiconductor device 100, or a variation of lateral doping (VLD) that surrounds the cell region with a p-type well layer with a concentration gradient. The number of ring-shaped p-type termination well layers used in the FLR or the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. Alternatively, a p-type termination well layer may be provided over substantially the entire signal pad region 40, and an IGBT cell or a diode cell may be provided in the signal pad region 40.

[0034] The control pads 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, a temperature sense diode pad 41d which is an anode pad, and a temperature sense diode pad 41e which is a cathode pad.

[0035] The current sense pad 41a is a control pad for detecting the current flowing in the cell region of the semiconductor device 100, and is a control pad electrically connected to a portion of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is a fraction to several tens of thousands of the current flowing in the entire cell region flows.

[0036] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage is applied for on / off control of the semiconductor device 100. The Kelvin emitter pad 41b is electrically connected to a p-type base layer of the IGBT cell, and the gate pad 41c is electrically connected to a gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p+ type contact layer.

[0037] The temperature sensing diode pad 41d and the temperature sensing diode pad 41e are control pads electrically connected to the anode electrode and the cathode electrode of a temperature sensing diode provided in the semiconductor device 100. The temperature sensing diode pad 41d and the temperature sensing diode pad 41e measure the voltage between the anode electrode and the cathode electrode of a temperature sensing diode (not shown here) provided in the cell region to measure the temperature of the semiconductor device 100.

[0038] 18 and 19 are plan views showing examples of the arrangement of temperature sensing diodes in the semiconductor device 100. The temperature detection region in which the temperature sensing diode is provided is arranged at an arbitrary position inside the termination region in the chip.

[0039] As shown in the example of FIG. 18, the temperature sensing diode 52 has a wiring 52b connected to the temperature sensing diode pad 41d, which is an anode pad, and a wiring 52a connected to the temperature sensing diode pad 41e, which is a cathode pad, and is arranged in a temperature detection region surrounded by the IGBT region 10.

[0040] Also, as shown in an example in FIG. 19, the temperature sensing diode 54 may be arranged in a temperature detection region surrounded by the diode region 20, while having a wiring 54b connected to the temperature sensing diode pad 41d and a wiring 54a connected to the temperature sensing diode pad 41e.

[0041] <About the overall island structure> 2, a semiconductor device 101 includes an IGBT region 10 and a diode region 20a. A plurality of diode regions 20a are arranged side by side in the vertical direction (Y-axis direction) and horizontal direction (X-axis direction) within the semiconductor device, and each diode region 20a is surrounded by the IGBT region 10. In other words, a plurality of diode regions 20a are arranged in an island shape within the IGBT region 10.

[0042] In FIG. 2, the diode regions 20a are configured in a matrix of four columns in the left-right direction (X-axis direction) of the paper and two rows in the up-down direction (Y-axis direction) of the paper, but the number and arrangement of the diode regions 20a are not limited to this, and it is sufficient that one or more diode regions 20a are scattered within the IGBT region 10, and each diode region 20a is surrounded by the IGBT region 10.

[0043] 2, a signal pad region 40 is provided adjacent to the lower side (negative Y-axis direction) of the IGBT region 10. The signal pad region 40 is a region where a control pad 41 for controlling the semiconductor device 101 is provided.

[0044] The IGBT region 10 and the diode region 20a are collectively referred to as a cell region. A termination region 30 is provided around the combined region of the cell region and the signal pad region 40 to maintain the breakdown voltage of the semiconductor device 101.

[0045] A known breakdown voltage support structure may be appropriately selected and provided in the termination region 30. For example, the breakdown voltage support structure may include an FLR, which surrounds the combined region of the cell region and the signal pad region 40 with a p-type termination well layer of a p-type semiconductor, or a VLD, which surrounds the cell region with a p-type well layer having a concentration gradient, provided on the first principal surface side, i.e., the front surface side, of the semiconductor device 101. The number of ring-shaped p-type termination well layers used in the FLR or the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 101. Alternatively, a p-type termination well layer may be provided over substantially the entire signal pad region 40, or an IGBT cell or a diode cell may be provided in the signal pad region 40.

[0046] The control pads 41 may be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, a temperature sense diode pad 41d, and a temperature sense diode pad 41e.

[0047] The current sense pad 41a is a control pad for detecting the current flowing in the cell region of the semiconductor device 101. When a current flows in the cell region of the semiconductor device 101, it is a control pad electrically connected to some IGBT cells or diode cells in the cell region so that a current of one fraction to one ten-thousandth of the current flowing through the entire cell region flows.

[0048] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for on / off controlling the semiconductor device 101 is applied. The Kelvin emitter pad 41b is electrically connected to the p-type base layer and the n+-type source layer of the IGBT cell, and the gate pad 41c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 41b and the p-type base layer may be electrically connected via a p+-type contact layer.

[0049] The temperature sense diode pads 41d and 41e are control pads electrically connected to the anode electrode and the cathode electrode of the temperature sense diode provided in the semiconductor device 101. The temperature sense diode pads 41d and 41e measure the voltage between the anode and the cathode of a temperature sense diode (not shown here) provided in the cell region to measure the temperature of the semiconductor device 101.

[0050] The temperature sense diode may be arranged in the signal pad region 40, or may be arranged at an arbitrary position inside the terminal region in plan view using wiring. The temperature sense diode may be arranged at a position surrounded by the IGBT region, or may be arranged at a position surrounded by the diode region.

[0051] <Regarding the structure of the IGBT region> FIG. 3 is a plan view showing an example of the configuration of the IGBT region in an RC-IGBT. FIGS. 4 and 5 are cross-sectional views showing examples of the configuration of the IGBT region in an RC-IGBT.

[0052] FIG. 3 is a diagram showing the configuration of the region surrounded by the dashed line 82 in the semiconductor device 100 shown in FIG. 1 or the semiconductor device 101 shown in FIG.

[0053] 4 is a cross-sectional view corresponding to the AA section of the configuration shown in FIG. 3, and FIG. 5 is a cross-sectional view corresponding to the BB section of the configuration shown in FIG.

[0054] As shown in FIG. 3, an IGBT region 10 has active trench gates 11 and dummy trench gates 12 arranged in a stripe pattern.

[0055] In the semiconductor device 100, the active trench gate 11 and the dummy trench gate 12 extend in the longitudinal direction (X-axis direction) of the IGBT region 10, and the longitudinal direction (X-axis direction) of the IGBT region 10 is the longitudinal direction of the active trench gate 11 and the dummy trench gate 12.

[0056] On the other hand, in the semiconductor device 101, there is no particular distinction between the longitudinal direction and the lateral direction of the IGBT region 10, but the left-right direction on the paper (X-axis direction) may be the longitudinal direction of the active trench gate 11 and the dummy trench gate 12, and the up-down direction on the paper (Y-axis direction) may be the longitudinal direction of the active trench gate 11 and the dummy trench gate 12.

[0057] The active trench gate 11 is configured by providing an active trench electrode 11a in a trench formed in a semiconductor substrate via an active trench insulating film 11b.

[0058] The dummy trench gate 12 is configured by providing a dummy trench electrode 12a in a trench formed in a semiconductor substrate via a dummy trench insulating film 12b.

[0059] The active trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0060] N+ type source layers 13 (also referred to as n+ type emitter layers) are provided on both sides of the active trench gate 11 in the width direction so as to be in contact with the active trench insulating film 11b. The n+ type source layers 13 are semiconductor layers containing, for example, arsenic or phosphorus as n-type impurities. The concentration of the n-type impurities is, for example, 1.0×10 17 / cm 3 or more, and 1.0×10 20 / cm 3 The n+ type source layers 13 are provided alternately with the p+ type contact layers 14 along the extension direction of the active trench gate 11.

[0061] The p+ type contact layer 14 is also provided between two adjacent dummy trench gates 12. The p+ type contact layer 14 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity. The concentration of the p-type impurity is, for example, 1.0×10 15 / cm 3 or more, and 1.0×10 20 / cm 3 The following is the result.

[0062] 3, the IGBT region 10 of the semiconductor device 100 or 101 has a configuration in which three active trench gates 11 and three dummy trench gates 12 are alternately arranged. That is, the IGBT region 10 has a configuration in which pairs of active trench gates 11 and pairs of dummy trench gates 12 are alternately arranged.

[0063] 3, the number of active trench gates 11 included in one set of active trench gates 11 is three, but the number of active trench gates 11 may be one or more. Furthermore, the number of dummy trench gates 12 included in one set of dummy trench gates 12 may be one or more, or the number of dummy trench gates 12 may be zero. In other words, all of the trenches provided in the IGBT region 10 may be active trench gates 11.

[0064] FIG. 4 is a cross-sectional view of the semiconductor device 100 or 101 corresponding to the cross section AA in FIG. 3, and specifically, a cross-sectional view of the IGBT region 10. In FIG.

[0065] The semiconductor device 100 or 101 has an n-type drift layer 1 made of a semiconductor substrate. The n-type drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0×10 12 / cm 3 or more, and 1.0×10 15 / cm 3 The following is the result.

[0066] In FIG. 4, the semiconductor substrate corresponds to the configuration ranging from n+ type source layer 13 and p+ type contact layer 14 to p type collector layer 16.

[0067] 4, the upper ends (positive Z-axis direction) of n+ type source layer 13 and p+ type contact layer 14 on the paper are referred to as the first main surface of the semiconductor substrate, and the lower end (negative Z-axis direction) of p-type collector layer 16 on the paper are referred to as the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of semiconductor device 100.

[0068] The semiconductor device 100 has an n-type drift layer 1 between a first main surface and a second main surface opposite to the first main surface in an IGBT region 10 which is a cell region.

[0069] As shown in FIG. 4, in IGBT region 10, n-type carrier accumulation layer 2 having a higher concentration of n-type impurities than n-type drift layer 1 is provided on the first main surface side of n-type drift layer 1.

[0070] The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0×10 13 / cm 3 or more, and 1.0×10 17 / cm 3 The following is the result.

[0071] Note that the semiconductor device 100 or the semiconductor device 101 may have a configuration in which the n-type carrier accumulation layer 2 is not provided, and the n-type drift layer 1 is also provided in the region of the n-type carrier accumulation layer 2 shown in FIG.

[0072] By providing the n-type carrier accumulation layer 2, it is possible to reduce the conduction loss when a current flows through the IGBT region 10.

[0073] The n-type carrier accumulation layer 2 and the n-type drift layer 1 may be collectively referred to as a drift layer.

[0074] The n-type carrier accumulation layer 2 is formed by ion-implanting n-type impurities into the semiconductor substrate that constitutes the n-type drift layer 1, and then diffusing the implanted n-type impurities into the semiconductor substrate that is the n-type drift layer 1 by an annealing process.

[0075] A p-type base layer 15 is provided on the surface layer on the first principal surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is, for example, 1.0×10 12 / cm 3 End , and 1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the active trench insulating film 11b of the active trench gate 11.

[0076] In the surface layer on the first main surface side of the p-type base layer 15, an n+ type source layer 13 is provided in the region in contact with the active trench insulating film 11b of the active trench gate 11, and a p+ type contact layer 14 is provided in the remaining region (i.e., the region not in contact with the active trench insulating film 11b).

[0077] The n+ type source layer 13 and the p+ type contact layer 14 form a first main surface of the semiconductor substrate. The p+ type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15. When it is necessary to distinguish between the p+ type contact layer 14 and the p-type base layer 15, they may be referred to individually, or the p+ type contact layer 14 and the p-type base layer 15 may be collectively referred to as the p-type base layer.

[0078] Furthermore, in semiconductor device 100 or semiconductor device 101, n-type buffer layer 3 having a higher concentration of n-type impurities than n-type drift layer 1 is provided on the second main surface side of n-type drift layer 1.

[0079] The n-type buffer layer 3 is provided to prevent a depletion layer extending from the p-type base layer 15 toward the second main surface from punching through when the semiconductor device 100 is in an off state.

[0080] The n-type buffer layer 3 may be formed by implanting, for example, phosphorus (P) or protons (H+), or may be formed by implanting both phosphorus (P) and protons (H+). The concentration of n-type impurities in the n-type buffer layer 3 is, for example, 1.0×10 12 / cm 3 or more, and 1.0×10 18 / cm 3 The following is the result.

[0081] Note that the semiconductor device 100 or the semiconductor device 101 may have a configuration in which the n-type buffer layer 3 is not provided, and the n-type drift layer 1 is also provided in the region of the n-type buffer layer 3 shown in Fig. 4. The n-type buffer layer 3 and the n-type drift layer 1 may be collectively referred to as the drift layer.

[0082] In the semiconductor device 100 or 101, a p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. That is, the p-type collector layer 16 is provided between the n-type drift layer 1 and the second main surface.

[0083] The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0×10 16 / cm 3 or more, and 1.0×10 20 / cm 3 The following is the result.

[0084] The p-type collector layer 16 forms the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 provided in the termination region 30 forms a p-type termination collector layer 16a (described later). The p-type collector layer 16 may also be provided so that a portion of it extends from the IGBT region 10 into the diode region 20.

[0085] 4, semiconductor device 100 or semiconductor device 101 has a trench formed therein that extends from the first main surface of the semiconductor substrate through p-type base layer 15 and reaches n-type drift layer 1. An active trench electrode 11a is provided in the trench with an active trench insulating film 11b interposed therebetween, thereby forming active trench gate 11. Active trench electrode 11a faces n-type drift layer 1 with active trench insulating film 11b interposed therebetween.

[0086] Furthermore, a dummy trench electrode 12a is provided in the trench via a dummy trench insulating film 12b, thereby forming a dummy trench gate 12. The dummy trench electrode 12a faces the n-type drift layer 1 via the dummy trench insulating film 12b.

[0087] The active trench insulating film 11b of the active trench gate 11 is in contact with the p-type base layer 15 and the n+ type source layer 13. When a gate drive voltage is applied to the active trench electrode 11a, a channel is formed in the p-type base layer 15 that is in contact with the active trench insulating film 11b of the active trench gate 11.

[0088] 4, an interlayer insulating film 4 is provided on the upper surface of the active trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the upper surface of the interlayer insulating film 4 and on the upper surface of the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided.

[0089] The barrier metal 5 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi, an alloy of titanium and silicon (Si). As shown in the example of FIG. 4, the barrier metal 5 is in ohmic contact with the n+ type source layer 13, the p+ type contact layer 14, and the dummy trench electrode 12a, and is electrically connected to the n+ type source layer 13, the p+ type contact layer 14, and the dummy trench electrode 12a. An emitter electrode 6 is provided on the upper surface of the barrier metal 5.

[0090] The emitter electrode 6 may be formed of an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode made of a multi-layer metal film in which a plating film is formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film.

[0091] Furthermore, when there is a minute region, such as between adjacent interlayer insulating films 4, in which the emitter electrode 6 cannot be satisfactorily embedded, tungsten, which has better embedding properties than the emitter electrode 6, may be disposed in the minute region, and the emitter electrode 6 may be provided on the upper surface of the tungsten.

[0092] The emitter electrode 6 may be provided on the upper surfaces of the n+ type source layer 13, the p+ type contact layer 14, and the dummy trench electrode 12a without providing the barrier metal 5. Alternatively, the barrier metal 5 may be provided only on the upper surfaces of the n-type semiconductor layers such as the n+ type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as the emitter electrode.

[0093] 4, the interlayer insulating film 4 is not provided on the upper surface of the dummy trench electrode 12a of the dummy trench gate 12, but the interlayer insulating film 4 may be formed on the upper surface of the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the upper surface of the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in another cross section.

[0094] A collector electrode 7 is provided on the second principal surface side of the p-type collector layer 16. Like the emitter electrode 6, the collector electrode 7 may be made of an aluminum alloy or an aluminum alloy and a plating film. The collector electrode 7 may also have a different structure from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0095] FIG. 5 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 corresponding to the cross section BB in FIG. 3, and specifically, a cross-sectional view of the IGBT region 10. In FIG.

[0096] The cross-sectional view corresponding to the BB cross section shown in Figure 5 differs from the cross-sectional view corresponding to the AA cross section shown in Figure 4 in that the n+ type source layer 13 provided on the first main surface side of the semiconductor substrate while contacting the active trench gate 11 is not visible. That is, as shown in the example in Figure 4, the n+ type source layer 13 is selectively provided on the first main surface side of the p-type base layer. Note that the p-type base layer referred to here refers to the p-type base layer 15 and the p+ type contact layer 14 collectively.

[0097] <Diode region structure> Fig. 6 is a plan view showing an example of the configuration of a diode region in an RC-IGBT, and Figs. 7 and 8 are cross-sectional views showing examples of the configuration of a diode region in an RC-IGBT.

[0098] Fig. 6 is a diagram showing the configuration of a region surrounded by a dashed line 83 in the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2. In the following, this will be described as a diode region 20, but the same applies to a diode region 20a.

[0099] 7 is a cross-sectional view corresponding to the CC cross section of the configuration shown in FIG. 6, and FIG. 8 is a cross-sectional view corresponding to the DD cross section of the configuration shown in FIG.

[0100] The diode trench gate 21 extends from one end of the diode region 20, which is a cell region, to the opposing other end along the first main surface of the semiconductor device. The diode trench gate 21 is configured by providing a diode trench electrode 21a via a diode trench insulating film 21b in a trench formed in the semiconductor substrate of the diode region 20. The diode trench electrode 21a faces the n-type drift layer 1 via the diode trench insulating film 21b.

[0101] A p+ type contact layer 24 and a p-type anode layer 25 are provided between two adjacent diode trench gates 21. The p+ type contact layer 24 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0×10 15 / cm 3 or more, and 1.0×10 20 / cm 3 The following is the result.

[0102] The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0×10 12 / cm 3 or more, and 1.0×10 19 / cm 3 below is.

[0103] The p+ type contact layers 24 and the p type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 (the X-axis direction).

[0104] FIG. 7 is a cross-sectional view corresponding to the CC cross section in FIG. 6, and specifically, is a cross-sectional view of the diode region 20. In FIG.

[0105] The semiconductor device 100 or 101 has an n-type drift layer 1 made of a semiconductor substrate in the diode region 20 (or diode region 20a) as in the IGBT region 10. The n-type drift layer 1 in the diode region 20 and the n-type drift layer 1 in the IGBT region 10 are formed as a continuous, integrated unit using the same semiconductor substrate. In FIG. 7, the semiconductor substrate corresponds to the configuration ranging from the p+ type contact layer 24 to the n+ type cathode layer 26.

[0106] 7, the upper end of the p+ type contact layer 24 on the page (positive side of the Z axis) is called the first main surface of the semiconductor substrate, and the lower end of the n+ type cathode layer 26 on the page (negative side of the Z axis) is called the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are flush with each other, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are flush with each other.

[0107] As shown in the example in FIG. 7, in the diode region 20, similar to the IGBT region 10, an n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, and an n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1.

[0108] The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the IGBT region 10. Note that the n-type carrier accumulation layer 2 does not necessarily need to be provided in the IGBT region 10 and the diode region 20; even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, the n-type carrier accumulation layer 2 may not be provided in the diode region 20. Also, as with the IGBT region 10, the n-type drift layer 1, n-type carrier accumulation layer 2, and n-type buffer layer 3 may be collectively referred to as the drift layer.

[0109] A p-type anode layer 25 is provided on the first principal surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is provided between the n-type drift layer 1 and the first principal surface. The p-type anode layer 25 may have the same p-type impurity concentration as the p-type base layer 15 of the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. Alternatively, the p-type impurity concentration of the p-type anode layer 25 may be set lower than the p-type impurity concentration of the p-type base layer 15 of the IGBT region 10 to reduce the number of holes injected into the diode region 20 during diode operation. Note that reducing the number of holes injected during diode operation can reduce recovery loss during diode operation.

[0110] A p+-type contact layer 24 is provided on the first main surface side of the p-type anode layer 25. The concentration of p-type impurities in the p+-type contact layer 24 may be the same as or different from the concentration of p-type impurities in the p+-type contact layer 14 of the IGBT region 10. The p+-type contact layer 24 constitutes the first main surface of the semiconductor substrate. Note that the p+-type contact layer 24 is a region having a higher concentration of p-type impurities than the p-type anode layer 25. When it is necessary to distinguish between the p+-type contact layer 24 and the p-type anode layer 25, they may be referred to individually, or the p+-type contact layer 24 and the p-type anode layer 25 may be collectively referred to as the p-type anode layer.

[0111] In the diode region 20, an n+ type cathode layer 26 is provided on the second main surface side of the n- type buffer layer 3. The n+ type cathode layer 26 is provided between the n- type drift layer 1 and the second main surface. The n+ type cathode layer 26 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is, for example, 1.0×10 16 / cm 3 or more, and 1.0×10 21 / cm 3 The following is the result.

[0112] The n+ type cathode layer 26 is provided in part or all of the diode region 20. The n+ type cathode layer 26 constitutes the second main surface of the semiconductor substrate. Note that, as described above, a p-type impurity may be further selectively implanted into the region where the n+ type cathode layer 26 is formed, thereby providing a p-type cathode layer as a p-type semiconductor in part of the region where the n+ type cathode layer 26 is formed.

[0113] 7, a trench is formed in the diode region 20, penetrating the p-type anode layer 25 from the first main surface of the semiconductor substrate and reaching the n-type drift layer 1. A diode trench electrode 21a is provided in the trench of the diode region 20 via a diode trench insulating film 21b, thereby forming a diode trench gate 21. The diode trench electrode 21a faces the n-type drift layer 1 via the diode trench insulating film 21b.

[0114] 7, a barrier metal 5 is provided on the upper surfaces of the diode trench electrode 21a and the p+ type contact layer 24. The barrier metal 5 is in ohmic contact with the diode trench electrode 21a and the p+ type contact layer 24, and is electrically connected to the diode trench electrode and the p+ type contact layer 24.

[0115] The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. On the upper surface of the barrier metal 5, an emitter electrode 6 is provided.

[0116] The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. As in the case of the IGBT region 10, the diode trench electrode 21a and the p+-type contact layer 24 may be in ohmic contact with the emitter electrode 6 without providing the barrier metal 5. Although the interlayer insulating film 4 is not provided on the upper surface of the diode trench electrode 21a of the diode trench gate 21 in FIG. 7, the interlayer insulating film 4 may be formed on the upper surface of the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the upper surface of the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in another cross section.

[0117] A collector electrode 7 is provided on the second principal surface side of the n+ type cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is in ohmic contact with the n+ type cathode layer 26 and is electrically connected to the n+ type cathode layer 26.

[0118] FIG. 8 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 corresponding to the cross section DD in FIG. 6, and specifically, is a cross-sectional view of the diode region 20. In FIG.

[0119] The cross-sectional view corresponding to the D-D cross section shown in FIG. 8 is different from the cross-sectional view corresponding to the C-C cross section shown in FIG. 7 in that a p+-type contact layer 24 is not provided between the p-type anode layer 25 and the barrier metal 5, and the p-type anode layer 25 constitutes the first main surface of the semiconductor substrate. That is, the p+-type contact layer 24 shown in FIG. 7 is selectively provided on the first main surface side of the p-type anode layer 25.

[0120] <Regarding the boundary region between the IGBT region and the diode region> FIG. 9 is a cross-sectional view showing an example of the structure of the boundary region between the IGBT region and the diode region in the RC-IGBT. FIG. 9 is a cross-sectional view corresponding to the G-G cross section in the semiconductor device 100 or the semiconductor device 101 shown in FIG. 1.

[0121] As shown by the example in FIG. 9, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 protrudes by a distance U1 toward the diode region 20 from the boundary between the IGBT region 10 and the diode region 20.

[0122] Thus, by providing the p-type collector layer 16 to protrude into the diode region 20, the distance between the n+-type cathode layer 26 in the diode region 20 and the active trench gate 11 can be increased.

[0123] Then, even when a gate drive voltage is applied to the active trench electrode 11a during the operation of the freewheeling diode, it is possible to suppress the current from flowing from the channel formed adjacent to the active trench gate 11 in the IGBT region 10 to the n+-type cathode layer 26.

[0124] The distance U1 may be, for example, 100 μm. Note that depending on the application of the semiconductor device 100 or the semiconductor device 101 which is an RC-IGBT, the distance U1 may be zero or a distance smaller than 100 μm.

[0125] <Regarding the structure of the termination region> 10 and 11 are cross-sectional views showing examples of the configuration of the termination region in an RC-IGBT. Fig. 10 is a cross-sectional view corresponding to the E-E cross-section in Fig. 1 or 2, specifically a cross-sectional view from the IGBT region 10 to the termination region 30. Fig. 11 is a cross-sectional view corresponding to the F-F cross-section in Fig. 1, specifically a cross-sectional view from the diode region 20 to the termination region 30.

[0126] 10 and 11 , termination region 30 of semiconductor device 100 has n-type drift layer 1 between the first and second main surfaces of the semiconductor substrate. The first and second main surfaces of termination region 30 are flush with the first and second main surfaces of IGBT region 10 and diode region 20, respectively. Furthermore, n-type drift layer 1 of termination region 30 has the same configuration as n-type drift layers 1 of IGBT region 10 and diode region 20, respectively, and is formed continuously and integrally.

[0127] A p-type termination well layer 31 is provided on the first main surface side of the n-type drift layer 1, i.e., between the first main surface of the semiconductor substrate and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is, for example, 1.0×10 14 / cm 3 or more, and 1.0×10 19 / cm 3 The following is the result.

[0128] The p-type termination well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in the shape of a plurality of rings, and the number of p-type termination well layers 31 provided is appropriately selected depending on the breakdown voltage design of the semiconductor device 100 or the semiconductor device 101.

[0129] Furthermore, an n+ type channel stopper layer 32 is provided on the outer edge side of the p-type termination well layer 31. The n+ type channel stopper layer 32 surrounds the p-type termination well layer 31.

[0130] A p-type termination collector layer 16a is provided between the n-type drift layer 1 and the second main surface of the semiconductor substrate. The p-type termination collector layer 16a is formed continuously and integrally with the p-type collector layer 16 provided in the cell region. Therefore, the p-type collector layer 16 may be referred to as the p-type collector layer 16, including the p-type termination collector layer 16a.

[0131] In addition, in a configuration in which the diode region 20 is provided adjacent to the termination region 30, such as the semiconductor device 100 shown in FIG. 1, the end of the p-type termination collector layer 16a on the diode region 20 side is provided so as to extend into the diode region 20 by a distance U2, as shown in the example of FIG.

[0132] In this way, by providing the p-type termination collector layer 16a so as to extend into the diode region 20, the distance between the n+ type cathode layer 26 in the diode region 20 and the p-type termination well layer 31 can be increased, and the p-type termination well layer 31 can be prevented from functioning as the anode of the diode. The distance U2 may be, for example, 100 μm.

[0133] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is formed continuously and integrally from the cell region including the IGBT region 10 and the diode region 20 to the termination region 30. On the other hand, an emitter electrode 6 continuing from the cell region and a termination electrode 6a separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the termination region 30.

[0134] The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, sinSiN (semi-insulating silicon nitride).

[0135] The termination electrode 6a is electrically connected to the p-type termination well layer 31 and the n+-type channel stopper layer 32 via contact holes formed in the interlayer insulating film 4 provided on the first main surface of the termination region 30.

[0136] In addition, in the termination region 30, a termination protective film 34 is provided to cover the emitter electrode 6, the termination electrode 6a, and the semi-insulating film 33. The termination protective film 34 may be made of, for example, polyimide.

[0137] <About the structure of the temperature sensing diode> Fig. 12 is a cross-sectional view showing an example of the structure of a temperature sense diode (temperature detection diode). As shown in the example in Fig. 12, a temperature sense diode 200 is formed on the upper surface of a p-type diffusion layer 202. The p-type diffusion layer 202 is formed on the surface layer of an n-type drift layer 1, and an n-type buffer layer 3 is formed on the lower surface of the n-type drift layer 1. Furthermore, a p+ type collector layer 204 is formed on the lower surface of the n-type buffer layer 3, and an electrode layer 206 is formed on the lower surface of the p+ type collector layer 204.

[0138] The temperature sensing diode 200 includes an interlayer insulating film 208a formed on the upper surface of the p-type diffusion layer 202, a p+ type anode layer 210 partially formed on the upper surface of the interlayer insulating film 208a, a p-type drift layer 212 adjacent to the p+ type anode layer 210 and partially formed on the upper surface of the interlayer insulating film 208a, an n+ type cathode layer 214 sandwiched between the p-type drift layers 212 and partially formed on the upper surface of the interlayer insulating film 208a, an interlayer insulating film 208b formed to cover part of the upper surface of the p+ type anode layer 210, the upper surface of the p-type drift layer 212, and part of the upper surface of the n+ type cathode layer 214, an anode electrode 216 formed in contact with the upper surface of the p+ type anode layer 210 exposed from the interlayer insulating film 208b, and a cathode electrode 218 formed in contact with the upper surface of the n+ type cathode layer 214 exposed from the interlayer insulating film 208b. Although not shown here, a barrier metal may be formed at the interface between the electrode and the interlayer insulating film and at the interface between the electrode and the PolySi layer.

[0139] The diode for detecting the element temperature of the IGBT is formed on the upper surface of the interlayer insulating film 208a on the Si substrate using a polysilicon (PolySi) film. Therefore, the area where the temperature detection (temperature sense) diode is formed forms a step, and the step may cause problems such as the generation of residual foreign matter, unevenness in the resist coating during photolithography, and defocusing.

[0140] Fig. 13 is a cross-sectional view showing another example of the structure of a temperature sensing diode. As shown in the example in Fig. 13, the temperature sensing diode is formed in a p-type diffusion layer 202. The p-type diffusion layer 202 is formed on the surface layer of an n-type drift layer 1, and an n-type buffer layer 3 is formed on the lower surface of the n-type drift layer 1. Furthermore, a p+ type collector layer 204 is formed on the lower surface of the n-type buffer layer 3, and an electrode layer 206 is formed on the lower surface of the p+ type collector layer 204.

[0141] The temperature sensing diode includes an n-type well diffusion layer 220 formed by diffusion into the surface layer of the p-type diffusion layer 202, a p+-type anode layer 222 formed by diffusion into the surface layer of the n-type well diffusion layer 220, an n+-type cathode layer 224 formed by diffusion into the surface layer of the n-type well diffusion layer 220 while being spaced apart from the p+-type anode layer 222, an interlayer insulating film 226 formed to cover a part of the upper surface of the p+-type anode layer 222 and a part of the upper surface of the n+-type cathode layer 224, an anode electrode 216 formed in contact with the upper surface of the p+-type anode layer 222 exposed from the interlayer insulating film 226, and a cathode electrode 218 formed in contact with the upper surface of the n+-type cathode layer 224 exposed from the interlayer insulating film 226. Although not shown here, barrier metals may be formed at the interfaces between the electrodes and the interlayer insulating film and between the electrodes and the PolySi layer.

[0142] A diode for detecting the temperature of the IGBT element is formed within the Si substrate. The temperature sensing diode is constructed within the junction isolation provided by the N-type well diffusion layer 220 while suppressing interference with adjacent IGBT elements.

[0143] With this structure, the step can be reduced compared to a temperature sensing diode made of a PolySi film on the upper surface of the interlayer insulating film.

[0144] However, in such a structure, there exists a parasitic PNP bipolar transistor consisting of the p+ type anode layer 222, the N-type well diffusion layer 220, and the P-type diffusion layer 202. When this parasitic PNP bipolar transistor operates, the characteristics of the temperature sensing diode fluctuate. Therefore, it is necessary to suppress the operation of this parasitic PNP bipolar transistor. To achieve this, measures such as forming the N-type well diffusion layer 220 sufficiently deep can be considered, but it is difficult to completely suppress the operation of the parasitic PNP bipolar transistor.

[0145] 14 is a cross-sectional view showing an example of the configuration of a temperature sensing diode in a temperature detection region according to this embodiment. As shown in the example in FIG. 14, the temperature sensing diode is formed in a p-type diffusion layer 202. The p-type diffusion layer 202 is formed on the surface of an n-type drift layer 1, and an n-type buffer layer 3 is formed on the lower surface of the n-type drift layer 1. Furthermore, a p+ type collector layer 204 is formed on the lower surface of the n-type buffer layer 3, and an electrode layer 206 is formed on the lower surface of the p+ type collector layer 204.

[0146] The temperature sensing diode includes an n-type well diffusion layer 220 formed by diffusion into the surface layer of the p-type diffusion layer 202, an n+ type cathode layer 224 formed by diffusion into the surface layer of the n-type well diffusion layer 220, an interlayer insulating film 226 formed to cover part of the upper surface of the n-type well diffusion layer 220 and part of the upper surface of the n+ type cathode layer 224, an anode electrode 216 formed in contact with the upper surface of the n-type well diffusion layer 220 exposed from the interlayer insulating film 226, and a cathode electrode 218 formed in contact with the upper surface of the n+ type cathode layer 224 exposed from the interlayer insulating film 226.

[0147] Although not shown here, a barrier metal may be formed at the interface between the electrode and the interlayer insulating film and at the interface between the electrode and the PolySi layer. However, the Schottky junction surface where the anode electrode 216 and the n-type well diffusion layer 220 come into contact varies in barrier height of the Schottky diode depending on the electrode material. Therefore, the electrode is selected according to the required characteristics of the temperature sensing diode. For example, Al or an Al-based alloy is desirable for the electrode.

[0148] As described above, the anode electrode 216 is in direct contact with the n-type well diffusion layer 220, so that the n-type well diffusion layer 220 and the n+ type cathode layer 224 form a Schottky diode. The Schottky diode operates in a unipolar manner driven only by electrons, and therefore can suppress the operation of a parasitic PNP bipolar transistor.

[0149] Here, the p-type diffusion layer 202 may be formed simultaneously with the p-type base layer 15 of the IGBT region 10, and may have the same depth and concentration as the p-type base layer 15.

[0150] Furthermore, p-type diffusion layer 202 may be formed simultaneously with p-type termination well layer 31 in termination region 30, and may have the same depth and concentration as p-type termination well layer 31.

[0151] Furthermore, the n+ type cathode layer 224 may be formed simultaneously with the n+ type source layer 13 in the IGBT region 10, and may have the same depth and concentration as the n+ type source layer 13.

[0152] By combining these, the additional process for forming the temperature sensing diode can be limited to the process for forming the n-type well diffusion layer 220. Therefore, it is possible to suppress an increase in the number of steps for manufacturing the temperature sensing diode.

[0153] <Second embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0154] <Configuration of semiconductor device> Fig. 15 is a cross-sectional view showing an example of the configuration of a temperature sensing diode according to this embodiment. As shown in the example in Fig. 15, the temperature sensing diode is formed in a p-type diffusion layer 202. The p-type diffusion layer 202 is formed on the surface of an n-type drift layer 1, and an n-type buffer layer 3 is formed on the lower surface of the n-type drift layer 1. Furthermore, a p+ type collector layer 204 is formed on the lower surface of the n-type buffer layer 3, and an electrode layer 206 is formed on the lower surface of the p+ type collector layer 204.

[0155] The temperature sensing diode includes an n-type well diffusion layer 220 formed by diffusion into the surface layer of the p-type diffusion layer 202, a p+ type anode layer 228 formed by diffusion into the surface layer of the n-type well diffusion layer 220, an n+ type cathode layer 224 formed by diffusion into the surface layer of the n-type well diffusion layer 220 while being spaced apart from the p+ type anode layer 228, an interlayer insulating film 226 formed to cover part of the upper surface of the n-type well diffusion layer 220, part of the upper surface of the p+ type anode layer 228, and part of the upper surface of the n+ type cathode layer 224, an anode electrode 216 formed in contact with the upper surface of the n-type well diffusion layer 220 and the upper surface of the p+ type anode layer 228 exposed from the interlayer insulating film 226, and a cathode electrode 218 formed in contact with the upper surface of the n+ type cathode layer 224 exposed from the interlayer insulating film 226.

[0156] The p+ type anode layer 228 is formed so as to cover the end portion, in plan view, of the Schottky junction surface where the n-type well diffusion layer 220 and the anode electrode 216 come into contact with each other. By forming it in this manner, it is possible to stabilize the breakdown voltage of the Schottky junction.

[0157] The distance between the ends of the p+ type anode layer 228, which serves as a path for current flowing from the Schottky junction, at the Schottky junction surface is set to be sufficiently wide so that the diode formed by the p+ type anode layer 228 and the n-type well diffusion layer 220 does not operate.

[0158] Furthermore, the p+ type anode layer 228 may be formed simultaneously with the p+ type contact layer 14 formed in the IGBT region 10, and may have the same depth and concentration as the p+ type contact layer 14. In this way, the above configuration can be manufactured without adding any additional steps.

[0159] <Third embodiment> A semiconductor device according to the present embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0160] <Configuration of semiconductor device> Fig. 16 is a cross-sectional view showing an example of the configuration of a temperature sensing diode according to this embodiment. As shown in the example in Fig. 16, the temperature sensing diode is formed in a p-type diffusion layer 202. The p-type diffusion layer 202 is formed on the surface of an n-type drift layer 1, and an n-type buffer layer 3 is formed on the lower surface of the n-type drift layer 1. Furthermore, a p+ type collector layer 204 is formed on the lower surface of the n-type buffer layer 3, and an electrode layer 206 is formed on the lower surface of the p+ type collector layer 204.

[0161] The temperature sensing diode includes an n-type well diffusion layer 220 formed by diffusion in the surface layer of the p-type diffusion layer 202, an n+-type cathode layer 224 formed by diffusion in the surface layer of the n-type well diffusion layer 220, an interlayer insulating film 226 formed to cover a part of the upper surface of the n-type well diffusion layer 220, a part of the upper surface of the p-type diffusion layer 202, and a part of the upper surface of the n+-type cathode layer 224, an anode electrode 216 formed in contact with the upper surface of the n-type well diffusion layer 220 exposed from the interlayer insulating film 226, a cathode electrode 218 formed in contact with the upper surface of the n+-type cathode layer 224 exposed from the interlayer insulating film 226, and an emitter electrode 6 formed in contact with the upper surface of the p-type diffusion layer 202 exposed from the interlayer insulating film 226. The anode electrode 216 and the cathode electrode 218 may be formed simultaneously with the emitter electrode 6 and may have the same thickness.

[0162] According to this configuration, by connecting the p-type diffusion layer 202 to the emitter electrode 6 of the IGBT, it is possible to stabilize the junction isolation, and it is possible to further stabilize the characteristics of the temperature sensing diode.

[0163] Fig. 17 is a cross-sectional view showing another example of the configuration of a temperature sensing diode according to this embodiment. As shown in the example in Fig. 17, the temperature sensing diode is formed in a p-type diffusion layer 202. The p-type diffusion layer 202 is formed in the surface layer of an n-type drift layer 1, and an n-type buffer layer 3 is formed on the lower surface of the n-type drift layer 1. Furthermore, a p+ type collector layer 204 is formed on the lower surface of the n-type buffer layer 3, and an electrode layer 206 is formed on the lower surface of the p+ type collector layer 204.

[0164] The temperature sensing diode includes an n-type well diffusion layer 220 formed by diffusion in the surface layer of the p-type diffusion layer 202, an n+-type cathode layer 224 formed by diffusion in the surface layer of the n-type well diffusion layer 220, an interlayer insulating film 226 formed to cover part of the upper surface of the n-type well diffusion layer 220, part of the upper surface of the p-type diffusion layer 202, and part of the upper surface of the n+-type cathode layer 224, an anode electrode 216 formed in contact with the upper surface of the n-type well diffusion layer 220 exposed from the interlayer insulating film 226, and an emitter electrode 6b formed in contact with the upper surface of the n+-type cathode layer 224 exposed from the interlayer insulating film 226 and the upper surface of the p-type diffusion layer 202 exposed from the interlayer insulating film 226. The anode electrode 216 may be formed simultaneously with the emitter electrode 6b and may have the same thickness.

[0165] With this configuration, the cathode electrode can be configured as a part of the emitter electrode 6b of the IGBT.

[0166] <Effects of the above-described embodiments> Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained. In other words, for convenience, only one of the corresponding specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another corresponding specific configuration.

[0167] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0168] According to the embodiment described above, the semiconductor device includes a temperature detection region, an IGBT region 10 (corresponding to a switching element region) at least partially surrounding the temperature detection region in a plan view, and a signal pad region 40. A diffusion layer of a second conductivity type, a well layer of a first conductivity type, and a cathode layer of the first conductivity type are provided in the temperature detection region. Here, the diffusion layer corresponds to, for example, a p-type diffusion layer 202. The well layer corresponds to, for example, an n-type well diffusion layer 220. The cathode layer corresponds to, for example, an n+-type cathode layer 224. The p-type diffusion layer 202 is provided in a surface layer of a drift layer of the first conductivity type. Here, the drift layer corresponds to, for example, an n-type drift layer 1. The n-type well diffusion layer 220 is provided in a surface layer of the p-type diffusion layer 202. The n-type well diffusion layer 220 is electrically connected to an anode electrode 216. The n+ type cathode layer 224 is provided on the surface layer of the n-type well diffusion layer 220. The n+ type cathode layer 224 is electrically connected to the cathode electrode 218. The n+ type cathode layer 224 has a higher impurity concentration than the n-type well diffusion layer 220. The IGBT region 10 is provided with a second conductivity type base layer, a first conductivity type source layer, multiple trenches, and a gate electrode. The base layer corresponds to, for example, the p-type base layer 15. The source layer corresponds to, for example, the n+ type source layer 13. The gate electrode corresponds to, for example, the active trench electrode 11a or the dummy trench electrode 12a. The p-type base layer 15 is provided on the surface layer of the first conductivity type semiconductor layer. The semiconductor layer corresponds to, for example, the n- type drift layer 1 or the n- type carrier accumulation layer 2. The n+ type source layer 13 is partially provided on the surface layer of the p type base layer 15. A plurality of trenches are provided from the upper surface of the p type base layer 15 to the inside of the n- type drift layer 1. The active trench electrode 11a is provided in the trench and surrounded by the active trench insulating film 11b. The signal pad region 40 is provided with an anode pad electrically connected to the anode electrode 216 and a cathode pad electrically connected to the cathode electrode 218.Here, the anode pad corresponds to, for example, the temperature sensing diode pad 41d, etc., and the cathode pad corresponds to, for example, the temperature sensing diode pad 41e, etc.

[0169] With this configuration, by using a Schottky diode that operates unipolarly as the temperature sensing diode, it is possible to suppress the operation of the parasitic bipolar transistor and suppress the variation in the characteristics of the temperature sensing diode, thereby improving the accuracy of temperature detection.

[0170] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0171] Furthermore, according to the embodiment described above, an anode layer of a second conductivity type is provided in the temperature detection region. Here, the anode layer corresponds to, for example, the p+ type anode layer 228. The p+ type anode layer 228 is provided at the end of the Schottky junction portion in plan view, at the Schottky junction portion where the n-type well diffusion layer 220 and the anode electrode 216 come into contact. With this configuration, the end of the Schottky junction portion can be covered with the p+ type anode layer 228, thereby stabilizing the breakdown voltage of the Schottky junction.

[0172] Furthermore, according to the embodiment described above, in the IGBT region 10, the n+ type source layer 13 is electrically connected to the emitter electrode 6. In the temperature detection region, the p-type diffusion layer 202 is connected to the emitter electrode 6. With this configuration, the p-type diffusion layer 202 constituting the junction isolation can be set at the same potential as the emitter electrode 6, thereby stabilizing the junction isolation. This allows the characteristics of the temperature sensing diode to be stabilized.

[0173] Furthermore, according to the embodiment described above, the semiconductor device includes the diode region 20 (or the diode region 20a) provided adjacent to the IGBT region 10. The temperature detection region is provided surrounded by the IGBT region 10. With this configuration, even in an RC-IGBT where the temperature detection region is arranged in a position surrounded by the IGBT region 10, it is possible to suppress characteristic variations in the temperature sense diode.

[0174] Furthermore, according to the embodiment described above, the semiconductor device includes the diode region 20 (or the diode region 20a) that surrounds the temperature detection region in a plan view. The IGBT region 10 at least partially surrounds the diode region 20 (or the diode region 20a). With this configuration, even in an RC-IGBT where the temperature detection region is located in a position surrounded by the diode region 20 (or the diode region 20a), it is possible to suppress variations in the characteristics of the temperature sensing diode. Furthermore, it is possible to detect the temperature during diode operation.

[0175] <Modifications of the above-described embodiments> In the embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0176] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0177] Furthermore, in the embodiments described above, when a material name is mentioned without any particular specification, it is assumed that the material may contain other additives, such as an alloy, unless a contradiction arises.

[0178] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, it is also understood that "one or more" of that component may be provided.

[0179] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to part of a structure, and even cases where multiple components are provided in one structure.

[0180] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0181] Furthermore, in the above-described embodiment, a semiconductor device provided with the IGBT region 10 and the diode region 20 has been shown, but it is also possible to imagine a case where the IGBT in the IGBT region 10 is replaced with a metal-oxide-semiconductor field-effect transistor (MOSFET). That is, the component provided in the region corresponding to the IGBT region 10 may be a switching element including an IGBT and a MOSFET.

[0182] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art. [Explanation of symbols]

[0183] 1 n-type drift layer, 2 n-type carrier accumulation layer, 3 n-type buffer layer, 4, 208a, 208b, 226 interlayer insulating film, 5 barrier metal, 6, 6b emitter electrode, 6a termination electrode, 7 collector electrode, 10 IGBT region, 11 active trench gate, 11a active trench electrode, 11b active trench insulating film, 12 dummy trench gate, 12a dummy trench electrode, 12b dummy trench insulating film, 13 n+ type source layer, 14 p+ type contact layer, 15 p-type base layer, 16 p-type collector layer, 16a p-type termination collector layer, 20, 20a diode region, 21 diode trench gate, 21a diode trench electrode, 21b diode trench insulating film, 24 p+ type contact layer, 25 p-type anode layer, 26, 214, 224 n+ type cathode layer, 30 Termination region, 31 p-type termination well layer, 32 n+ type channel stopper layer, 33 semi-insulating film, 34 termination protection film, 40 signal pad region, 41 control pad, 41a current sense pad, 41b Kelvin emitter pad, 41c gate pad, 41d, 41e temperature sense diode pad, 52, 54, 200 temperature sense diode, 52a, 52b, 54a, 54b wiring, 82, 83 dashed lines, 100, 101 semiconductor device, 202 p-type diffusion layer, 204 p+ type collector layer, 206 electrode layer, 210, 222, 228 p+ type anode layer, 212 p-type drift layer, 216 anode electrode, 218 cathode electrode, 220 n-type well diffusion layer.

Claims

1. A semiconductor device comprising: a temperature detection region; a switching element region that at least partially surrounds the temperature detection region in a plan view; and a signal pad region; the temperature detection region is provided with a diffusion layer of a second conductivity type provided on a surface layer of a drift layer of a first conductivity type, a well layer of the first conductivity type provided on the surface layer of the diffusion layer and in contact with an anode electrode, and a cathode layer of the first conductivity type provided on the surface layer of the well layer and electrically connected to a cathode electrode; the cathode layer has a higher impurity concentration than the well layer, the diffusion layer is connected to an emitter electrode; the switching element region is provided with a base layer of a second conductivity type provided on a surface layer of a semiconductor layer of a first conductivity type, a source layer of the first conductivity type partially provided on the surface layer of the base layer, a plurality of trenches provided from an upper surface of the base layer to the inside of the semiconductor layer, and a gate electrode provided in the trench and surrounded by a gate insulating film; the source layer is electrically connected to the emitter electrode; the cathode electrode is electrically connected to the emitter electrode; an anode pad electrically connected to the anode electrode and a cathode pad electrically connected to the cathode electrode are provided in the signal pad area; Semiconductor device.

2. 2. The semiconductor device according to claim 1, In the temperature detection region, a second conductivity type anode layer is further provided at an end of a Schottky junction portion where the well layer and the anode electrode are in contact with each other in a plan view. Semiconductor device.

3. 3. The semiconductor device according to claim 1, a diode region provided adjacent to the switching element region, The temperature detection region is surrounded by the switching element region. Semiconductor device.

4. 3. The semiconductor device according to claim 1, Further, a diode region surrounding the temperature detection region in a plan view is provided, the switching element region at least partially surrounds the diode region; Semiconductor device.

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