Semiconductor device and method for manufacturing the same

Abstract

To provide technology that enables sub-modules to be easily removed from semiconductor devices and to reuse the sub-modules.SOLUTION: A semiconductor device has a sub-module 1 in which a conductor plate 21 and a semiconductor element 11 mounted on the top surface of the conductor plate 21 via a first bonding material 13 are sealed with a first sealing material 24, an insulating substrate 31 bonded to the bottom surface of the sub-module 1 via a second bonding material 12, a case 33 surrounding the insulating substrate 31 and the sub-module 1, and a second sealing material 34 sealing an area surrounded by the case 33 so that the top surface of the sub-module 1 is at least exposed.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. [Background technology]

[0002] For example, Patent Document 1 discloses a semiconductor device including multiple submodules. In the technology described in Patent Document 1, submodules each having multiple SiC chips (corresponding to semiconductor elements) sandwiched between upper and lower electrodes are incorporated into a semiconductor device, and then the periphery of the SiC chips is sealed with a sealing resin to insulate them. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 047474 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the technology described in Patent Document 1, the entire submodule is sealed with sealing resin, so if one tries to reuse the submodule to manufacture another semiconductor device, it is difficult to remove the submodule from the semiconductor device.

[0005] Therefore, an object of the present disclosure is to provide a technique that allows a submodule to be easily removed from a semiconductor device and reused. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure includes a submodule in which a conductor plate and a semiconductor element mounted on an upper surface of the conductor plate via a first bonding material are sealed with a first sealing material, an insulating substrate bonded to a lower surface of the submodule via a second bonding material, a case surrounding the periphery of the insulating substrate and the submodule, and a second sealing material sealing an area surrounded by the case so that at least the upper surface of the submodule is exposed. a current-carrying electrode connected to the semiconductor element; and a connection member connecting the current-carrying electrode and the circuit pattern of the insulating substrate. Equipped with a part of the connection member is exposed from the second sealing material, and the connection member forms a loop shape on the upper surface of the sub-module; . [Effects of the Invention]

[0007] According to the present disclosure, the submodule is not completely covered by the second sealing material, and at least the top surface of the submodule is exposed, so that the submodule can be easily removed from the semiconductor device without melting the second sealing material, thereby enabling the submodule to be reused. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a perspective view showing an internal structure of a submodule included in the semiconductor device according to the first embodiment. [Figure 2] 1 is a perspective view of a submodule included in the semiconductor device according to the first embodiment. [Figure 3] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device according to a modification of the first embodiment. [Figure 5] FIG. 10 is a perspective view of a submodule included in a semiconductor device according to a second embodiment. [Figure 6] FIG. 11 is a perspective view of a submodule included in a semiconductor device according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] <First Embodiment> <Submodule configuration> The first embodiment will be described below with reference to the drawings. Fig. 1 is a perspective view showing the internal structure of a submodule 1 included in a semiconductor device according to the first embodiment. Fig. 2 is a perspective view of the submodule 1 included in the semiconductor device according to the first embodiment. Note that Fig. 1 shows a state in which a first sealing material 24 has been removed from the submodule 1 to make the internal structure easier to see.

[0010] In FIG. 1, the X direction, Y direction, and Z direction are perpendicular to one another. The X direction, Y direction, and Z direction shown in the following figures are also perpendicular to one another. Hereinafter, the direction including the X direction and the −X direction opposite to the X direction will also be referred to as the “X-axis direction.” Hereinafter, the direction including the Y direction and the −Y direction opposite to the Y direction will also be referred to as the “Y-axis direction.” Hereinafter, the direction including the Z direction and the −Z direction opposite to the Z direction will also be referred to as the “Z-axis direction.”

[0011] As shown in Figures 1 and 2, the submodule 1 includes two conductive plates 21, two lead frames 21a, ten semiconductor elements 11, two current-carrying electrodes 22, four signal terminals 23, and a first sealing material 24.

[0012] The number of semiconductor elements 11 can be changed, and the numbers of conductive plates 21, lead frames 21a, current-carrying electrodes 22, and signal terminals 23 can be changed according to the number of semiconductor elements 11.

[0013] Each conductor plate 21 is formed in a rectangular shape when viewed from above. The two conductor plates 21 are arranged side by side in the X-axis direction with their long sides adjacent to each other. When the two conductor plates 21 are arranged side by side, one end of the long side on the outer periphery of each of the two conductor plates 21 (the end in the -Y direction) is formed longer than one end of the long side on the inner periphery.

[0014] Two lead frames 21a are arranged side by side in the X-axis direction and adjacent to each other in the longitudinal direction between the two conductive plates 21. The longitudinal length of each lead frame 21a is the same as the length of the long side on the outer periphery of the two conductive plates 21 when the two conductive plates 21 are arranged side by side.

[0015] Five semiconductor elements 11 are mounted on the upper surface (surface in the Z direction) of each conductive plate 21 via a first bonding material 13 (see FIG. 3). A source electrode and a gate electrode (not shown) are provided on the upper surface (surface in the Z direction) of each semiconductor element 11, and a drain electrode (not shown) is provided on the lower surface (surface in the -Z direction) of each semiconductor element 11. Each conductive plate 21 is bonded to the drain electrodes of the five semiconductor elements 11 via the first bonding material 13 (see FIG. 3). In addition, each current-carrying electrode 22 is connected to the source electrodes of the five semiconductor elements 11.

[0016] The semiconductor elements 11 are made of a so-called wide bandgap semiconductor such as SiC or GaN. The semiconductor elements 11 are MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). In each conductor plate 21 in the submodule 1, five semiconductor elements 11 are connected in parallel along the Y-axis direction. Note that the semiconductor elements 11 may be, in addition to MOSFETs, diodes, IGBTs (Insulated Gate Bipolar Transistors), reverse-conducting IGBTs (RC-IGBTs), or the like.

[0017] A control pad (for example, a gate electrode) (not shown) is provided on each semiconductor element 11. When a gate signal is input from the control pad, the on / off of each semiconductor element 11 is controlled.

[0018] The control pad of the semiconductor element 11 may include not only a gate electrode (gate pad) to which a gate drive voltage is applied for controlling the on / off of the semiconductor element 11, but also, for example, a current sense pad, a Kelvin source pad, or a temperature sense diode pad, although not shown.

[0019] The current sense pad is a control pad for detecting the current flowing in the cell region of the semiconductor element 11. Specifically, the current sense pad is a control pad electrically connected to a part of the cell region so that when a current flows in the cell region of the semiconductor element 11, a current that is one-several to one-tens-of-thousandth of the current flowing in the entire cell region flows.

[0020] The Kelvin source pad is a control pad to which a gate drive voltage for controlling the on / off of the semiconductor element 11 is applied.

[0021] The temperature sensing diode pad is a control pad electrically connected to the anode and cathode of a temperature sensing diode (not shown) provided in the semiconductor element 11. The temperature of the semiconductor element 11 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode provided in the cell region.

[0022] The four signal terminals 23 are formed in an L-shape in side view and are arranged on the other end sides (Y direction) of the two conductor plates 21. Of the four signal terminals 23, the two central signal terminals 23 are formed integrally with the lead frame 21a. One end of each of the four signal terminals 23 is electrically connected to the control pads of the ten semiconductor elements 11. By inputting a control signal to the signal terminals 23 from the outside, the ten semiconductor elements 11 are controlled simultaneously. The other end of each of the four signal terminals 23 is bent so as to extend upward (Z direction).

[0023] 2, the two conductive plates 21, the ten semiconductor elements 11, and the two current-carrying electrodes 22 are sealed with a first sealing material 24. The other ends of the four signal terminals 23 protrude and are exposed from the side surface of the first sealing material 24 in the Y direction.

[0024] <Configuration of semiconductor device> Next, the configuration of the semiconductor device will be described with reference to Fig. 3, which is a cross-sectional view of the semiconductor device according to the first embodiment.

[0025] 3, the semiconductor device includes two submodules 1, an insulating substrate 31, a cooler 32, a case 33, a case lid 37, a second sealing material 34, two connecting members 35, and a control board 36. The semiconductor device is a functional semiconductor device including a plurality of semiconductor elements 11, and specifically, forms a circuit such as an inverter or converter, and further has a control function or a protection function.

[0026] The insulating substrate 31 is bonded to the lower surface (the surface in the -Z direction) of the submodule 1 via the second bonding material 12. The insulating substrate 31 is further bonded to the upper surface (the surface in the Z direction) of the cooler 32.

[0027] The insulating substrate 31 includes an insulating layer 31a, a lower surface pattern 31b, and a circuit pattern 31c. The circuit pattern 31c is provided on the upper surface (surface in the Z direction) of the insulating layer 31a, and the lower surface pattern 31b is provided on the lower surface (surface in the -Z direction) of the insulating layer 31a. The circuit pattern 31c is divided into multiple parts.

[0028] The circuit pattern 31c is made mainly of, for example, Cu, and the insulating layer 31a is made mainly of, for example, ceramic such as silicon nitride, aluminum oxide, or aluminum nitride.

[0029] When expensive SiC is used for semiconductor element 11, silicon nitride is often used as the main material for insulating layer 31a to improve cooling performance. A bottom surface pattern 31b for bonding to cooler 32 is further provided on the cooler 32 side (-Z direction) of insulating substrate 31, and is made mainly of Cu, similar to circuit pattern 31c.

[0030] The cooler 32 is, for example, a pin fin with water-cooling pins on the cooling surface, and is made mainly of Cu, with at least the surface of the cooling surface being coated mainly with Ni. The top view area of ​​the cooler 32 is larger than the top view area of ​​the insulating substrate 31, and the insulating substrate 31 is bonded to the mounting surface (surface in the Z direction) of the insulating substrate 31 in the cooler 32, i.e., the area excluding the peripheral edge portion of the cooler 32.

[0031] A case 33 that surrounds the insulating substrate 31 and the submodule 1 is joined to the peripheral edge of the mounting surface (surface in the Z direction) of the insulating substrate 31 in the cooler 32. The case 33 is formed in a rectangular frame shape when viewed from above, and the area surrounded by the case 33 is filled with a second sealing material 34. Specifically, the area surrounded by the case 33 is the area surrounded by the case 33 and the cooler 32. In addition, a case lid 37 is attached to the upper end (end in the Z direction) of the case 33 so as to be detachable from the case 33.

[0032] The two connection members 35 are connected to the four current-carrying electrodes 22 of the two submodules 1. To explain this, holes 24a extending to the sides of the current-carrying electrodes 22 are formed in the left and right side surfaces (side surfaces in the X-axis direction) of each submodule 1. Holes 24a are also formed between the two current-carrying electrodes 22 of each submodule 1. Each connection member 35 electrically connects the two current-carrying electrodes 22 of each submodule 1 to the circuit pattern 31c via the holes 24a.

[0033] The second sealing material 34 seals the insulating substrate 31 and the submodule 1 except for at least the top surface (surface in the Z direction). The second sealing material 34 is filled up to near the top end (end in the Z direction) of the submodule 1. Therefore, the top end of the submodule 1 is exposed from the second sealing material 34.

[0034] A step 38 that protrudes inward is provided around the entire periphery of the inner peripheral wall 33a of the case 33. The step 38 is provided below (in the -Z direction) the center in the height direction (Z-axis direction) of the case 33. In the region surrounded by the case 33, the area of ​​the portion above the step 38 (in the Z direction) is larger than the area of ​​the portion below the step 38 (in the -Z direction) in top view.

[0035] This allows the rate at which the second sealing material 34 rises after being filled above the circuit pattern 31c of the insulating substrate 31 (in the Z direction) in the process of filling the second sealing material 34 to slow down, thereby more reliably exposing the upper surface (surface in the Z direction) of the submodule 1 from the second sealing material 34.

[0036] The eight signal terminals 23 provided on the two sub-modules 1 are connected to the control board 36. One end of each signal terminal 23 is a press-fit terminal, and one end of each of the eight signal terminals 23 is inserted into eight holes (not shown) formed in the control board 36, thereby electrically connecting the eight signal terminals 23 and the control board 36.

[0037] The control board 36 is disposed above the submodule 1 (in the Z direction). More specifically, the control board 36 is disposed at the upper end (end in the Z direction) of the case 33 and above the case lid 37 (in the Z direction). The control board 36 is electrically connected to the ten semiconductor elements 5 via the four signal terminals 23 of each submodule 1, and controls the ten semiconductor elements 5.

[0038] <Method of manufacturing a semiconductor device> Next, a brief description will be given of a method for manufacturing the semiconductor device and a method for manufacturing another semiconductor device using the extracted submodule 1. First, a description will be given of a method for manufacturing the semiconductor device.

[0039] First, a submodule 1 is prepared in which a semiconductor element 11 is mounted on the upper surface (surface in the Z direction) of a conductor plate 21 via a first bonding material 13, and the conductor plate 21 and the semiconductor element 11 are sealed with a first sealing material 24. Next, the lower surface (surface in the -Z direction) of the submodule 1 is bonded to an insulating substrate 31 with a second bonding material 12, a case 33 is placed so as to surround the periphery of the insulating substrate 31 and the submodule 1, and the area surrounded by the case 33 is sealed with a second sealing material 34 so that at least the upper surface of the submodule 1 is exposed.

[0040] After filling with second sealing material 34, case lid 37 is attached to case 33, and one end of signal terminal 23 is exposed from case lid 37 and connected to control board 36. It is desirable that case lid 37 be attached to case 33 in a way that allows it to be easily removed in the removal process, and it is fixed to case 33, for example, by bonding with an adhesive or by fitting into case 33. With the above steps, the semiconductor device is completed.

[0041] Next, a method for manufacturing another semiconductor device using the extracted submodule 1 will be described. First, in the semiconductor device described above, the submodule 1 is extracted from the second encapsulant 34. It is desirable to use a material whose Young's modulus of the second encapsulant 34 is lower than that of the first encapsulant 24. For example, if the first encapsulant 24 is made of epoxy resin, it is desirable to use a material whose Young's modulus is lower than that of the first encapsulant 24. For example, if the first encapsulant 24 is made of epoxy resin, it is desirable to use a material whose second encapsulant 34 is made of gel or rubber. This allows the submodule 1 to be easily separated and extracted from the second encapsulant 34.

[0042] Here, since the width of the signal terminal 23 is usually smaller than the width of the current-carrying electrode 22, even if the other end side of the signal terminal 23 is buried in the second sealing material 34, it is unlikely to be an obstacle when removing the submodule 1.

[0043] Furthermore, it is desirable that the melting point of the first bonding material 13 that bonds the conductor plate 21 and the semiconductor element 11 is higher than the melting point of the second bonding material 12 that bonds the submodule 1 and the circuit pattern 31c of the insulating substrate 31. For example, it is desirable that the first bonding material 13 is a sintered bonding material containing Ag or Cu as a main material, and the second bonding material 12 is a solder material containing Sn as a main material. Even when the second bonding material 12, which is a solder material, is melted by heat treatment at about 200°C to 300°C and the submodule 1 is removed, the first bonding material 13, which is a sintered bonding material inside the submodule 1, does not reach its melting point and can therefore be removed stably.

[0044] The bottom surface (the surface in the -Z direction) of the extracted submodule 1 and another insulating substrate 31 are bonded with a second bonding material 12 different from the second bonding material 12, and another case 33 is placed to surround the other insulating substrate 31 and the submodule 1, and the area surrounded by the other case 33 is sealed with a second sealing material 34 different from the second sealing material 34 so that at least the top surface of the submodule 1 is exposed. Through the above steps, another semiconductor device using the extracted submodule 1 is completed.

[0045] Although not explained above, an inspection process is carried out on the extracted submodule 1 to prove that it can be reused. The inspection process may include, for example, electrical testing of the semiconductor elements 11, comparison and verification with data at the time of initial shipment, electrical screening tests, mechanical verification such as ultrasonic flaw detection tests, or visual inspection of the submodule 1, and any combination or all of these are carried out to guarantee the quality of the submodule 1 as a reused product depending on the application.

[0046] Furthermore, when the conductor plate 21 and the insulating substrate 31 are joined with a solder material, an intermetallic compound layer made of Sn may remain on the solder-removed surface of the conductor plate 21. Therefore, a regeneration process is carried out to obtain an appropriate bonding interface in the process of mounting the inverter again, such as by performing a mechanical removal process to remove the intermetallic compound layer or by performing an Sn plating process to return the surface to a state that can be remounted. In the process of mounting the inverter again, solder bonding may be performed as in the first case, or if there is no plan to reuse it further, a high-melting point bonding method such as sinter bonding may be used.

[0047] The current-carrying electrodes 22 can be bonded by ultrasonic bonding of wire or ribbon as wiring material, which is removed, for example, by a pulling process when removing the submodule 1. If any residue remains, it is desirable to polish it so that it does not affect the next bonding. Alternatively, if the residue is sufficiently small, polishing can be omitted and the remounted wiring material can be connected while avoiding the residue and any deformation caused by ultrasonic bonding, making it even easier to reuse the submodule 1.

[0048] <Modification of the First Embodiment> Next, a description will be given of a modified example of the first embodiment. Fig. 4 is a cross-sectional view of a semiconductor device according to a modified example of the first embodiment.

[0049] As shown in Figure 4, in a modified example of embodiment 1, the current-carrying electrode 22 is exposed on the upper surface (Z-direction surface) of the submodule 1, and the semiconductor device further includes two connection members 35A instead of two connection members 35.

[0050] In the submodule 1 on the left side (-X direction) of FIG. 4, one end portion of the connection member 35A is connected to the upper surface (surface in the Z direction) of the current-carrying electrode 22. Meanwhile, the other end portion of the connection member 35A is connected to the circuit pattern 31c. In the submodule 1 on the right side (X direction) of FIG. 4, the central portion of the connection member 35A in the longitudinal direction is connected to the upper surface (surface in the Z direction) of the current-carrying electrode 22. Meanwhile, one end portion and the other end portion of the connection member 35A are connected to the circuit pattern 31c. In this way, each connection member 35A electrically connects the two current-carrying electrodes 22 in each submodule 1 to the circuit pattern 31c.

[0051] At this time, a central portion of the connection member 35A in the longitudinal direction is exposed from the second sealing material 34. In this case, the insulation distance can be made longer, and therefore, even if the second sealing material 34 partially exposes the submodule 1, insulation can be easily and reliably ensured.

[0052] 3, in which the connecting member 35A is not used, the current-carrying electrode 22 is taken out from the side surface of the submodule 1, which shortens the distance between the current-carrying electrode 22 and the circuit pattern 31c, making it difficult to adjust the amount of filling with the second sealing material 34 to insulate them. However, when the connecting member 35A is used, the filling with the second sealing material 34 can be stopped at any height position (position in the Z-axis direction) on the side surface of the submodule 1, making it possible to easily and reliably ensure insulation.

[0053] The connecting member 35A may form a loop shape on the upper surface (surface in the Z direction) of the submodule 1. This allows a hanging handle to be inserted into this loop shape to apply a lifting force when removing the submodule 1.

[0054] <Actions and Effects> When reusing an inverter using the submodule 1, the cooler 32, the second bonding material 12, the case 33, and the control terminals (not shown) attached to the case 33 are renewed, and only the submodule 1 is reused to form the inverter. For this reason, it is desirable that the submodule 1 be easily removable from the inverter, reattachable, highly reliable, and easily inspectable.

[0055] In particular, automotive inverters, for which demand has been expanding in recent years, are often highly integrated and miniaturized, with pin fins and cooling structures integrated into the semiconductor device, making it difficult to repair any damage that occurs when reusing the inverter.If the submodule 1 can be easily removed, inspected, and its reliability can be guaranteed, it can be reused in the inverter as if it were new.

[0056] The semiconductor device according to the first embodiment and its modified example includes a submodule 1 in which a conductor plate 21 and a semiconductor element 11 mounted on the upper surface (Z-direction surface) of the conductor plate 21 via a first bonding material 13 are sealed with a first sealing material 24, an insulating substrate 31 bonded to the lower surface of the submodule 1 via a second bonding material 12, a case 33 surrounding the insulating substrate 31 and the submodule 1, and a second sealing material 34 sealing the area surrounded by the case 33 so that at least the upper surface of the submodule 1 is exposed.

[0057] Therefore, the submodule 1 is not completely covered with the second sealing material 34, and at least the top surface (the surface in the Z direction) of the submodule 1 is exposed, so that the submodule 1 can be easily removed from the semiconductor device without melting the second sealing material 34. This allows the submodule 1 to be reused. As a result, the environmental impact can be reduced at each stage in the product life cycle.

[0058] The most expensive component in a semiconductor device is the semiconductor element 11, and the manufacturing cost of the semiconductor element 11 made of a SiC wide bandgap semiconductor is particularly high, and the cost difference with other components is large, so there is great value in reusing it. In addition, because multiple semiconductor elements 11 are integrated into one submodule 1, the submodule 1, which is an integrated unit, can be removed and reattached, allowing the semiconductor elements 11, which have a high unit price, to be efficiently reused.

[0059] Furthermore, the cooler 32 and case 33 that constitute the outer periphery of the semiconductor device are subject to deterioration, deformation, and damage during the process of mounting the semiconductor device on the inverter and removing it from the inverter, but the submodule 1 contained within the semiconductor device is not affected by these factors and is therefore suitable for reuse. The submodule 1 is easier to handle than the semiconductor element 11 alone, and electrical testing can be carried out under strict thermal and electrical conditions, so the test time required for reassurance can be minimized.

[0060] The semiconductor device further includes a current-carrying electrode 22 connected to the semiconductor element 11, and connection members 35, 35A connecting the current-carrying electrode 22 to the circuit pattern 31c of the insulating substrate 31, and portions of the connection members 35, 35A are exposed from the second sealing material 34.

[0061] Therefore, a worker can remove the submodule 1 from the semiconductor device by grasping the connecting members 35, 35A. In addition, the connecting members 35, 35A can increase the insulation distance between the circuit pattern 31c and the current-carrying electrodes 22, so that insulation can be easily and reliably ensured.

[0062] Furthermore, since the connecting member 35A forms a loop on the upper surface (surface in the Z direction) of the submodule 1, the submodule 1 can be easily removed from the semiconductor device by inserting a hanging handle into the loop.

[0063] Furthermore, the Young's modulus of the second sealing material 34 is lower than that of the first sealing material 24. Specifically, the first sealing material 24 is made of an epoxy resin, and the second sealing material 34 is made of a gel or rubber. Therefore, the submodule 1 can be easily separated and taken out from the second sealing material 34.

[0064] Furthermore, sinter bonding has a longer thermal cycle life than solder bonding, and epoxy resin sealing prevents moisture penetration and suppresses humidity deterioration of semiconductor element 11 compared to gel sealing, making it easier to extend the life of the semiconductor device, but using sinter bonding and epoxy resin sealing for the entire semiconductor device complicates the assembly process and increases the size of the manufacturing equipment, resulting in higher manufacturing costs. In embodiment 1, sinter bonding and epoxy resin sealing are not used in the manufacture of submodule 1, making it easier to share the same product with other types of devices without increasing the size of the manufacturing equipment, and reducing the manufacturing costs of the semiconductor device.

[0065] Furthermore, by not completely covering the upper surface (surface in the Z direction) of the submodule 1 with the second sealing material 34, but rather exposing at least the upper surface of the submodule 1 from the second sealing material 34, the insulation around the semiconductor element 11 is ensured by the first sealing material 24, and the submodule 1 can be easily removed from the semiconductor device without melting the first sealing material 24.

[0066] Furthermore, although a portion of the connection members 35, 35A is exposed from the second sealing material 34, the connection members 35, 35A are at the same potential as the top electrode (source electrode) of the semiconductor element 11, and the signal terminal 23 also has the source potential, so insulation problems are unlikely to occur even if they are exposed from the second sealing material 34. In order to miniaturize the semiconductor device, it is necessary to design the insulation distances as short as possible between the cooler 32 and the circuit pattern 31c, between the circuit pattern 31c, and between the cooler 32 and the connection members 35, 35A. Therefore, it is desirable to ensure insulation by covering these with the second sealing material 34.

[0067] Furthermore, the melting point of the first bonding material 13 is higher than the melting point of the second bonding material 12. Specifically, the first bonding material 13 is a sintered bonding material, and the second bonding material 12 is a solder material. Therefore, when the second bonding material 12 is melted and the submodule 1 is removed, deformation and deterioration inside the submodule 1 can be suppressed.

[0068] In addition, a step 38 protruding inward is provided on the inner wall 33a of the case 33, and the top view area of ​​the portion above the step 38 (in the Z direction) in the area surrounded by the case 33 is larger than the top view area of ​​the portion below the step 38 (in the -Z direction), and an insulating substrate 31 is arranged in the portion below the step 38 (in the -Z direction) in the area surrounded by the case 33.

[0069] Therefore, in the process of filling the second sealing material 34, after filling the second sealing material 34 up to above the circuit pattern 31c of the insulating substrate 31 (in the Z direction), the rate at which the second sealing material 34 rises in volume can be slowed down, thereby more reliably exposing the upper surface (surface in the Z direction) of the submodule 1.

[0070] <Embodiment 2> Next, a semiconductor device according to embodiment 2 will be described. Fig. 5 is a perspective view of a submodule 1A included in the semiconductor device according to embodiment 2. Note that in embodiment 2, the same components as those described in embodiment 1 are denoted by the same reference numerals and description thereof will be omitted.

[0071] 5, in the second embodiment, the submodule 1A is provided with four signal terminals 23A instead of the four signal terminals 23. Each signal terminal 23A is formed in a cylindrical shape with a hole (not shown). Each signal terminal 23A is sealed with a first sealing material 24 so that a part of the upper surface (surface in the Z direction) of each signal terminal 23A is exposed on the upper surface (surface in the Z direction) of the submodule 1A.

[0072] The semiconductor device also has eight external signal terminals 40 with press-fit terminals at both ends, and in each submodule 1A, one end of each of the four external signal terminals 40 is inserted into holes (not shown) in the four signal terminals 23A, respectively, and the other ends of the four external signal terminals 40 are inserted into four holes (not shown) formed in the control board 36 (see FIG. 3), respectively, thereby electrically connecting the four signal terminals 23A and the control board 36 via the four external signal terminals 40. Note that only one external signal terminal 40 is shown in FIG. 5. When the submodule 1A is removed, the external signal terminal 40 inserted into the hole in the signal terminal 23A is pulled out, and when the submodule 1A is remounted, a new external signal terminal 40 is used.

[0073] <Actions and Effects> The semiconductor device of embodiment 2 further includes a control board 36 that is arranged above the submodule 1A (in the Z direction) and controls the semiconductor element 11, and a signal terminal 23A that connects the semiconductor element 11 and the control board 36, and a portion of the signal terminal 23A is sealed with a first sealing material 24 so as to be exposed on the upper surface (the surface in the Z direction) of the submodule 1A.

[0074] Therefore, the insulation between the signal terminals 23A and the circuit pattern 31c is ensured, and the ease of removal of the submodule 1A is also ensured.

[0075] The semiconductor device further includes an external signal terminal 40 that connects the control board 36 and the signal terminal 23A, and the signal terminal 23A is formed in a cylindrical shape having a hole into which one end of the external signal terminal 40 is inserted.

[0076] This ensures ease of removal of the external signal terminals 40. In particular, if both ends of the external signal terminals 40 are press-fit terminals, even if the external signal terminals 40 are deformed when the submodule 1A is removed, they can be easily replaced with new external signal terminals 40.

[0077] <Third Embodiment> Next, a semiconductor device according to embodiment 3 will be described. Fig. 6 is a perspective view of a submodule 1B included in the semiconductor device according to embodiment 3. Note that in embodiment 3, the same components as those described in embodiments 1 and 2 are denoted by the same reference numerals and descriptions thereof will be omitted.

[0078] 6, in the third embodiment, the submodule 1B is provided with four signal terminals 23B instead of the four signal terminals 23. Each signal terminal 23B is formed in a rectangular pillar shape without a hole, and is sealed with a first sealing material 24 so that a part of the upper surface (surface in the Z direction) of each signal terminal 23B is exposed on the upper surface (surface in the Z direction) of the submodule 1B.

[0079] Although not shown, eight second signal terminals are provided on the case 33 (see FIG. 3), and the eight second signal terminals are connected to the eight signal terminals 23B of the two sub-modules 1B via wires made of Al or Cu. Furthermore, the eight signal terminals 23B are also connected to the control board 36 (see FIG. 3) via wires made of Al or Cu.

[0080] <Actions and Effects> The semiconductor device of embodiment 3 further includes a control board 36 that is arranged above the submodule 1B (in the Z direction) and controls the semiconductor element 11, and a signal terminal 23B that connects the semiconductor element 11 and the control board 36, and a portion of the signal terminal 23B is sealed with a first sealing material 24 so as to be exposed on the upper surface (the surface in the Z direction) of the submodule 1B.

[0081] Therefore, the insulation between the signal terminals 23B and the circuit pattern 31c is ensured, and the ease of removal of the submodule 1B is also ensured.

[0082] Furthermore, by employing the second signal terminal provided on the case 33, even if the second signal terminal is deformed when the submodule 1B is removed, it can be easily replaced with a new second signal terminal.

[0083] <Other variations> The semiconductor device according to the second or third embodiment may be combined with the configuration of the semiconductor device according to the modification of the first embodiment.

[0084] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0085] Various aspects of the present disclosure are summarized below as appendices.

[0086] (Appendix 1) a submodule in which a conductor plate and a semiconductor element mounted on an upper surface of the conductor plate via a first bonding material are sealed with a first sealing material; an insulating substrate bonded to the lower surface of the submodule via a second bonding material; a case surrounding the insulating substrate and the submodule; a second sealing material that seals the area surrounded by the case so that at least the top surface of the sub-module is exposed; and A semiconductor device comprising:

[0087] (Appendix 2) a current-carrying electrode connected to the semiconductor element; and a connection member connecting the current-carrying electrode and the circuit pattern of the insulating substrate, 2. The semiconductor device according to claim 1, wherein a portion of the connection member is exposed from the second sealing material.

[0088] (Appendix 3) 3. The semiconductor device according to claim 2, wherein the connecting member forms a loop shape on an upper surface of the submodule.

[0089] (Appendix 4) a control board disposed above the submodule and controlling the semiconductor device; and a signal terminal connecting the semiconductor device and the control board, 4. The semiconductor device according to claim 1, wherein a portion of the signal terminal is sealed with the first sealing material so as to be exposed on an upper surface of the submodule.

[0090] (Appendix 5) an external signal terminal for connecting the control board and the signal terminal; 5. The semiconductor device according to claim 4, wherein the signal terminal is formed in a cylindrical shape having a hole into which one end of the external signal terminal is inserted.

[0091] (Appendix 6) 6. The semiconductor device according to claim 1, wherein the second encapsulant has a lower Young's modulus than the first encapsulant.

[0092] (Appendix 7) 7. The semiconductor device according to claim 1, wherein the first sealing material is made of an epoxy resin, and the second sealing material is made of a gel or rubber.

[0093] (Appendix 8) 8. The semiconductor device according to claim 1, wherein the melting point of the first bonding material is higher than the melting point of the second bonding material.

[0094] (Appendix 9) 9. The semiconductor device according to claim 1, wherein the first bonding material is a sintered bonding material, and the second bonding material is a solder material.

[0095] (Appendix 10) The inner peripheral wall of the case is provided with a step that protrudes inward, a top view area of ​​a portion above the step in a region surrounded by the case is larger than a top view area of ​​a portion below the step, 10. The semiconductor device according to claim 1, wherein the insulating substrate is disposed below the step in the area surrounded by the case.

[0096] (Appendix 11) (a) preparing a submodule in which a semiconductor element is mounted on an upper surface of a conductor plate via a first bonding material and the conductor plate and the semiconductor element are sealed with a first sealing material; (b) joining the bottom surface of the submodule and the insulating substrate with a second bonding material, arranging a case so as to surround the insulating substrate and the submodule, and sealing the area surrounded by the case with a second sealing material so that at least the top surface of the submodule is exposed; A method for manufacturing a semiconductor device, comprising:

[0097] (Appendix 12) A method for manufacturing another semiconductor device using the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 10, (c) removing the sub-module from the second encapsulant; (d) joining the bottom surface of the extracted submodule and an insulating substrate different from the insulating substrate with a second bonding material different from the second bonding material, arranging a case different from the case so as to surround the other insulating substrate and the submodule, and sealing the area surrounded by the other case with a second sealing material different from the second sealing material so that at least the top surface of the submodule is exposed; A method for manufacturing a semiconductor device, comprising: [Explanation of symbols]

[0098] 1, 1A, 1B submodule, 11 semiconductor element, 12 second bonding material, 13 first bonding material, 21 conductive plate, 22 current-carrying electrode, 23, 23A, 23B signal terminal, 24 first sealing material, 31 insulating substrate, 31c circuit pattern, 33 case, 33a inner peripheral wall, 38 step, 34 second sealing material, 35, 35A connecting member, 36 control board, 40 external connection terminal.

Claims

1. a sub-module in which a conductor plate and a semiconductor element mounted on an upper surface of the conductor plate via a first bonding material are sealed with a first sealing material; an insulating substrate bonded to the lower surface of the submodule via a second bonding material; a case surrounding the insulating substrate and the submodule; a second sealing material that seals the area surrounded by the case so that at least the top surface of the sub-module is exposed; and a current-carrying electrode connected to the semiconductor element; and a connection member connecting the current-carrying electrode and the circuit pattern of the insulating substrate; Equipped with a portion of the connection member is exposed from the second sealing material; The connecting member forms a loop on the upper surface of the submodule.

2. a control board disposed above the submodule and controlling the semiconductor device; and a signal terminal connecting the semiconductor device and the control board, 2. The semiconductor device according to claim 1, wherein a portion of said signal terminal is sealed with said first sealing material so as to be exposed on an upper surface of said submodule.

3. an external signal terminal for connecting the control board and the signal terminal; 3. The semiconductor device according to claim 2, wherein said signal terminal is formed in a cylindrical shape having a hole into which one end of said external signal terminal is inserted.

4. 2. The semiconductor device according to claim 1, wherein the second encapsulant has a Young's modulus lower than that of the first encapsulant.

5. 2. The semiconductor device according to claim 1, wherein said first sealing material is made of an epoxy resin, and said second sealing material is made of a gel or rubber.

6. The semiconductor device according to claim 1 , wherein the melting point of said first bonding material is higher than the melting point of said second bonding material.

7. 2. The semiconductor device according to claim 1, wherein said first bonding material is a sintered bonding material, and said second bonding material is a solder material.

8. The inner peripheral wall of the case is provided with a step that protrudes inward, a top view area of ​​a portion above the step in a region surrounded by the case is larger than a top view area of ​​a portion below the step, The semiconductor device according to claim 1 , wherein the insulating substrate is disposed below the step in the region surrounded by the case.

9. A submodule in which a conductor plate and a semiconductor element mounted on an upper surface of the conductor plate via a first bonding material are sealed with a first sealing material; an insulating substrate bonded to the lower surface of the submodule via a second bonding material; a case surrounding the insulating substrate and the submodule; a second sealing material that seals the area surrounded by the case so that at least the top surface of the sub-module is exposed; and A method for manufacturing another semiconductor device using a semiconductor device comprising: (c) removing the sub-module from the second encapsulant; (d) joining the bottom surface of the removed submodule to an insulating substrate different from the insulating substrate with a second bonding material different from the second bonding material, arranging a case different from the case so as to surround the other insulating substrate and the submodule, and sealing the area surrounded by the other case with a second sealing material different from the second sealing material so that at least the top surface of the submodule is exposed; A method for manufacturing a semiconductor device, comprising:

10. a current-carrying electrode connected to the semiconductor element; and a connection member connecting the current-carrying electrode and the circuit pattern of the insulating substrate, The method for manufacturing a semiconductor device according to claim 9 , wherein a portion of the connection member is exposed from the second sealing material.

11. The method for manufacturing a semiconductor device according to claim 10 , wherein the connecting member forms a loop shape on the upper surface of the submodule.

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