Processing circuit and information processing device

Abstract

At each cycle time, a fetch circuit (110) fetches an instruction at the cycle time as a reference instruction and fetches an instruction at the cycle time shifted back in time one or more cycles from the cycle time as a comparison instruction. At each cycle time, a comparison circuit (120) compares the fetched comparison instruction with the reference instruction fetched at a cycle time shifted back in time from the cycle time when the comparison instruction was fetched. At each cycle time, an arithmetic circuit (140) computes the compared reference instruction if the compared reference instruction matches the compared comparison instruction.

Description

[Technical Field]

[0001] The present disclosure relates to fault-tolerant processors. [Background technology]

[0002] Security bypass attacks using fault attacks are becoming a problem. The assumption that a program will work as written breaks down due to the following mechanisms. Mechanism 1: A setup time violation caused by a power or clock glitch causes an instruction skip. Mechanism 2: Data corruption (bit flips) occurs due to photocurrents or eddy currents.

[0003] When a fault attack is launched against a typical processor with a five-stage pipeline, errors such as memory access are likely to occur along the critical path, which is the longest path that takes processing time. In particular, Instruction Fetch (IF) or Memory Access (MEM) are prone to failure. The simplest fault mechanism is an instruction skip due to a fetch error.

[0004] Patent Document 1 discloses the following data processing device. The data processing device includes a first processing device, a second processing device, and a comparison device. The first processing device processes the input data during a first processing period to generate first output data. A second processing unit processes the input data during a second processing period to generate second output data. The comparator compares the first output data with the second output data to determine whether a processing error has occurred. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 4386766 Summary of the Invention [Problem to be solved by the invention]

[0006] The data processing device of Patent Document 1 shifts the processing period to make the processing redundant, and is unable to notice an instruction skip (NOP) caused by a fetch error before processing.

[0007] The present disclosure aims to make it possible to notice instruction skips due to fetch errors. [Means for solving the problem]

[0008] The processing circuit of the present disclosure includes: a fetch circuit that fetches, for each cycle time, an instruction at the cycle time as a reference instruction and also fetches, as a comparison instruction, an instruction at a cycle time that is shifted by one or more cycles before the cycle time; a comparison circuit that compares, for each cycle time, a fetched comparison instruction with a reference instruction fetched at a cycle time that is the shift time before the cycle time at which the comparison instruction was fetched; an operation circuit for operating the compared reference instruction when the compared reference instruction matches the compared comparison instruction at each cycle time; Equipped with. [Effects of the Invention]

[0009] According to the present disclosure, it becomes possible to detect an instruction skip caused by a fetch error. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a configuration diagram of a processing circuit 100 according to a first embodiment. [Figure 2] FIG. 2 is a configuration diagram of a fetch circuit 110 according to the first embodiment. [Figure 3] 1 is a diagram showing an example of the configuration of a processing circuit 100 according to a first embodiment. [Figure 4]FIG. 2 is a diagram illustrating an example of a timing chart according to the first embodiment. [Figure 5] FIG. 1 is a diagram illustrating the configuration of a conventional processor. [Figure 6] 3 is a diagram showing the difference in operation between the processing circuit 100 according to the first embodiment and a conventional processor. [Figure 7] FIG. 2 is a diagram showing an example of the processing circuit 100 according to the first embodiment. [Figure 8] FIG. 2 is a diagram showing an example of the processing circuit 100 according to the first embodiment. [Figure 9] FIG. 2 is a diagram showing an example of the processing circuit 100 according to the first embodiment. [Figure 10] FIG. 1 is a configuration diagram of an information processing device 200 according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the embodiments and drawings, the same or corresponding elements are denoted by the same reference numerals. The description of elements denoted by the same reference numerals as those already described will be omitted or simplified as appropriate. Arrows in the drawings primarily indicate the flow of signals, data, or processes.

[0012] Embodiment 1 The processing circuit 100 will be described with reference to FIGS.

[0013] ***Configuration Description*** The configuration of the processing circuit 100 will be described with reference to FIG. The processing circuit 100 is hardware that realizes the execution of any processing. Examples of the processing circuit 100 are a processor and an FPGA. Examples of a processor are a CPU and a GPU. CPU is an abbreviation for Central Processing Unit. GPU is an abbreviation for Graphics Processing Unit. FPGA is an abbreviation for Field Programmable Gate Array.

[0014] The processing circuit 100 includes a fetch circuit 110 , a comparison circuit 120 , a decode circuit 130 , an arithmetic circuit 140 , and a bus control circuit 150 . The processing circuit 100 features a fetch circuit 110 and a compare circuit 120 .

[0015] The fetch circuit 110 is a circuit that fetches, for each cycle time, an instruction at that cycle time as a reference instruction, and also fetches an instruction at a cycle time that is shifted by one or more cycles before that cycle time as a comparison instruction. The cycle time corresponds to the time at which the clock signal occurs. The shift time is a time corresponding to a predetermined number of cycles. The instruction at the cycle time is an instruction stored in a memory area specified by the program counter value (address) at the cycle time.

[0016] The comparison circuit 120 is a circuit that compares, for each cycle time, a fetched comparison instruction with a reference instruction fetched at a cycle time that is the shift time before the cycle time at which the comparison instruction was fetched. The comparison circuit 120 outputs an alert signal when the compared reference command does not match the compared comparison command.

[0017] The decode circuit 130 is a circuit that decodes the compared reference instruction when the compared reference instruction matches the compared comparison instruction.

[0018] The arithmetic circuit 140 is a circuit that performs an arithmetic operation on the compared reference instruction (decoded reference instruction) when the compared reference instruction matches the compared comparison instruction at each cycle time.

[0019] The bus control circuit 150 is a circuit that controls the bus of the processing circuit 100.

[0020] In the first embodiment, the processing circuit 100 functions as follows. The fetch circuit 110 fetches, for each cycle time, two or more comparison instructions corresponding to two or more different stagger times.

[0021] The comparison circuit 120 compares, at each cycle time, two or more fetched comparison instructions with a reference instruction fetched at a cycle time that is the shift time before the cycle time at which each of the two or more comparison instructions was fetched. The decode circuit 130 decodes the compared reference instruction every cycle time if the compared reference instruction matches two or more of the compared comparison instructions. The calculation circuit 140 calculates the compared reference instruction (decoded reference instruction) at each cycle time when the compared reference instruction matches two or more compared instructions.

[0022] At each cycle time, when the compared reference instruction does not match at least one of the two or more compared instructions, the comparison circuit 120 selects an instruction to be operated by a majority vote between the compared reference instruction and the two or more compared instructions. The decode circuit 130 decodes the instruction selected by majority vote at each cycle time if the compared reference instruction does not match at least one of the compared two or more comparison instructions. At each cycle time, if the compared reference instruction does not match at least one of the two or more compared instructions, the operation circuit 140 operates the instruction (decoded instruction) selected by majority vote.

[0023] The comparison circuit 120 outputs an alert signal when the compared reference instruction does not match at least one of the compared two or more comparison instructions at each cycle time. The output alert signal is input to the bus control circuit 150. When an alert signal is input, the bus control circuit 150 performs bus control for exception handling. For example, the bus control circuit 150 sets a program counter value for exception handling in the program counter.

[0024] The configuration of the fetch circuit 110 will be described with reference to FIG. The fetch circuit 110 includes a program counter group 111 , an instruction memory 112 , and a register group 113 . Fetch circuitry 110 features program counters 111 and registers 113 .

[0025] The program counter group 111 is two or more program counters, each of which stores a program counter value corresponding to each cycle time. One of the program counters in the program counter group 111 is called a main program counter. The main program counter stores a program counter value at each cycle time. The program counter value stored in the main program counter is referred to as the main program counter value. The instruction stored in the memory area specified by the main program counter value is the reference instruction. Each program counter other than the main program counter is called a sub-program counter. The sub-program counter stores the main program counter value at the cycle time that is a shift time before the cycle time for each cycle time. The program counter value stored in the sub-program counter is called a sub-program counter value. The instruction stored in the memory area specified by the subprogram counter value is the comparison instruction.

[0026] The instruction memory 112 is a memory in which two or more instructions are stored in sequence.

[0027] The register group 113 is a plurality of registers, each of which stores one instruction for each cycle time. The register set 113 includes one or more registers for each program counter. One or more registers for the main program counter store one or more reference instructions corresponding to one or more cycle times. The one or more registers for the subprogram counter store one or more comparison instructions corresponding to one or more cycle times.

[0028] FIG. 3 shows an example of the configuration of the fetch circuit 110. The program counter group 111 is made up of three program counters (PC). The register group 113 is made up of six registers (FR). The register group 113 includes a program counter PC t Three registers for t ~FR3 t ) The register group 113 includes a program counter PC t-1 Two registers for t-1 , FR2 t-1 ) The register group 113 includes a program counter PC t-2 One register (FR1 t-2 )

[0029] The decode circuit 130 includes an instruction decoder 131 and a register 132 (DR).

[0030] In Figure 3, "IF" stands for Instruction Fetch. Also, "ID" stands for Instruction Decode. Also, "EX" stands for Execution.

[0031] ***Explanation of Operation*** The procedure of operation of the processing circuit 100 corresponds to a fault-tolerant processing method.

[0032] Based on FIG. 3, the fault tolerance processing method will be explained. Program counter PC tis the main program counter, and the program counter (PC t-1 , PC t-2 ) is the subprogram counter. Program counter PC t-1 The shift time is set to the time equivalent to one cycle. Program counter PC t-2 The shift time is set to a time equivalent to two cycles.

[0033] At each cycle time t, the processing circuit 100 operates as follows. Program counter PC t-2 is the program counter PC t-1 The program counter value V stored in t-2 The program counter value V t-2 is the program counter PC two cycles ago. t is the program counter value. Register FR1 t-2 is the program counter value V t-2 This register stores the instruction for the memory area specified by FR1. t-2 The instruction stored in the t-2 It is called. Comparison instruction I1 t-2 is the value of register FR1 at cycle time t. t-2 This is the instruction fetched in

[0034] Register FR2 t-1 register FR1 t-1 Stores the instruction stored in register FR2. t-1 The instruction stored in is compared with the instruction I2 t-1 It is called. Comparison instruction I2 t-1 is set to register FR1 one cycle before cycle time t. t-1 This is the instruction fetched in Program counter PC t-1 is the program counter PC t The program counter value V stored in t-1 The program counter value Vt-1 is the program counter PC from one cycle ago. t is the program counter value. Register FR1 t-1 is the program counter value V t-1 The instruction for the memory area specified by is stored.

[0035] Register FR3 t register FR2 t Stores the instruction stored in register FR3. t The command stored in the standard command I3 t It is called. Standard instruction I3 t is set to register FR1 two cycles before cycle time t. t This is the instruction fetched in Register FR2 t register FR1 t The instruction stored in the The bus control circuit 150 calculates the program counter value V at cycle time t. t Program Counter PC t Set to. Program counter PC t is the program counter value V t Remember. Register FR1 t is the program counter value V t The instruction for the memory area specified by is stored.

[0036] The comparator circuit 120 is connected to the register FR3. t The standard instruction I3 stored in t to register FR2 t-1 The comparison instruction I2 stored in t-1 and register FR1 t-2 The comparison instruction I1 stored in t-2 Compare with:

[0037] Standard instruction I3 t and comparison instruction I2 t-1 and comparison instruction I1 t-2If all of the above match, processing circuit 100 operates as follows. The comparison circuit 120 compares the reference instruction I3 t The standard instruction I3 output from the comparison circuit 120 t is input to the instruction decoder 131. The instruction decoder 131 receives the basic instruction I3 t Decode the Register 132 contains the decoded standard instruction I3 t Remember. The arithmetic circuit 140 executes the basic instruction I3 stored in the register 132. t Calculates and outputs the calculation result. The calculation result is input to the bus control circuit 150, for example.

[0038] Standard instruction I3 t and comparison instruction I2 t-1 and comparison instruction I1 t-2 If only two of the instructions match, the processing circuit 100 operates as follows. The comparison circuit 120 compares the reference instruction I3 t and comparison instruction I2 t-1 and comparison instruction I1 t-2 The instruction is selected by majority vote and output. The output instruction is called the selected instruction. The instruction decoder 131 decodes the selected instruction. Register 132 stores the decoded selection instruction. The arithmetic circuit 140 performs an operation on the selection instruction stored in the register 132 and outputs the operation result. The comparator circuit 120 also outputs an alert signal, which is input to the bus control circuit 150. The bus control circuit 150 controls the bus for exception handling.

[0039] Standard instruction I3 t and comparison instruction I2 t-1 and comparison instruction I1 t-2 If all of the above do not match, processing circuit 100 operates as follows. The comparator circuit 120 outputs an alert signal, which is input to the bus control circuit 150. The bus control circuit 150 controls the bus for exception handling.

[0040] A specific example of the operation of the processing circuit 100 will be described with reference to FIG. At cycle time t2, register FR1 t-2 stores instruction A and register FR2 t-1 stores instruction A and register FR3 t stores instruction A. That is, register FR1 t-2 and register FR2 t-1 and register FR3 t All instructions in are consistent with instruction A. In this case, instruction A is decoded, stored in register DR, and then executed.

[0041] The fault attack causes an error in the fetch at cycle time t4, and the three registers in the first stage (FR1 t , FR1 t-1 , FR1 t-2 ) are destroyed. At cycle time t4, register FR1 t-2 stores instruction C' and register FR2 t-1 stores instruction C and register FR3 t stores instruction C. That is, register FR1 t-2 The instruction C' is in register FR2 t-1 and register FR3 t does not match instruction C. In this case, instruction C is selected by majority vote, decoded, stored in register DR, and executed. An alert signal is also output. At cycle time t5, register FR1 t-2 stores instruction D and register FR2 t-1 stores instruction D' and register FR3 t has instruction D memorized. That is, register FR2t-1 The instruction D' is in register FR1 t-2 and register FR3 t This does not match instruction D. In this case, instruction D is selected by majority vote, decoded, stored in register DR, and executed. An alert signal is also output. At cycle time t6, register FR1 t-2 stores instruction E, and register FR2 t-1 stores instruction E and register FR3 t stores the instruction E'. That is, register FR3 t The instruction E' is in register FR1 t-2 and register FR2 t-1 does not match instruction E. In this case, instruction E is selected by majority vote, decoded, stored in register DR, and executed. An alert signal is also output.

[0042] ***Comparison with conventional technology*** FIG. 5 shows the configuration of a conventional processor. In a conventional processor, a fetch circuit (IF) includes one program counter PC and one register FR.

[0043] On the other hand, the processing circuit 100 is configured as follows (see FIG. 3). The fetch circuit 110 includes two or more program counters PC and a plurality of registers FR. The fetch circuit 110 has two or more fetch units. In FIG. 3, the first fetch unit is a program counter PC t and instruction memory 112 and three registers (FR1 t , FR2 t , FR3 t The second fetch unit is composed of a program counter PC t-1 and instruction memory 112 and two registers (FR1 t-1 , FR2 t-1 The third fetch unit is composed of the program counter PC t-2and instruction memory 112 and one register FR1 t-2 It is composed of: The fetch circuit 110 has two or more stages of fetch units. In FIG. 3, the first stage fetch unit (IF1) has three registers (FR1 t , FR1 t-1 , FR1 t-2 The second stage fetch (IF2) has two registers (FR2 t , FR2 t-1 The third stage register section (IF3) has one register FR3 t It is equipped with: The fetch circuit 110 further includes a comparison circuit 120 .

[0044] The difference between the operation of a conventional processor and the operation of the processing circuit 100 will be described with reference to FIG. A conventional processor decodes and executes an instruction fetched by a fetch circuit (IF) at each cycle time. The processing circuit 100 fetches two or more instructions in different orders at each cycle time using two or more systems of fetch units (IF1, IF2, IF3). The processing circuit 100 compares two or more instructions fetched at different cycle times (t0, t1, t2) by two or more systems of fetch units for each cycle time, and decodes and performs an operation on the instruction selected by majority vote.

[0045] ***Effects of the First Embodiment*** The first embodiment discloses a processing circuit 100 that is fault tolerant.

[0046] The processing circuit 100 can protect fetches by making the fetches redundant.

[0047] The processing circuit 100 does not simply make the fetch redundant, but fetches two or more different instructions simultaneously. Therefore, it is difficult to cause the processing circuit 100 to skip an instruction by targeting only one instruction, and there is a high possibility that other instructions fetched at the same time will also be erroneously fetched. In the processing circuit 100, the fetch module is not simply reused for time redundancy, but is instead pipelined. Therefore, in order to cause a fault to be introduced into the processing circuit 100 once and destroy an instruction so that the processing circuit 100 does not notice the fault, it is necessary to similarly destroy other instructions that are fetched at the same time. However, it is generally difficult to insert consecutive faults with good control of timing and intensity so as to corrupt other instructions in the same way. Even if other instructions can be corrupted in the same way, new instructions fetched at the same time as the other instructions will likely also be corrupted, allowing the processing circuit 100 to notice the fault. Ultimately, in order to prevent a fault from being detected by the processing circuit 100, it would be necessary to continue to insert faults indefinitely and maintain instruction consistency in the pipelined fetch module, but this is not realistic. Therefore, the processing circuit 100 can notice the fetch fault, i.e., the processing circuit 100 can defend the fetch.

[0048] Additionally, processing circuit 100 is capable of noticing faults targeted at stages other than fetch. If a fault is inserted targeting a stage other than the fetch stage, the fetch stage, which tends to be a critical path, will also be broken. Therefore, by looking at the fetch, you can notice faults in stages other than the fetch.

[0049] ***Example of Embodiment 1*** FIG. 7 shows an example of the configuration of the processing circuit 100. The fetch circuit 110 may have two systems and two stages of fetch units as shown in FIG. In this case, register FR2 t Instruction and register FR1t-1 If the instructions match, the instructions are executed. Also, register FR2 t Instruction and register FR1 t-1 If the instructions do not match, neither instruction is computed and an alert signal is output.

[0050] FIG. 8 shows an example of the configuration of the processing circuit 100. The fetch circuit 110 may have four or more systems and four or more stages of fetch units. In FIG. 8, the fetch circuit 110 has four systems and four stages of fetch units. In this case, register FR4 t Instruction and register FR3 t-1 Instruction and register FR2 t-2 Instruction and register FR1 t-3 If the instructions match, the instructions are executed. Also, register FR4 t Instruction and register FR3 t-1 Instruction and register FR2 t-2 Instruction and register FR1 t-3 If the instructions do not match, the instruction is selected by majority vote, the selected instruction is executed, and an alert signal is output. Also, register FR4 t Instruction and register FR3 t-1 Instruction and register FR2 t-2 Instruction and register FR1 t-3 If all of the instructions are different, then none of the instructions are calculated and an alert signal is output.

[0051] When the fetch circuit 110 has four or more systems of fetch units, the processing circuit 100 may operate as follows. The fetch circuit 110 fetches the reference instruction at each cycle time, and also fetches three or more comparison instructions corresponding to three or more different stagger times. For each cycle time, the comparison circuit 120 randomly selects three or more instructions from the three or more fetched comparison instructions and the reference instruction fetched at a cycle time that is the shift time before the cycle time at which each of the two or more comparison instructions was fetched, and then compares the selected three or more instructions. The decode circuit 130 decodes the compared instructions every cycle time if three or more of the compared instructions match. The arithmetic circuit 140 performs an operation on the compared instructions (decoded instructions) when three or more compared instructions match at each cycle time. If the three or more compared instructions do not match at each cycle time, the comparison circuit 120 selects the instruction to be operated by a majority vote of the three or more compared instructions. At each cycle time, if three or more compared instructions do not match, the decode circuit 130 decodes the instruction selected by majority vote. At each cycle time, if three or more compared instructions do not match, the arithmetic circuit 140 executes the instruction (decoded instruction) selected by majority vote. The comparison circuit 120 outputs an alert signal every cycle time if three or more compared instructions do not match.

[0052] When the fetch circuit 110 has three or more systems of fetch units, the processing circuit 100 may operate as follows. The fetch circuit 110 fetches a reference instruction at each cycle time, and also fetches two or more comparison instructions corresponding to two or more different stagger times. For each cycle time, the comparison circuit 120 randomly selects two instructions from the two or more fetched comparison instructions and the reference instruction fetched at a cycle time that is the shift time before the cycle time at which each of the two or more comparison instructions was fetched, and then compares the two selected instructions. The decode circuit 130 decodes the compared instruction every cycle time if the two compared instructions match. The arithmetic circuit 140 performs an operation on the compared instruction (decoded instruction) at each cycle time if the two compared instructions match. The comparison circuit 120 outputs an alert signal every cycle time if the two compared instructions do not match.

[0053] FIG. 9 shows an example of the configuration of the processing circuit 100. The shift time between the systems does not have to be a time corresponding to one cycle, but may be a time corresponding to two or more cycles. In FIG. 9, the fetch circuit 110 has two systems of fetch units, and the shift time between the systems is a time equivalent to two cycles. In this case, the fetch circuit 110 stores the reference instruction of the cycle time in the register FR1 at each cycle time. t Fetch to. At the same time, the fetch circuit 110 reads the compare instruction at the cycle time two cycles before the cycle time from the register FR1. t-2 Fetch to.

[0054] Even when the shift time between the systems is a time equivalent to two or more cycles, the fetch circuit 110 may have three systems of fetch units, or four or more systems of fetch units.

[0055] FIG. 10 shows an example of the configuration of an information processing device 200 equipped with the processing circuit 100. The processing circuit 100 is mainly mounted on an information processing device 200 for use. The information processing device 200 is a computer that includes hardware such as the processing circuit 100, a memory 201, and an input / output interface 202.

[0056] ***Supplement to the first embodiment*** The first embodiment is an example of a preferred embodiment and is not intended to limit the technical scope of the present disclosure. Each embodiment may be implemented in part or in combination with other embodiments. [Explanation of symbols]

[0057] 100 processing circuit, 110 fetch circuit, 111 program counter group, 112 instruction memory, 113 register group, 120 comparison circuit, 130 decoding circuit, 131 instruction decoder, 132 register, 140 arithmetic circuit, 150 bus control circuit, 200 information processing device, 201 memory, 202 input / output interface.

Claims

1. a fetch circuit that fetches, for each cycle time, an instruction at the cycle time as a reference instruction and also fetches, as a comparison instruction, an instruction at a cycle time that is shifted by one or more cycles before the cycle time; a comparison circuit that compares, for each cycle time, a fetched comparison instruction with a reference instruction fetched at a cycle time that is the shift time before the cycle time at which the comparison instruction was fetched; an operation circuit for operating the compared reference instruction when the compared reference instruction matches the compared comparison instruction at each cycle time; A processing circuit comprising:

2. The comparison circuit outputs an alert signal when the compared reference command does not match the compared comparison command.

2. The processing circuit of claim 1.

3. the fetch circuit fetches, for each cycle time, two or more comparison instructions corresponding to two or more different stagger times; the comparison circuit compares, for each cycle time, two or more fetched comparison instructions with a reference instruction fetched at a cycle time that is the shift time before the cycle time at which each of the two or more comparison instructions was fetched; The calculation circuit calculates the compared reference instruction at each cycle time when the compared reference instruction matches two or more of the compared comparison instructions.

2. The processing circuit of claim 1.

4. The calculation circuit calculates, for each cycle time, an instruction selected by majority vote between the compared reference instruction and the compared two or more compared instructions when the compared reference instruction does not match at least one of the compared two or more compared instructions.

4. The processing circuit of claim 3.

5. The comparison circuit outputs an alert signal at each cycle time when the compared reference instruction does not match at least one of the compared two or more comparison instructions.

4. The processing circuit of claim 3.

6. the fetch circuit fetches the reference instruction and two or more comparison instructions corresponding to two or more different stagger times at each cycle time; the comparison circuit randomly selects two instructions from the two or more fetched comparison instructions and a reference instruction fetched at a cycle time that is the shift time before the cycle time at which each of the two or more comparison instructions is fetched, and compares the two selected instructions; The arithmetic circuit executes the compared instructions when the two compared instructions match at each cycle time.

2. The processing circuit of claim 1.

7. The comparison circuit outputs an alert signal at each cycle time if the two compared instructions do not match.

7. A processing circuit according to claim 6.

8. the fetch circuit fetches the reference instruction and three or more comparison instructions corresponding to three or more different stagger times at each cycle time; the comparison circuit randomly selects, for each cycle time, three or more instructions from among the three or more fetched comparison instructions and a reference instruction fetched at a cycle time that is the shift time before each of the cycle times at which the three or more comparison instructions were fetched, and compares the selected three or more instructions; The calculation circuit calculates the compared instructions when three or more compared instructions match at each cycle time.

2. The processing circuit of claim 1.

9. The arithmetic circuit arithmetically operates an instruction selected by a majority vote of the three or more compared instructions when the three or more compared instructions do not match at each cycle time.

9. A processing circuit according to claim 8.

10. The comparison circuit outputs an alert signal at each cycle time when the three or more compared instructions do not match.

9. A processing circuit according to claim 8.

11. 11. The processing circuit of any one of claims 1 to 10, which is a processor or an FPGA.

12. An information processing device equipped with the processing circuit according to any one of claims 1 to 10.

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