MEMORY SYSTEM AND MEMORY SYSTEM CONTROL METHOD

Abstract

To provide a memory system configured to improve performance, and a control method of the memory system.SOLUTION: A memory system includes a non-volatile memory including first and second sections, a randomly accessible memory, and a controller configured to generate a plurality of messages in accordance with a received command. The messages include a message addressed to the first section and a message addressed to the second section. The controller includes an input port, a first output port connected to the first section, a second output port connected to the second section, and a repeater. The repeater is configured to: write the messages input via the input port to the randomly accessible memory, read the message addressed to the first section from the randomly accessible memory when the first section is ready to receive messages, and output the read message to the first section via the first output port.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a memory system and a method for controlling a memory system. [Background technology]

[0002] A memory system is a system for storing data, and includes a nonvolatile semiconductor memory (hereinafter referred to as nonvolatile memory) and a controller.

[0003] The non-volatile memory includes multiple memory chips.

[0004] The controller is an integrated circuit and includes a processing unit, a repeater, and a plurality of memory controllers.

[0005] The processing unit divides a command received from an external device into multiple requests. The command is information used by the external device to instruct the operation of the memory system. The request is information used by the controller to instruct the operation of the nonvolatile memory. The processing unit transmits the multiple requests to the repeater.

[0006] The relay selects one memory controller from among the multiple memory controllers based on the received request and transmits the received request to the selected memory controller. The relay has the functions of a request receiver and a request transmitter. The relay includes a queue, which is a memory with a first-in first-out (FIFO) structure that stores received requests. Requests written to the queue are read in the order in which they were written. For this reason, even if the memory controller that receives the request written later is in an operable state, the memory controller that receives the request written later has to wait to operate until the memory controller that receives the request written earlier receives the request. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-149619 [Patent Document 2] Japanese Patent Application Publication No. 9-101901 [Patent Document 3] U.S. Patent No. 8,307,074 Summary of the Invention [Problem to be solved by the invention]

[0008] An object of the present invention is to provide a memory system and a control method that can improve performance. [Means for solving the problem]

[0009] According to an embodiment, a memory system includes a non-volatile memory, a randomly accessible memory, and a controller. The non-volatile memory includes a first portion and a second portion. The controller generates a plurality of messages in response to a command received from an external device. The plurality of messages include a message addressed to the first portion and a message addressed to the second portion. The controller includes a first input port to which the plurality of messages is input, a first output port connected to the first portion, a second output port connected to the second portion, and a repeater. The repeater writes the plurality of messages input via the first input port to the randomly accessible memory, and when the first portion becomes capable of receiving messages, reads the messages addressed to the first portion from the randomly accessible memory and outputs the read messages to the first portion via the first output port. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram illustrating an example of an information processing system according to a first embodiment. [Figure 2] 2 is a block diagram showing an example of functional blocks of a CPU in the memory system according to the first embodiment. FIG. [Figure 3] FIG. 2 is a diagram illustrating an example of an empty slot number memory according to the first embodiment. [Figure 4] 2 is a block diagram showing an example of a nonvolatile memory I / F circuit and a nonvolatile memory according to the first embodiment. FIG. [Figure 5] FIG. 4 is a diagram showing an example of a message according to the first embodiment. [Figure 6] FIG. 2 is a block diagram showing an example of an FTL processing unit, a repeater, a shared memory, an empty slot number memory, and a memory I / F circuit according to the first embodiment. [Figure 7] (a) A diagram showing an example of a queue in an empty state according to the first embodiment. (b) A diagram showing an example of a queue in a full state according to the first embodiment. (c) A diagram showing another example of a queue in an empty state according to the first embodiment. (d) A diagram showing another example of a queue in a full state according to the first embodiment. [Figure 8] (a) A diagram showing an example of a queue in an empty state according to the first embodiment. (b) A diagram showing an example of a queue that is neither empty nor full according to the first embodiment. (c) A diagram showing an example of a queue in a full state according to the first embodiment. (d) A diagram showing another example of a queue that is neither empty nor full according to the first embodiment. (e) A diagram showing another example of a queue in an empty state according to the first embodiment. [Figure 9] 10 is a flowchart showing an example of a message copying process from an input queue to a shared memory by a relay controller according to the first embodiment. [Figure 10] (a) A diagram showing an example of a linked list according to the first embodiment at a first timing, (b) A diagram showing an example of a linked list according to the first embodiment at a second timing, and (c) A diagram showing an example of a linked list according to the first embodiment at a third timing. [Figure 11] 10 is a flowchart showing an example of a message copy process from a shared memory to an output queue by a relay controller according to the first embodiment. [Figure 12](a) A diagram showing an example of a linked list according to the first embodiment at a fourth timing, (b) A diagram showing an example of a linked list according to the first embodiment at a fifth timing, and (c) A diagram showing an example of a linked list according to the first embodiment at a sixth timing. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, a description will be given of an embodiment of the invention with reference to the drawings. The following description exemplifies an apparatus and a method for embodying the technical idea. The dimensional relationships and ratios between the drawings may differ. Corresponding elements are given the same reference numerals. Although one element may be given multiple names, these names are merely examples.

[0012] 1 is a block diagram showing an example of an information processing system 1 according to the first embodiment. The information processing system 1 includes a host 10 and a memory system 20.

[0013] The host 10 is an information processing device that transmits various commands to the memory system 20.

[0014] The memory system 20 is a system for storing data. The memory system 20 is also called a solid state drive (SSD). The memory system 20 is provided outside the host 10 and connected to the host 10 via a cable or a network. The memory system 20 may also be built into the host 10. The memory system 20 includes a controller 22, a nonvolatile memory 24, and a volatile memory 26.

[0015] The controller 22 is an integrated circuit such as a system on a chip (SoC), and controls the operations of the nonvolatile memory 24 and the volatile memory 26.

[0016] The nonvolatile memory 24 is, for example, a flash memory. The nonvolatile memory 24 stores data. The nonvolatile memory 24 can retain the stored data even when power is not supplied. The flash memory is, for example, a NAND-type flash memory or a NOR-type flash memory.

[0017] The volatile memory 26 is, for example, a dynamic random access memory (DRAM). The volatile memory 26 stores data. The volatile memory 26 can retain the stored data only while power is being supplied. The volatile memory 26 complies with, for example, the double data rate 3 low voltage (DDR3L) standard. The volatile memory 26 may be provided inside the controller 22. In that case, the volatile memory 26 is, for example, a static random access memory (SRAM).

[0018] Next, the internal configuration of the controller 22 will be described. The controller 22 includes a host interface circuit 32 (also referred to as a host I / F circuit), a nonvolatile memory interface circuit 34 (also referred to as a nonvolatile memory I / F circuit), a volatile memory interface circuit 36 ​​(also referred to as a volatile memory I / F circuit), and a CPU 38. The host I / F circuit 32, the nonvolatile memory I / F circuit 34, the volatile memory I / F circuit 36, and the CPU 38 are connected to one another via a bus line 40. Part of the internal configuration of the controller 22 may be provided outside the controller 22.

[0019] The host I / F circuit 32 supports SATA (Serial ATA), SAS (Serial Attached SCSI), UFS, PCI Express (PCIe) TM , Ethernet TM The host I / F circuit 32 connects the controller 22 and the host 10 so that they can communicate with each other.

[0020] The nonvolatile memory I / F circuit 34 is an interface such as a Toggle NAND flash interface or an Open NAND flash interface (ONFI). The nonvolatile memory I / F circuit 34 communicatively connects the controller 22 and the nonvolatile memory 24. The nonvolatile memory I / F circuit 34 is connected to the nonvolatile memory 24 via multiple channels Ch. Multiple memory chips 44 are connected to each channel Ch. Alternatively, a single memory chip 44 is connected to each channel Ch.

[0021] The volatile memory I / F circuit 36 ​​is an interface with the volatile memory 26. The volatile memory I / F circuit 36 ​​connects the controller 22 and the volatile memory 26 so that they can communicate with each other.

[0022] The CPU 38 is a processor that can execute various commands such as a read command and a write command.

[0023] Next, the internal configuration of the nonvolatile memory 24 will be described. The nonvolatile memory 24 includes multiple memory chips 44. Each memory chip 44 includes a memory cell array. The memory cell array includes multiple blocks. Each block includes multiple pages. A block functions as a processing unit for erasing data. Each page includes multiple memory cells connected to the same word line. A page functions as a processing unit for writing and reading data. Instead of a page, a word line may be used as the processing unit for writing and reading data.

[0024] Next, a description will be given of the functions of the CPU 38. Fig. 2 is a block diagram showing an example of functional blocks of the CPU 38 of the memory system 20 according to the first embodiment. The CPU 38 includes a flash translation layer processing unit 52 (also referred to as an FTL processing unit), a repeater 56 (also referred to as a dispatcher), a shared memory 58, and an empty slot number memory 59.

[0025] The FTL processing unit 52 is a module that performs data management, block management, and command control of the nonvolatile memory 24. The FTL processing unit 52 is connected to the bus line 40. The FTL processing unit 52 divides a received read command into multiple requests and transmits the multiple requests to the relay 56. The requests are information indicating the processing to be executed by the memory chip 44. The requests are also information that the nonvolatile memory I / F circuit 34 transmits to the memory chip 44. Hereinafter, requests are referred to as messages. The FTL processing unit 52 divides a received read command into multiple memory read messages and transmits the multiple memory read messages to the relay 56. The memory read messages are information indicating the processing to be executed by the nonvolatile memory I / F circuit 34 on the memory chip 44.

[0026] The repeater 56 is a message routing module for configuring a message transmission / reception path. The message transmission / reception path is a path for transmitting messages from the FTL processing unit 52 to the nonvolatile memory I / F circuit 34. The repeater 56 has multiple input ports and multiple output ports. The input port is a terminal for receiving messages. The output port is a terminal for transmitting messages. The repeater 56 configures a one-to-multiple message transmission / reception path that transmits a message received by one input port to one of multiple output ports. The repeater 56 writes the message received from the FTL processing unit 52 to the shared memory 58. When the nonvolatile memory I / F circuit 34 is ready to receive the message, the repeater 56 reads the message from the shared memory 58. The repeater 56 transmits the read message to the nonvolatile memory I / F circuit 34 via the bus line 40.

[0027] The shared memory 58 is a randomly accessible memory. The shared memory 58 temporarily stores multiple messages transmitted from the FTL processing unit 52. The shared memory 58 may be disposed in the repeater 56. An area in the shared memory 58 that stores one message is called a slot.

[0028] 3 is a diagram showing an example of an empty slot number memory 59 according to the first embodiment. The empty slot number memory 59 is a memory with a FIFO structure. The empty slot number memory 59 stores empty slot numbers in the shared memory 58. An empty slot number is information indicating an empty slot. An empty slot is a slot in the shared memory 58 that does not store a message. The empty slot number memory 59 may be disposed in the repeater 56.

[0029] FIG. 4 is a block diagram showing an example of the nonvolatile memory I / F circuit 34 and the nonvolatile memory 24 of the memory system 20 according to the first embodiment.

[0030] The nonvolatile memory I / F circuit 34 includes a plurality of memory controllers 35. The memory controllers 35 are connected to a repeater 56 via a bus line 40. The memory controllers 35 receive messages transmitted from the repeater 56. The number of the plurality of memory controllers 35 is equal to the number of memory chips 44. The nonvolatile memory I / F circuit 34 includes, for example, 32 memory controllers 35-0, 35-1, ... 35-31.

[0031] The memory controllers 35 of the nonvolatile memory I / F circuit 34 are connected to the memory chips 44 of the nonvolatile memory 24 via channels Ch. For example, memory controller 35-0 is connected to memory chip 44-0 via channel Ch0. Memory controller 35-1 is connected to memory chip 44-1 via channel Ch1. Memory controller 35-31 is connected to memory chip 44-31 via channel Ch31.

[0032] FIG. 5 is a diagram showing an example of a message according to the first embodiment. A message is multiple bytes of data. For example, a message is 32 bytes of data. Multiple messages generated from one command may indicate processes to be executed by multiple memory chips. Multiple messages generated from one command must be received by the memory controller 35 in the order in which they were generated. A message includes an output port number 62, a message body 64, a link pointer 66, and a command ID 68.

[0033] The output port number 62 is identification information of the output port of the repeater 56 .

[0034] The message body 64 is information indicating the process that the memory controller 35 is to execute on the memory chip 44 .

[0035] The link pointer 66 is information that points to a slot in the shared memory 58. The link pointer 66 indicates the output order of messages that are output from one output port 72.

[0036] The command ID 68 is an identifier of the command. Multiple messages generated from one command have the same command ID 68.

[0037] 6 is a block diagram showing an example of an FTL processing unit 52, a relay 56, a shared memory 58, an empty slot number memory 59, and a non-volatile memory I / F circuit 34 according to the first embodiment. The FTL processing unit 52 includes a message generation unit 74. The relay 56 includes an input port 70, an input queue 76, a relay controller 78, and an output port 72. The non-volatile memory I / F circuit 34 includes a memory controller 35.

[0038] The message generator 74 is a circuit that divides a command into multiple messages. The number of message generators 74 may be one or multiple. For example, if there is one message generator 74, the FTL processing unit 52 includes a message generator 74-0. If there are multiple message generators 74, the FTL processing unit 52 includes message generators 74-0 and 74-1. The message generator 74-0 generates multiple first messages from the received first read command. The message generator 74-1 generates multiple second messages from the received second read command.

[0039] The input port 70 is an input terminal that receives a message. The input port 70 is connected to the message generator 74. The number of input ports 70 is equal to the number of message generators 74. The number of input ports 70 may be one, two, three or more. For example, when there is one message generator 74, the input port 70 is input port 70-0. When there are multiple message generators 74, the input port 70 includes input ports 70-0 and 70-1. The input port 70-0 is connected to the message generator 74-0. The input port 70-1 is connected to the message generator 74-1.

[0040] The input queue 76 is a memory with a FIFO structure and a ring buffer structure. The input queue 76 stores multiple messages input to the input port 70. The number of input queues 76 is equal to the number of input ports 70. The number of input queues 76 may be one, two, three or more. For example, when there is one input port 70, the input queue 76 is input queue 76-0. When there are two input ports 70, the input queues 76 are input queues 76-0 and 76-1. The input queue 76-0 is connected to the input port 70-0 and the relay controller 78. The input queue 76-1 is connected to the input port 70-1 and the relay controller 78.

[0041] The relay controller 78 is a module that manages the copying of messages from the input queue 76 to the shared memory 58 and the copying of messages from the shared memory 58 to the output port 72. The relay controller 78 is connected to the input queue 76, the shared memory 58, and the output port 72. The relay controller 78 reads messages from the input queue 76 and writes the read messages to the shared memory 58. The relay controller 78 reads messages from the shared memory 58 and outputs the read messages from the output port 72. By referencing the command ID 68 of the message read from the shared memory 58, the relay controller 78 can recognize that messages with the same command ID 68 are messages generated from the same read command. The relay controller 78 can continuously output multiple messages generated from one read command to the memory controller 35. The relay controller 78 writes the message Msg to the shared memory 58.

[0042] The output port 72 is an output terminal for messages. The number of output ports 72 is equal to the number of memory chips 44. For example, if the number of memory chips 44 is two, the output ports 72 are output ports 72-0 and 72-1. The output port 72 is connected to the nonvolatile memory I / F circuit 34. The output port 72-0 is connected to the memory controller 35-0. The output port 72-1 is connected to the memory controller 35-1.

[0043] The shared memory 58 stores messages that the shared memory relay controller 78 reads from the input queue 76. The number of slots in the shared memory 58 is the maximum number of messages Msg that the message generator 74 can issue simultaneously. Therefore, when the message generator 74 generates a message Msg, the shared memory 58 always includes an empty slot. The message Msg generated by the message generator 74 is always written to the shared memory 58.

[0044] The empty slot number memory 59 is connected to the relay controller 78 .

[0045] The nonvolatile memory I / F circuit 34 includes memory controllers 35. The number of memory controllers 35 is equal to the number of memory chips 44. For example, if there are two memory chips 44, the nonvolatile memory I / F circuit 34 includes memory controllers 35-0 and 35-1. The memory controller 35-0 is connected to the output port 72-0. The memory controller 35-1 is connected to the output port 72-1.

[0046] The input queue 76 will now be described in more detail.

[0047] The input queue 76 stores multiple messages. A message storage area is called an entry. The input queue 76 includes multiple entries 84. The number of entries 84 is called the queue depth. In the input queue 76, which has a ring buffer structure, the multiple entries 84 are logically connected in a circular fashion. For example, if the queue depth is 4, the input queue 76 includes four entries 84a, 84b, 84c, and 84d. Entry 84b is logically connected to entry 84a, entry 84c is logically connected to entry 84b, entry 84d is logically connected to entry 84c, and entry 84a is logically connected to entry 84d.

[0048] The input queue 76 includes a sender head pointer Hs, a sender tail pointer Ts, a receiver head pointer Hr, and a receiver tail pointer Tr, which are pointers to entries 84 that store messages.

[0049] The sender head pointer Hs is a pointer that points to the entry 84 that was the least recently free entry among the plurality of free entries 84. An entry 84 that does not store a message is called a free entry.

[0050] The sending tail pointer Ts is a pointer that points to the entry 84 that has become the most recently free entry among a plurality of free entries 84 .

[0051] The receiving side head pointer Hr is a pointer that points to the entry 84 to which a message was written most recently among the multiple entries 84 to which a message is written. If all the entries 84 are free entries, the receiving side head pointer Hr points to the entry 84 that became free most recently among the multiple free entries 84. A message is written to the entry 84 pointed to by the receiving side head pointer Hr. A message is read from the entry 84 pointed to by the receiving side head pointer Hr.

[0052] The receiving tail pointer Tr is a pointer that points to the entry 84 that was the most recently empty entry among the plurality of empty entries 84 .

[0053] The entry 84 pointed to by the sending side head pointer Hs and the sending side tail pointer Ts is updated in response to the message generator 74 writing a message to the input queue 76. The entry 84 pointed to by the receiving side head pointer Hr and the receiving side tail pointer Tr is updated in response to the relay controller 78 reading a message from the input queue 76.

[0054] The memory controller 35 includes an output queue 80 and a processing unit 82 .

[0055] The output queue 80 is a memory with a FIFO structure and a ring buffer structure. The output queue 80 stores multiple messages output from the output port 72. Messages read from the shared memory 58 by the repeater 56 are written to the output queue 80. The messages read from the output queue 80 are sent to the processing unit 82. The number of output queues 80 is equal to the number of output ports 72. The output queues 80 are connected to the output ports 72. For example, if there are two output ports 72, the output queues 80 are output queues 80-0 and 80-1. The output queue 80-0 is connected to the output port 72-0, and the output queue 80-1 is connected to the output port 72-1.

[0056] The processing unit 82 is a processing circuit that executes processing according to a message. The processing unit 82 is connected to the output queue 80. For example, if there are two output queues 80, the processing units 82 are processing units 82-0 and 82-1. The processing unit 82-0 is connected to the output queue 80-0. The processing unit 82-1 is connected to the output queue 80-1. When the processing unit 82 completes processing according to the previously received message and becomes able to receive the next message, it reads the message from the output queue 80.

[0057] The output queue 80 includes a number of entries 85 .

[0058] In the output queue 80, which has a ring buffer structure, multiple entries 85 are logically connected in a circular fashion. For example, if the queue depth is 4, the output queue 80 includes four entries 85a, 85b, 85c, and 85d. Entry 85b is logically connected to entry 85a, entry 85c is logically connected to entry 85b, entry 85d is logically connected to entry 85c, and entry 85a is logically connected to entry 85d.

[0059] The output queue 80 includes a sending head pointer Hs, a receiving head pointer Hr, a sending tail pointer Ts, and a receiving tail pointer Tr, which are pointers to entries 85 that store messages.

[0060] The sending head pointer Hs is a pointer that points to the entry 85 that was the most recently free entry among a plurality of free entries 85 .

[0061] The sending tail pointer Ts is a pointer that points to the most recently free entry 85 among a plurality of free entries 85 .

[0062] The receiving side head pointer Hr is a pointer that points to the entry 85 to which a message was written most recently among the multiple entries 85 to which a message is written. If all the entries 85 are free entries, the receiving side head pointer Hr points to the entry 85 that became free most recently among the multiple free entries 85. A message is written to the entry 85 pointed to by the receiving side head pointer Hr. A message is read from the entry 85 pointed to by the receiving side head pointer Hr.

[0063] The receiving tail pointer Tr is a pointer that points to the entry 85 that was the most recently free entry among the plurality of free entries 85 .

[0064] The entries 85 pointed to by the sending head pointer Hs and the sending tail pointer Ts are updated in response to the writing of a message by the repeater 56 to the output queue 80. The entries 85 pointed to by the receiving head pointer Hr and the receiving tail pointer Tr are updated in response to the reading of a message from the output queue 80 by the processing unit 82.

[0065] The operation of the input queue 76 and the output queue 80 will be explained using examples where the queue depth is 2 and where the queue depth is 8.

[0066] An example of the operation of the input queue 76 and the output queue 80 when the queue depth is 2 (the number of entries is two) will be described. Because the operation of the input queue 76 and the operation of the output queue 80 are the same, the input queue 76 and the output queue 80 will be referred to as queues 94 in the following description. FIG. 7(a) is a diagram showing an example of the queue 94 in an empty state according to the first embodiment. FIG. 7(b) is a diagram showing an example of the queue 94 in a full state according to the first embodiment. FIG. 7(c) is a diagram showing another example of the queue 94 in an empty state according to the first embodiment. FIG. 7(d) is a diagram showing another example of the queue 94 in a full state according to the first embodiment. The queue 94 includes two entries 94a and 94b. The queue 94 can store one message less than the queue depth. A state in which either entry 94a or entry 94b stores a message is called a full state. A state in which entries 94a and 94b are free entries of the queue 94 is called an empty state.

[0067] In the state of Figure 7(a), two entries 94a and 94b are free entries. Assume that the first entry 94a becomes free first, and then the second entry 94b becomes free. In the state of Figure 7(a), the sending side tail pointer Ts points to the second entry 94b, and the sending side head pointer Hs, receiving side head pointer Hr, and receiving side tail pointer Tr all point to the first entry 94a. When the sending side head pointer Hs and the sending side tail pointer Ts point to different entries, this means that the queue 94 is not full and a message can be written. When the receiving side head pointer Hr and the receiving side tail pointer Tr point to the same entry, this means that the queue 94 is empty and does not contain a message to be read.

[0068] When a message is written to the first entry 94a in the state shown in Figure 7(a), the sending side head pointer Hs and the receiving side tail pointer Tr are both updated to point to the second entry 94b, resulting in the state shown in Figure 7(b).

[0069] In the state of Figure 7(b), when a message is read from the first entry 94a, the sending side tail pointer Ts is updated to point to the first entry 94a, and the receiving side head pointer Hr is updated to point to the second entry 94b, resulting in the state of Figure 7(c).

[0070] In the state shown in Figure 7(c), when a message is written to the second entry 94b, the sending side head pointer Hs and the receiving side tail pointer Tr are both updated to point to the first entry 94a, resulting in the state shown in Figure 7(d).

[0071] In the state of Fig. 7(d), when a message is read from the second entry 94b, the second entry 94b becomes an empty entry, and as a result, the two entries 94a and 94b become empty entries (Fig. 7(a)).

[0072] An example of the operation of the input queue 76 and the output queue 80 when the queue depth is 8 (the number of entries is 8) will be described. Because the operation of the input queue 76 and the operation of the output queue 80 are the same, the input queue 76 and the output queue 80 will be referred to as queues 96 to describe this example of operation. FIG. 8(a) is a diagram illustrating an example of an empty queue 96 according to the first embodiment. FIG. 8(b) is a diagram illustrating an example of a queue 96 that is neither empty nor full according to the first embodiment. FIG. 8(c) is a diagram illustrating an example of a full queue 96 according to the first embodiment. FIG. 8(d) is a diagram illustrating another example of a queue 96 that is neither empty nor full according to the first embodiment. FIG. 8(e) is a diagram illustrating another example of an empty queue 96 according to the first embodiment. The queue 96 includes eight entries 96a, 96b, 96c, 96d, 96e, 96f, 96g, and 96h.

[0073] In the state of Figure 8(a), all eight entries 96a, 96b, 96c, 96d, 96e, 96f, 96g, and 96h are free entries. In the state of Figure 8(a), the sending side tail pointer Ts points to the third entry 96c, and the sending side head pointer Hs, receiving side head pointer Hr, and receiving side tail pointer Tr point to the fourth entry 96d.

[0074] In the state shown in Figure 8(a), when a message is written to the fourth entry 96d and the fifth entry 96e, the sending side head pointer Hs and the receiving side tail pointer Tr are both updated to point to the sixth entry 96f, resulting in the state shown in Figure 8(b).

[0075] In the state of Figure 8(b), if five more messages are written to the sixth, seventh, eighth, first, and second entries 96f, 96g, 96h, 96a, and 96b, the sending side head pointer Hs is updated to point to the third entry 96c, and the receiving side tail pointer Tr is updated to point to the fourth entry 96d, resulting in the state of Figure 8(c).

[0076] In the state of Figure 8(c), when one message is read from the fourth entry 96d, the sending side tail pointer Ts is updated to point to the fourth entry 96d, and the receiving side head pointer Hr is updated to point to the fifth entry 96e, resulting in the state of Figure 8(d).

[0077] In the state of Figure 8(d), if six more messages are read from the fifth entry 96e, the sixth entry 96f, the seventh entry 96g, the eighth entry 96h, the first entry 96a, and the second entry 96b, the sending side tail pointer Ts is updated to point to the second entry 96b, and the receiving side head pointer Hr is updated to point to the third entry 96c, resulting in the state of Figure 8(e).

[0078] FIG. 9 is a flowchart showing an example of a message copying process from the input queue 76 to the shared memory 58 by the relay controller 78 according to the first embodiment.

[0079] When the CPU 38 detects that a message has been sent from the FTL processing unit 52 to the relay 56, it causes the relay controller 78 to start copying the message from the input queue 76 to the shared memory 58 (START in FIG. 9).

[0080] The relay controller 78 determines whether the receiving side tail pointer Tr and the receiving side head pointer Hr of the input queue 76 in which the message has been written match (S104).

[0081] If the receiving side tail pointer Tr and the receiving side head pointer Hr of the input queue 76 in which the message is written do not match (NO in S104), the relay controller 78 reads the message from the entry pointed to by the receiving side head pointer Hr (S106).

[0082] The relay controller 78 adds 1 to the receiving side head pointer Hr of the input queue 76 from which the message has been read (increment) (S108).

[0083] The relay controller 78 writes the read message into any free slot in the shared memory 58 (S110). The relay controller 78 retrieves the free slot number from the free slot number memory 59 and determines the free slot according to the free slot number.

[0084] The relay controller 78 updates the linked list by adding the new message to the linked list assigned to the output port 72 corresponding to the output destination of the message (S112).

[0085] A linked list is management data with a table structure whose components are a head pointer, a tail pointer, and the number of messages. The head pointer HP is a pointer that points to a slot in the shared memory 58 that stores the oldest message in a series of messages written to the shared memory 58. The tail pointer TP is a pointer that points to a slot in the shared memory 58 that stores the most recently written message in a series of messages written to the shared memory 58. The number of messages is a value that indicates the number of messages in a series written to the shared memory 58.

[0086] After updating the linked list (S112), the relay controller 78 determines whether the receiving side tail pointer Tr and the receiving side head pointer Hr of the input queue 76 in which the message has been written match (S104).

[0087] If the receiving side tail pointer Tr and receiving side head pointer Hr of the input queue 76 in which the message is written match (YES in S104), the relay controller 78 ends the message copy process from the input queue 76 to the shared memory 58 (END).

[0088] Next, we will explain how the linked list assigned to one output port 72, for example, output port 72-0, is updated when an input queue 76, for example, input queue 76-0, stores a series of messages addressed to one output port 72, for example, output port 72-0. FIG. 10(a) is a diagram showing an example of a linked list according to the first embodiment at a first timing. FIG. 10(b) is a diagram showing an example of a linked list according to the first embodiment at a second timing. FIG. 10(c) is a diagram showing an example of a linked list according to the first embodiment at a third timing.

[0089] For ease of explanation, the shared memory 58 includes eight slots 58a, 58b, 58c, 58d, 58e, 58f, 58g and 58h.

[0090] At a certain timing (called timing 1), the shared memory 58 does not store any messages, and all slots 58a-58h are empty. The head pointer HP of the linked list assigned to output port 72-0 is null, the tail pointer TP points to an arbitrary slot (here, slot 58h), and the number of messages is 0 (Figure 10(a)).

[0091] When a message belonging to a series of messages destined for output port 72-0 is written to input queue 76-0, relay controller 78 reads one message (called the first message) from input queue 76-0 and writes the read first message to any available slot (here, slot 58g) in shared memory 58.

[0092] At a subsequent timing (called the second timing), the relay controller 78 updates the head pointer HP and tail pointer TP of the linked list of the output port 72-0 so that they point to the slot into which the first message was written (here, slot 58g), and increments the number of messages in the linked list by 1 (FIG. 10(b)). The initial value of the link pointer 66 for the first message is maintained at 0.

[0093] If the input queue 76 stores a further message belonging to the series of messages destined for output port 72-0, the relay controller 78 reads the further message (called the second message) from the input queue 76 and writes the read message into any free slot in the shared memory 58 (here, slot 58a).

[0094] At a subsequent timing (called the third timing), the relay controller 78 leaves the head pointer HP of the linked list of output port 72-0 as it is (still pointing to slot 58g), updates the linked list so that the tail pointer TP points to the slot into which the message was written (here, slot 58a), and increments the number of messages by 1 (FIG. 10(c)). When writing the second message to slot 68g, the relay controller 78 updates the value of the link pointer 66 of the first message so that it points to slot 58a into which the second message was written. The initial value of the link pointer 66 of the second message is maintained at 0.

[0095] When the relay controller 78 reads the first message from the shared memory 58, it can read the second message that was written to the shared memory 58 after the first message by referring to the link pointer 66 of the first message.

[0096] 11 is a flowchart showing an example of a message copying process from the shared memory 58 to the output queue 80-0 by the relay controller 78 according to the first embodiment. Here, it is assumed that the shared memory 58 stores a series of messages addressed to one output port 72-0.

[0097] Here, the relationship between the linked list and the output port 72-0 is not one-to-one, but rather a linked list for multiple messages is assigned to one output port 72-0. This is to allow the relay controller 78 to process commands (messages) evenly across multiple linked lists, rather than simply processing the commands (messages) in the order they were issued.

[0098] When the relay controller 78 completes the message copy process from the input queue 76 to the shared memory 58 (FIG. 9), the CPU 38 causes the relay device 56 to start the message copy process from the shared memory 58 to the output queue 80-0 (START in FIG. 11).

[0099] The relay controller 78 selects one linked list from which to extract the message from among the multiple linked lists assigned to the output port 72-0 (S202). The processing of S202 is also called linked list arbitration processing.

[0100] The relay controller 78 acquires the number of messages in the selected linked list (S204).

[0101] The relay controller 78 reads the first message of the selected linked list from the shared memory 58 (S206).

[0102] The relay controller 78 extracts the command ID from the read message (S208).

[0103] The relay controller 78 writes the extracted command ID into the volatile memory 26 (S212).

[0104] The relay controller 78 updates the linked list to release the slot storing the first message of the selected linked list (S214). The updating of the linked list will be described later.

[0105] The relay controller 78 sends the read message to the output queue 80-0 (S220).

[0106] The relay controller 78 determines whether the output queue 80-0 is full (S222). The relay controller 78 determines whether the output queue 80-0 is full depending on whether the sending side head pointer Hs and the sending side tail pointer Ts of the output queue 80-0 point to the same slot.

[0107] If the output queue 80-0 is full (YES in S222), the relay controller 78 waits until the output queue 80-0 is no longer full (S224).

[0108] If the output queue 80-0 is not in a full state (NO in S222 or after completion of S224), the relay controller 78 determines whether the selected linked list is empty (S228). The selected linked list being empty means that the number of messages in the linked list is 0. The reason for determining whether the linked list is empty when the output queue 80-0 is not full is to create an opportunity for a message with the same command ID to be added to the linked list between the time when the output queue 80-0 becomes full and the time when it transitions to a not-full state.

[0109] If the selected linked list is empty (YES in S228), the relay controller 78 executes linked list arbitration processing (S202).

[0110] If the selected linked list is not empty (NO in S228), the relay controller 78 reads the head pointer HP and the number of messages from the linked list (S232).

[0111] The relay controller 78 reads the message from the slot in the shared memory 58 pointed to by the read head pointer HP (S234).

[0112] The relay controller 78 extracts the command ID from the read message (S236).

[0113] The relay controller 78 determines whether the extracted ID command matches the command ID stored in the volatile memory 26 (S238).

[0114] If the extracted ID command matches the command ID stored in the volatile memory 26 (YES in S238), the relay controller 78 writes the command ID into the non-volatile memory 26 (S212).

[0115] If the extracted ID command does not match the command ID stored in the volatile memory 26 (NO in S238), the relay controller 78 determines whether the shared memory 58 stores a message (S240).

[0116] If the shared memory 58 stores the message (YES in S240), the relay controller 78 executes linked list arbitration processing (S202).

[0117] If the shared memory 58 does not store a message (NO in S240), the relay controller 78 ends the processing shown in FIG. 11 (END).

[0118] When the shared memory 58 stores a series of multiple messages addressed to multiple output ports 72, the relay controller 78 executes the process shown in FIG.

[0119] 11, the arbitration process (S202) was performed because it was assumed that linked lists for multiple messages were assigned to one output port 72-0. If one linked list were assigned to one output port 72-0, the arbitration process (S202) would not be performed.

[0120] Next, we will explain how the linked list assigned to one output port 72, for example output port 72-0, is updated when the shared memory 58 stores a series of messages addressed to that output port. Figure 12(a) shows an example of a linked list according to the first embodiment at a fourth timing. Figure 12(b) shows an example of a linked list according to the first embodiment at a fifth timing. Figure 12(c) shows an example of a linked list according to the first embodiment at a sixth timing.

[0121] At a certain timing (called timing 4), shared memory 58 stores a series of two messages destined for output port 72-0 in slots 58g and 58a. Assume that the first message is written to slot 58g, and then the second message is written to slot 58a. The link pointer of the first message points to slot 58a, where the second message was written. The head pointer HP of the linked list assigned to output port 72-0 points to slot 58g, the tail pointer TP points to slot 58a, and the number of messages is 2 (Figure 12(a)).

[0122] If the head pointer HP and tail pointer TP of the linked list point to different slots, that is, if the shared memory 58 stores two or more messages and the head pointer HP is not a null pointer, the relay controller 78 reads the message from the slot of the shared memory 58 pointed to by the head pointer HP and writes the read message to the output queue 80-0 via the output port 72-0. Therefore, after the fourth timing, the relay controller 78 reads the first message from the slot 58g of the shared memory 58 pointed to by the head pointer HP, writes the read message to the output queue 80-0 via the output port 72-0, and writes the slot number of the slot 58g to the empty slot number memory 59 as an empty slot number.

[0123] At a subsequent timing (called the fifth timing), the relay controller 78 updates the head pointer HP of the linked list to point to slot 58a pointed to by the link pointer of the first message, leaves the tail pointer TP unchanged (still pointing to slot 58a), and subtracts 1 from the number of messages (Figure 12(b)).

[0124] If the head pointer HP and tail pointer TP of the linked list point to the same slot, that is, if the shared memory 58 stores one message and the head pointer HP is not a null pointer, the relay controller 78 reads the message from the slot of the shared memory 58 pointed to by the head pointer HP and writes the read message to the output queue 80-0 via the output port 72-0. Therefore, after the fifth timing, the relay controller 78 reads the second message from slot 58a of the shared memory 58 pointed to by the head pointer HP, writes the read message to the output queue 80-0 via the output port 72-0, and writes the slot number of slot 58a to the empty slot number memory 59 as an empty slot number.

[0125] At a subsequent timing (called the sixth timing), the relay controller 78 updates the head pointer HP of the linked list to a null pointer, leaves the tail pointer TP unchanged (pointing to slot 58a), and subtracts one from the number of messages (Figure 12(c)).

[0126] By executing the process of Figure 12, a series of messages to be sent to memory controller 35-0 (messages d, e, and f in Figure 6) are read from shared memory 58 in that order and written to output queue 80-0, and a message to be sent to memory controller 35-1 (the single message D in Figure 6) is read from shared memory 58 and written to output queue 80-1.

[0127] The processing unit 82 reads a message from the output queue 80 and executes processing according to the read message. When the processing is completed, the processing unit 82 reads the next message from the output queue 80 and executes the next processing. The processing is, for example, reading / writing from / to the memory chip 44.

[0128] The relay controller 78 according to the embodiment writes messages received by the relay device 56 and stored in the multiple input queues 76 into the shared memory 58 as a series of messages for each destination using a linked list that indicates the transmission order for each destination. Because the shared memory 58 is randomly accessible rather than having a FIFO structure, the relay controller 78 can read messages from any slot of the shared memory 58. Therefore, even if the amount of first messages addressed to the output port 72-0 is much greater than the amount of second messages addressed to the output port 72-1 and the output queue 80-0 is full, if the output queue 80-1 is not full, the second messages addressed to the output queue 80-1 can be read from the shared memory 58 and written to the output queue 80-1.

[0129] If shared memory 58 is not provided and input queues 76-0 and 76-1 are storing messages, when input queue 76-0 or 76-1 stores a first message addressed to output queue 80-0, which is full, followed by a second message addressed to output queue 80-1, which is not full, the subsequent second message cannot be read ahead of the preceding first message, causing a delay in transmission of the second message and a delay in processing the request indicated by the second message.

[0130] This prevents delays when the repeater 68 sends or receives messages to the nonvolatile memory I / F circuit 34. Therefore, the nonvolatile memory I / F circuit 34 can process messages without delay, improving the performance of the memory system.

[0131] According to the memory system of the embodiment, each output queue 80 does not need to have the maximum number of entries for the system's processing, and one shared memory 58 only needs to have this maximum number of slots, thereby reducing the amount of memory used.

[0132] The relay controller 78 writes information pointing to the slot in the shared memory 58 that stores the subsequent message to the link pointer 66 of the message written in the shared memory 58. This allows the relay controller 78 to read a certain message and then read the message that follows that message.

[0133] A modified example of writing a message to the shared memory 58 will now be described. In the above-described embodiment, the message generation unit 74 temporarily writes the message to the input queue 76, and the relay controller 78 reads the message from the input queue 76 and writes it to the shared memory 58. Alternatively, the message generation unit 74 may write the message directly to the shared memory 58. In this case, the message generation unit 74 includes an empty slot number memory. The message generation unit 74 may refer to the empty slot number memory to determine whether the shared memory 58 includes an empty slot, and if it detects that the shared memory 58 includes an empty slot, it may assign one of the empty slots to the message and write the message in the assigned slot. In this case, the message generation unit 74 may notify the relay controller 78 of the slot number into which the message was written. The relay controller 78 may update the linked list based on this notification.

[0134] The embodiments are merely examples, and the scope of the invention is not limited thereto. [Explanation of symbols]

[0135] 1. Information processing system 10...Host 20...Memory system 22...Controller 24...Non-volatile memory 26...Volatile memory 32...Host I / F circuit 34...Non-volatile memory I / F circuit 35...Memory controller 36...Volatile memory I / F circuit 38...CPU 40...Bus line 44...Memory chip 52...FTL processing unit 56...Repeater 58...Shared memory 59...Free slot number memory 62...Output port number 64...Message body 66...Link pointer 70...input port 72...Output port 74...Message generation unit 76...input queue 78...Relay controller 80...Output queue 82...Processing section 84a, 84b, 84c, 84d, 85a, 85b, 85c, 85d… entries 94...Queue 94a, 94b...entries 96...Queue 96a, 96b, 96c, 96d, 96e, 96f, 96g, 96h… entries

Claims

1. a non-volatile memory including a first portion and a second portion; a randomly accessible memory; a controller that generates a plurality of first messages in response to a first command received from an external device; The plurality of first messages include: a first message addressed to the first portion; and a first message addressed to the second portion; The controller a first input port to which the plurality of first messages are input; a first output port connected to the first portion; a second output port connected to the second portion; a repeater; The repeater is writing the plurality of first messages input via the first input port into the randomly accessible memory; When the first part is ready to receive a message, reading a first message addressed to the first part from the randomly accessible memory; outputting the read first message to the first part via the first output port; Memory system.

2. the controller generates a plurality of second messages in response to a second command received from the external device; the plurality of second messages include a second message addressed to the first portion and a second message addressed to the second portion; the controller further comprises a second input port to which the plurality of second messages are input; The repeater is writing the plurality of second messages input via the second input port into the randomly accessible memory; when the first part is ready to receive a message, reading a first message addressed to the first part and a second message addressed to the first part from the randomly accessible memory; outputting the read first message and second message to the first part via the first output port; 10. The memory system of claim 1.

3. The repeater is when the second part is ready to receive a message, reading a first message addressed to the second part from the randomly accessible memory; outputting the read first message to the second part via the second output port; 3. The memory system of claim 2.

4. The repeater is when writing the plurality of first messages addressed to the first portion into the randomly accessible memory, adding a first pointer to each of the plurality of first messages addressed to the first portion, the first pointer indicating a storage area for a message to be output to the first portion next to each of the plurality of first messages; 4. The memory system of claim 3.

5. The repeater is a second pointer indicating a storage area of ​​a message to be read first among the plurality of first messages read from the randomly accessible memory; and managing a third pointer indicating a storage area of ​​a message that is last read out of the plurality of first messages read out from the randomly accessible memory.

5. The memory system of claim 4.

6. the controller includes a queue connected to the first input port; writing the plurality of first messages to the queue; The first messages are read from the queue in the same order as they were written; The repeater is reading the first plurality of messages from the queue; writing the read first messages into the randomly accessible memory; 6. The memory system of claim 5.

7. a non-volatile memory including a first portion and a second portion; a randomly accessible memory; a controller that generates a plurality of first messages in response to a first command received from an external device; The controller an input port to which the plurality of first messages are input; a first output port connected to the first portion; a second output port connected to the second portion, The plurality of first messages include: a first message addressed to the first portion; and a first message addressed to the second portion; writing the plurality of first messages input via the input port into the randomly accessible memory; When the first part is ready to receive a message, reading a first message addressed to the first part from the randomly accessible memory; outputting the read first message to the first part via the first output port; A method for controlling a memory system.

8. a non-volatile memory; a randomly accessible memory; a controller; The controller generating a plurality of first messages in response to a first command received from an external device; generating a plurality of second messages in response to a second command received from the external device; a first input port to which the plurality of first messages are input; a second input port to which the plurality of second messages are input; an output port connected to the nonvolatile memory; a repeater; The repeater is writing the plurality of first messages input via the first input port and the plurality of second messages input via the second input port into the randomly accessible memory; when the nonvolatile memory is ready to receive a message, reading the plurality of first messages and the plurality of second messages from the randomly accessible memory; outputting the read first messages and the read second messages to the nonvolatile memory via the output port; Memory system.

9. a non-volatile memory; a randomly accessible memory; a controller; The controller generating a plurality of first messages in response to a first command received from an external device; generating a plurality of second messages in response to a second command received from the external device; a first input port to which the plurality of first messages are input; a second input port to which the plurality of second messages are input; and an output port connected to the nonvolatile memory, writing the plurality of first messages input via the first input port and the plurality of second messages input via the second input port into the randomly accessible memory; when the nonvolatile memory is ready to receive a message, reading the plurality of first messages and the plurality of second messages from the randomly accessible memory; outputting the read first messages and the read second messages to the nonvolatile memory via the output port; A method for controlling a memory system.

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