Semiconductor device, semiconductor device manufacturing method, inverter circuit, drive device, vehicle, and elevator

Abstract

To provide a semiconductor device in which mobility of a carrier is improved.SOLUTION: A semiconductor device comprises: a silicon carbide layer; a silicon oxide layer of which a peak vibration frequency of a longitudinal wave optical mode at a position away from the silicon carbide layer by 0.5 nm is 1245 cm-1 or more; and a region which is positioned between the silicon carbide layer and the silicon oxide layer and in which the concentration of nitrogen is 1×1021 cm-3 or more. The concentration distribution of nitrogen in the silicon carbide layer, the silicon oxide layer and the area has a peak in the region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, a method for manufacturing a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon (Si), silicon carbide has excellent physical properties, such as a band gap three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these properties will enable the realization of semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] For example, when a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is formed using silicon carbide, there is a problem that the mobility of carriers decreases. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-153168 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device in which carrier mobility is improved. [Means for solving the problem]

[0006] The semiconductor device of the embodiment has a silicon carbide layer and a longitudinal wave optical mode having a peak frequency of 1245 cm at a position 0.5 nm away from the silicon carbide layer. -1 a silicon oxide layer having a nitrogen concentration of 1×10 or more and a silicon carbide layer located between the silicon carbide layer and the silicon oxide layer; 21 cm-3 and a nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has a peak in the region. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] A diagram showing the crystal structure of a SiC semiconductor. [Figure 3] FIG. 2 is a diagram showing the peak frequency of a longitudinal optical mode in a gate insulating layer of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is a diagram showing the element concentration distribution of the semiconductor device according to the first embodiment. [Figure 5] FIG. 2 is a process flow diagram of the method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] FIG. 10 is a process flow diagram of a method for manufacturing a semiconductor device according to a comparative example. [Figure 7] FIG. 10 is a diagram showing the peak frequency of a longitudinal wave optical mode in a gate insulating layer of a semiconductor device according to a comparative example. [Figure 8] FIG. 10 is a diagram showing the element concentration distribution of a semiconductor device of a comparative example. [Figure 9] FIG. 10 is an explanatory diagram of defects in a gate insulating layer of a comparative example. [Figure 10] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 11] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a third embodiment. [Figure 12] FIG. 10 is a schematic diagram of a drive device according to a fourth embodiment. [Figure 13] FIG. 10 is a schematic diagram of a vehicle according to a fifth embodiment. [Figure 14] FIG. 10 is a schematic diagram of a vehicle according to a sixth embodiment. [Figure 15] FIG. 13 is a schematic diagram of an elevator according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n + , n, n - and p + , p, p - When the notation is used, it indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type may be simply referred to as p-type. Unless otherwise specified, the impurity concentration of each region is represented by the value of the impurity concentration at the center of each region.

[0010] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distances, such as the width and depth, of the impurity region can be determined by, for example, SIMS. The distances, such as the width and depth, of the impurity region can also be determined from, for example, an SCM image.

[0011] The depth of the trench, the thickness of the insulating layer, etc. can be measured on an image obtained by, for example, SIMS or a Transmission Electron Microscope (TEM).

[0012] The bonding states of silicon atoms, carbon atoms, nitrogen atoms, and oxygen atoms in the silicon carbide layer can be identified by, for example, X-ray photoelectron spectroscopy (XPS), and the concentrations of various bonding states and the magnitude relationship between the concentrations can be determined by, for example, X-ray photoelectron spectroscopy (XPS).

[0013] The peak frequency of the longitudinal optical mode in the silicon oxide layer can be measured, for example, by Attenuated Total Reflection (ATR) of Fourier Transform Infrared Spectroscopy (FTIR).

[0014] (First embodiment) The semiconductor device of the first embodiment has a silicon carbide layer and a longitudinal optical mode with a peak frequency of 1245 cm at a position 0.5 nm away from the silicon carbide layer. -1 a silicon oxide layer having a nitrogen concentration of 1×10 or more and a silicon carbide layer located between the silicon oxide layer and the silicon carbide layer; 21 cm -3 The silicon carbide layer, the silicon oxide layer, and the region have a nitrogen concentration distribution peak in the region.

[0015] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The semiconductor device is a MOSFET 100. The MOSFET 100 is a double implantation MOSFET (DIMOSFET) in which a p-well and a source region are formed by ion implantation. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0016] The MOSFET 100 includes a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, and an interface termination region 40 (region).

[0017] The silicon carbide layer 10 includes a drain region 12 , a drift region 14 , a p-well region 16 , a source region 18 , and a p-well contact region 20 .

[0018] The silicon carbide layer 10 is, for example, a single crystal of 4H—SiC. The silicon carbide layer 10 is located between a source electrode 34 and a drain electrode 36.

[0019] Figure 2 is a diagram showing the crystal structure of SiC semiconductor. A typical crystal structure of SiC semiconductor is a hexagonal system like 4H-SiC. One of the faces (top faces of the hexagonal prism) whose normal is the c-axis along the axial direction of the hexagonal prism is the (0001) face. A face equivalent to the (0001) face is called the silicon face (Si face) and is written as the {0001} face. Silicon atoms (Si) are arranged on the top surface of the silicon face.

[0020] The other surface (top surface of the hexagonal prism) normal to the c-axis along the axial direction of the hexagonal prism is the (000-1) surface. The surface equivalent to the (000-1) surface is called the carbon surface (C-surface) and is written as the {000-1} surface. Carbon atoms (C) are arranged on the outermost surface of the carbon surface.

[0021] On the other hand, the side surfaces of the hexagonal prism (cylindrical surfaces) are m-planes, i.e., {1-100} planes, which are equivalent to the (1-100) plane. Furthermore, the planes passing through pairs of non-adjacent ridges are a-planes, i.e., {11-20} planes, which are equivalent to the (11-20) plane. Both silicon atoms (Si) and carbon atoms (C) are arranged on the outermost surfaces of the m-plane and a-plane.

[0022] Hereinafter, an example will be described in which the front surface of silicon carbide layer 10 is inclined at an angle of 0 to 8 degrees relative to the silicon surface, and the back surface is inclined at an angle of 0 to 8 degrees relative to the carbon surface. The front surface of silicon carbide layer 10 has an off angle of 0 to 8 degrees relative to the silicon surface.

[0023] The drain region 12 is n + The drain region 12 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm-3 More than 1×10 21 cm -3 The following is the result.

[0024] The drift region 14 is provided on the drain region 12. The drift region 14 has an n - The drift region 14 is made of SiC of n-type. The drift region 14 contains, for example, nitrogen as an n-type impurity.

[0025] The n-type impurity concentration of the drift region 14 is lower than the n-type impurity concentration of the drain region 12. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The drift region 14 is, for example, an epitaxially grown layer of SiC formed on the drain region 12 by epitaxial growth.

[0026] The thickness of the drift region 14 is, for example, not less than 5 μm and not more than 100 μm.

[0027] The p-well region 16 is provided on a part of the surface of the drift region 14. The p-well region 16 is made of p-type SiC. The p-well region 16 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the p-well region 16 is, for example, 1×10 16 cm -3 More than 1×10 20 cm -3 The following is the result.

[0028] The depth of the p-well region 16 is, for example, not less than 0.4 μm and not more than 0.8 μm. The p-well region 16 functions as a channel region of the MOSFET 100.

[0029] The source region 18 is provided on a part of the surface of the p-well region 16. The source region 18 is an n + The source region 18 is made of n-type SiC. The source region 18 contains, for example, phosphorus (P) as an n-type impurity. The n-type impurity concentration of the source region 18 is, for example, 1×10 18 cm -3 More than 1×1022 cm -3 It is less than cm.

[0030] The depth of the source region 18 is shallower than the depth of the p-well region 16. The depth of the source region 18 is, for example, not less than 0.2 μm and not more than 0.4 μm.

[0031] The p-well contact region 20 is provided on a part of the surface of the p-well region 16. The p-well contact region 20 is provided on the side of the source region 18. The p-well contact region 20 is provided on the p + It is a type of SiC.

[0032] The p-well contact region 20 contains, for example, aluminum as a p-type impurity. The p-type impurity concentration of the p-well contact region 20 is, for example, 1×10 18 cm -3 More than 1×10 22 cm -3 The following is the result.

[0033] The depth of the p-well contact region 20 is shallower than the depth of the p-well region 16. The depth of the p-well contact region 20 is, for example, not less than 0.2 μm and not more than 0.4 μm.

[0034] The gate insulating layer 28 is provided between the silicon carbide layer 10 and the gate electrode 30. The gate insulating layer 28 is provided between the drift region 14 and the p-well region 16 and the gate electrode 30. The gate insulating layer 28 is provided on the drift region 14 and the p-well region 16. The gate insulating layer 28 is continuously formed on the surfaces of the drift region 14 and the p-well region 16.

[0035] The gate insulating layer 28 is made of silicon oxide. The gate insulating layer 28 is an example of a silicon oxide layer.

[0036] The gate insulating layer 28 has a thickness of, for example, 30 nm to 100 nm. The gate insulating layer 28 functions as a gate insulating layer for the MOSFET 100.

[0037] FIG. 3 is a diagram showing the peak frequency of a longitudinal optical mode in the gate insulating layer of the semiconductor device of the first embodiment.

[0038] As shown in FIG. 3, the peak frequency of the longitudinal optical mode of the gate insulating layer 28 at a position 0.5 nm away from the silicon carbide layer is 1245 cm -1 The peak frequency of the longitudinal optical mode of the gate insulating layer 28 at any position 0.5 nm or more away from the silicon carbide layer is 1245 cm -1 That's all.

[0039] The interface termination region 40 is located between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 includes the interface between the silicon carbide layer 10 and the gate insulating layer 28. The interface termination region 40 is located between the drift region 14 and the p-well region 16 and the gate insulating layer 28.

[0040] Interface termination region 40 includes the interface between silicon carbide layer 10 and gate insulating layer 28. Interface termination region 40 is a region near the interface between silicon carbide layer 10 and gate insulating layer 28, with a thickness of about two to three atomic layers, for example.

[0041] Interface termination region 40 contains nitrogen (N) as a terminating element that terminates dangling bonds in silicon carbide layer 10. Interface termination region 40 is an example of a region.

[0042] The nitrogen concentration in the interface termination region 40 is 1×10 21 cm -3 The nitrogen concentration in interface termination region 40 is, for example, 1×10 23 cm -3 The following is the result.

[0043] Fig. 4 is a diagram showing the element concentration distribution of the semiconductor device of the first embodiment. Fig. 4 is a diagram showing the element concentration distribution in gate insulating layer 28, interface termination region 40, and silicon carbide layer 10. Fig. 4 shows the concentration distribution of nitrogen and carbon.

[0044] The nitrogen concentration distribution has a peak in the interface termination region 40. The peak nitrogen concentration is, for example, 1×10 22 cm -3 That is all. The full width at half maximum of the peak of the nitrogen concentration distribution is, for example, 1 nm or less. Nitrogen segregates at the interface between the silicon carbide layer 10 and the gate insulating layer 28.

[0045] The nitrogen concentration at the first position X, which is 1 nm away from the peak of the nitrogen concentration distribution on the gate insulating layer 28 side, is 1×10 18 cm -3 The nitrogen concentration at a second position Y, which is 1 nm away from the peak of the nitrogen concentration distribution toward the silicon carbide layer 10 side, is 1×10 18 cm -3 The following is the result.

[0046] The carbon concentration distribution decreases from the interface termination region 40 toward the gate insulating layer 28. The carbon concentration at the first position X is 1×10 18 cm -3 The following is the result.

[0047] The gate electrode 30 is provided on the gate insulating layer 28. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the silicon carbide layer 10. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the drift region 14. The gate electrode 30 sandwiches the gate insulating layer 28 between itself and the p-well region 16.

[0048] The gate electrode 30 is made of, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0049] The interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0050] The source electrode 34 is electrically connected to the source region 18 and the p-well contact region 20. The source electrode 34 also functions as a p-well electrode that applies a potential to the p-well region 16.

[0051] The source electrode 34 is formed, for example, by laminating a Ni (nickel) barrier metal layer and an aluminum metal layer on the barrier metal layer. The nickel barrier metal layer and the silicon carbide layer may react to form nickel silicide (NiSi, NiSi, etc.). The nickel barrier metal layer and the aluminum metal layer may react to form an alloy.

[0052] The drain electrode 36 is provided on the opposite side of the silicon carbide layer 10 to the source electrode 34, i.e., on the back surface side. The drain electrode 36 is made of, for example, nickel. Nickel may react with the drain region 12 to form nickel silicide (NiSi, NiSi, etc.).

[0053] In the first embodiment, the n-type impurity is, for example, nitrogen or phosphorus. Arsenic (As) or antimony (Sb) can also be used as the n-type impurity.

[0054] In the first embodiment, the p-type impurity is, for example, aluminum. Boron (B), gallium (Ga), and indium (In) can also be used as the p-type impurity.

[0055] Next, an example of a method for manufacturing the semiconductor device of the first embodiment will be described.

[0056] The method for manufacturing a semiconductor device of the first embodiment includes forming a silicon oxide film having an atomic ratio of oxygen (O) to silicon (Si) of less than 2 on the surface of a silicon carbide layer by vapor phase growth, performing a first heat treatment in an atmosphere containing nitrogen oxide at a temperature of 350°C or less and a pressure of 5 MPa or more, and after the first heat treatment, performing a second heat treatment in a non-oxidizing atmosphere at a temperature of 900°C or more.

[0057] FIG. 5 is a process flow diagram of the method for manufacturing the semiconductor device of the first embodiment.

[0058] As shown in FIG. 5, the method for manufacturing the semiconductor device of the first embodiment includes silicon carbide layer preparation (step S100), p-type impurity ion implantation (step S101), n-type impurity ion implantation (step S102), p-type impurity ion implantation (step S103), silicon oxide film formation (step S104), first heat treatment (step S105), second heat treatment (step S106), gate electrode formation (step S107), interlayer insulating film formation (step S108), source electrode formation (step S109), and drain electrode formation (step S110).

[0059] In step S100, a silicon carbide layer 10 is prepared. The silicon carbide layer 10 has an n + type drain region 12 and n - The semiconductor device includes a drift region 14. The drift region 14 is formed on the drain region 12 by, for example, epitaxial growth.

[0060] The drain region 12 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drain region 12 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0061] The drift region 14 contains nitrogen as an n-type impurity. The n-type impurity concentration of the drift region 14 is, for example, 1×10 15 cm -3 Over 2×10 16 cm -3 The thickness of the drift region 14 is, for example, not less than 5 μm and not more than 100 μm.

[0062] In step S101, a first mask material is formed by patterning using photolithography and etching. Then, using the first mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift region 14. The ion implantation forms a p-well region 16.

[0063] In step S102, first, a second mask material is formed by patterning using photolithography and etching. Then, using the second mask material as an ion implantation mask, phosphorus, which is an n-type impurity, is ion-implanted into the drift region 14 to form the source region 18.

[0064] In step S103, a third mask material is formed by patterning using photolithography and etching. Using the third mask material as an ion implantation mask, aluminum, which is a p-type impurity, is ion-implanted into the drift region 14 to form the p-well contact region 20.

[0065] In step S104, a silicon oxide film is formed on the silicon carbide layer 10. The silicon oxide film will eventually become the gate insulating layer .

[0066] The silicon oxide film is formed by vapor phase growth. The silicon oxide film is formed by, for example, a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD method). The silicon oxide film is a deposited film. The thickness of the silicon oxide film is, for example, 30 nm or more and 100 nm or less.

[0067] The silicon oxide film formed in step S104 has an atomic ratio (O / Si) of oxygen (O) to silicon (Si) of less than 2. The silicon oxide film formed in step S104 has a chemical composition that does not satisfy the stoichiometric ratio of silicon dioxide. The silicon oxide film formed in step S104 is a film deficient in oxygen (O).

[0068] In other words, the silicon oxide film formed in step S104 is a film in which silicon (Si) is excessive, or in other words, the silicon oxide film formed in step S104 is a silicon-rich silicon oxide film.

[0069] The chemical composition of the silicon oxide film formed in step S104 is SiO 2-δIn this case, for example, 0.002≦δ≦0.1 is satisfied. That is, the silicon oxide film has, for example, an atomic ratio of oxygen (O) to silicon (Si) of 1.900 or more and 1.998 or less. That is, the silicon oxide film has, for example, an oxygen deficiency rate of 0.1% or more and 5% or less.

[0070] The amount of oxygen vacancies in the silicon oxide film formed in step S104 can be increased by, for example, reducing the oxygen partial pressure in the atmosphere during vapor deposition. The oxygen partial pressure in the atmosphere during the formation of the silicon oxide film in step S104 is, for example, 10% or less.

[0071] The temperature at which the silicon oxide film is formed in step S104 is, for example, 350° C. or less. By forming the silicon oxide film at a temperature of 350° C. or less, oxidation of the surface of the silicon carbide layer 10 can be suppressed.

[0072] In step S105, a first heat treatment is performed. The first heat treatment is performed to remove nitrogen oxides (NO X ) at a temperature of 350°C or less and a pressure of 5 MPa or more.

[0073] The first heat treatment is a low-temperature, high-pressure heat treatment. The first heat treatment is performed, for example, in a supercritical fluid. The first heat treatment is performed, for example, under conditions in which nitrogen oxides become a supercritical fluid.

[0074] The nitrogen oxide used in the first heat treatment is, for example, nitrous oxide (N2O) or nitric oxide (NO).

[0075] Nitrous oxide (N2O) becomes a supercritical fluid under conditions of, for example, 36.3°C or higher and 7.24 MPa or higher.

[0076] The temperature of the first heat treatment is, for example, 30° C. or more and 350° C. or less. The pressure of the first heat treatment is, for example, 5 MPa or more and 200 MPa or less.

[0077] The first heat treatment forms an interface termination region 40 at the interface between silicon carbide layer 10 and gate insulating layer 28.

[0078] In step S106, a second heat treatment is performed. The second heat treatment is performed in a non-oxidizing atmosphere at a temperature of 900° C. or higher. The second heat treatment is performed in a non-oxidizing atmosphere in which the surface of silicon carbide layer 10 is not oxidized.

[0079] The second heat treatment is performed, for example, in an atmosphere containing an inert gas. The second heat treatment is performed, for example, in an atmosphere containing argon (Ar) or nitrogen (N). The second heat treatment is performed, for example, in an atmosphere containing argon gas or nitrogen gas.

[0080] The oxygen partial pressure in the second heat treatment is, for example, 100 ppm or less.

[0081] The temperature of the second heat treatment is higher than the temperature of the first heat treatment, and is, for example, 900°C or higher and 1250°C or lower.

[0082] The second heat treatment functions as a densifying anneal for the silicon oxide film, and the silicon oxide film becomes a high-density film through the second heat treatment.

[0083] In step S107, the gate electrode 30 is formed on the gate insulating layer 28. The gate electrode 30 is, for example, polycrystalline silicon containing n-type impurities or p-type impurities.

[0084] In step S108, the interlayer insulating film 32 is formed on the gate electrode 30. The interlayer insulating film 32 is, for example, a silicon oxide film.

[0085] In step S109, the source electrode 34 is formed. The source electrode 34 is formed on the source region 18 and the p-well contact region 20. The source electrode 34 is formed by, for example, sputtering nickel (Ni) and aluminum (Al).

[0086] In step S110, the drain electrode 36 is formed. The drain electrode 36 is formed on the back surface side of the silicon carbide layer 10. The drain electrode 36 is formed by, for example, sputtering nickel.

[0087] By the above manufacturing method, the MOSFET 100 shown in FIG. 1 is formed.

[0088] Next, the functions and effects of the semiconductor device and the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0089] When forming a MOSFET using silicon carbide, there is a problem of reduced carrier mobility. One factor that reduces carrier mobility is thought to be the intersurface state between the silicon carbide layer and the gate insulating layer. The interface state is thought to be caused by dangling bonds present on the surface of the silicon carbide layer.

[0090] The MOSFET 100 of the first embodiment includes an interface termination region 40 in which nitrogen is segregated between the silicon carbide layer 10 and the gate insulating layer 28. The nitrogen contained in the interface termination region 40 terminates dangling bonds, reducing the number of dangling bonds present on the surface of the silicon carbide layer. This results in a MOSFET with improved carrier mobility.

[0091] The concentration of nitrogen in the interface termination region 40 is 1×10 21 cm -3 From the viewpoint of suppressing a decrease in the carrier mobility of the MOSFET 100, the nitrogen concentration at the peak of the nitrogen concentration distribution in the interface termination region 40 is set to 1×10 22 cm -3 It is preferable that the value is 5×10 or more. 22 cm -3 More preferably, it is equal to or greater than this.

[0092] Another factor that reduces the carrier mobility of MOSFETs is thought to be stress generated near the interface between the silicon carbide layer and the gate insulating layer. For example, stress generated near the interface can cause lattice distortion or defects on the surface of the silicon carbide layer, which can reduce the carrier mobility of MOSFETs.

[0093] As shown in FIG. 3, the MOSFET 100 of the first embodiment has a peak frequency of 1245 cm of the longitudinal optical mode of the gate insulating layer 28 at a position 0.5 nm away from the silicon carbide layer. -1 The peak frequency of the longitudinal optical mode of the gate insulating layer 28 at any position 0.5 nm or more away from the silicon carbide layer is 1245 cm -1 That's all.

[0094] The gate insulating layer 28 of the MOSFET 100 of the first embodiment is silicon oxide. The peak frequency of the longitudinal optical mode of silicon oxide is an index of the magnitude of strain in the silicon oxide. When the strain in the silicon oxide is large, the peak frequency of the longitudinal optical mode of silicon oxide decreases.

[0095] When silicon oxide is completely unstrained, the peak frequency of the longitudinal optical mode is 1255 cm -1 is.

[0096] The silicon oxide in the gate insulating layer 28 of the MOSFET 100 of the first embodiment does not decrease in peak frequency of the longitudinal optical mode up to the vicinity of the interface with the silicon carbide layer 10. Therefore, the silicon oxide in the gate insulating layer 28 of the MOSFET 100 is in a state of small strain up to the vicinity of the interface with the silicon carbide layer 10.

[0097] This suppresses the strain in gate insulating layer 28 from causing lattice distortion or defects on the surface of silicon carbide layer 10, thereby improving the carrier mobility of MOSFET 100.

[0098] The MOSFET 100 of the first embodiment is manufactured by the method for manufacturing a semiconductor device of the first embodiment, and thereby strain in the gate insulating layer 28 near the interface with the silicon carbide layer 10 is particularly reduced.

[0099] That is, by forming a silicon-rich silicon oxide film, performing a first heat treatment at low temperature and high pressure in an atmosphere containing nitrogen oxide, and performing a second heat treatment in a non-oxidizing atmosphere at a temperature higher than that of the first heat treatment, strain in the gate insulating layer 28 near the interface with the silicon carbide layer 10 is reduced.

[0100] 6 is a process flow diagram of a semiconductor device manufacturing method of the comparative example. The semiconductor device manufacturing method of the comparative example differs from the semiconductor device manufacturing method of the first embodiment in that a heat treatment (step S905) is performed in a high-temperature atmosphere containing nitrogen oxides (NOx), instead of the first heat treatment (step S105) at low temperature and high pressure in an atmosphere containing nitrogen oxides and the second heat treatment (step S106) in a non-oxidizing atmosphere at a temperature higher than the first heat treatment. Also, in the silicon oxide film formation (step S104), the method differs from the semiconductor device manufacturing method of the first embodiment in that a silicon oxide film satisfying the stoichiometric ratio of silicon dioxide is formed.

[0101] In step S905, a heat treatment is performed in an atmosphere containing nitrogen oxides (NOx). The nitrogen oxides are, for example, nitric oxide (NO) or dinitrogen oxide (N2O).

[0102] The temperature of the heat treatment in step S905 is, for example, not less than 1100° C. and not more than 1450° C. The temperature of the heat treatment in step S905 is higher than the temperature of the first heat treatment (step S105) in the method for manufacturing a semiconductor device according to the first embodiment.

[0103] The heat treatment in step S905 forms an interface termination region at the interface between the silicon carbide layer and the silicon oxide film.

[0104] Fig. 7 is a diagram showing the peak frequency of the longitudinal optical mode in the gate insulating layer of a semiconductor device of a comparative example. The semiconductor device of the comparative example is a MOSFET manufactured by the manufacturing method shown in Fig. 6. Fig. 7 is a diagram corresponding to Fig. 3 of the first embodiment. For comparison, Fig. 7 also shows the peak frequency of the longitudinal optical mode in the gate insulating layer of the semiconductor device of the first embodiment.

[0105] 7, in the region of the gate insulating layer of the comparative example close to the silicon carbide layer, the peak frequency of the longitudinal optical mode is reduced. For example, the peak frequency of the longitudinal optical mode at a position 0.5 nm away from the silicon carbide layer is 1200 cm -1 That's about it.

[0106] 7, the MOSFET of the comparative example has a low peak frequency of the longitudinal optical mode in the region of the gate insulating layer close to the silicon carbide layer. That is, the silicon oxide in the gate insulating layer of the MOSFET of the comparative example has large strain near the interface with the silicon carbide layer.

[0107] Therefore, in the MOSFET of the comparative example, the strain in the gate insulating layer causes lattice distortion and defects on the surface of the silicon carbide layer, which reduces the carrier mobility of the MOSFET of the comparative example.

[0108] 8 is a diagram showing the element concentration distribution of a semiconductor device of a comparative example, which is a MOSFET manufactured by the manufacturing method shown in FIG.

[0109] Fig. 8 shows the element concentration distribution in the gate insulating layer, the interface termination region, and the silicon carbide layer. Fig. 8 shows the concentration distribution of nitrogen and carbon. Fig. 8 corresponds to Fig. 4 of the first embodiment.

[0110] The nitrogen concentration distribution has a peak in the interface termination region. The peak nitrogen concentration is, for example, 1×10 21 cm -3 More than 1×10 22 cm -3The peak nitrogen concentration is lower than that of the MOSFET 100 of the first embodiment. In the case of the MOSFET of the comparative example, the nitrogen concentration at the interface termination is low, so that dangling bonds on the surface of the silicon carbide layer may not be terminated sufficiently.

[0111] In the comparative example, high-temperature processing in a nitrogen oxide atmosphere (step S905) simultaneously oxidizes and nitrides the substrate surface. Because oxidation causes the interface to move toward the substrate, it is believed that there is an upper limit to the amount of nitridation, preventing the nitrogen concentration in the interface termination region from becoming high. In the comparative example, interface states remain, which may lead to a decrease in mobility.

[0112] The nitrogen concentration at the first position X, which is 1 nm away from the peak of the nitrogen concentration distribution of the MOSFET of the comparative example toward the gate insulating layer side, is 1×10 18 cm -3 That is, the concentration of nitrogen at the first position X is higher than that in the MOSFET 100 of the first embodiment.

[0113] The carbon concentration distribution of the comparative MOSFET decreases from the interface termination region 40 toward the gate insulating layer 28. The carbon concentration at the first position X is 1×10 18 cm -3 That is, the carbon concentration at the first position X is higher than that in the MOSFET 100 of the first embodiment.

[0114] The MOSFET of the comparative example has a higher concentration of carbon and nitrogen in the gate insulating layer than the MOSFET 100 of the first embodiment. It is believed that the carbon and nitrogen in the gate insulating layer form defects in the gate insulating layer.

[0115] FIG. 9 is an explanatory diagram of defects in the gate insulating layer of the comparative example. FIG. 9 shows a complex containing a carbon atom bonded to an oxygen atom and a nitrogen atom bonded to an oxygen atom. FIG. 9 shows a CON bond. The carbon and nitrogen atoms in the CON bond are inserted into the silicon site of silicon oxide. It is believed that the carbon and nitrogen in the gate insulating layer of the MOSFET of the comparative example form, for example, defects having a CON bond (hereinafter referred to as CON defects).

[0116] The carbon in the gate insulating layer of the comparative example is thought to be derived from carbon released from the silicon carbide layer when the surface of the silicon carbide layer is oxidized. Also, nitrogen from nitrogen oxides in the atmosphere of the heat treatment in step S905 is thought to combine with carbon released from the silicon carbide layer to form CON defects, which remain in the gate insulating layer.

[0117] As shown in FIG. 7, the reason why the strain near the interface of the silicon carbide layer of the gate insulating layer in the MOSFET of the comparative example becomes large is thought to be because many CON defects are formed near the interface of the silicon carbide layer of the gate insulating layer.

[0118] The carbon and nitrogen atoms of the CON defects in the silicon oxide film are inserted into the silicon sites of the silicon oxide. The CON defects in the silicon oxide film can be removed by adding sufficient silicon atoms and nitrogen oxides to the silicon oxide film.

[0119] That is, when there are enough silicon atoms and nitrogen oxides in a silicon oxide film, carbon atoms in CON defects leave the silicon sites as CO gas, and silicon atoms fill the silicon sites. Also, when there are enough silicon atoms and nitrogen oxides in a silicon oxide film, nitrogen atoms in CON defects leave the silicon sites as nitrogen gas (N2), and silicon atoms fill the silicon sites.

[0120] The reaction in which the above-mentioned CON defects are removed from the silicon oxide film is a reaction that energetically stabilizes the system.

[0121] However, if nitrogen oxide is supplied in a high-temperature atmosphere, as in step S905 of the comparative MOSFET manufacturing method, carbon atoms are released from the silicon carbide layer when the surface of the silicon carbide layer is oxidized, resulting in the generation of new CON defects, which makes it difficult to remove the CON defects from the silicon oxide film.

[0122] In the semiconductor device manufacturing method of the first embodiment, a silicon-rich silicon oxide film is formed in step S104, thereby ensuring that a sufficient amount of silicon atoms are present in the silicon oxide film. Furthermore, a first heat treatment is performed in step S105 at low temperature and high pressure in an atmosphere containing nitrogen oxide, thereby suppressing oxidation of the surface of the silicon carbide layer 10 and ensuring that a sufficient amount of nitrogen oxide is present in the silicon oxide film. The first heat treatment is performed at low temperature but high pressure, thereby supplying a sufficient amount of nitrogen oxide to the silicon oxide film. The low temperature allows unstable defects at the SiO2 / SiC interface to be repaired without promoting substrate oxidation. As a result, an interfacial nitrogen-terminated structure containing a sufficient amount of nitrogen is achieved.

[0123] In the MOSFET 100 of the first embodiment, the formation of the silicon-rich silicon oxide film and the first heat treatment can remove CON defects from the silicon oxide film.

[0124] Furthermore, by performing a second heat treatment in a non-oxidizing atmosphere at a temperature higher than that of the first heat treatment, the silicon oxide film from which the CON defects have been removed is densified, resulting in reduced distortion and the formation of a high-density silicon oxide gate insulating layer 28.

[0125] From the viewpoint of suppressing oxidation of the surface of silicon carbide layer 10, the silicon oxide film is preferably formed at a temperature of 350°C or less, and more preferably at a temperature of 300°C or less.

[0126] From the viewpoint of ensuring that a sufficient number of silicon atoms are present in the silicon oxide, the atomic ratio (O / Si) of oxygen (O) to silicon (Si) in the silicon oxide film to be formed is preferably 1.998 or less, and more preferably 1.990 or less.

[0127] The oxygen partial pressure in the atmosphere when forming the silicon oxide film is preferably 10% or less, and more preferably 5% or less. By lowering the oxygen partial pressure in the atmosphere when forming the silicon oxide film, the atomic ratio (O / Si) of oxygen (O) to silicon (Si) in the silicon oxide film to be formed can be reduced. Furthermore, oxidation of the surface of the silicon carbide layer 10 when forming the silicon oxide film can be suppressed.

[0128] To ensure that a sufficient amount of nitrogen oxide is present in the silicon oxide film, the pressure of the first heat treatment is preferably 6 MPa or more, more preferably 7 MPa or more, and even more preferably 10 MPa or more. A pressure of 200 MPa or less allows annealing to be performed using a simple device, so a pressure of 200 MPa or less is preferred.

[0129] In order to ensure that a sufficient amount of nitrogen oxide is present in the silicon oxide film, the first heat treatment is preferably carried out in a supercritical fluid.

[0130] From the viewpoint of suppressing oxidation of the surface of silicon carbide layer 10, the first heat treatment is preferably performed at a temperature of 200°C or less, and more preferably at a temperature of 100°C or less. The high pressure makes it easier to incorporate nitrogen oxide into silicon oxide, so the temperature can be lowered. However, since the higher the temperature, the easier it is to incorporate nitrogen oxide into silicon oxide, a temperature of 30°C or more is preferable, and 35°C or more is more preferable.

[0131] From the viewpoint of increasing the density of the silicon oxide film, the temperature of the second heat treatment is preferably 950° C. or higher, and more preferably 1000° C. or higher.

[0132] From the viewpoint of suppressing oxidation of the surface of the silicon carbide layer 10, the oxygen partial pressure in the atmosphere for the second heat treatment is preferably 100 ppm or less, more preferably 50 ppm or less, and even more preferably 10 ppm or less. The interface between the SiC substrate and the silicon oxide film is nitrogen-terminated by the first heat treatment. Therefore, the oxidation resistance of the SiC substrate is improved, and even a trace amount of oxygen will not oxidize the substrate. From the viewpoint of chamber protection, it is desirable for the oxygen concentration to be 1 ppm or more.

[0133] CON defects in the gate insulating layer form trap levels, which can cause problems such as threshold voltage fluctuations, increased leakage current in the gate insulating layer, and reduced reliability of the gate insulating layer.

[0134] The MOSFET 100 of the first embodiment has a reduced amount of CON defects in the gate insulating layer 28. This reduces the variation in threshold voltage, the increase in leakage current in the gate insulating layer, or the deterioration in reliability of the gate insulating layer, which are caused by CON defects.

[0135] As described above, according to the first embodiment, a semiconductor device and a method for manufacturing the semiconductor device are realized in which the strain in the gate insulating layer is reduced and the carrier mobility is improved.

[0136] (Second embodiment) The semiconductor device of the second embodiment differs from the first embodiment in that it is a trench-gate MOSFET having a gate electrode in a trench. Hereinafter, some of the description overlapping with the first embodiment will be omitted.

[0137] 10 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a MOSFET 200. The MOSFET 200 is a trench-gate MOSFET having a gate electrode in a trench. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers.

[0138] The MOSFET 200 includes a silicon carbide layer 10, a gate insulating layer 28 (silicon oxide layer), a gate electrode 30, an interlayer insulating film 32, a source electrode 34, a drain electrode 36, an interface termination region 40 (region), and a trench 50.

[0139] The silicon carbide layer 10 includes a drain region 12 , a drift region 14 , a p-well region 16 , a source region 18 , and a p-well contact region 20 .

[0140] The trench 50 penetrates the source region 18 and the p-well region 16 and reaches the drift region 14. The bottom surface of the trench 50 is located in the drift region 14.

[0141] A gate insulating layer 28 and a gate electrode 30 are provided in the trench 50. The side surface of the trench 50 is a plane having an off angle of, for example, 0 degrees or more and 8 degrees or less with respect to the m-plane.

[0142] As described above, according to the second embodiment, a semiconductor device with improved carrier mobility can be realized by reducing the strain in the gate insulating layer. In addition, because it is a trench gate type, the channel density per unit area of ​​the chip is increased, and the on-resistance of the MOSFET is reduced.

[0143] (Third embodiment) The semiconductor device of the third embodiment differs from the first embodiment in that a gate insulating layer is present in the termination region of the MOSFET. Some of the description overlapping with the first embodiment will be omitted.

[0144] 11 is a schematic cross-sectional view of a semiconductor device according to the third embodiment. The semiconductor device according to the third embodiment is a MOSFET 300. The MOSFET 300 includes an element region and a termination region provided around the element region. The termination region has a function of improving the breakdown voltage of the MOSFET 300.

[0145] In the element region, for example, the MOSFET 100 of the first embodiment is arranged as a unit cell.

[0146] The termination region is a p-type resurf region 60, p + The gate insulating layer 28 (silicon oxide layer) and the field oxide film 33 are provided.

[0147] The configuration of the gate insulating layer 28 is similar to that of the MOSFET 100 of the first embodiment.

[0148] The field oxide film 33 is, for example, a silicon oxide film.

[0149] An interface termination region containing nitrogen (not shown) is provided between silicon carbide layer 10 and gate insulating layer 28.

[0150] When the MOSFET 300 is turned off, a depletion layer is formed in the resurf region 60, the guard ring region 64, and the drift region 14 between the guard ring regions 64, thereby improving the breakdown voltage of the MOSFET 300.

[0151] However, if the strain in the gate insulating layer 28 is large, defects due to the stress of the gate insulating layer 28 are formed on the surface of the resurf region 60. If defects are formed, for example, the defects may become n-type, preventing the desired depletion layer from being formed. In this case, the breakdown voltage of the MOSFET 300 is degraded.

[0152] According to the third embodiment, the distortion of the gate insulating layer 28 is reduced, and therefore a desired depletion layer is formed in the termination region, realizing a MOSFET with stable breakdown voltage.

[0153] (Fourth embodiment) The inverter circuit and the drive device of the fourth embodiment are an inverter circuit and a drive device that include the semiconductor device of the first embodiment.

[0154] 12 is a schematic diagram of a driving device according to the fourth embodiment. The driving device 700 includes a motor 140 and an inverter circuit 150.

[0155] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, each of which uses the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140.

[0156] According to the fourth embodiment, the inverter circuit 150 and the driving device 700 are provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the inverter circuit 150 and the driving device 700.

[0157] (Fifth embodiment) The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0158] 13 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 800 according to the fifth embodiment is a railcar. The vehicle 800 includes a motor 140 and an inverter circuit 150.

[0159] The inverter circuit 150 is composed of three semiconductor modules that use the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 800 are rotated by the motor 140.

[0160] According to the fifth embodiment, the vehicle 800 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 800.

[0161] (Sixth embodiment) The vehicle of the sixth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0162] 14 is a schematic diagram of a vehicle according to the sixth embodiment. The vehicle 900 according to the sixth embodiment is an automobile. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0163] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0164] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the wheels 90 of the vehicle 900.

[0165] According to the sixth embodiment, the vehicle 900 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 900.

[0166] (Seventh embodiment) The elevator of the seventh embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0167] 15 is a schematic diagram of an elevator according to the seventh embodiment. The elevator 1000 according to the seventh embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0168] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0169] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoisting machine 616, causing the car 610 to rise and fall.

[0170] According to the seventh embodiment, the elevator 1000 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the elevator 1000.

[0171] In the above, the first to third embodiments have been described using an example in which the silicon carbide crystal structure is 4H—SiC, but the present invention can also be applied to silicon carbide with other crystal structures, such as 6H—SiC and 3C—SiC.

[0172] Furthermore, in the first to third embodiments, the gate insulating layer 28 is provided on the silicon surface or the m surface of the silicon carbide layer. However, the present invention can also be applied to cases where the gate insulating layer 28 is provided on other surfaces of silicon carbide, such as the carbon surface, the a surface, or the (0-33-8) surface.

[0173] The present invention can also be applied to an n-channel IGBT (Insulated Gate Bipolar Transistor).

[0174] Furthermore, the present invention is not limited to an n-channel type, but can also be applied to a p-channel type MOSFET or IGBT.

[0175] Furthermore, in the fourth to seventh embodiments, the semiconductor device of the present invention has been described as being applied to vehicles and elevators, but the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0176] Furthermore, in the fourth to seventh embodiments, the semiconductor device of the first embodiment is used as an example, but it is also possible to use the semiconductor device of the second or third embodiment, for example.

[0177] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0178] 10 Silicon carbide layer 28 Gate insulating layer (silicon oxide layer) 30 gate electrode 40 Interface termination area (area) 100 MOSFET (semiconductor device) 200 MOSFET (semiconductor device) 300 MOSFET (semiconductor device) 700 Drive Unit 800 vehicles 900 vehicles 1000 elevators

Claims

1. a silicon carbide layer; The peak frequency of the longitudinal optical mode at a position 0.5 nm away from the silicon carbide layer is 1245 cm －１ the silicon oxide layer; a silicon carbide layer and a silicon oxide layer, the silicon carbide layer and the silicon oxide layer being interposed therebetween, and the concentration of nitrogen is 1×10 ２１ cm －３ The above areas, The semiconductor device has a nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region that has a peak in the region.

2. The concentration of nitrogen at a first position 1 nm away from the peak toward the silicon oxide layer is 1×10 １８ cm －３ the concentration of carbon at the first location is 1×10 or less １８ cm －３ 2. The semiconductor device according to claim 1, wherein:

3. the concentration of nitrogen at a second position 1 nm away from the peak toward the silicon carbide layer is 1×10 １８ cm －３ 2. The semiconductor device according to claim 1, wherein:

4. The nitrogen concentration at the peak is 1×10 ２２ cm －３ 2. The semiconductor device according to claim 1, wherein:

5. The semiconductor device according to claim 1 , further comprising a gate electrode sandwiching the silicon oxide layer between itself and the silicon carbide layer.

6. 6. An inverter circuit comprising the semiconductor device according to claim 1.

7. A driving device comprising the semiconductor device according to any one of claims 1 to 5.

8. A vehicle comprising the semiconductor device according to any one of claims 1 to 5.

9. An elevator comprising the semiconductor device according to any one of claims 1 to 5.

10. forming a silicon oxide film having an atomic ratio of oxygen (O) to silicon (Si) of less than 2 on the surface of the silicon carbide layer by a vapor phase growth method; After forming the silicon oxide film, a first heat treatment is performed in an atmosphere containing nitrogen oxide at a temperature of 350° C. or less and a pressure of 5 MPa or more; After the first heat treatment, a second heat treatment is performed in a non-oxidizing atmosphere at a temperature of 900° C. or higher.

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the silicon oxide film is formed at a temperature of 350[deg.] C. or less.

12. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the nitrogen oxide is dinitrogen oxide.

13. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the first heat treatment is performed in a supercritical fluid.

14. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the oxygen partial pressure in the atmosphere for the second heat treatment is 100 ppm or less.

15. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the silicon oxide film has a thickness of 30 nm or more and 100 nm or less.

16. 11. The method for manufacturing a semiconductor device according to claim 10, further comprising forming a gate electrode on the silicon oxide film after the second heat treatment.

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