Processor, information processing device, and information processing method

Abstract

To provide a processor, an information processing device and an information processing method that improve an arithmetic performance.SOLUTION: A processor is arranged with plurality of cores to which individual destination notification dedicated lines are connected respectively. A destination core selection circuit receives a plurality of packets which has some of the cores as destinations, respectively, executes arbitration, and selects one first core among the cores serving as the destinations of the plurality of packets. A data matching circuit compares first transmission data contained in a packet for the first core with second transmission data contained in a packet for the core other than the first core serving as a destination to participate in the arbitration, extracts one or more second cores of which the second transmission data matches the first transmission data, designates the first core and the second cores as the destinations using the respective destination notification dedicated lines, and transmits the first transmission data through a data notification line.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a processor, an information processing device, and an information processing method. [Background technology]

[0002] In recent years, the development of many-core technology, which implements multiple cores in a single processor, has progressed, and the use of processors with multiple cores has increased. In such processors with multiple cores, there is a technology that transfers register values ​​managed centrally to multiple cores and has each core perform processing. This technology is used, for example, in the field of HPC (High Performance Computing) to perform barrier synchronization. This technology also provides a dedicated line from the register to each core for each destination, allowing packets to be transferred in parallel when sending the same register value to multiple cores, thereby reducing latency.

[0003] For example, in a processor with multiple cores that utilizes control between cores, a central control unit that manages registers is located within the processor, and each core holds a copy of the register. When a register value is updated, the central control unit packets the updated register value and notifies each core, thereby notifying each core of the latest value in its copy register. This allows each core to obtain the register value by referencing its internal copy register without having to refer to the central control unit, thereby reducing the latency of register value read commands.

[0004] In addition, a technology that utilizes register values ​​has been proposed in which data representing the state of an interrupt notification signal and identification information of the calculation unit that output the signal are output, the data are written to a register corresponding to the calculation unit that output the signal, and an interrupt is initiated based on the written data. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-191789 Summary of the Invention [Problem to be solved by the invention]

[0006] However, in conventional methods for notifying each core of register values, even when the same register value is sent to multiple cores, each core is selected in turn through arbitration, and the process of sending packets to the selected core is repeated the number of times corresponding to the number of destination cores. In this way, the processor sends packets while alternating between sending register values ​​to the cores and arbitrating through the arbitration circuit. As the number of destination cores increases, the time required to complete sending all packets increases. For this reason, when notifying the completion of barrier synchronization between cores, for example, delays in register value notification can affect computing performance. To address this delay, it is conceivable to provide dedicated buses for data notification lines between all cores and the central control unit for sending packets notifying register values. However, this approach would require a large wiring area and would be difficult to implement.

[0007] Furthermore, in conventional techniques that control interrupts using data representing the state of an interrupt notification signal and identification information of the processing unit that is the source of the signal, it is possible to reduce the number of signal lines used for interrupt communication, but it is difficult to reduce delays in notifying register values, making it difficult to prevent a decrease in processing performance due to delays in notifying register values.

[0008] The disclosed technology has been made in view of the above, and aims to provide a processor, an information processing device, and an information processing method that improve computing performance. [Means for solving the problem]

[0009] In one aspect of the processor, information processing device, and information processing method disclosed herein, a plurality of cores are arranged, each connected to a separate destination notification dedicated line. A destination core selection circuit receives a plurality of packets addressed to each of the cores, performs arbitration, and selects one first core from among the cores that is the destination of the plurality of packets. A data match circuit compares transmission data included in packets addressed to the first core selected by the arbitration circuit with transmission data included in packets addressed to cores other than the first core that is the destination of participation in the arbitration, extracts one or more second cores whose transmission data values ​​match, and specifies the first core and the second core as destinations using the destination notification dedicated line, and transmits the transmission data to the first core via the data notification line. [Effects of the Invention]

[0010] In one aspect, the present invention can improve the calculation performance. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic diagram of an information processing device. [Figure 2] FIG. 2 is a block diagram showing the details of the CPU. [Figure 3] FIG. 3 is a block diagram illustrating details of the arbitration circuit according to the first embodiment. [Figure 4] FIG. 4 is a sequence diagram of a register value update process according to the first embodiment. [Figure 5] FIG. 5 is a flowchart of a register value update process in the CPU according to the first embodiment. [Figure 6] FIG. 6 is a block diagram illustrating details of the arbitration circuit according to the second embodiment. [Figure 7] FIG. 7 is a sequence diagram of a register value update process when no collision occurs according to the second embodiment. [Figure 8] FIG. 8 is a sequence diagram of a process of updating a register value when a collision occurs according to the second embodiment. [Figure 9] FIG. 9 is a flowchart of a register value update process in the CPU according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of a processor, an information processing device, and an information processing method disclosed in the present application will be described in detail with reference to the accompanying drawings. Note that the processor, the information processing device, and the information processing method disclosed in the present application are not limited to the following embodiments. [Example]

[0013] 1 is a schematic diagram of an information processing apparatus 1. The information processing apparatus 1 includes a central processing unit (CPU) 10, a dual inline memory module (DIMM) 20, and an input / output (I / O) device 30.

[0014] The CPU 10 includes a central control unit 11, cores 101 to 104, a cache 12, a MAC (Memory Access Control) interface 13, and an external bus interface 14. The MAC interface 13 is connected to a DIMM 20. The external bus interface 14 is connected to an I / O device 30.

[0015] The central control unit 11 is connected to each of the cores 101 to 104 via destination notification dedicated lines 201 to 204. The central control unit 11 is also connected to the cores 101 to 104 via a data notification line 210. The central control unit 11 manages the updating and holding of register values ​​used by the cores 101 to 104 in calculations. For example, when the central control unit 11 updates a register value it holds, it notifies the cores 101 to 104 that use the updated register value of the new register value.

[0016] The cores 101 to 104 execute arithmetic processing using register values ​​notified by the central control unit 11, data stored in the DIMM 20, and the like. The register value notification process in the CPU 10 will be described in detail later. Furthermore, the cores 101 to 104 store execution instructions generated by the arithmetic processing in the cache 12. Although four cores 101 to 104 are shown in FIG. 1 as an example, there is no particular limit to the number as long as there is more than one. Furthermore, since the cores 101 to 104 all perform the same operation, in the following description, when there is no need to distinguish between them, they will be referred to as "core 100."

[0017] The cache 12 is connected to the central control unit 11, the MAC interface 13, and the external bus interface 14. The cache 12 stores executable instructions output from the core 100. The executable instructions stored in the cache 12 are then output to the central control unit 11, the DIMM 20, and the I / O device 30 according to their destinations.

[0018] The DIMM 20 is a main memory device that stores data used in calculations by the core 100. The DIMM 20 reads and writes data in accordance with an execution command sent via the MAC interface 13.

[0019] The I / O device 30 is, for example, a hard disk, a solid state drive (SSD), a network interface, etc. The I / O device 30 operates according to an execution command sent via the external bus interface 14.

[0020] 2 is a block diagram showing the details of the CPU. Next, the notification process of the register value of the CPU will be described in detail with reference to FIG.

[0021] The cores 101 to 104 each have copy registers 111 to 114. For example, the cores 101 to 104 check the register values ​​stored in the copy registers 111 to 114, perform barrier synchronization, and proceed with arithmetic processing. Hereinafter, when there is no need to distinguish between the copy registers 111 to 114, the copy registers 111 to 114 will be referred to as "copy registers 110." When using a register value, the core 100 can perform an arithmetic operation using the register value stored in its own copy register 110 without accessing the corresponding registers 131 to 134.

[0022] Next, the operation of the central control unit 11 will be described. As shown in Fig. 2, the central control unit 11 has a central register operation unit 120, registers 131 to 134, and an arbitration circuit 150. The dashed arrows in Fig. 2 indicate the flow of data representing register values. Furthermore, the solid arrows in Fig. 2 indicate the flow of various control data.

[0023] Registers 131 to 134 are arranged to correspond to cores 101 to 104, respectively. The register value held in register 131 is a register value used by core 101. The register value held in register 132 is a register value used by core 102. The register value held in register 133 is a register value used by core 104. The register value held in register 134 is a register value used by core 104. For example, the register value held in register 131 is copied to copy register 111 of core 101, and core 101 performs arithmetic processing using the register value stored in copy register 111. Since registers 131 to 134 all perform the same operation, they will be referred to as "register 130" in the following description unless they are to be distinguished from one another.

[0024] The register 130 generates a register value notification packet for notifying the register value it holds. The register value notification packet includes identification information of the destination core 100 and the register value used by that core 100. The register 130 then outputs the generated packet to the arbitration circuit 150.

[0025] Furthermore, when the register 130 receives an instruction to update the register value, it maintains the old register value while storing the new register value, which is the update data, as standby data.The register 130 then generates a register value notification packet including the new register value and identification information of the destination core 100, and outputs it to the arbitration circuit 150.After that, when the register 130 receives a data update command from the arbitration circuit 150, it updates the register value with the standby data.Then, the register 130 outputs a data update completion notification to the central register operation unit 120.

[0026] The central register operation unit 120 obtains the control command for the register 130 output from the core 100 from the cache 12. Then, the central register operation unit 120 controls the register 130 in accordance with the control command.

[0027] For example, the central register operation unit 120 receives a control command from the core 100 to change a register value. In this case, the central register operation unit 120 updates the register value of the specified register 130 in accordance with the control command. Specifically, the central register operation unit 120 outputs a new register value, which will become update data, to the register 130. Thereafter, the central register operation unit 120 completes updating the register value of the register 130 upon receiving a data update completion notification from the register 130 to which the update data was sent.

[0028] As shown in FIG. 2, the arbitration circuit 150 is individually connected to each of the cores 101 to 104 via destination notification dedicated lines 201 to 204. Hereinafter, when the destination notification dedicated lines 201 to 204 are not distinguished from one another, they will be referred to as the "destination notification dedicated line 200." The arbitration circuit 150 receives register value notification packets from the register 130. The arbitration circuit 150 then arbitrates between the register value notification packets and selects the core 100 to which the register value notification is to be sent. The arbitration circuit 150 then turns on the destination notification dedicated line 200 connected to the selected core 100 to enable the selected core 100. The arbitration circuit 150 then outputs a data update command to the register 130 corresponding to the selected core 100 to update the register value to a new value. Next, the arbitration circuit 150 transmits the new register value to the enabled core 100, and updates the register value held in the copy register 110 of the selected core 100 to the new register value.

[0029] Fig. 3 is a block diagram illustrating details of the arbitration circuit according to the first embodiment. Next, the operation of the arbitration circuit 150 will be described in more detail with reference to Fig. 3. As shown in Fig. 3, the arbitration circuit 150 includes a destination core selection circuit 501, a data match circuit 502, and AND circuits 511 to 514. Since the AND circuits 511 to 514 all have the same function, they will be referred to as "AND circuit 510" in the following description when they are not distinguished from one another.

[0030] One of the two input terminals of the AND circuit 510 is connected to the register 130. The other of the two input terminals of the AND circuit 510 is connected to the data match circuit 502. Furthermore, the output terminals of the AND circuits 510 are connected to the destination notification dedicated lines 200, and are connected to the corresponding cores 100 via the destination notification dedicated lines 200. Furthermore, the destination notification dedicated lines 200 extending from the AND circuit 510 branch off and are connected to the corresponding registers 130.

[0031] The AND circuit 510 receives as one input a signal notifying arbitration participation sent from the corresponding register 130. The signal notifying arbitration participation is included in a register value notification packet generated by the register 130. When the register value held by the register 130 is updated, the signal notifying arbitration participation is turned on. The AND circuit 510 also receives as the other input a destination selection signal from the data match circuit 502. When the core 100 connected to the input-destination AND circuit 510 is selected by the data match circuit 502 as a destination to which the register value, which is update data, is to be sent, the destination selection signal is turned on. When both the signal notifying arbitration participation and the destination selection signal are on, the AND circuit 510 turns on the destination notification dedicated line 200 to enable the connected core 100.

[0032] The destination core selection circuit 501 acquires a signal notifying participation in arbitration sent to each AND circuit 510. Here, if the signal notifying participation in arbitration is on, the core 100 that is the destination of the signal notifying participation in arbitration is the core 100 that will participate in arbitration. Then, the destination core selection circuit 501 selects one core 100 from the cores 100 participating in arbitration as the destination core 100 to which the register value will be transmitted. Here, the core 100 selected as the destination to which the register value will be transmitted is referred to as the "selected update core 100." Thereafter, the destination core selection circuit 501 outputs information about the selected update core 100 and information about the other cores 100 that have notified participation in arbitration to the data match circuit 502.

[0033] The data match circuit 502 receives input of information about the update selected core 100 and information about other cores 100 participating in arbitration from the destination core selection circuit 501. The data match circuit 502 also receives input of register values ​​for each core 100 from the register 130. The register values ​​for the core 100 are included in the register value notification packet generated by the register 130.

[0034] The data match circuit 502 then determines whether or not the other cores 100 participating in the arbitration include an update-matched core 100 whose register value matches the update-selected core 100. If an update-matched core 100 exists, the data match circuit 502 determines whether or not the update-matched cores 100 include an update-unnotified core 100 whose register value has not yet been notified of update.

[0035] If there is no update unnotified core 100, the data match circuit 502 turns on the destination selection signal that is input to the AND circuit 510 connected to the update selected core 100. In this case, the data match circuit 502 leaves the destination selection signal that is input to the AND circuit 510 connected to the other cores 100 off. As a result, the destination notification dedicated line 200 connected to the update selected core 100 is turned on, and the destination notification dedicated line 200 connected to the other cores 100 remains off. Also, in this case, the signal that turns on the destination notification dedicated line 200, output from the AND circuit 510 corresponding to the update selected core 100, is input as a data update command to the register 130 corresponding to the update selected core 100. As a result, the register value of the register 130 corresponding to the update selected core 100 is updated.

[0036] On the other hand, if an update unnotified core 100 is present, the data match circuit 502 turns on the destination selection signal input to the update selected core 100 and the AND circuit 510 connected to the update unnotified core 100. In this case, the data match circuit 502 leaves off the destination selection signal input to the AND circuit 510 connected to the cores 100 other than the update selected core 100 and the update unnotified core 100. As a result, the destination notification dedicated line 200 connected to the update selected core 100 and the update unnotified core 100 is turned on, and the destination notification dedicated line 200 connected to the other cores 100 remains off. Furthermore, in this case, the signal output from the AND circuit 510 corresponding to the update selected core 100 and the update unnotified core 100, which turns on the destination notification dedicated line 200, is input as a data update command to the register 130 corresponding to the update selected core 100. As a result, the register values ​​of the registers 130 corresponding to the update selected core 100 and the update unnotified core 100 are updated.

[0037] Furthermore, the data match circuit 502 transmits the register value, which is update data included in the register value notification packet addressed to the update selected core 100, to the core 100 whose connected destination notification dedicated line 200 is turned on, via the data notification line 210. As a result, the register value held in the copy register 110 of the core 100 whose connected destination notification dedicated line 200 is turned on is updated.

[0038] FIG. 4 is a sequence diagram of the register value update process according to the first embodiment. The arrows connecting the axes represent the transmission and reception of data or command signals. The symbols enclosed in dashed lines on each axis represent the register values ​​held at that time. That is, in this case, the registers 131 and 132 and the copy registers 111 and 112 start processing from a state in which they hold R1 as the register value. Here, an example will be described in which the register values ​​held by the registers 131 and 132 are updated to the same value.

[0039] The central register operation unit 120 transmits the register value R2 to the registers 131 and 132 (steps S101 and S102).

[0040] The register 131 maintains R1 as the register value and holds R2 as standby data. Then, the register 131 generates a register value notification packet whose destination is the core 101 and whose register value of the update data is R2. Thereafter, the register 131 outputs the generated register value notification packet to the arbitration circuit 140, causing the core 101 to participate in arbitration (step S103).

[0041] The register 132 generates a register value notification packet whose destination is the core 102 and whose register value of the update data is R2. Then, the register 132 outputs the generated register value notification packet to the arbitration circuit 140, causing the core 102 to participate in arbitration (step S104).

[0042] Thereafter, the arbitration circuit 140 performs arbitration and selects the core 101 as the update-selected core 100. The arbitration circuit 140 also selects the core 102, whose register value matches that of the core 101, as the update-matching core 100. Furthermore, because the update notification of the register value of the core 102 has not yet been sent, the core 102 is designated as the update-unnotified core 100. The arbitration circuit 140 then outputs a data update command to the registers 131 and 132. As a result, the register values ​​of the registers 131 and 132 are updated to R2 (steps S105 and S106).

[0043] The arbitration circuit 140 also turns on destination notification dedicated lines 201 and 202 connected to core 101, which is the update selected core 100, and core 102, which is the update unnotified core 100. Furthermore, the arbitration circuit 140 outputs R2, which is a register value, as update data using the data notification line 210. As a result, the arbitration circuit 140 transmits R2 as a register value of the update data to copy registers 111 and 112 included in the cores 101 and 102, whose destination notification dedicated lines 201 and 202 are turned on. Upon receiving the update data, the copy registers 111 and 112 update their register values ​​from R1 to R2, which is standby data (steps S107 and S108).

[0044] The registers 131 and 132 transmit a data update completion notification to the central register operation unit 120 (steps S109 and S110), thereby completing the update process of the register values.

[0045] 5 is a flowchart of the process of updating register values ​​in the CPU according to the embodiment 1. Next, the flow of the process of updating register values ​​in the CPU 10 according to the embodiment will be described with reference to FIG.

[0046] The central register operation unit 120 receives register control instructions from one or more cores 100 (step S1).

[0047] Next, the central register operation unit 120, in accordance with the received control command, controls the corresponding register 130. Each register 130, under the control of the central register operation unit 120, determines whether or not to update the register value (step S2).

[0048] If the register values ​​have not been updated in all of the registers 130 (step S2: No), the register value update process ends.

[0049] On the other hand, if the register value is to be updated in any of the registers 130 (step S2: Yes), the register 130 that received the register value update command holds the new register value, which is the updated data, as standby data. Then, the register 130 generates a register value notification packet for notifying the new register value, outputs it to the arbitration circuit 150, and participates in arbitration (step S3).

[0050] The destination core selection circuit 501 of the arbitration circuit 150 receives input of information about the cores 100 participating in the arbitration, which is included in the register value notification packet. Then, the destination core selection circuit 501 selects one update selected core 100 from the cores 100 participating in the arbitration (step S4). Thereafter, the destination core selection circuit 501 outputs the information about the update selected core 100 and information about the other cores 100 participating in the arbitration to the data match circuit 502.

[0051] The data match circuit 502 receives input of information about the update selected core 100 and information about other cores 100 participating in arbitration from the destination core selection circuit 501. Then, the data match circuit 502 determines whether or not the register value that is the update data of the update selected core 100 matches the register value that is the update data of the other cores 100 participating in arbitration (step S5).

[0052] If there is an update-matched core 100 among the other cores 100 participating in arbitration whose update data matches that of the update-selected core 100 (step S5: Yes), the data match circuit 502 determines whether there is an update-unnotified core 100 among the update-matched cores 100 whose register values ​​are before the update notification (step S6).

[0053] If an update unnotified core 100 exists among the update matched cores 100 (step S6: Yes), the data match circuit 502 turns on the destination selection signal input to the AND circuit 510 connected to the update selected core 100 and the update unnotified core 100. As a result, the arbitration circuit 150 turns on the destination notification dedicated line 200 connected to the update selected core 100 and the update unnotified core 100 (step S7).

[0054] Thereafter, the arbitration circuit 150 outputs a signal similar to the signal that turns on the destination notification dedicated line 200 as a data update command to the registers 130 corresponding to the update selected core 100 and the update unnotified cores 100. As a result, the register values ​​of the registers 130 corresponding to the update selected core 100 and the update unnotified cores 100 are updated to standby data. Thereafter, the registers 130 whose register values ​​have been updated output an update completion notification to the central register operation unit 120 (step S8). Thereafter, the register value update process proceeds to step S11.

[0055] On the other hand, if there is no update-matched core 100 whose update data matches that of the update-selected core 100 among the other cores 100 participating in arbitration (step S5: No), or if there is no update-unnotified core 100 among the update-matched cores 100 (step S6: No), the following process is performed: The data match circuit 502 turns on the destination selection signal input to the AND circuit 510 connected to the update-selected core 100. As a result, the arbitration circuit 150 turns on the destination notification dedicated line 200 connected to the update-selected core 100 (step S9).

[0056] Thereafter, the arbitration circuit 150 outputs a signal similar to the signal that turns on the destination notification dedicated line 200 as a data update command to the register 130 corresponding to the update selection core 100. As a result, the register value of the register 130 corresponding to the update selection core 100 is updated to the standby data. Thereafter, the register 130 whose register value has been updated outputs an update completion notification to the central register operation unit 120 (step S10). Thereafter, the register value update process proceeds to step S11.

[0057] Next, the arbitration circuit 150 transmits the register value, which is the update data, to the copy register 110 of the core 100 whose destination notification dedicated line 200 is turned on, and updates the register value held by the copy register 110 to the new register value (step S11).

[0058] As described above, when updating a register value of a specific core, if there is another core that updates its register value to the same value, the processor according to this embodiment updates the register values ​​of the specific core and the other cores that update their register values ​​to the same value together. This allows the processor to reduce the time required to rewrite multiple register values. For example, when performing barrier synchronization between cores, the same register value is notified to multiple cores, reducing the delay in notifying register values ​​and improving computing performance. Furthermore, since there is no need to add a dedicated line or the like for notifying register values, the increase in wiring area can be suppressed. [Example]

[0059] 6 is a block diagram showing details of an arbitration circuit according to a second embodiment. The CPU 10 according to this embodiment differs from the first embodiment in that, when an additional register value update command is received before updating with update data, the CPU 10 executes the subsequent register value update command. In the following explanation, explanations of the operations of the same parts as those in the first embodiment will be omitted.

[0060] 6, in the arbitration circuit 150 according to this embodiment, a data notification line 210 extending from a data match circuit 502 to a core 100 branches off and is connected to each register 130. The register 130 has a function of comparing a register value input from the data notification line 210 with a register value held as standby data.

[0061] When the register 130 receives input of a new register value, which is update data, from the central register operation unit 120, it holds the register value, which is update data, as standby data. Then, the register 130 generates a register value notification packet for notifying the register value, which is update data, and outputs the packet to the arbitration circuit 150, thereby allowing the corresponding core 100 to participate in arbitration.

[0062] Here, if register 130 receives a new register value as the next update data from central register operation unit 120 after participating in arbitration but before receiving a data update command from arbitration circuit 150, register 130 rewrites the waiting data to the register value sent as the next update data. For example, we will explain a case where register 130 participates in arbitration when it receives a first register value as update data, and then receives a second register value as the next update data before receiving a data update command to the first register value. In this case, register 130 holds the waiting data as the first register value, and then rewrites the waiting data from the first register value to the second register value.

[0063] Furthermore, among the registers 130 participating in the arbitration, the registers 130 corresponding to the update selected core 100 and the update unselected cores receive a data update command from the arbitration circuit 150. At this time, in this embodiment, the registers 130 receive input of update data from the arbitration circuit 150 via the data notification line 210. Then, if the waiting data and the update data match, the register 130 updates the register value to the waiting data and outputs an update completion notification to the central register operation unit 120.

[0064] On the other hand, if the waiting data and the update data do not match, the register 130 does not update the register value, but instead sends a register value notification packet with the waiting data as the update data, and rejoins the arbitration. Then, when the register 130 receives the next data update command and the waiting data and the update data match, it updates the register value to the waiting data and outputs an update completion notification to the central register operation unit 120.

[0065] For example, a case will be described in which the register 130 receives a new second register update instruction while the register value update process for the arbitration it participated in based on the register value update instruction using the first register value is incomplete. Here, the register value update process is incomplete when the following two conditions are satisfied. One is a state after the data match circuit 502 receives information about the update selected core 100 and the other cores 100 participating in the arbitration from the destination core selection circuit 501 and starts the destination selection process. The other is a state in which the data update command has not yet arrived at the register 130 corresponding to the core 100 selected as the destination by the data match circuit 502. Hereinafter, this state will be referred to as a "state in which the previous update process is incomplete."

[0066] In this case, the register 130, which holds the second register value as standby data, receives a data update command from the arbitration circuit 150, specifying the first register value as update data. Since the first register value notified as update data differs from the second register value, which is standby data, the register 130 waits without updating the register value. In this case, the register 130 does not output an update completion notification to the central register operation unit 120.

[0067] Thereafter, the register 130 receives a data update command from the arbitration circuit 150, specifying the second register value as the update data. The register 130 then confirms that the notified update data and the standby data are both the second register value and match. The register 130 then updates the register value because the notified first register value matches the second register value, which is the standby data. In this case, the register 130 outputs an update completion notification to the central register operation unit 120.

[0068] After performing arbitration, the destination core selection circuit 501 of the arbitration circuit 150 receives an input of a register value notification packet that notifies new register values, which are update data, from the register 130 corresponding to the core 100 that participated in the arbitration. Here, if a data update command has already been sent to the register 130 corresponding to the update-selected core 100 selected in the previous arbitration or to an update-unnotified core 100, the destination core selection circuit 501 performs arbitration by allowing the core 100 notified as the destination in the register value notification packet to participate. On the other hand, if the previous update process is in an incomplete state, the destination core selection circuit 501 transmits information on the notified register values ​​to the data match circuit 502.

[0069] The data match circuit 502 of the arbitration circuit 150 receives an input of the register value of the update selected core 100 from the destination core selection circuit 501. If an update unnotified core 100 exists, the data match circuit 502 extracts the update unnotified core 100. Here, a case where an update unnotified core 100 exists will be described. However, if there is no update unnotified core 100, the data match circuit 502 executes the following process only on the update selected core 100.

[0070] The data match circuit 502 outputs a destination selection signal to an AND circuit 510 connected to each of the update selected core 100 and the update unnotified core 100. As a result, the destination notification dedicated line 200 connected to the update selected core 100 and the update unnotified core 100 is turned on, and a data update command is input to the register 130 corresponding to each of the update selected core 100 and the update unnotified core 100.

[0071] Here, if a data update command has been output to the register 130 after the previous arbitration, the data match circuit 502 receives input of information on the update selected core 100 and other cores 100 that participated in the arbitration from the destination core selection circuit 501.

[0072] On the other hand, when the next register value notification packet is transmitted from either the update selected core 100 or the update unnotified core 100 in the previous arbitration while the previous update process is incomplete, the data match circuit 502 performs the following process. Here, the update selected core 100 or the update unnotified core 100 in the previous arbitration that transmitted the register value notification packet while the previous update process is incomplete is referred to as the "additional update core 100."

[0073] In this case, the data match circuit 502 receives, from the destination core selection circuit 501, information on the new register value included in the register value notification packet transmitted from the additional update core 100. Thereafter, the data match circuit 502 holds the new register value notified from the additional update core 100 and outputs a destination selection signal to the AND circuits 510 connected to the update selected core 100 and the update unnotified core 100 in the previous arbitration. As a result, a data update command is transmitted to the registers 130 corresponding to the update selected core 100 and the update unnotified core 100 in the previous arbitration. Furthermore, the data match circuit 502 outputs the update data used to update the register value corresponding to the previous arbitration to the data notification line 210 and to each register 130. Thereafter, the data match circuit 502 outputs a destination selection signal to the AND circuit 510 connected to the additional update core 100 and turns on the destination notification dedicated line 200 connected to the additional update core 100. As a result, a data update command is transmitted to the register 130 corresponding to the additional update core 100. Furthermore, the data match circuit 502 outputs the new register value notified by the addition / update core 100 that it holds to the data notification line 210 and also to each register 130 .

[0074] For example, a case will be described in which the update data in the register value update process corresponding to the previous arbitration is a first register value, and then a second register value is transmitted as update data from the additional update core 100. As a process corresponding to the previous arbitration, the data match circuit 502 outputs a destination selection signal to the AND circuit 510 connected to each of the update selected cores 100 and update unnotified cores 100 in the previous arbitration, including the additional update core 100. Furthermore, the data match circuit 502 outputs information on the first register value as update data to each register 130. As an additional update process, the data match circuit 502 outputs a destination selection signal to the AND circuit 510 connected to the additional update core 100. Furthermore, the data match circuit 502 outputs information on the second register value as update data to each register 130.

[0075] 7 is a sequence diagram of a register value update process when no collision occurs according to the second embodiment. In this case, the registers 131 and 132 and the copy registers 111 and 112 start the process from a state in which they hold R1 as the register value. Here, an example will be described in which the register values ​​held by the registers 131 and 132 are updated from R1 to R2, and before the data match circuit 502 starts the destination selection process, the register values ​​held by the registers 131 and 132 are updated from R2 to R3.

[0076] The central register operation unit 120 transmits the register value R2 to the registers 131 and 132 to instruct them to update the register value (steps S201 and S202).

[0077] The register 131 maintains R1 as the register value and holds R2 as standby data. Next, the register 131 generates a register value notification packet whose destination is the core 101 and whose register value of the update data is R2. The register 131 then outputs the generated register value notification packet to the arbitration circuit 140 to participate in arbitration. The arbitration circuit 140 acquires the register value of R2 as update data for the core 101 (step S203).

[0078] The register 132 maintains R1 as the register value and holds R2 as standby data. Next, the register 132 generates a register value notification packet whose destination is the core 102 and whose register value of the update data is R2. The register 132 then outputs the generated register value notification packet to the arbitration circuit 140 to participate in arbitration. The arbitration circuit 140 acquires the register value of R2 as update data for the core 102 (step S204).

[0079] Thereafter, before the data match circuit 502 starts the destination selection process, the central register operation unit 120 transmits the register value R3 to the registers 131 and 132 to instruct them to update the register values ​​(steps S205 and S206).

[0080] The register 131 maintains R1 as the register value and rewrites the waiting data it holds from R2 to R3. Next, the register 131 generates a register value notification packet whose destination is the core 101 and whose register value of the update data is R3. The register 131 then outputs the generated register value notification packet to the arbitration circuit 140 to participate in arbitration. The arbitration circuit 140 acquires a new register value of R3 as update data for the core 101 and rewrites the previously held register value of R2 (step S207).

[0081] The register 132 maintains R1 as the register value and rewrites the waiting data it holds from R2 to R3. Next, the register 132 generates a register value notification packet whose destination is the core 102 and whose register value of the update data is R2. The register 132 then outputs the generated register value notification packet to the arbitration circuit 140 to participate in arbitration. The arbitration circuit 140 acquires a new register value of R3 as update data for the core 102 and replaces the previously held register value R2 (step S208).

[0082] The arbitration circuit 140 performs arbitration according to the register value notification packet in which the update data is the register value of R3, and selects core 101 as the update-selected core 100. The arbitration circuit 140 also selects core 102, whose register value matches that of core 101, as the update-matching core 100. Furthermore, because the update notification of the register value of core 102 has not yet been received, core 102 is designated as the update-unnotified core 100. The arbitration circuit 140 then outputs a data update command to registers 131 and 132. At the same time, the arbitration circuit 140 outputs the register value of R3 as update data to registers 131 and 132. In this case, because both the standby data and the received update data in registers 131 and 132 have the register value of R3, the register values ​​of registers 131 and 132 are updated from R1 to R3, which is the standby data (steps S209 and S210).

[0083] The arbitration circuit 140 also turns on destination notification dedicated lines 201 and 202 connected to core 101, which is the update selected core 100, and core 102, which is the update unnotified core 100. Furthermore, the arbitration circuit 140 outputs the register value R3 as update data using the data notification line 210. As a result, the arbitration circuit 140 transmits R3 as the register value of the update data to the copy registers 111 and 112 of the cores 101 and 102 whose destination notification dedicated lines 201 and 202 are turned on. The copy registers 111 and 112 receive the update data and update their register values ​​from R1 to R3 (steps S211 and S212).

[0084] The registers 131 and 132 do not transmit a data update completion notification, and continue to receive subsequent update commands. This completes one round of register value update processing.

[0085] 8 is a sequence diagram of a register value update process when a collision occurs according to the second embodiment. In this case, the registers 131 and 132 and the copy registers 111 and 112 start the process from a state in which they hold R1 as the register value. Here, an example will be described in which the register values ​​held by the registers 131 and 132 are updated from R1 to R2, and the register value held by the register 131 is updated from R2 to R3 while the previous update process is incomplete.

[0086] The central register operation unit 120 transmits the register value R2 to the registers 131 and 132 to instruct them to update the register value (steps S301 and S302).

[0087] The register 131 maintains R1 as the register value and holds R2 as standby data. Next, the register 131 generates a register value notification packet whose destination is the core 101 and whose register value of the update data is R2. The register 131 then outputs the generated register value notification packet to the arbitration circuit 140 to participate in arbitration. The arbitration circuit 140 acquires the register value of R2 as update data for the core 101 (step S303).

[0088] The register 132 maintains R1 as the register value and holds R2 as standby data. Next, the register 132 generates a register value notification packet whose destination is the core 102 and whose register value of the update data is R2. The register 132 then outputs the generated register value notification packet to the arbitration circuit 140 to participate in arbitration. The arbitration circuit 140 acquires the register value of R2 as update data for the core 102 (step S304).

[0089] Thereafter, while the previous update process is still incomplete, the central register operation unit 120 transmits the register value R3 to the register 131 to instruct it to update the register value (step S305).

[0090] The register 131 maintains R1 as the register value and rewrites the waiting data it holds from R2 to R3. Next, the register 131 generates a register value notification packet whose destination is the core 101 and whose register value of the update data is R3. The register 131 then outputs the generated register value notification packet to the arbitration circuit 140. The arbitration circuit 150 continues the previous update process and acquires a new register value of R3 as additional update data for the core 101 (step S306).

[0091] The arbitration circuit 140 performs arbitration according to the register value notification packet in which the update data is the register value of R2, and selects core 101 as the update-selected core 100. The arbitration circuit 140 also selects core 102, whose register values ​​are both R2 and match core 101, as the update-matching core 100. Furthermore, because the update notification of the register value of core 102 has not yet been received, core 102 is designated as the update-unnotified core 100. The arbitration circuit 140 then outputs a data update command to registers 131 and 132. At the same time, the arbitration circuit 140 outputs the register value of R2 as update data to registers 131 and 132. In this case, since the waiting data is the register value of R3 and the received update data is the register value of R2, which do not match, register 131 does not update its register value and maintains the register value as R1 (step S307). In response to this, the register 132 updates the register value from R1 to R2, which is the standby data, because both the standby data and the received update data are the register value of R2 and match (step S308).

[0092] The arbitration circuit 140 also turns on destination notification dedicated lines 201 and 202 connected to core 101, which is the update selected core 100, and core 102, which is the update unnotified core 100. Furthermore, the arbitration circuit 140 outputs register value R3 as update data using data notification line 210. As a result, the arbitration circuit 140 transmits R2 as the register value of the update data to copy registers 111 and 112 included in cores 101 and 102 whose destination notification dedicated lines 201 and 202 are turned on. Upon receiving the update data, the copy registers 111 and 112 update their register values ​​from R1 to R2 (steps S309 and S310).

[0093] Thereafter, the arbitration circuit 140 outputs a data update command to the register 131 that has received the register value of R3 as new update data. At the same time, the arbitration circuit 140 outputs the register value of R3 as update data to the register 131. In this case, since the standby data and the received update data are the register value of R3 and match, the register 131 updates the register value from R1 to R3, which is the standby data (step S311).

[0094] The arbitration circuit 140 also turns on the destination notification dedicated lines 201 and 202 connected to the core 101, which is the update selected core 100. Furthermore, the arbitration circuit 140 outputs the register value R3 as update data using the data notification line 210. As a result, the arbitration circuit 140 transmits R3 as the register value of the update data to the copy registers 111 of the cores 101 and 102 whose destination notification dedicated lines 201 and 202 are turned on. Upon receiving the update data, the copy register 111 updates the register value from R2 to R3 (step S312). This completes one register value update process.

[0095] 9 is a flowchart of the process of updating register values ​​in the CPU according to the embodiment 2. Next, the flow of the process of updating register values ​​in the CPU 10 according to the embodiment will be described with reference to FIG.

[0096] The central register operation unit 120 receives register control instructions from one or more cores 100 (step S21).

[0097] Next, the central register operation unit 120 controls the corresponding register 130 according to the received control command. Each register 130, under the control of the central register operation unit 120, determines whether or not to update the register value (step S22).

[0098] If the register values ​​have not been updated in all the registers 130 (step S22: No), the register value update process ends.

[0099] On the other hand, if the register value is to be updated in any of the registers 130 (step S22: Yes), the register 130 that received the register value update command holds the new register value, which is the update data, as standby data.Then, the register 130 generates a register value notification packet for notifying the new register value, outputs it to the arbitration circuit 150, and participates in arbitration (step S23).

[0100] The destination core selection circuit 501 of the arbitration circuit 150 receives input of information about the cores 100 participating in the arbitration, which is included in the register value notification packet. Then, the destination core selection circuit 501 selects one update selected core 100 from the cores 100 participating in the arbitration (step S24). Thereafter, the destination core selection circuit 501 outputs the information about the update selected core 100 and information about the other cores 100 participating in the arbitration to the data match circuit 502.

[0101] The data match circuit 502 receives input of information about the update selected core 100 and information about other cores 100 participating in arbitration from the destination core selection circuit 501. Then, the data match circuit 502 determines whether or not the register value that is the update data of the update selected core 100 matches the register value that is the update data of the other cores 100 that participated in arbitration (step S25).

[0102] If there is an update-matched core 100 among the other cores 100 participating in arbitration whose update data matches that of the update-selected core 100 (step S25: Yes), the data match circuit 502 determines whether there is an update-unnotified core 100 among the update-matched cores 100 whose register values ​​are before the update notification (step S26).

[0103] If an update unnotified core 100 exists among the update matched cores 100 (step S26: Yes), the data match circuit 502 turns on the destination selection signal input to the AND circuit 510 connected to the update selected core 100 and the update unnotified core 100. As a result, the arbitration circuit 150 turns on the destination notification dedicated line 200 connected to the update selected core 100 and the update unnotified core 100 (step S27).

[0104] Next, each register 130 receives the data update notification and the update data from the arbitration circuit 150. Then, each register 130 determines whether the notified update data matches the standby data, thereby determining whether there is a register 130 whose update data does not match the standby data (step S28).

[0105] If there is a register 130 whose update data and standby data do not match (step S28: Yes), the register 130 whose update data and standby data do not match will participate in arbitration again (step S29). Here, the register 130 whose update data and standby data do not match will be called a "mismatch register 130."

[0106] Then, the arbitration circuit 150 outputs a signal similar to the signal that turns on the destination notification dedicated line 200 as a data update command to the registers 130 corresponding to the update selected core 100 and the update unnotified cores 100 excluding the mismatch register 130. As a result, the register values ​​of the registers 130 corresponding to the update selected core 100 and the update unnotified cores 100 excluding the mismatch register 130 are updated to standby data (step S30). Thereafter, the register value update process branches into two processes: a process related to the mismatch register 130, and a process related to the registers 130 corresponding to the update selected core 100 and the update unnotified cores 100 excluding the mismatch register 130. The process related to the registers 130 corresponding to the update selected core 100 and the update unnotified cores 100 excluding the mismatch register 130 proceeds to step S31, and the process related to the mismatch register 130 returns to step S24.

[0107] The arbitration circuit 150 transmits the register value, which is the update data, to the copy register 110 of the core 100 whose destination notification dedicated line 200 is turned on, and updates the register value held by the copy register 110 to the new register value (step S31). Thereafter, the register value update process ends.

[0108] On the other hand, if there is no register 130 in which the update data does not match the standby data (step S28: No), the arbitration circuit 150 outputs a signal similar to the signal that turns on the destination notification dedicated line 200 as a data update command to the registers 130 corresponding to the update selected core 100 and the update unnotified core 100. As a result, the register values ​​of the registers 130 corresponding to the update selected core 100 and the update unnotified core 100 are updated to the standby data (step S32). Thereafter, the register value update process proceeds to step S35.

[0109] On the other hand, if there is no update-matched core 100 whose update data matches that of the update-selected core 100 among the other cores 100 participating in the arbitration (step S25: No), the register value update process proceeds to step S33. Similarly, if there is no update-unnotified core 100 among the update-matched cores 100 (step S26: No), the register value update process also proceeds to step S33. In this case, the data match circuit 502 turns on the destination selection signal to be input to the AND circuit 510 connected to the update-selected core 100. As a result, the arbitration circuit 150 turns on the destination notification dedicated line 200 connected to the update-selected core 100 (step S33).

[0110] Thereafter, the arbitration circuit 150 outputs a signal similar to the signal that turns on the destination notification dedicated line 200 as a data update command to the register 130 corresponding to the update selection core 100. As a result, the register value of the register 130 corresponding to the update selection core 100 is updated to the standby data. Thereafter, the register 130 whose register value has been updated outputs an update completion notification to the central register operation unit 120 (step S34). Thereafter, the register value update process proceeds to step S35.

[0111] Thereafter, the arbitration circuit 150 transmits the register value, which is the update data, to the copy register 110 of the core 100 whose destination notification dedicated line 200 is turned on, and updates the register value held by the copy register 110 to the new register value (step S35). Thereafter, the register value update process ends.

[0112] As described above, the processor according to this embodiment does not update the register value or notify the central register operation unit of update completion when the standby data held in the register does not match the update data used for updating. This makes it possible to suppress update completion notification when the register value has not been updated appropriately, and to prevent malfunctions due to a mismatch between the register value update timing and the data transmission timing. [Explanation of symbols]

[0113] 1. Information processing equipment 10 CPU 11 Central Control Unit 12 Cache 13 MAC Interface 14 External Bus Interface 20 DIMM 30 I / O devices 100~104 cores 110~114 Copy register 120 Central register operation unit 130~134 Registers 150 Arbitration circuit 200~204 Destination notification dedicated line 210 Data Notification Line 501 Destination Core Selection Circuit 502 Data Match Circuit 510~514 AND circuit

Claims

1. Multiple cores, each connected to a dedicated line for destination notification, a destination core selection circuit that receives and arbitrates a plurality of packets destined for each of the cores, and selects a first core from among the cores that are destinations of the plurality of packets; a data match circuit that compares first transmission data included in a packet for the first core selected by the destination core selection circuit with second transmission data included in a packet for a core other than the first core that is the destination of participation in the arbitration, extracts one or more second cores for which the second transmission data matches the first transmission data, and transmits the first transmission data via a data notification line, specifying the first core and the second core as destinations using the destination notification dedicated line; A processor comprising:

2. 2. The processor according to claim 1, wherein the data match circuit enables the first core and the second core using the destination notification dedicated line connected to the first core and the second core, and transmits the first transmission data to the enabled first core and the second core via the data notification line.

3. Further comprising a plurality of registers corresponding to each of the cores; The data match circuit receives the packets for arbitration participation, which are addressed to each of the cores and notify a register value as the first transmission data or the second transmission data, from the registers corresponding to the cores, identifies, from the packets, the packets that include the second transmission data and in which the register value notified as the second transmission data matches the register value notified as the first transmission data by a packet including the first transmission data, and extracts the second core that is the destination of the identified packet.

3. The processor according to claim 1 or 2.

4. 4. The processor according to claim 3, wherein the register transmits the packet for arbitration participation notifying the second register value to the data match circuit when there is a difference between the first register value it holds and the newly notified second register value.

5. when transmitting the first transmission data to the first core and the second core, the data match circuit transmits a data update command to the registers corresponding to the first core and the second core together with the first transmission data; When transmitting the packet for arbitration participation, the registers corresponding to the first core and the second core hold the second register value as standby data, receive the data update command and the first transmission data from the data match circuit, and if the second register value matches the register value indicated by the first transmission data, update the first register value to the second register value and terminate the update process, and if the second register value does not match the register value indicated by the first transmission data, retransmit the packet for arbitration participation without updating the first register value.

5. The processor of claim 4.

6. An information processing device having a processor, The processor: Multiple cores, each connected to a dedicated line for destination notification, a destination core selection circuit that receives and arbitrates a plurality of packets destined for each of the cores, and selects a first core from among the cores that are destinations of the plurality of packets; a data match circuit that compares first transmission data included in a packet for the first core selected by the destination core selection circuit with second transmission data included in a packet for a core other than the first core that is the destination of participation in the arbitration, extracts one or more second cores for which the second transmission data matches the first transmission data, and transmits the first transmission data via a data notification line, specifying the first core and the second core as destinations using the destination notification dedicated line; An information processing device comprising:

7. receiving and arbitrating a plurality of packets addressed to some of the cores among a plurality of cores to which individual destination notification dedicated lines are respectively connected, and selecting one first core from among the cores that are the destinations of the plurality of packets; comparing first transmission data included in a packet for the selected first core with second transmission data included in a packet for a core other than the first core that is the destination of participation in the arbitration, extracting one or more second cores for which the second transmission data matches the first transmission data, specifying the first core and the second core as destinations using the destination notification dedicated line, and transmitting the first transmission data via a data notification line; An information processing method characterized by causing a computer to execute processing.

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