Self-diagnosis circuit and semiconductor device

Abstract

A self-diagnostic circuit (BST1) diagnoses an abnormality detection circuit (20) having a first comparator (CMP1) to which a first reference voltage (Vref1) and a voltage based on an abnormality detection target voltage (Vo1) can be inputted. The self-diagnostic circuit has: a voltage switching unit (50) that switches the level of a voltage based on a second reference voltage (Vref2) and outputs same; a first path switching unit (51) that switches between the path on which the voltage outputted from the voltage switching unit is inputted to the first comparator, and the path on which the voltage based on the abnormality detection target voltage is inputted to the first comparator; and a control unit (15) that controls the voltage switching unit and the path switching unit.

Description

[Technical Field]

[0001] The present disclosure relates to self-diagnostic circuits. [Background technology]

[0002] Conventionally, various ICs such as power supply ICs are often equipped with a function for detecting and protecting against abnormalities. Examples of such functions include a function for detecting and protecting against undervoltage of the output voltage of a power supply circuit, a function for detecting and protecting against overvoltage of the output voltage, a function for detecting and protecting against undervoltage of the power supply voltage of an IC (UVLO), and a function for detecting and protecting against overheating of an IC chip (TSD) (see Patent Document 1 for an example of a UVLO function). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-175816 Summary of the Invention [Problem to be solved by the invention]

[0004] Nowadays, it is becoming increasingly important for in-vehicle devices and other equipment to have a self-diagnostic function (BIST: Built-In Self Test).Therefore, there is a demand for ICs to have a self-diagnostic function that diagnoses whether the functions for detecting and protecting against the above-mentioned abnormalities are functioning properly.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a self-diagnostic circuit that can realize an effective configuration for diagnosing whether a circuit that detects an abnormality is functioning normally. [Means for solving the problem]

[0006] One aspect of the present disclosure is a self-diagnostic circuit that diagnoses an abnormality detection circuit having a first comparator to which a voltage based on an abnormality detection target voltage and a first reference voltage can be input, a voltage switching unit that switches and outputs a voltage level based on a second reference voltage; a first path switching unit that switches between a path through which the voltage output from the voltage switching unit is input to the first comparator and a path through which a voltage based on the abnormality detection target voltage is input to the first comparator; a control unit that controls the voltage switching unit and the path switching unit; The self-diagnosis circuit has the following features. [Effects of the Invention]

[0007] The self-diagnosis circuit of the present disclosure can provide an effective configuration for diagnosing whether a circuit for detecting an abnormality is functioning normally. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram illustrating a configuration related to external connections of a PMIC according to an exemplary embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating the internal configuration of a PMIC according to an exemplary embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing the configuration of a self-diagnosis circuit that diagnoses each of the undervoltage detection circuit and the overvoltage detection circuit. [Figure 4] FIG. 4 is a timing chart showing an example of the operation of the PMIC at startup. [Figure 5] FIG. 5 is a timing chart showing an example of the self-diagnosis operation of the undervoltage detection circuit in the analog self-diagnosis mode (A-BIST) or the like. [Figure 6] FIG. 6 is a diagram illustrating a configuration of an abnormality detection circuit according to a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0010] <1. Comparative Example> First, before describing an embodiment of the present disclosure, a comparative example for comparison with the embodiment of the present disclosure will be described. By describing the comparative example, the significance of the present disclosure will become clear.

[0011] FIG. 6 is a diagram showing the configuration of an abnormality detection circuit according to a comparative example. FIG. 6 shows the configuration of an undervoltage detection circuit 101 as the abnormality detection circuit. In addition to the abnormality detection circuit, FIG. 6 also shows the configuration of a self-diagnosis circuit BST101. The circuit configuration shown in FIG. 6 is provided in a power supply IC. The power supply IC has a DC / DC converter function.

[0012] The voltage reduction detection circuit 101 is a circuit that detects a voltage reduction in the output voltage Vo (DC output voltage) due to the DC / DC converter function. Specifically, the voltage reduction detection circuit 101 has a comparator CMP11, an inverter IV11, resistors R11 to R15, and an NMOS transistor (N-channel MOSFET (metal-oxide-semiconductor field-effect transistor)) NM11.

[0013] One end of the resistor R11 is connected to the FB terminal. The output voltage Vo is applied to the FB terminal. The other end of the resistor R11 is connected to one end of the resistor R12 at a node N11. The node N11 is connected to the non-inverting input terminal (+) of the comparator CMP11. One end of the resistor R13 is connected to the terminal to which the reference voltage Vref is applied. The other end of the resistor R13 is connected to one end of the resistor R14 at a node N13. The node N13 is connected to the inverting input terminal (-) of the comparator CMP11. The output terminal of the comparator CMP11 is connected to the input terminal of the inverter IV11 at a node N15. The node N15 is connected to the gate of the NMOS transistor NM11. The source of the NMOS transistor NM11 is connected to the terminal to which the ground potential is applied. The drain of the NMOS transistor NM11 is connected to a node N14 to which the other end of the resistor R14 and one end of the resistor R15 are connected. The other end of the resistor R15 is connected to the terminal to which the ground potential is applied.

[0014] The self-test circuit BST101 also includes an NMOS transistor NM12, a resistor R16, and a control logic unit 100. One end of the resistor R16 is connected to the other end of the resistor R12 at a node N12. The other end of the resistor R16 is connected to a terminal to which a ground potential is applied. The drain of the NMOS transistor NM12 is connected to the node N12. The source of the NMOS transistor NM12 is connected to a terminal to which a ground potential is applied. The control logic unit 100 applies a BIST signal Bst12 as a gate signal to the gate of the NMOS transistor NM12.

[0015] During normal operation, the BIST signal Bst12 is low and the NMOS transistor NM12 is off, which causes the output voltage Vo to be divided by the resistors R11, R12, and R16, and the comparator input signal CMP11INp generated at the node N11 is input to the non-inverting input terminal (+) of the comparator CMP11.

[0016] Furthermore, the NMOS transistor NM11 and resistor R15 are components for a hysteresis function. Specifically, when the output of the comparator CMP11 is Low, the NMOS transistor NM11 is in an OFF state, and a comparator input signal CMP11INn generated at a node N13 by dividing the reference voltage Vref by resistors R13 to R15 is input to the inverting input terminal (-) of the comparator CMP11. When the output of the comparator CMP11 is High, the NMOS transistor NM11 is in an ON state, and a comparator input signal CMP11INn generated at a node N13 by dividing the reference voltage Vref by resistors R13 and R14 is input to the inverting input terminal (-) of the comparator CMP11.

[0017] When the comparator input signal CMP11INp exceeds the comparator input signal CMP11INn and the output of the comparator CMP11 goes high, the undervoltage detection signal UVD, which is the output of the inverter IV11, goes low. On the other hand, when the comparator input signal CMP11INp is equal to or lower than the comparator input signal CMP11INn and the output of the comparator CMP11 goes low, the undervoltage detection signal UVD goes high. Since the undervoltage detection signal UVD is input to the control logic unit 100, the control logic unit 100 determines that the output voltage Vo is in an undervoltage abnormal state based on the undervoltage detection signal UVD going high, and performs protective operation.

[0018] In addition, in the BIST mode (diagnostic mode), the control logic unit 100 sequentially switches between different levels (Low, High) of the BIST signal Bst12 and outputs it. When the BIST signal Bst12 is Low, the NMOS transistor NM12 is in the OFF state, and the output voltage Vo is divided by the resistors R11, R12, and R16 to generate a comparator input signal CMP11INp at the node N11, which is input to the non-inverting input terminal (+) of the comparator CMP11.

[0019] Also, when the BIST signal Bst12 is High, the NMOS transistor NM12 is in the ON state, and the output voltage Vo is divided by the resistors R11 and R12 to generate a comparator input signal CMP11INp at the node N11, which is input to the non-inverting input terminal (+) of the comparator CMP11.

[0020] Therefore, if the comparator CMP11 is operating normally, after the power supply IC starts up and the output voltage Vo rises, if the BIST signal Bst12 is Low in BIST mode, the output of the comparator CMP11 becomes High and the undervoltage detection signal UVD becomes Low.On the other hand, if the BIST signal Bst12 is High in BIST mode, the output of the comparator CMP11 becomes Low and the undervoltage detection signal UVD becomes High.

[0021] In this way, the self-diagnosis circuit BST101 can detect whether the level of the undervoltage detection signal UVD switches by forcibly switching the level of the comparator input signal CMP11INp, and determine whether the undervoltage detection circuit 101 is operating normally.

[0022] However, the self-diagnosis operation is performed after the output voltage Vo has risen and stabilized. In this case, the self-diagnosis operation takes a certain amount of time, so if the abnormality detection function is found to be abnormal, there is a risk that an abnormal output voltage Vo will be output until the self-diagnosis determines that the abnormality detection function is abnormal and the IC is shut down.

[0023] Therefore, it is conceivable to perform a self-diagnostic operation before the output voltage Vo rises. In this case, if the abnormality detection function is abnormal, the IC can be shut down without raising the output voltage Vo. However, since the output voltage Vo at startup is undefined depending on the timing of IC startup, the self-diagnostic operation may not work properly depending on the output voltage Vo. For example, if the output voltage Vo is 0V at startup, in the configuration shown in Figure 6, even if the level of the BIST signal Bst12 is changed, the comparator input signal CMP11INp will only be 0V, and the output logic of the comparator CMP11 cannot be changed. Therefore, the self-diagnostic operation becomes impossible.

[0024] In view of the problems that the inventors of the present application have independently discovered as described above, they have devised a configuration that enables self-diagnosis operation regardless of the value of the abnormality detection target voltage (output voltage Vo in the example of FIG. 6) that is the target for detecting abnormalities by the abnormality detection circuit. Hereinafter, embodiments of the present disclosure will be described.

[0025] <2. PMIC Configuration> Here, the configuration of a PMIC (Power Management IC) according to an exemplary embodiment of the present disclosure will be described. Fig. 1 is a diagram showing a configuration related to external connections of a PMIC 1 according to an exemplary embodiment of the present disclosure. Fig. 2 is a diagram showing an internal configuration of the PMIC 1.

[0026] 1 and 2 is a semiconductor device (power supply IC package) that includes a plurality of power supply circuits for supplying power to an in-vehicle CMOS sensor device 30. The CMOS sensor device 30 is mounted on an in-vehicle camera system.

[0027] As shown in FIG. 1, PMIC1 has external terminals for establishing electrical connection with the outside, including a VIN terminal, a VREG50 terminal, a VREG15 terminal, a BOOT1 terminal, a SW1 terminal, a PGND1 terminal, an FB1 terminal, an FB2 terminal, a PVIN2 terminal, a SW2 terminal, a PGND23 terminal, a SW3 terminal, a PVIN3 terminal, an FB3 terminal, a VO4 terminal, a RSTOUT terminal, a WAROUT terminal, an SCL terminal, an SDA terminal, and a GND terminal.

[0028] As shown in FIG. 2 , the PMIC 1 includes an internal voltage generation unit 2, an internal voltage generation unit 3, a reference voltage generation unit 4, a power supply voltage UVLO (Under Voltage Lock Out) circuit 5, an internal voltage UVLO circuit 6, an internal voltage UVLO circuit 7, an OTP (One Time Programmable ROM) 8, a TSD (Thermal Shut Down) circuit 9, a TW (Thermal Warning) circuit 10, a first DC / DC circuit 11, a second DC / DC circuit 12, a third DC / DC circuit 13, an LDO (Low Dropout) 14, a control logic unit 15, an I2C input / output unit 16, a reset input / output unit 17, and a warning input / output unit 18.

[0029] As shown in FIG. 2 , the PMIC 1 further includes a first overvoltage detection circuit 19, a first undervoltage detection circuit 20, a second overvoltage detection circuit 21, a second undervoltage detection circuit 22, a second undervoltage protection circuit 23, a third overvoltage detection circuit 24, a third undervoltage detection circuit 25, a third undervoltage protection circuit 26, a fourth overvoltage detection circuit 27, a fourth undervoltage detection circuit 28, and a fourth undervoltage protection circuit 29.

[0030] The VIN terminal is connected to an application terminal of a power supply voltage (input power supply voltage) Vin. The internal voltage generation unit 2 generates an internal voltage Vreg50 (=5.0V) based on the power supply voltage Vin applied to the VIN terminal. The internal voltage Vreg50 becomes the power supply voltage for the internal voltage generation unit 3 and the first DC / DC circuit 11. The internal voltage Vreg50 can be output externally from the VREG50 terminal.

[0031] The internal voltage generation unit 3 generates an internal voltage Vreg15 (=1.5V) based on the internal voltage Vreg50. The internal voltage Vreg15 serves as a power supply voltage for each unit in the PMIC 1. The internal voltage Vreg15 is also used as a reference voltage for the first, second, and third DC / DC circuits 11, 12, and 13 and the LDO 14. The internal voltage Vreg15 can be output externally from the VREG15 terminal.

[0032] The reference voltage generating unit 4 generates a first reference voltage Vref1 and a second reference voltage Vref2 based on the internal voltage Vreg15. The first reference voltage Vref1 is used as a reference voltage for various abnormality detection circuits and abnormality protection circuits in the PMIC 1. The second reference voltage Vref2 is used as a reference voltage for a self-diagnosis circuit, which will be described later.

[0033] The power supply voltage UVLO circuit 5 is an abnormality protection circuit that detects an abnormally low voltage of the power supply voltage Vin. The power supply voltage UVLO circuit 5 outputs a UVLO signal UVLOVIN to the control logic unit 15. When an abnormally low voltage of the power supply voltage Vin is detected, the control logic unit 15 shuts down the IC.

[0034] The internal voltage UVLO circuit 6 is an abnormality protection circuit that detects an undervoltage abnormality in the internal voltage Vreg 50. The internal voltage UVLO circuit 6 outputs a UVLO signal UVLOREG50 to the control logic unit 15. When an undervoltage abnormality in the internal voltage Vreg 50 is detected, the control logic unit 15 transitions to a safe mode state.

[0035] The internal voltage UVLO circuit 7 is an abnormality protection circuit that detects an undervoltage abnormality in the internal voltage Vreg 15. The internal voltage UVLO circuit 7 outputs a UVLO signal UVLOREG15 to the control logic unit 15. When an undervoltage abnormality in the internal voltage Vreg 15 is detected, the control logic unit 15 transitions to a standby state.

[0036] The OTP 8 is a ROM that can be written to only once, and stores various data. Data is read from the OTP 8 by the control logic unit 15.

[0037] The TSD circuit 9 is an overheat protection circuit that outputs an overheat protection signal TSD to the control logic unit 15. When the TSD circuit 9 detects that the junction temperature of the IC chip has exceeded a first predetermined temperature (e.g., 175°C), the control logic unit 15 shuts down the IC.

[0038] The TW circuit 10 is an overheat detection circuit that outputs an overheat warning signal TW to the control logic unit 15. When the TW circuit 10 detects that the junction temperature of the IC chip exceeds a second predetermined temperature (< the first predetermined temperature, for example, 140°C), it issues an overheat warning.

[0039] The first DC / DC circuit 11 constitutes a first DC / DC converter 41 (FIG. 1) together with an inductor L1, an output capacitor Co1, and a boot capacitor Cb1 that are arranged outside the PMIC 1. The first DC / DC converter 41 is a step-down converter that receives a power supply voltage Vin (e.g., 15.0 V) as an input and outputs an output voltage Vo1 (e.g., 3.7 V).

[0040] The SW1 terminal is a terminal to which the switching output of the first DC / DC circuit 11 is applied. The SW1 terminal is connected to one end of the inductor L1. The other end of the inductor L1 is connected to one end of the output capacitor Co1. The other end of the output capacitor Co1 is connected to the PGND1 terminal. The PGND1 terminal is connected to the application terminal of the ground potential and is a ground terminal for the first DC / DC circuit 11. The boot capacitor Cb1 forms a bootstrap. One end of the boot capacitor Cb1 is connected to the BOOT1 terminal. The other end of the boot capacitor Cb1 is connected to the SW1 terminal. The boot voltage generated at the BOOT1 terminal is supplied to the high-side driver in the first DC / DC circuit 11.

[0041] An output voltage Vo1 is generated at the node connecting the inductor L1 and the output capacitor Co1 by switching control in the first DC / DC circuit 11. The output voltage Vo1 is applied to the PVIN2 terminal and the PVIN3 terminal, and is used as the input power supply for each of the second DC / DC circuit 12 and the third DC / DC circuit 13.

[0042] The output voltage Vo1 is applied to the FB1 terminal. The FB1 terminal is a terminal for feeding back the output voltage Vo1 to the first DC / DC circuit 11. In addition, the output voltage Vo1 applied to the FB1 terminal is also used as an input power supply for the LDO 14.

[0043] The second DC / DC circuit 12 constitutes a second DC / DC converter 42 (FIG. 1) together with an inductor L2 and an output capacitor Co2 arranged outside the PMIC 1. The second DC / DC converter 42 is a step-down converter that receives an output voltage Vo1 applied to the PVIN2 terminal as an input and outputs an output voltage Vo2 (e.g., 1.1 V).

[0044] The SW2 terminal is a terminal to which the switching output of the second DC / DC circuit 12 is applied. The SW2 terminal is connected to one end of the inductor L2. The other end of the inductor L2 is connected to one end of the output capacitor Co2. The other end of the output capacitor Co2 is connected to the PGND23 terminal. The PGND23 terminal is connected to an application terminal of ground potential and is a ground terminal for the second DC / DC circuit 12 and the third DC / DC circuit 13.

[0045] An output voltage Vo2 is generated at the node where the inductor L2 and the output capacitor Co2 are connected by switching control in the second DC / DC circuit 12. The output voltage Vo2 is supplied to the CMOS sensor device 30 as a power supply voltage. The output voltage Vo2 is also applied to the FB2 terminal. The FB2 terminal is a terminal for feeding back the output voltage Vo2 to the second DC / DC circuit 12.

[0046] The third DC / DC circuit 13, together with an inductor L3 and an output capacitor Co3 arranged outside the PMIC 1, constitutes a third DC / DC converter 43 (FIG. 1). The third DC / DC converter 43 is a step-down converter that receives an output voltage Vo1 applied to the PVIN3 terminal as an input and outputs an output voltage Vo3 (e.g., 1.8 V).

[0047] The SW3 terminal is a terminal to which the switching output of the third DC / DC circuit 13 is applied. The SW3 terminal is connected to one end of an inductor L3. The other end of the inductor L3 is connected to one end of an output capacitor Co3. The other end of the output capacitor Co3 is connected to the PGND23 terminal.

[0048] By switching control in the third DC / DC circuit 13, an output voltage Vo3 is generated at the node where the inductor L3 and the output capacitor Co3 are connected. The output voltage Vo3 is supplied to the CMOS sensor device 30 as a power supply voltage. The output voltage Vo3 is also applied to the FB3 terminal. The FB3 terminal is a terminal for feeding back the output voltage Vo3 to the third DC / DC circuit 13.

[0049] The LDO 14 is a linear regulator that receives the output voltage Vo1 applied to the FB1 terminal as an input and outputs an output voltage Vo4 (e.g., 3.3 V). The output voltage Vo4 is output from the VO4 terminal and supplied to the CMOS sensor device 30 as a power supply voltage. The VO4 terminal is also used as a terminal for feeding back the output voltage Vo4 to the LDO 14.

[0050] The control logic unit 15 is a control unit that controls the PMIC 1 in an overall manner.

[0051] The I2C input / output unit 16 performs I2C communication with the CMOS sensor device 30 via the SDA and SCL terminals. I2C is a type of serial interface. The SDA terminal is used for inputting and outputting serial interface data. The SCL terminal is used for inputting the serial interface clock.

[0052] The reset input / output unit 17 outputs a reset output signal Rsto via the RSTOUT terminal to the CMOS sensor device 30. As will be described later, when an abnormality is detected by the abnormality protection circuit, the reset output signal Rsto is set to a level indicating the abnormality (for example, Low).

[0053] The warning input / output unit 18 outputs a warning output signal Wo via the WAROUT terminal to the CMOS sensor device 30. As will be described later, the warning output signal Wo is set to a level indicating an abnormality (for example, Low) when an abnormality is detected by the abnormality detection circuit or the abnormality protection circuit.

[0054] <3. Abnormality detection circuit> The first overvoltage detection circuit 19, the second overvoltage detection circuit 21, the third overvoltage detection circuit 24, and the fourth overvoltage detection circuit 27 are abnormality detection circuits that detect an overvoltage abnormality.

[0055] The first overvoltage detection circuit 19 is a circuit that detects an overvoltage of the output voltage Vo1 applied to the FB1 terminal and outputs an overvoltage detection signal OVD1. The second overvoltage detection circuit 21 is a circuit that detects an overvoltage of the output voltage Vo2 applied to the FB2 terminal and outputs an overvoltage detection signal OVD2. The third overvoltage detection circuit 24 is a circuit that detects an overvoltage of the output voltage Vo3 applied to the FB3 terminal and outputs an overvoltage detection signal OVD3. The fourth overvoltage detection circuit 27 is a circuit that detects an overvoltage of the output voltage Vo4 applied to the VO4 terminal and outputs an overvoltage detection signal OVD4.

[0056] The first undervoltage detection circuit 20, the second undervoltage detection circuit 22, the third undervoltage detection circuit 25, and the fourth undervoltage detection circuit 28 are abnormality detection circuits that detect undervoltage abnormalities.

[0057] The first voltage reduction detection circuit 20 is a circuit that detects a voltage reduction in the output voltage Vo1 applied to the FB1 terminal and outputs a voltage reduction detection signal UVD1. The second voltage reduction detection circuit 22 is a circuit that detects a voltage reduction in the output voltage Vo2 applied to the FB2 terminal and outputs a voltage reduction detection signal UVD2. The third voltage reduction detection circuit 25 is a circuit that detects a voltage reduction in the output voltage Vo3 applied to the FB3 terminal and outputs a voltage reduction detection signal UVD3. The fourth voltage reduction detection circuit 28 is a circuit that detects a voltage reduction in the output voltage Vo4 applied to the VO4 terminal and outputs a voltage reduction detection signal UVD4.

[0058] The TW circuit 10 is an abnormality detection circuit that detects an overheat abnormality.

[0059] When an abnormality is detected by any of the abnormality detection circuits, the control logic unit 15 continues the active state (normal operating state), but sets the warning output signal Wo to a level indicating an abnormality (for example, Low) to warn the CMOS sensor device 30. At this time, the reset output signal Rsto is set to a level indicating normality (for example, High).

[0060] <4. Abnormality protection circuit> The second under-voltage protection circuit 23, the third under-voltage protection circuit 26, and the fourth under-voltage protection circuit 29 are abnormality protection circuits that detect under-voltage abnormalities.

[0061] The second undervoltage protection circuit 23 is a circuit that detects a voltage drop in the output voltage Vo2 applied to the FB2 terminal and outputs an undervoltage protection signal UVP2. The third undervoltage protection circuit 26 is a circuit that detects a voltage drop in the output voltage Vo3 applied to the FB3 terminal and outputs an undervoltage protection signal UVP3. The fourth undervoltage protection circuit 29 is a circuit that detects a voltage drop in the output voltage Vo4 applied to the VO4 terminal and outputs an undervoltage protection signal UVP4.

[0062] The power supply voltage UVLO circuit 5, the internal voltage UVLO circuits 6 and 7, and the TSD circuit 9 are all abnormality protection circuits.

[0063] If any of the above-mentioned abnormality protection circuits detect an abnormality, the control logic unit 15 transitions to one of a shutdown state, a safe mode state, or a standby state. If an abnormality is detected by the undervoltage protection circuit, the control logic unit 15 transitions to the safe mode. At this time, the control logic unit 15 also sets both the warning output signal Wo and the reset output signal Rsto to a level indicating an abnormality (for example, Low), and notifies the CMOS sensor device 30 of the abnormality.

[0064] The abnormality protection circuit has a function of detecting abnormalities, and therefore can also be regarded as an abnormality detection circuit.

[0065] <5. Self-diagnosis function> The PMIC 1 according to this embodiment has a built-in self test (BIST) function for diagnosing whether the abnormality detection circuit and the abnormality protection circuit are operating normally. The self-diagnosis function will be described below.

[0066] As shown in FIG. 2, a self-diagnosis circuit is provided corresponding to each of the first to fourth overvoltage detection circuits 19, 21, 24, 27, the first to fourth undervoltage detection circuits 20, 22, 25, 28, and the second to fourth undervoltage protection circuits 23, 26, 29 ("A-BIST" in FIG. 2).

[0067] <5-1. Self-diagnosis circuit configuration> Here, the configuration of the self-diagnosis circuit BST1 that diagnoses each of the undervoltage detection circuit 20 and the overvoltage detection circuit 19 will be described with reference to FIG.

[0068] The undervoltage detection circuit 20 includes a comparator CMP1, an inverter IV1, resistors R1 to R3, and an NMOS transistor NM1. More specifically, one end of the resistor R1 is connected to the FB1 terminal. The other end of the resistor R1 is connected to one end of a resistor R2 at a node N1. The node N1 is connected to one end of a second path switching switch SW_UVD2 included in a self-diagnosis circuit BST1 (described later). The other end of the second path switching switch SW_UVD2 is connected to a non-inverting input terminal (+) of the comparator CMP1 at a node N3. The inverting input terminal (-) of the comparator CMP1 is connected to an application terminal of a first reference voltage Vref1 generated by the reference voltage generation unit 4. The output terminal of the comparator CMP1 is connected to an input terminal of the inverter IV1.

[0069] The NMOS transistor NM1 and resistor R3 are provided for the hysteresis function. The output terminal of the inverter IV1 is connected to the gate of the NMOS transistor NM1. The source of the NMOS transistor NM1 is connected to a terminal to which the ground potential is applied. The drain of the NMOS transistor NM1 is connected to a node N2 to which the other terminal of the resistor R2 and one terminal of the resistor R3 are connected. The other terminal of the resistor R3 is connected to a terminal to which the ground potential is applied.

[0070] Furthermore, the self-diagnosis circuit BST1 has a first path switching switch SW_UVD1, a second path switching switch SW_UVD2, a first path switching switch SW_OVD1, a second path switching switch SW_OVD2, a high-side switch SW_BIST_H, a low-side switch SW_BIST_L, resistors R7 to R9, and a control logic unit 15. The first path switching switch SW_UVD1, the second path switching switch SW_UVD2, the first path switching switch SW_OVD1, the second path switching switch SW_OVD2, the high-side switch SW_BIST_H, and the low-side switch SW_BIST_L are each on / off controlled by the control logic unit 15.

[0071] One end of resistor R7 is connected to a node to which a second reference voltage Vref2 generated by the reference voltage generating unit 4 is applied. The other end of resistor R7 is connected to one end of resistor R8 at node N4. The other end of resistor R8 is connected to one end of resistor R9 at node N5. The other end of resistor R9 is connected to a node to which a ground potential is applied.

[0072] The node N4 is connected to one end of the high-side switch SW_BIST_H. The other end of the high-side switch SW_BIST_H is connected to one end of the first path switching switch SW_UVD1 at a node N6. The other end of the first path switching switch SW_UVD1 is connected to a node N3.

[0073] The node N5 is connected to one end of the low-side switch SW_BIST_L. The other end of the low-side switch SW_BIST_L is connected to the node N6 at a node N7.

[0074] The overvoltage detection circuit 19 also includes a comparator CMP2, an inverter IV2, resistors R4 to R6, and an NMOS transistor NM2.

[0075] The configuration of the overvoltage detection circuit 19 is similar to the connection relationship in the configuration of the undervoltage detection circuit 20, so a detailed description of the connection relationship in the configuration of the overvoltage detection circuit 19 will be omitted. The node N7 is connected to one end of the first path switching switch SW_OVD1. The other end of the first path switching switch SW_OVD1 is connected to a node N8 to which the second path switching switch SW_OVD2 and the non-inverting input terminal (+) of the comparator CMP2 are connected.

[0076] <5-2. Operation of the abnormality detection circuit and self-diagnosis circuit> Next, the operation of the configuration shown in Fig. 3 will be described. During normal operation, the first path switching switch SW_UVD1 is in the OFF state, and the second path switching switch SW_UVD2 is in the ON state. In this case, the high-side switch SW_BIST_H and the low-side switch SW_BIST_L are both in the OFF state. As a result, the voltage generated by dividing the output voltage Vo1 applied to the FB1 terminal by R1 to R3 is input as a comparator input signal CMP1IN to the non-inverting input terminal (+) of the comparator CMP1 via the second path switching switch SW_UVD2. The comparator CMP1 compares the comparator input signal CMP1IN with the first reference voltage Vref1.

[0077] As a result, when the comparator input signal CMP1IN, which is a voltage based on the output voltage Vo1, exceeds the first reference voltage Vref1, the output of the comparator CMP1 goes High and the undervoltage detection signal UVD1, which is the output of the inverter IV1, goes Low. On the other hand, when the comparator input signal CMP1IN is equal to or lower than the first reference voltage Vref1, the output of the comparator CMP1 goes Low and the undervoltage detection signal UVD1, which is the output of the inverter IV1, goes High. The undervoltage detection signal UVD1 is input to the control logic unit 15. In this way, when an undervoltage occurs in the output voltage Vo1, the undervoltage detection signal UVD1 goes High, indicating an abnormality, and is notified to the control logic unit 15.

[0078] During normal operation, the first path selector switch SW_OVD1 is in the OFF state, and the second path selector switch SW_OVD2 is in the ON state. In this case, the output voltage Vo1 applied to the FB1 terminal is divided by R4 to R6, and the resulting voltage is input to the non-inverting input terminal (+) of the comparator CMP2 via the second path selector switch SW_OVD2 as the comparator input signal CMP2IN. The comparator CMP2 compares the comparator input signal CMP2IN with the first reference voltage Vref1.

[0079] As a result, when the comparator input signal CMP2IN, which is a voltage based on the output voltage Vo1, is equal to or lower than the first reference voltage Vref1, the overvoltage detection signal OVD1, which is the output of the comparator CMP2, goes low. On the other hand, when the comparator input signal CMP2IN exceeds the first reference voltage Vref1, the overvoltage detection signal OVD1, which is the output of the comparator CMP2, goes high. The overvoltage detection signal OVD1 is input to the control logic unit 15. In this way, when an overvoltage occurs in the output voltage Vo1, the control logic unit 15 can be notified of a high overvoltage detection signal OVD1 indicating an abnormality.

[0080] Furthermore, during the self-diagnosis operation of the undervoltage detection circuit 20, the control logic unit 15 sets the first path switching switch SW_UVD1 to the ON state and the second path switching switch SW_UVD2 to the OFF state. Furthermore, the control logic unit 15 sets the first path switching switch SW_OVD1 to the OFF state. In this case, the control logic unit 15 switches between a first state in which the high-side switch SW_BIST_H is to the ON state and the low-side switch SW_BIST_L is to the OFF state, and a second state in which the high-side switch SW_BIST_H is to the OFF state and the low-side switch SW_BIST_L is to the ON state.

[0081] As a result, in the first state, the voltage (first level voltage) generated at node N4 by dividing second reference voltage Vref2 using resistors R7 to R9 is input as comparator input signal CMP1IN to the non-inverting input terminal (+) of comparator CMP1 via the high-side switch SW_BIST_H and the first path switching switch SW_UVD1. In this case, if comparator CMP1 is operating normally, the output of comparator CMP1 becomes High and the undervoltage detection signal UVD1 becomes Low.

[0082] On the other hand, in the second state, the voltage (second-level voltage) generated at node N5 by dividing second reference voltage Vref2 using resistors R7 to R9 is input as comparator input signal CMP1IN to the non-inverting input terminal (+) of comparator CMP1 via the low-side switch SW_BIST_L and the first path switching switch SW_UVD1. In this case, if comparator CMP1 is operating normally, the output of comparator CMP1 will be low and the undervoltage detection signal UVD1 will be high.

[0083] Therefore, the control logic unit 15 can diagnose whether the undervoltage detection circuit 20 is normal by determining whether the level of the undervoltage detection signal UVD1 switches between High and Low.

[0084] Furthermore, during the self-diagnosis operation of the overvoltage detection circuit 19, the control logic unit 15 turns on the first path switching switch SW_OVD1 and turns off the second path switching switch SW_OVD2. The control logic unit 15 also turns off the first path switching switch SW_UVD1. In this case, the control logic unit 15 switches between the first state and the second state.

[0085] As a result, in the first state, the voltage generated at node N4 by dividing second reference voltage Vref2 using resistors R7 to R9 is input as comparator input signal CMP2IN to the non-inverting input terminal (+) of comparator CMP2 via high-side switch SW_BIST_H and first path switching switch SW_OVD1. In this case, if comparator CMP2 is operating normally, the overvoltage detection signal OVD1 output from comparator CMP2 becomes High.

[0086] On the other hand, in the second state, the voltage generated at node N5 by dividing second reference voltage Vref2 using resistors R7 to R9 is input as comparator input signal CMP2IN to the non-inverting input terminal (+) of comparator CMP2 via low-side switch SW_BIST_L and first path switching switch SW_OVD1. In this case, if comparator CMP2 is operating normally, the overvoltage detection signal OVD1 output from comparator CMP2 will be Low.

[0087] Therefore, the control logic unit 15 can diagnose whether the overvoltage detection circuit 19 is normal by determining whether the level of the overvoltage detection signal OVD1 is switching between High and Low.

[0088] As described above, in this embodiment, the resistors R7 to R9, the high-side switch SW_BIST_H, and the low-side switch SW_BIST_L constitute a voltage switching unit 50 that switches and outputs a voltage level based on the second reference voltage Vref2. The first path switching switches SW_UVD1 and SW_OVD1 and the second path switching switches SW_UVD2 and SW_OVD2 constitute path switching units 51 and 52 that switch between a first path that applies a voltage based on the second reference voltage Vref2 to the comparator and a second path that applies a voltage based on the output voltage Vo1 to the comparator. The first path switching unit 51 is composed of the first path switching switch SW_UVD1 and the second path switching switch SW_UVD2. The second path switching unit 52 is composed of the first path switching switch SW_OVD1 and the second path switching switch SW_OVD2.

[0089] During self-diagnosis operation, the first path selector switches SW_UVD1 and SW_OVD1 are turned on and the second path selector switches SW_UVD2 and SW_OVD2 are turned off, thereby blocking the second path and ensuring the first path. In this state, the high-side switch SW_BIST_H and the low-side switch SW_BIST_L are used to switch between the first state and the second state, causing the voltage switching unit 50 to output voltages of different levels and apply them to the comparator regardless of the output voltage Vo1. This allows the control logic unit 15 to diagnose the abnormality detection circuit based on whether the output level of the comparator has been switched.

[0090] In this way, in this embodiment, the abnormality detection circuit can be diagnosed regardless of the value of the output voltage Vo1, which is the voltage subject to abnormality detection. As a result, as will be described later, it becomes possible to perform a self-diagnosis operation before the output voltage Vo1 rises when the IC is started up.

[0091] <5-3. Modifications, etc.> The self-diagnostic operation for the undervoltage detection circuit 20 and the self-diagnostic operation for the overvoltage detection circuit 19 are performed in chronological order, but the order in which they are performed does not matter.

[0092] Furthermore, the switching between the first state and the second state by the high-side switch SW_BIST_H and the low-side switch SW_BIST_L may start from either state, and the number of times of switching does not matter as long as it is one or more.

[0093] Furthermore, the on / off states of the second path changeover switches SW_UVD2 and SW_OVD2 do not matter in the one abnormality detection circuit that performs the self-diagnosis operation and the other abnormality detection circuit.

[0094] The second overvoltage detection circuit 21 and the second undervoltage detection circuit 22 can also be provided with self-diagnosis circuits having the same configuration as that shown in Fig. 3. Note that, for the second undervoltage protection circuit 23 and its self-diagnosis circuit, configurations similar to the first undervoltage detection circuit 20, the first path switching switch SW_UVD1, and the second path switching switch SW_UVD2 shown in Fig. 3 can be added to the second overvoltage detection circuit 21 and the second undervoltage detection circuit 22.

[0095] The third overvoltage detection circuit 24, the third undervoltage detection circuit 25, the third undervoltage protection circuit 26, and their self-diagnosis circuits, as well as the fourth overvoltage detection circuit 27, the fourth undervoltage detection circuit 28, the fourth undervoltage protection circuit 29, and their self-diagnosis circuits, may be configured in the same manner as the second overvoltage detection circuit 21, the second undervoltage detection circuit 22, the second undervoltage protection circuit 23, and their self-diagnosis circuits.

[0096] Furthermore, in the above, the voltages to be detected for abnormalities were the output voltages Vo1 to Vo4 of the power supply circuit, but this is not limiting. The self-diagnosis circuit may also be configured in a similar manner to the above to detect the power supply voltage Vin, an internal voltage (Vreg50, etc.), or a junction temperature. In other words, the self-diagnosis circuit can be applied to a UVLO circuit or an overheat detection and protection circuit.

[0097] <6. Example of IC startup behavior> 4 is a timing chart showing an example of startup operation of the PMIC 1. In FIG. 4, the control logic unit 15 is in a standby state, and the IC is not operating. In this state, at timing t1, the power supply voltage Vin starts to rise, and accordingly, the internal voltages Vreg50 and Vreg15 also start to rise.

[0098] Then, at timing t2, when the internal voltage UVLO circuit 7 detects that the internal voltage Vreg15 has been released from the UVLO, the control logic unit 15 transitions from the standby state to the digital self-diagnosis mode state (D-BIST).

[0099] If the digital self-diagnosis mode determines that the device is normal, the control logic unit 15 transitions to an OTP load state, where the control logic unit 15 reads data from the OTP 8 and initializes the settings.

[0100] When the OTP load state is completed, the control logic unit 15 transitions to the analog self-diagnosis mode state (A-BIST). In the analog self-diagnosis mode state, the self-diagnosis operations of the various overvoltage detection circuits, undervoltage detection circuits, and undervoltage protection circuits described above are performed. Note that the self-diagnosis operations of the UVLO circuit and overheat abnormality detection / protection circuit may also be performed here, as described above.

[0101] Then, in the analog self-diagnosis mode state, if it is determined that all circuits are normal, and if the UVLO of the power supply voltage Vin and the UVLO of the internal voltage Vreg50 are released, the control logic unit 15 transitions from the analog self-diagnosis mode state to the startup state.

[0102] When the system transitions to the startup state, the control logic unit 15 controls the first to third DC / DC circuits 11, 12, 13 and the LDO 14 to sequentially raise the output voltages Vo1 to Vo4. More specifically, the rise of the output voltage Vo1 starts first, and when the reduced voltage state of the output voltage Vo1 is released and it is detected that the output voltage Vo1 has risen normally, the rise of the output voltage Vo2 starts. Then, when the reduced voltage state of the output voltage Vo2 is released and it is detected that the output voltage Vo2 has risen normally, the rise of the output voltage Vo3 starts. Then, when the reduced voltage state of the output voltage Vo3 is released and it is detected that the output voltage Vo3 has risen normally, the rise of the output voltage Vo4 starts.

[0103] Then, when it is detected that the reduced voltage state of the output voltage Vo4 has been released and that the output voltage Vo4 has risen normally, the control logic unit 15 raises the warning output signal Wo to High. If no abnormality is detected by the abnormality protection circuit within a predetermined delay time after the warning output signal Wo is raised to High, the control logic unit 15 raises the reset output signal Rsto to High and transitions from the startup state to the active state (normal operating state).

[0104] 4, the self-diagnosis operation (A-BIST) can be performed before the output voltages Vo1 to Vo4 rise. This allows the diagnosis to be performed without outputting abnormal output voltages Vo1 to Vo4. If an abnormality is detected, the control logic unit 15 transitions to safe mode.

[0105] <7. Self-diagnosis operation example> 5 is a timing chart showing an example of the self-diagnosis operation of the first undervoltage detection circuit 20 (FIG. 3) in the analog self-diagnosis mode (A-BIST), etc. In FIG. 5, High indicates the on state and Low indicates the off state of the switch.

[0106] As shown in Figure 5, in the analog self-diagnosis mode, the first path selector switch SW_UVD1 is in the ON state, and the second path selector switch SW_UVD2 is in the OFF state. Meanwhile, the ON / OFF states of the high-side switch SW_BIST_H and the low-side switch SW_BIST_L are switched in the order of first state → second state → first state. As a result, the comparator input signal CMP1IN is switched from High to Low to High. In the example of Figure 5, the comparator CMP11 is normal, so the undervoltage detection signal UVD1 is switched from Low to High to Low. Therefore, the control logic unit 15 diagnoses that the undervoltage detection circuit 20 is normal.

[0107] 5, the control logic unit 15 can also transition from the active state to a self-diagnosis mode state (SELF TEST). This transition is made in response to a command from the CMOS sensor device 30 via I2C communication. In this self-diagnosis mode state, the self-diagnosis operation in the undervoltage detection circuit 20 is also performed, as in the analog self-diagnosis mode state.

[0108] <8.Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present invention should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0109] <9. Notes> As described above, for example, a self-diagnosis circuit (BST1) according to one aspect of the present disclosure is a self-diagnosis circuit that diagnoses an abnormality detection circuit (20) having a first comparator (CMP1) to which a voltage based on an abnormality detection target voltage (Vo1) and a first reference voltage (Vref1) can be input, a voltage switching unit (50) that switches and outputs a voltage level based on a second reference voltage (Vref2); a first path switching unit (51) that switches between a path through which a voltage output from the voltage switching unit is input to the first comparator and a path through which a voltage based on the abnormality detection target voltage is input to the first comparator; and a control unit (15) that controls the voltage switching unit and the path switching unit (first configuration).

[0110] In addition, in the above first configuration, the voltage switching unit (50) may have a first switch (SW_BIST_H) having one end connected to a first node (N4) at which a first level voltage based on the second reference voltage (Vref2) is generated, and a second switch (SW_BIST_L) having one end connected to a second node (N5) at which a second level voltage based on the second reference voltage is generated and the other end connected to the other end of the first switch, and the first switch and the second switch may be configured to be on / off controlled by the control unit (15) (second configuration).

[0111] In the second configuration, the voltage switching unit (50) The third configuration includes a first resistor (R7) having one end connected to the application terminal of the second reference voltage (Vref2), a second resistor (R8) having one end connected to the other end of the first resistor and the first node (N4), and a third resistor (R9) having one end connected to the other end of the second resistor and the second node (N5).

[0112] Furthermore, in any of the first to third configurations, the first path switching unit (51) may be configured to include a third switch (SW_UVD1) arranged between a third node (N6) to which a voltage output from the voltage switching unit (50) is applied and an input terminal of the first comparator (CMP1), and a fourth switch (SW_UVD2) arranged between a fourth node (N1) to which a voltage based on the abnormality detection target voltage (Vo1) is applied and the input terminal of the first comparator (fourth configuration).

[0113] Furthermore, in the fourth configuration, the abnormality detection circuit (20) may be configured to include a fourth resistor (R1) having one end connected to the application terminal of the abnormality detection target voltage (Vo1), a fifth resistor (R2) having one end connected to the other end of the fourth resistor and the fourth node (N1), a sixth resistor (R3) having one end connected to the other end of the fifth resistor and a fifth node (N2), and an NMOS transistor (NM1) including a gate driven based on the output of the first comparator and a drain connected to the fifth node (5th configuration).

[0114] Furthermore, in any of the first to fifth configurations, the first reference voltage (Vref1) may be applied to one input terminal of the first comparator (CMP1), the abnormality detection circuit (20, 19) may have a second comparator (CMP2) having one input terminal to which the first reference voltage is applied, and the self-diagnosis circuit (BST1) may have a second path switching unit (52) that switches between a path in which a voltage output from the voltage switching unit (50) is input to the other input terminal of the second comparator and a path in which a voltage based on the abnormality detection target voltage (Vo1) is input to the other input terminal of the second comparator (sixth configuration).

[0115] In any of the first to sixth configurations, the abnormality detection target voltage (Vo1) may be an output voltage of a power supply circuit (41) (seventh configuration).

[0116] In addition, in the seventh configuration, the self-diagnosis operation may be performed before the output voltage (Vo1) rises when starting up the IC (1) including the self-diagnosis circuit (BST1) (eighth configuration).

[0117] Furthermore, a semiconductor device (1) according to an aspect of the present disclosure has a configuration including a self-diagnosis circuit (BST1) having any one of the first to eighth configurations (ninth configuration).

[0118] In addition, the ninth configuration may be configured to include a power supply circuit (14) that supplies power to the in-vehicle device (30), and the abnormality detection target voltage (Vo4) may be an output voltage of the power supply circuit (tenth configuration). [Industrial Applicability]

[0119] The present disclosure can be used, for example, in an automotive PMIC. [Explanation of symbols]

[0120] 1 PMIC 2,3 Internal voltage generator 4. Reference voltage generation section 5 Power supply voltage UVLO circuit 6,7 Internal voltage UVLO circuit 8 One-Time-Pass 9 TSD circuit 10 TW Circuit 11,12,13 DC / DC circuit 14 LDO 15 Control logic section 16 I2C input / output section 17 Reset input / output section 18 Warning input / output section 19 First overvoltage detection circuit 20 First undervoltage detection circuit 21 Second overvoltage detection circuit 22 Second undervoltage detection circuit 23 Second undervoltage protection circuit 24 Third overvoltage detection circuit 25 Third undervoltage detection circuit 26 Third undervoltage protection circuit 27 4th overvoltage detection circuit 28 4th undervoltage detection circuit 29 4th undervoltage protection circuit 30 CMOS sensor device 41 First DC / DC converter 42 Second DC / DC converter 43 Third DC / DC converter BST1 self-diagnosis circuit CMP1, CMP2 comparators Cb1 Boot capacitor Co1~Co3 output capacitors IV1,IV2 inverter L1~L3 inductors NM1, NM2 NMOS transistors R1~R9 Resistors SW_BIST_H High-side switch SW_BIST_L Low-side switch SW_UVD1 1st path selector switch SW_UVD2 Second path selector switch SW_OVD1 1st path changeover switch SW_OVD2 Second path selector switch

Claims

1. A self-diagnosis circuit for diagnosing an abnormality detection circuit, the self-diagnosis circuit having a first comparator to which a voltage based on an abnormality detection target voltage and a first reference voltage can be input, a voltage switching unit that switches and outputs a voltage level based on a second reference voltage; a first path switching unit that switches between a path through which the voltage output from the voltage switching unit is input to the first comparator and a path through which a voltage based on the abnormality detection target voltage is input to the first comparator; a control unit that controls the voltage switching unit and the first path switching unit; and the first path switching unit includes a third switch disposed between a third node to which the voltage output from the voltage switching unit is applied and an input terminal of the first comparator; a fourth switch disposed between a fourth node to which a voltage based on the abnormality detection target voltage is applied and the input end of the first comparator; and the abnormality detection circuit includes a fourth resistor having one end connected to an application end of the voltage to be detected; a fifth resistor having one end connected to the other end of the fourth resistor at the fourth node; a sixth resistor having one end connected to the other end of the fifth resistor at a fifth node; an NMOS transistor including a gate driven based on the output of the first comparator and a drain connected to the fifth node; A self-diagnosis circuit having:

2. A self-diagnosis circuit for diagnosing an abnormality detection circuit, the self-diagnosis circuit having a first comparator to which a voltage based on an abnormality detection target voltage and a first reference voltage can be input, a voltage switching unit that switches and outputs a voltage level based on a second reference voltage; a first path switching unit that switches between a path through which the voltage output from the voltage switching unit is input to the first comparator and a path through which a voltage based on the abnormality detection target voltage is input to the first comparator; a control unit that controls the voltage switching unit and the first path switching unit; and the abnormality detection target voltage is an output voltage of a power supply circuit, A self-diagnostic circuit that performs a self-diagnostic operation before the output voltage rises when starting up an IC including the self-diagnostic circuit.

3. a self-diagnostic circuit having an analog self-diagnostic mode state for diagnosing an abnormality detection circuit having a first comparator to which a voltage based on an abnormality detection target voltage and a first reference voltage can be input, a voltage switching unit that switches and outputs a voltage level based on a second reference voltage; a first path switching unit that switches between a path through which the voltage output from the voltage switching unit is input to the first comparator and a path through which a voltage based on the abnormality detection target voltage is input to the first comparator; a control unit that controls the voltage switching unit and the first path switching unit; and The control unit transitions from a digital self-diagnosis mode state to the analog self-diagnosis mode state.

4. The voltage switching unit a first switch having one end connected to a first node at which a voltage of a first level based on the second reference voltage is generated; a second switch having one end connected to a second node at which a voltage of a second level based on the second reference voltage is generated, and the other end connected to the other end of the first switch; and 4. The self-diagnostic circuit according to claim 1, wherein the first switch and the second switch are on / off controlled by the control unit.

5. The voltage switching unit a first resistor having one end connected to the application terminal of the second reference voltage; a second resistor having one end connected to the other end of the first resistor at the first node; a third resistor having one end connected to the other end of the second resistor at the second node; 5. The self-diagnostic circuit of claim 4, comprising:

6. the first reference voltage is applied to one input terminal of the first comparator; the abnormality detection circuit includes a second comparator having one input terminal to which the first reference voltage is applied; 6. The self-diagnosis circuit according to claim 1, further comprising a second path switching unit that switches between a path through which the voltage output from the voltage switching unit is input to the other input terminal of the second comparator and a path through which a voltage based on the voltage subject to abnormality detection is input to the other input terminal of the second comparator.

7. A semiconductor device comprising the self-diagnosis circuit according to any one of claims 1 to 6.

8. a power supply circuit for supplying power to the in-vehicle device; 8. The semiconductor device according to claim 7, wherein said voltage for which abnormality detection is to be performed is an output voltage of said power supply circuit.

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