Modular System Verification Platform for Computing Devices - Patent application

Abstract

Described herein are apparatus, systems, and techniques relating to a modular system validation platform for a computing device. The modular system validation platform (102) includes an interface board (108) for interfacing a host (106) and a peripheral device (110). The interface board (108) includes a device identifier, a first connector (208-1) configured to couple to the host, and a second connector (212) configured to couple to the peripheral device. The interface board (108) includes a reconfigurable interface circuit (602) to allow different peripheral devices to operate with the host using the same interface board. The interface circuit enables interoperability between the host and the peripheral device by distributing power from the host to the peripheral device and facilitating communication between the host and the peripheral device. Using a reconfigurable interface board to test and troubleshoot the interoperability of the processor and the peripheral device can minimize resources, time, and costs spent during the design and testing phase of the computing device.

Description

[Background technology]

[0001] background Hardware system design often involves integrating a central platform (e.g., a platform containing a specific processor) with a set of peripherals (e.g., a camera, keyboard, hard drive) to form a new platform based on the specifications and functionality desired for the end product. Some peripherals provide core functionality for the new platform, such as an embedded controller that controls many aspects of the power system and peripheral interaction. Other peripherals may be more accessory, such as an input device or storage interface (e.g., a Secure Digital Card (SD Card) slot). Many of these peripherals have interoperability requirements, including peripheral-specific data signaling, level shifting, power, and power sequencing.

[0002] One approach to designing and testing a new platform is to copy the reference schematics for connecting peripherals from the current platform onto the new platform's circuit board and then adjust the design to meet the new platform's sequencing and signaling requirements. However, this process is typically error-prone and can result in improper voltages, undesirable power leakage paths, cost-ineffective interfaces, and other integration issues. Often, the problems are discovered and fixed on the next circuit board, but the next circuit board introduces a different combination of issues, causing the problems to recur. This regression can occur when more peripherals are added to the subsequent platform or when one or more of the peripherals on the new platform are replaced with different peripherals on the subsequent platform. These integrations can require extensive and time-consuming reviews, repeated circuit board fabrications, and testing to ensure the interoperability of the integrated hardware system. Summary of the Invention [Problem to be solved by the invention]

[0003] overview This document describes apparatus, systems, and techniques directed to a modular system verification platform for computing devices. Aspects described below include an apparatus for verifying a system including a host and at least one peripheral device. The apparatus includes a printed circuit board (PCB) including a device identifier. The apparatus further includes a first connector coupled to the PCB and configured to couple to the host, and a second connector coupled to the PCB and configured to couple to the peripheral device. The apparatus further includes an interface circuit coupled to the PCB between the first and second connectors, the interface circuit configured to enable the host to operate with the peripheral device by distributing power from the host to the peripheral device or by facilitating communication between the host and the peripheral device. Aspects of the present disclosure may enable rapid prototyping or more efficient development of new computing devices or systems. In some cases, the reconfigurable interface circuit may enable the reuse of an apparatus to test multiple processor and peripheral device combinations without redesigning and manufacturing a new verification platform, thus minimizing resources, time, and costs associated with designing and prototyping new computing devices. Additionally, aspects of the present disclosure may enable dynamic reconfiguration of the interface circuit so that alternative implementations of the interface circuit can be tested without disengaging the host and peripheral, potentially enabling rapid circuit optimization without the time and resources associated with redesigning and building a new verification platform.

[0004] This summary introduces simplified concepts related to a modular system validation platform for computing devices, which is further described in the detailed description and drawings. This summary is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.

[0005] The details of one or more aspects of a modular system validation platform for computing devices are described herein with reference to the following figures, wherein the same numbers are often used to reference like features and components throughout the drawings. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 illustrates an example environment for a modular system verification platform for computing devices. [Figure 2] FIG. 1 illustrates an example of a modular system verification platform for a computing device including a host board, an interface board, and a peripheral board implemented in accordance with one or more aspects. [Figure 3] 3 illustrates the host board of FIG. 2 as it may be implemented in a modular system verification platform for computing devices. [Figure 4] FIG. 1 illustrates an exemplary host board including an intelligent module and a debug bridge module in accordance with one or more aspects. [Figure 5] 3 illustrates the peripheral board of FIG. 2 as it may be implemented in a modular system verification platform for a computing device. [Figure 6-1] 3 illustrates the interface board of FIG. 2 as it may be implemented in a modular system verification platform for a computing device. [Figure 6-2]FIG. 2 illustrates a multiplexer interface board of an example modular system verification platform for computing devices. [Figure 6-3] 1A-1C illustrate example configurations of multiplexer interface boards, according to one or more aspects. [Figure 6-4] 1A-1C illustrate example configurations of multiplexer interface boards, according to one or more aspects. [Figure 7] FIG. 1 illustrates an exemplary method for operation of an interface board of a modular system validation platform, in accordance with one or more aspects. [Figure 8-1] FIG. 1 illustrates a detailed exemplary method for operations implemented by an interface board of a modular system verification platform for a computing device. [Figure 8-2] FIG. 1 illustrates a detailed exemplary method for operations implemented by an interface board of a modular system verification platform for a computing device. DETAILED DESCRIPTION OF THE INVENTION

[0007] Detailed Description Overview Many processor manufacturers create reference platforms that allow system designers to test specific processors with multiple types of peripherals. These reference platforms typically include generic or predefined input / output (I / O) interfaces that allow limited plug-and-play functionality for basic data interface testing of different peripheral devices or chips. While useful for determining the functional accuracy of peripheral designs, the generic I / O interfaces of reference platforms generally do not translate directly into finalized or marketable system designs. The interfaces to each peripheral are often simplified, non-configurable, and limited to avoid various integration issues. While these reference platforms focus on processor bring-up, they are often not modular or have limited modularity for different types of peripherals. Processor bring-up involves connecting peripherals to simple interfaces, powering up the system, and checking functionality or compatibility in a single power state or with a single peripheral configuration. Furthermore, the peripherals for these reference platforms are often vendor-specific and statically configured for a particular reference platform. Peripheral modules designed for one vendor's reference platform may not work on a reference platform from a different vendor. Thus, while the reference platform design may form a general basis for circuits capable of interfacing with processors and peripherals, achieving the reliability and functionality required for the final product (e.g., the computing device being designed) typically requires redesign and iterative testing, resulting in wasted resources and effort. As the project progresses beyond the preliminary schematic stage, the reference platform may be neglected and become less useful for bringing about new or modified peripheral configurations.

[0008] In contrast to prior art for system verification, the present disclosure describes aspects of a modular system verification platform for computing devices that includes apparatus (e.g., interface boards) for interfacing a processor (e.g., a processor residing on a host board) with a peripheral device (e.g., a peripheral device residing on a peripheral board). Each interface board, host board, and peripheral board is a module. The modules can be arranged in different configurations depending on the desired functionality of the end product. In aspects, the interface board includes an identifier, which can be a digital ID code or circuitry, that identifies the interface board. The identifier can be provided to the host board, allowing the host board to verify that the interface board is the expected one in the current configuration of the verification platform. The interface board includes reconfigurable circuitry that allows different peripheral boards to operate with the processor board using the same interface board. The interface board can also include circuitry that monitors power and communication signals interfaced between the host board and the peripheral board. In some implementations, the circuitry of the interface board allows for configuration and / or monitoring of electrical nets, nodes, or paths (e.g., signal lines or power rails on internal PCB layers) that are not exposed on external layers or contacts (e.g., test points or connector headers) of the interface board or peripheral board. Thus, the interface board can enable control (e.g., level shifting or power sequencing) and measurement of electrical signals not normally exposed by preceding host, peripheral, or adapter boards. Any particular configuration (e.g., hardware settings or associated metadata) of the interface board circuitry can also represent or correspond to a hardware schematic that can be used when generating a schematic of a computing device including a processor and peripherals, thereby eliminating the need for repetitive board turns to reconfirm the interface circuitry.

[0009] The modular system verification platform (e.g., modular reference platform) for a computing device described herein can provide a modular reference platform that is highly reusable and applicable to end products or finalized system designs for computing devices. Some of the described advantages can be obtained through a configurable interface layer (e.g., interface board) that couples a host board to one or more peripheral boards. In one example, the interface board can accept a configuration file provided by the host board (e.g., a system configuration module) and provide level shifting and versatile power sequencing between peripheral devices and the host board containing the processor. The level shifting can be configured to direct connect, emulate common level shifting techniques, or a combination thereof. Power sequencing can be configured to accept any logical combination of signals from a connector coupled to the host board and use them to control load switches that distribute power to the peripheral boards. In a simple non-sequenced configuration, the load switches may always be on, while other sequenced configurations may sequence multiple power rails of a peripheral device to simulate bring-up, standby states, sleep states, bring-down, etc. In this way, circuitry specific to a modular reference platform can be implemented on an interface board, which can be physically installed between the host board and one or more peripheral boards to provide modularity and flexibility for system verification. In some cases, the interface board can be reused across any combination of host and peripheral boards. By centralizing the complexity of the reference design on the interface board, the complexity of the host and peripheral boards can be kept relatively simple, minimizing costs. Furthermore, the configuration (or reconfiguration) of the interface boards can be automated via their respective configuration files, eliminating the need to manually configure jumpers or switches on each peripheral's interface board.

[0010] In some aspects, to accommodate the wide range of functions that may be implemented in peripheral devices, connectors on interface boards, host boards, and peripheral boards may include more signal and power connections than typical designs for end products or finalized system designs. As described herein, a modular system verification platform strategy allows multiple types of peripheral devices to be connected to a host board using these enhanced, yet predefined, interfaces, which may include standardized data interfaces and additional sideband signals (e.g., for configuring the interface board). Furthermore, the predefined interfaces of an interface board, host board, or peripheral board can be used to test multiple platforms.

[0011] The described modular system verification platform also allows for increased design flexibility between implementing hardware and software configurations. The interface circuitry configured on the interface board can be fully defined in a configuration file. This allows software to generate a final product schematic using the configuration file, the host design, and the peripheral design. The schematic may include optimized or compacted circuitry (e.g., a folded schematic) that proves useful for the current platform and may not include circuitry that is redundant to the final product (e.g., unconfigured circuitry, monitoring and debug circuitry). In this way, the final product's circuit board assembly can be laid out and manufactured with equivalent functionality, software, and behavior to that verified on the modular platform.

[0012] In certain aspects, the modular system verification platform for computing devices described herein may provide additional opportunities for telemetry and debug assistance that may not be available in prior reference platforms. The described interface boards may be designed to provide a switching fabric that allows multiple alternative peripheral implementations, enabling comparison between solutions and highly scalable testing. For example, the interface board may provide power measurements of individual component power rails, as opposed to bulk measurements of the components. Similarly, the interface board may allow analog monitoring of logic signals to attached peripheral boards to verify expected operation or monitor for voltage or current leakage issues. The electrical paths or nets of the interface board that are measured or monitored may not be exposed to the interface board's outer layers or contacts; that is, test headers, leads, pads, or additional test equipment may not be required to debug or characterize the electrical interface between the host and peripheral. Alternatively or additionally, some interface boards may provide novel peripheral interfaces by combining multiple existing peripheral connectors onto a single board.

[0013] In prior reference platforms, many of the described features would be prohibitively expensive and resource intensive to implement on a platform or peripheral reference board because the circuitry must be included on every reference board of a particular peripheral type. As described herein, a modular system verification platform that includes these features on interface boards enables a developer or laboratory setup to have one set of interface boards that can be used with any number of different host and peripheral boards. Furthermore, removing complex circuitry from the host and peripheral boards allows those boards to be manufactured more cheaply than prior static or fixed reference platforms.

[0014] Example environment 1 illustrates an example environment 100 of a modular system validation platform 102 for a computing device 104. The example environment 100 may represent a development lab for a platform manufacturer, a processor manufacturer, a peripheral manufacturer, or any individual or organization that designs, manufactures, or tests computing platforms. In this example, the computing device 104 is designed in a development lab that includes a modular system validation platform 102 for computing devices.

[0015] Examples of computing devices 104 may include mobile computing devices, mobile communication devices, modems, cellular or mobile phones, mobile stations, gaming devices, navigation devices, media or entertainment devices (e.g., media streamers or game controllers), laptop computers, desktop computers, tablet computers, smart appliances, vehicle-based computing systems, wearable computing devices (e.g., clothing, watches, or reality-altering glasses), Internet of Things (IoT) devices, sensors, inventory control devices, computing portions of machines or equipment (e.g., vehicles or robots), server computers or portions thereof (e.g., server blades or racks, or another portion of a data center), etc. Illustrated examples of computing devices 104 in FIG. 1 include smartphone 104-1, tablet 104-2, laptop computer 104-3, and desktop computer 104-4.

[0016] In an exemplary implementation, the computing device 104 includes one or more integrated circuits (ICs) corresponding to the processor, memory, and peripherals of the computing device 104. The ICs may be implemented as one or more respective IC chips or IC packages mounted on a module, card, or printed circuit board (PCB) of the computing device 104. Examples of PCBs include flexible PCBs, rigid PCBs, single-layer or multi-layer PCBs, surface-mount or through-hole PCB assemblies, combinations thereof, etc. Each integrated circuit may be realized as a general-purpose processor, a system-on-chip (SoC), a security-oriented IC (e.g., a root-of-trust (RoT) IC chip), a memory chip, a communications IC (e.g., a modem or radio frequency IC), a graphics processor, an artificial intelligence (AI) accelerator, combinations thereof, etc. The integrated circuits may be packaged individually or together with other IC chips. The computing device 104 also includes a power system, which may be implemented as one or more power supplies and a power distribution network configured to provide power to the ICs and circuits of the computing device 104.

[0017] In one aspect, the modular system verification platform 102 includes a host board 106 (e.g., a PCB) that includes instances of the processor ICs, memory ICs, and power system (or power system ICs) of the computing device 104. In other words, the host board 106 may include the core components of the computing device without peripheral or peripheral interface circuitry. The memory may be random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NVRAM), or other variations of short-term memory. The host board may further include system configuration and debug circuitry. The system configuration and debug circuitry may be additional circuitry on the host board or on one or more separate PCBs coupled to the host board via respective connectors.

[0018] The modular system verification platform 102 may include one or more interface boards 108. Generally, the interface board 108 may include a reconfigurable interface circuit designed to interface the host board 106 to one or more peripheral boards 110. As described herein, the interface circuit may enable selective control of power and / or signals between the host board 106 and the peripheral board 110. The peripheral board 110 may include at least one peripheral device (e.g., peripheral ICs and related components) integrated with the processor and integrated circuits of the host board 106. In this example, four peripheral boards 110, which may include the same type of peripheral device (e.g., a hard drive) or different types of peripheral devices (e.g., a camera, a fingerprint reader, a mouse, a keyboard, a battery, etc.), are interfaced to the host board 106 via four respective interface boards 108. However, any quantity or combination of peripheral boards 110 based on the specifications of the computing device 104 may be interfaced to the host board 106 using the interface boards 108. In some embodiments, the interface board 108 may include multiple connectors (e.g., with multiplexed power and / or signals) for interfacing multiple peripheral boards 110 to the host board 106. The modular system verification platform 102 may enable interchangeable host boards 106 and peripheral boards 110 using the same set of interface boards 108. Furthermore, the peripheral boards 110 may be added, removed, or swapped (e.g., hot-swapped while power is applied to the host board 106) to rapidly test and evaluate different configurations of the computing device 104 (compared to a conventional reference platform).

[0019] Example architecture FIG. 2 illustrates an exemplary modular system verification platform 200 for a computing device including a host board (e.g., host board 106), an interface board (e.g., interface board 108), and a peripheral board (e.g., peripheral board 110) implemented in accordance with one or more aspects. Interface board 108 is configured to interface host board 106 with peripheral board 110. In some aspects, interface board 108 can be reconfigured to interface a peripheral board of a similar type to peripheral board 110. For example, if peripheral board 110 included a fingerprint reader (e.g., a fingerprint IC and sensor) manufactured by a first manufacturer, interface board 108 can be reconfigured to interface a peripheral board including a fingerprint reader manufactured by a second manufacturer. In other aspects, interface board 108 can be reconfigured to interface with other types of peripheral devices, such as, for example, a fingerprint reader swapped with an external hard drive.

[0020] The interface board 108 is coupled to the host board 106 by a predefined board connection 208-1. The predefined board connection 208, or connector interface, may include conductors for a predefined I / O signal port (e.g., a first USB or PCIe port), one or more power rails, and / or out-of-band control lines (or a second USB port) that allow the host board 106 to control or configure the circuitry of the interface board 108. The board connection 208-1 includes a connector on the host board 106 that is coupled to a connector on the interface board 108. The predefined board connection 208-2 represents one or more board connections 208 for connecting an additional board chain (e.g., a combination of the interface board 108 and a peripheral board 110) 210 to the host board 106. The additional board chain 210 may include a peripheral board similar to the peripheral board 110 or a peripheral board different from the peripheral board 110, depending on the specifications of the computing device 104.

[0021] The interface board 108 is coupled to the peripheral board 110 by board connections 212. The board connections 212 include board connectors on the peripheral board 110 coupled to board connectors on the interface board 108. The host board 202, interface board 204, and peripheral board 206 are described in more detail with reference to Figures 3-6, respectively.

[0022] 3 illustrates the host board 106 of FIG. 2 that can be implemented in a modular system verification platform for a computing device. The host board 106 includes core components of the computing device being prototyped, such as the SoC 302, the DRAM 304, a power management integrated circuit (PMIC) 306, and an SoC debug circuit 308. In some aspects, the host board 106 may include control circuitry (not shown) having configuration data indicating power and communication details of the host board. The host board 106 includes one or more predefined board connectors 310 (included in the board connections 208) for attaching a board chain. The core components may be coupled to each other on the host board PCB according to the specifications of the SoC 302 and other core components (e.g., the DRAM 304, the PMIC 306).

[0023] The core components are coupled to the board connector 310 with predefined circuitry 312 to allow for a configurable signal and / or power interface. The predefined circuitry 312 may include multiple power and signal paths between the core components and the board connector 310 that may or may not be utilized depending on the board chain coupled to the host board 106. The multiple power and signal paths allow for testing many different peripherals along with the core components of the host board 106. Any portion of the predefined circuitry 312 that is not utilized to power or communicate with a particular peripheral may not be included in the final schematic of the computing device being prototyped.

[0024] In some embodiments, host board 106 may represent a core platform of a particular processor or SoC manufacturer. Other host boards may be similar to host board 106 but represent core platforms of other SoC or processor manufacturers. Alternatively, host boards similar to host board 106 may be manufactured with the same SoC but with different additions or subtractions of memory, PMICs, and other components. However, predefined circuitry 312 may be included on any host board and modified to accommodate the power and signals available for a particular configuration of core components. Additionally, board connectors 310 are predefined so that interface boards included in a modular system verification platform (e.g., modular system verification platform 102) can connect to board connectors 310 on any host board. Any configuration of a core platform under development may be represented as a host board similar to host board 106.

[0025] 4 illustrates an exemplary host board 400 including an intelligent module 402 and a debug bridge module 404 in accordance with one or more aspects. The host board 400 may be similar to and include the same components as the host board 106. As shown in FIG. 4, the host board 400 includes an SoC 302, a DRAM 304, a power management integrated circuit (PMIC) 306, an SoC debug circuit 308, and a board connector 310. Additionally, the host board 400 may provide configuration and debug functionality through the intelligent module 402 and the debug bridge module 404, respectively. In some aspects, the intelligent module 402 and the debug bridge module 404 are separate PCBs coupled to the host board 400. In other aspects, one or both of the intelligent module 402 and the debug bridge module 404 are additional ICs and circuits included on the host board.

[0026] In an aspect, the intelligent module 402 can control the system configuration and reconfiguration of a modular system verification platform for a computing device. For example, the intelligent module 402 can determine or select respective configuration information to provide configuration for one or more interface boards 108. In some cases, the intelligent module also includes or manages a power supply that provides power to the control plane (e.g., for the configuration plane) of every board included in the modular system verification platform. The control plane can include circuitry that powers and communicates with board management logic (e.g., identifiers, non-transitory computer-readable media (CRM) including control circuitry) on the host board, peripheral boards, and interface boards. The intelligent module can use the control plane to configure the modular system verification platform independently of the functional circuit being tested.

[0027] The intelligent module may include a SoC 406 and a CRM 408 (e.g., read-only memory (ROM), flash memory, EEPROM) for storing a configuration module 410 and configuration data 412 for the platform being prototyped or tested. The configuration module 410 includes instructions that, when executed by the SoC 406, launch the control plane of the modular system verification platform and enable the configuration module 410 to detect and identify the host board 106, interface board 108, and peripheral board 110 that are part of the modular system verification platform. If the host board 106, interface board 108, or peripheral board 110 does not provide an identifier or provides an invalid identifier (e.g., based on a library of intelligent models of supported boards), the instructions may not allow the host board 106 to launch and / or disable other functionality of the modular platform. The configuration module 410 also includes instructions that, when executed by the SoC 406, configure the interface board 108 (e.g., configure level shifters, configure power sequencers, and load switches) to provide power from the host board 106 to the peripheral board 110 and establish communication between the host board 106 and the peripheral board 110. The configuration module 410 may also include instructions for monitoring power and communication between the host board 106 and the peripheral board 110. The configuration module 410 may also enable reconfiguration of the interface board 108. In one embodiment, the configuration module 410 can power down the host board 106, reconfigure the interface board 108, and then restart the host board 106. If a hot swap of the peripheral board 110 is desired, the configuration module 410 can reconfigure the interface board 108 without first powering down the host board 106 and / or power down the interface board 108 or the peripheral board 110, respectively, while the host board 106 remains powered.

[0028] The configuration data 412 may include identifiers for the expected host board 106, the expected interface board 108 attached to the host board 106, and the expected peripheral board 110 attached to the interface board 108. In some embodiments, the identifiers for the expected host board 106, interface board 108, and peripheral board 110 are stored as digital identification codes. The configuration data 412 includes the power and communication requirements of each peripheral board 110 that may be coupled to the platform. These requirements may be in the form of specific configurations for components (e.g., level shifters, power sequencers, load switches) present on the interface board 108 that provide the necessary power and communication connections for the peripheral board 110. One or more different configurations of the interface board 108 (or other embodiments of an interface board, including peripheral-specific interface boards) stored as configuration data 412 are represented as hardware circuit diagrams. Once the system design and testing are complete, the configuration data can be used to generate a circuit diagram for the final computing device by replacing the interface board 108 with the hardware circuit diagram. The hardware schematic may exclude any circuitry on the interface board 108 that is not used due to power and communication considerations of the attached peripherals. Thus, the schematic of the final design may include only the circuitry necessary to couple the core components of the host board 106 to the peripherals. Some specific examples of other data that may be included in the configuration data 412 include preferred voltages for multi-voltage I / O signals, preferred isolation for some I / O, preferred general-purpose I / O (GPIO) for controlling power for peripherals, and preferred devices to use when multiple options are available for a peripheral (e.g., a sensor).

[0029] In some embodiments, the intelligent module 402 provides a console to the debug bridge module 404. The debug bridge module 404 provides a connection for connecting a monitoring station to a modular system verification platform. The debug bridge module 404 is coupled to the interface board 108 to monitor power and signals passing through the interface board 108, including, but not limited to, detecting voltage and current levels, searching for leakage issues, and monitoring instrumentation amplifiers (INAs).

[0030] FIG. 5 illustrates the peripheral board 110 of FIG. 2 , which may be implemented in a modular system verification platform for a computing device. The peripheral board 110 includes a peripheral 502, a board connector 504, a CRM 506 (e.g., an EEPROM), and optional connectors 508 and 510. The peripheral board 110 may include additional circuitry (not shown) specific to the peripheral 502. The peripheral 502 may be an input peripheral, an output peripheral, a CRM storage device, or a battery. Some non-limiting examples of peripherals are user input devices (e.g., a mouse, keyboard, trackball, pen and pressure-sensitive pad, fingerprint reader), printers, scanners, hard drives, flash memory, WiFi and other network interfaces, sensors (e.g., a camera, temperature sensors, pressure sensors, motion sensors), audio-related peripherals (e.g., a microphone, speaker, audio codec), batteries, and universal serial bus (USB) controllers. In some aspects, multiple peripherals 502 may be mounted on a single peripheral board 110. For example, the peripheral board 110 may include multiple WiFi chipsets from different manufacturers. A multiplexer circuit may be implemented either on the attached interface board 108 or on the peripheral board 110 to switch between the different WiFi chipsets during testing.

[0031] The peripheral device 502 may be coupled to the board connector 504 via predefined circuitry. Similar to the host board 106 and the interface board 108, circuitry not utilized in the functionality of the peripheral device 502 may be excluded when generating the final circuit diagram for the end product. The board connector 504 may be predefined, i.e., the board connector 504 may be a common connector that couples to the generic interface board 108. In other aspects, the board connector may be a specific type of connector (e.g., a USB-C connector) that can couple to a peripheral-specific interface board.

[0032] The CRM 506 is coupled to the control plane interface and can store an identifier for the peripheral board 110. The identifier can be a digital ID code representing the type (or class) of the peripheral board 110 and / or the specific peripheral device 502 mounted on the peripheral board 110. In an embodiment, the interface board 108 can relay the peripheral device identifier received via the board connector 504 to the host board 106. The digital ID code can be used by the intelligent module 402 to identify the peripheral board 110 and determine whether the peripheral board 110 is supported by the configuration of the modular system verification platform being tested. If the peripheral board 110 is supported by the configuration data 412 stored in the intelligent module 402, the intelligent module 402 can proceed to boot the platform. Alternatively, if the peripheral board 110 is not supported by or available in the configuration data, the intelligent module 402 can decide not to boot the platform or to disable the peripheral board 110.

[0033] In some embodiments, peripheral board 110 includes one or more option connectors (e.g., option connectors 508 and 510). Option connectors 508 and 510 are coupled to peripheral device 502 (e.g., peripheral ICs) and can be used to connect peripheral device 502 to external devices, or can be implemented to extend a chain of modular peripheral boards. For example, if peripheral device 502 is a WiFi adapter, option connectors 508 and 510 can be connectors (e.g., RJ45 connectors) for other types of wired or wireless network modules.

[0034] 6-1 is a diagram illustrating an interface board 108 used in a modular system verification platform for a computing device. The interface board 108 includes an interface circuit 602 (and / or control circuitry, not shown) that enables the host board 106 to provide power to and communicate with the peripheral board 110. The interface board 108 also includes board connectors 604 and 606 (e.g., the board connectors of the interface board 108 included in board connections 208-1 and 212, respectively) and board management logic 608 (e.g., control circuitry).

[0035] The board connector 604 can be configured to connect to complementary board connectors on multiple different host substrates 106. The board connector 604 may include multiple power and signal paths that allow the interface board 108 to be configured in multiple ways. In most cases, some or a subset of these paths will be utilized in any specific configuration of the interface board 108. In other words, for a given peripheral device, not all of the available signal lines and / or power rails of the board connector 604 will be used to support testing and operation of the peripheral device. Similarly, the board connector 606 can be configured to connect to complementary board connectors 504 on multiple different peripheral boards 110, and the board connector 606 may include multiple power and signal paths that may not be utilized by a particular peripheral board. In some aspects, the board connector 606 may be a common connector used for standard communication protocols (e.g., USB, Ethernet, serial).

[0036] The interface circuit 602 may include a level shifter 602-1 used to supply the peripheral board 110 with its required voltages and a load switch 602-2 used to sequence power to the peripheral board 110 for startup and power-down purposes. As represented by the level shifter 602-1, there are several level shifting designs that may be implemented, either alone or in combination. For example, open-drain, non-inverting level shifting techniques may be implemented using Schottky diodes (either direction), field-effect transistors (FETs) in a pass configuration, a Schottky diode and FET in a pass configuration, or two FETs in a pass configuration. In some cases, open-drain, inverting level shifting techniques utilizing N-channel FETs (NFETs) or P-channel FETs (PFETs) are implemented. Push-pull level shifting techniques may be implemented using push-pull bidirectional level shifters, semi-push-pull bidirectional level shifters, or logic gate buffers. Alternatively, functions without level shifting may be implemented using direct connects. In some embodiments, the level shifting techniques configured for the attached peripheral board 110 may be represented in a circuit diagram for the end product (with unused or unnecessary circuitry omitted).

[0037] In one embodiment, voltage rails provided by the host board 106 are coupled to the level shifter 602-1 and the load switch 602-2 via a board connector 604. The voltage supplied by the host board may or may not match the voltage required by the peripheral device 502. The interface circuitry may control or modify the power provided to the peripheral device to provide logically equivalent rails that enable operation of the peripheral device. In some cases, a level shift manager (not shown) on the interface board 108 may monitor the sequence signals and turn on or off the level shifting components appropriately.

[0038] The load switch 602-2 can manage the power sequencing of the peripheral board 110 by coupling and decoupling the required power rails present on the host board 106 to the peripheral devices 502 in a set order during platform power-up and power-down. In this manner, a virtual rail is formed on the interface board 108 and coupled to the peripheral board 110 via the board connector 606. The host board 106 can include multiple power rails, each with a different voltage, and the power rail required by the peripheral board 110 is switched on by the load switch 602-2. Thus, the host board 106 does not need to wire multiple separate power rails of the same voltage to each board connector 310 on the host board 106 that connects to the interface board 108.

[0039] The load switch 602-2 can be implemented to support multiple operations. For example, power sequencing can be enabled based on determining whether the provided power is on and is an appropriate power source (e.g., power good) for the peripheral board 110. In some cases, the load switch 602-2 has reverse current protection and / or overcurrent protection. The load switch 602-2 can also have power good output verification for subsequent sequencing. In some aspects, the load switch 602-2 can have various on-time requirements, which may include minimum on-time requirements (e.g., soft start to avoid inrush) and maximum on-time requirements (e.g., to accommodate a poorly implemented power-on reset circuit within the IC). The load switch 602-2 may or may not also have an active discharge path for the power rail.

[0040] In some embodiments, the interface circuitry 602 or control circuitry of the interface board 108 includes debug circuitry (not shown) that may be coupled to the control plane of the host board. In some embodiments, the debug circuitry or test points are not exposed on the interface board 108. The monitor and debug circuitry may be coupled to a debug bridge module of the host board on the control plane. Generally, the debug circuitry allows for monitoring measurements of the power distributed and communications facilitated by the interface circuitry 602. Additionally, the debug circuitry may enable automated testing on the platform. For example, the debug circuitry may enable automated testing that continuously checks the analog voltages of various I / O lines or power rails in the system for leakage under any power state.

[0041] The board management logic 608 includes control circuitry coupled to the interface circuit 602, which in turn may be coupled to the intelligent module 402 over a control plane. The board management logic 608 may include a processor and CRM (e.g., a microcontroller) and manages the level shifter 602-1, the load switch 602-2, and any other logic that may be included in the interface circuit in alternative implementations. The CRM of the board management logic 608 may include an identifier for the interface board 108. The identifier may be used to identify the interface board 108. For example, the identifier may be a digital ID code representing the type of interface board 108. In some cases, the identifier is requested by the intelligent module 402 and checked against configuration data 412 on the intelligent module 402 to verify that the interface board 108 is the one expected in the current configuration of the modular system validation platform being tested.

[0042] In one aspect, the board management logic 608 receives configuration data 412 from the intelligent module 402 based on an identifier of the interface board 108. The configuration data 412 includes a configuration of the interface circuit 602 useful for interfacing the peripheral board 110 to the host board 106 by the interface board 108. In some aspects, the intelligent module 402 may send a new configuration to the board management logic 608 to reconfigure the interface circuit 602 in a different manner. This reconfiguration may be issued by the intelligent module 402 to test alternative implementations of the interface circuit 602 (e.g., power sequencing or level shifting for circuit optimization), or the reconfiguration may be issued because a different peripheral board 110 is connected to the interface board 108 and detected by the intelligent module 402. Similarly, there may be other circumstances for the intelligent module 402 to command a reconfiguration not described herein.

[0043] FIG. 6-2 illustrates an exemplary multiplexer interface board 600-2 that may be implemented in a modular system verification platform for a computing device. The multiplexer interface board 600-2 may include similar components to the interface board 108 (e.g., a level shifter 602-1, a load switch 602-2, board connectors 604 and 606, and board management logic 608). In this example, the interface circuit 602 further includes a multiplexer circuit 602-3 and one or more board connectors 610. The multiplexer circuit 602-3 couples the level shifter 602-1, the load switch 602-2, and the one or more board connectors 610 to one another. The multiplexer circuit 602-3 may also be coupled to the board connector 606. The multiplexer circuit 602-3 may be configured to switch or route power and communications between the board connector 604 and each of the multiple board connectors 606 and 610 via the level shifter 602-1 and the load switch 602-2. Figures 6-3 and 6-4 show some specific examples of the multiplexer interface board 600-2.

[0044] Configuration example of multiplexer interface board 6-3 and 6-4 illustrate example configurations 600-3 and 600-4 of a multiplexer interface board 600-2 used in a modular system verification platform for a computing device. In FIG. 3, the multiplexer interface board 600-2 is connected to the host board 106. The multiplexer interface board 600-2 may be connected to a peripheral device 612-1. In some aspects, an interposer board 614-1 is used to couple the peripheral device 612-1 (e.g., an M.2 solid-state drive) to the multiplexer interface board 600-2. The interposer board 614-1 can align a general-purpose high-speed IO 616 (HSIO) to the peripheral device 612-1 and couple a GPIO / low-speed IO (LSIO) 618 to the peripheral device 612-1. The host board 106 may include a greater amount of HSIO than required by the peripheral device 612-1. Because the interposer board 614-1 is specific to a distinct type of peripheral 612-1, it can bond or route the HSIOs 616 required for the peripheral 612-1 and not pass through unused HSIOs. The interposer board 614-1 can include a CRM (not shown) that stores an identifier that describes the peripheral 612-1. The multiplexer circuit 620-1 can switch the GPIOs / LSIOs 618 between the interposer board 614-1 and other connector boards 622 that may be included on the multiplexer interface board 600-2.

[0045] FIG. 6-4 illustrates another example configuration 600-4 of the multiplexer interface board 600-2 for use in a modular system verification platform for a computing device. The configuration 600-4 includes the same or similar circuitry as described with reference to the configuration 600-3. Additionally, the configuration 600-4 includes a second peripheral device 612-2, a second interposer board 614-2, a second multiplexer circuit 620-2, and n-pole double-throw (nPDT) multiplexer circuits 624-1 and 624-2 for routing power and / or I / O to different peripheral devices. The other connector board 622 is illustrated as two separate boxes for clarity of illustration.

[0046] A multiplexer circuit 620-2 switches the HSIO between interposer boards 614-1 and 614-2. Interposer board 614-2 is coupled to a second peripheral device 612-2. Although two chains of interposer boards 614 and peripheral devices 612 are illustrated in configuration 600-4, multiple chains of interposer boards 614 and peripheral devices 612 may be included in configuration 600-4. Similarly, second peripheral device 612-2 (or multiple peripheral devices 612) may be a peripheral device similar to peripheral device 612-1 (e.g., same brand, same model), or the peripheral devices 612 may be different from each other.

[0047] The nPDT multiplexer circuit 624-1 switches the coupling of GPIO / LSIO 618 among multiple interposer boards 614, and the nPDT multiplexer circuit 624-2 switches the coupling of GPIO / LSIO 618 among multiple other connector boards 622. Similarly, other configurations of multiplexer interface board 600-2 can be designed, with or without interposer board 614, for particular configurations of peripheral devices 612. Some examples of other configurations may include a USB-based multiplexer interface board 600-2 (e.g., a USB hub or USB switch) and a networking-based multiplexer interface board 600-2.

[0048] Example method 7, 8-1, and 8-2 illustrate detailed example methods 700 and 800 for operation of an interface board used in a modular system validation platform for a computing device. The illustrated methods include operations (or steps) that may be performed by or in conjunction with the control and / or interface circuitry of the interface board to implement various aspects of the modular system validation platform described herein. The operations or steps performed to implement methods 700 and / or 800 are not necessarily limited to the order or combination in which the operations are shown herein. As such, any one or more operations may be repeated, combined, or rearranged to provide other operations or alternative methods in accordance with aspects described herein.

[0049] FIG. 7 illustrates an example method 700 for operation of an interface board of a modular system validation platform, according to one or more aspects. At step 702, the interface board provides a device identifier to the host. The device identifier may be a digital ID code stored in the CRM, a code implemented by hardware (e.g., a voltage divider circuit), or an identifier implemented by some other means. The device identifier enables the host to verify that the attached interface board is expected to be part of the validation platform and to provide the correct configuration information to the interface board. Alternatively or additionally, the interface board may provide or relay a peripheral identifier that identifies a particular peripheral, class of peripheral, or type of peripheral coupled to the interface board.

[0050] In step 704, the interface board receives power from the host based on the device identifier provided to the host. Optionally, power or configuration for the interface board is provided from the host based on the device identifier and / or peripheral identifier. For example, the host or intelligent module may determine a configuration for the interface board and provide or sequence power through the interface board based on the device identifier and / or peripheral identifier. With respect to power, the host may include one or more power rails at different voltage levels. These power rails may be provided to the interface board (e.g., via a connection between the host and the interface board), but the interface board may couple only the power rails used by the attached peripheral to the peripheral connector. In some aspects, the interface board can interface a battery with the host. In such aspects, power may be supplied to the host from the battery via the interface board.

[0051] In step 706, the interface board distributes the power received from the host to the peripherals. The peripherals receive the power level for which they are designed. No other power levels are distributed to the peripherals.

[0052] Optionally, in step 708, the interface board receives communication signaling from the host based on a device identifier provided to the host. Optionally, communication signaling or configuration for the interface board is provided by the host based on the device identifier and / or peripheral identifier. For example, the host or intelligent module may determine a configuration for the interface board and provide or level shift communications via the interface board based on the device identifier and / or peripheral identifier. With respect to communications, communication signaling from the host may be specific to the type of peripheral connected to the interface board or the functionality provided by the interface board.

[0053] Optionally, in step 710, the interface board facilitates communication between the host and peripheral device based on communication signaling. Once a communication path between the host and peripheral device is established on the interface board, the host and peripheral device can communicate as if they were directly connected to each other and the interface board were not present. Such communication can simulate integration of the peripheral device with the host, and the configuration of the interface board can be used as the basis for circuit board schematics for subsequent stages of system integration.

[0054] 8-1 and 8-2 illustrate detailed exemplary methods 800, 801 of operation implemented by an interface board of a modular system verification platform for a computing device. As shown in FIG. 8-1, in step 802, the interface board receives configuration instructions from an intelligent module of a host board. The intelligent module may transmit the configuration instructions based on configuration data stored in a CRM on the intelligent module. In some cases, the intelligent module selects or determines the configuration instructions based on identifiers provided by the interface board and / or peripherals coupled to the interface board. The configuration instructions may be received and stored by control circuitry of the interface board, and the interface board may configure the interface circuitry of the interface board in response to receiving the configuration instructions.

[0055] In step 804, the interface board configures the interface circuitry present on the interface board based on the configuration instructions. In some cases, the control circuitry on the interface board configures load switches in a power distribution network to the peripheral connectors or sets parameters of level shifters for converting signal levels between the host connector and the peripheral connector on the interface board. As previously described, the control circuitry may configure the interface circuitry in response to receiving configuration instructions from the host board or the intelligent module.

[0056] The interface board distributes the power received from the host board to the peripheral boards via the interface circuitry in step 806. For example, the control circuitry of the interface board may selectively activate or deactivate load switches to distribute and / or sequence the power provided by the host board to the peripheral devices coupled to the interface board.

[0057] In step 808, the interface board facilitates communication between the host board and the peripheral board via the interface circuitry. For example, level shifters or other out-of-band signal lines on the interface board can facilitate communication between the host board and the peripheral board coupled to the interface board. Similarly, other logic (e.g., for signal filtering or status indication) may be present on the interface board.

[0058] In step 810, the interface board may receive a reconfiguration command from the intelligent module. The intelligent module may provide the reconfiguration instruction based on detecting a different interface configuration with the same peripheral, a different peripheral configuration, or a hot-swapped peripheral. If a reconfiguration command is received, steps 804 through 808 may be repeated.

[0059] FIG. 8-2 includes optional steps 812 and 814 shown in 801. In step 812, the power delivered and the communications facilitated are measured. The measurements may include voltage levels, current levels, I / O states, and / or other measurements that may be useful. In step 814, the measurements taken in step 812 are provided to a debug bridge module. In some cases, the intelligent board may provide a console interface to the debug module so that the measurements can be monitored. In other cases, the debug module may include the console interface.

[0060] In this manner, a generic, reconfigurable, modular system verification platform for computing devices may be implemented for rapid prototyping and testing of multiple configurations of the platform. The modular system verification platform described herein can reduce the resources, time, and costs associated with bringing new computing devices to market.

[0061] Various examples The following describes various embodiments of apparatus and techniques for a modular system verification platform for computing devices.

[0062] Example 1: An apparatus for validating a system including a host and at least one peripheral device, comprising: a printed circuit board (PCB) including a device identifier; a first connector coupled to the PCB and configured to couple to the host; a second connector coupled to the PCB and configured to couple to the peripheral device; and an interface circuit coupled to the PCB between the first connector and the second connector, wherein the interface circuit is configured to at least: enable the host to operate with the peripheral device by providing the device identifier to the host; receiving power from the host based on the device identifier provided to the host; and distributing power from the host to the peripheral device; or receiving communication signaling from the host based on the device identifier provided to the host; and facilitating communication between the host and the peripheral device based on the communication signaling.

[0063] The device of example 1, wherein the peripheral device is a first peripheral device, and the device further includes a control circuit coupled to the interface circuit, the control circuit configured to: establish a first configuration of the interface circuit to enable the host to operate with the first peripheral device; detect a second peripheral device coupled to the second connector or coupled to a third connector of the PCB configured to couple to another peripheral device; and, when coupled to the second connector or the third connector of the PCB, modify at least one operating characteristic of the interface circuit to establish a second configuration of the interface circuit that enables the host to operate with the second peripheral device.

[0064] The control circuitry is further configured to: receive, via the second connector, a first peripheral identifier from the first peripheral device, provide the first peripheral identifier to the host, and receive from the host first configuration information useful for establishing a first configuration of the interface circuit to enable the host to operate with the first peripheral device; or receive, via the second connector or the third connector, a second peripheral identifier from the second peripheral device, provide the second peripheral identifier to the host, and receive from the host second configuration information useful for establishing a second configuration of the interface circuit to enable the host to operate with the second peripheral device.

[0065] Example 4: The apparatus of any one of the preceding examples, wherein the interface circuit includes a plurality of level shifters configured to convert respective voltage levels of the one or more signals provided by the host to one or more different voltage levels, the one or more signals having different voltage levels being provided to the peripheral devices, and the interface circuit includes one or more switches coupled to power rails provided by the host and configured to distribute or sequence power to the peripheral devices.

[0066] Example 5: The device of any one of the preceding examples, wherein the second connector is a first peripheral connector, and the device further includes a plurality of peripheral connectors including the first peripheral connector, the plurality of peripheral connectors configured to couple the device with a plurality of respective peripheral devices.

[0067] Example 6: The device of Example 5, further including a multiplexer circuit configured to switch a power path or a communication path between the first connector of the device and other connectors of the plurality of peripheral connectors to enable communication between the host and respective peripheral devices coupled to the other peripheral connectors.

[0068] Example 7: The apparatus of example 5 or example 6, wherein each of the plurality of peripherals comprises a peripheral class or peripheral type, or wherein the plurality of peripheral connectors are configured to provide a respective power and communication interface for the peripheral class or peripheral type.

[0069] Example 8: The device of example 2 or example 3, wherein the host includes a host PCB, the host PCB including a system on a chip (SoC), a system configuration module configured to determine at least a first configuration or a second configuration of an interface circuit of the device, and a debug module configured to receive from the device measurements of power delivered by the device or signal levels of communications facilitated by the device.

[0070] Example 9: The apparatus of example 8, wherein the system configuration module includes a system configuration module PCB configured to couple to the host PCB, or the debug module includes a debug module PCB configured to couple to the host PCB.

[0071] Example 10: The device of example 8 or example 9, wherein the system configuration module is further configured to: identify the device using the device identifier; and determine the first configuration or the second configuration of the interface circuit based on the device identifier; or identify the first peripheral device, the first peripheral device class, or the first peripheral device type based on the first peripheral device identifier; and determine the first configuration of the interface circuit based on the identification of the first peripheral device, the first peripheral device class, or the first peripheral device type; or identify the second peripheral device, the second peripheral device class, or the second peripheral device type based on the second peripheral device identifier; and determine the second configuration of the interface circuit based on the identification of the second peripheral device, the second peripheral device class, or the second peripheral device type.

[0072] Example 11: The apparatus of any one of Examples 8 to 10, wherein the control circuit is configured to receive, from the system configuration module, first configuration information indicating a first configuration of the interface circuit, and configure the interface circuit based on the first configuration information to establish a first configuration of the interface circuit that enables the host to operate with the first peripheral device, or to receive, from the system configuration module, second configuration information indicating a second configuration of the interface circuit, and configure the interface circuit based on the second configuration information to establish a second configuration of the interface circuit that enables the host to operate with the first peripheral device.

[0073] Example 12: The apparatus of any one of Examples 8 to 11, wherein for at least one of the first configuration and the first peripheral device, or the second configuration and the second peripheral device, the interface circuitry corresponds to a net in a hardware circuit diagram of the respective configuration of the interface circuitry, useful for generating a circuit diagram of a system PCB including the SoC, the respective peripheral device, and a portion of the interface circuitry based on the respective configuration of the interface circuitry between the SoC and the respective peripheral device.

[0074] Example 13: The device of any one of the preceding examples, wherein the interface circuitry is configured to enable at least one of: swapping the first peripheral device with a second or other peripheral device without removing power from the device; adding or removing the first, second, or other peripheral device without removing power from the device; detecting the presence of the first, second, or other peripheral device when coupled to the device; or establishing a respective configuration of the interface circuitry of the first, second, or other peripheral device based on a respective peripheral device identifier.

[0075] Example 14: The device of any one of Examples 8 to 13, further including a monitoring circuit configured to provide, to the debug module, a measurement of a signal level of a communication distributed or facilitated by the device.

[0076] Example 15: The device of example 14, wherein the monitoring circuitry is further configured to provide measurements to a debug module to facilitate automated testing of distributed power or facilitated communication on electrical paths that are not exposed on an outer layer on a PCB of the device.

[0077] Example 16: A modular system verification platform comprising: a host PCB including a processor and at least one connector configured to be coupled to the device described in any one of the preceding examples; a peripheral PCB including at least one peripheral and a connector configured to be coupled to the device described in any one of the preceding examples; and the device described in any one of the preceding examples.

[0078] Example 17: A method for verifying a system including a host and at least one peripheral device, the method including: circuitry on an interface printed circuit board (PCB) providing an interface PCB identifier to the host, the interface PCB being coupled between the host and the at least one peripheral device; the method including: circuitry on the interface PCB receiving power from the host based on a device identifier provided to the host; and circuitry on the interface PCB distributing the power received from the host to the peripheral device; or circuitry on the interface PCB receiving communication signaling from the host based on the interface PCB identifier provided to the host; and circuitry on the interface PCB facilitating communication between the host and the peripheral device based on the communication signaling.

[0079] Example 18: The method of example 17, wherein the peripheral device is a first peripheral device, and the method further includes: a control circuit on the interface PCB establishing a first configuration of the circuit on the interface PCB that enables the host to operate with the first peripheral device; the control circuit detecting coupling of a second peripheral device to the interface PCB; and the control circuit altering at least one operating characteristic of the circuit on the interface PCB to establish a second configuration of the circuit that enables the host to operate with the second peripheral device when coupled to the interface PCB.

[0080] Example 19: The method of example 18, further comprising: the control circuit of the interface PCB receiving a first peripheral identifier from the first peripheral; the control circuit providing the first peripheral identifier to the host; and receiving from the host first configuration information useful to the control circuit for establishing a first configuration of the interface circuit that enables the host to operate with the first peripheral; or the control circuit receiving a second peripheral identifier from the second peripheral; the control circuit providing the second peripheral identifier to the host; and receiving from the host second configuration information useful to the control circuit for establishing a second configuration of the interface circuit that enables the host to operate with the second peripheral.

[0081] Example 20: The method of any one of Examples 15 to 19, further including: configuring one or more of a plurality of level shifters of the interface PCB to convert a respective voltage level of one or more signals provided from the host to one or more different voltage levels; and configuring one or more signals having different voltage levels to be provided to the peripheral devices, or configuring one or more load switches of the interface PCB to distribute or sequence power provided to the peripheral devices.

[0082] Example 21: The method of any of Examples 17 to 20, further including: configuring a monitoring circuit of the interface PCB to provide at least one measurement of power distributed by the interface PCB or a signal level of facilitated communication between the host and the at least one peripheral device; and providing the measurement of power distributed by the interface PCB or a signal level of facilitated communication between the host and the at least one peripheral device to a debug module of the host.

[0083] conclusion Unless the context dictates otherwise, the use of the word "or" herein may be considered an "inclusive or" or the use of a term permitting the inclusion or application of one or more items linked by the word "or" (e.g., the phrase "A or B" may be interpreted as permitting only "A," permitting only "B," or permitting both "A" and "B"). Also, as used herein, a phrase referring to "at least one" of a list of items refers to any combination of those items, including single members. For example, "at least one of a, b, or c" includes not only a, b, c, ab, ac, bc, and abc, but also multiple combinations of the same elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, ccc, or other permutations of a, b, and c). Additionally, items depicted in the accompanying figures and terms discussed herein may refer to one or more items or terms, and thus, the singular or plural forms of items and terms may be referred to interchangeably herein. Although implementations of a modular system validation platform for a computing device have been described in language specific to certain features and / or methods, the subject matter of the appended claims is not necessarily limited to the particular features or methods described. Rather, the particular features and methods are disclosed as example implementations for modular system validation.

Claims

1. An apparatus for verifying a system including a host (106) and at least one peripheral device (110), comprising: a printed circuit board, PCB (108), containing a device identifier; a first connector (208-1) coupled to the PCB and configured to couple to the host; a second connector (208-2) coupled to the PCB and configured to couple to the peripheral device; an interface circuit (602) coupled to the PCB between the first connector and the second connector; Including, The interface circuit includes at least providing the device identifier to the host; receiving power from the host based on the device identifier provided to the host; Distributing the power from the host to the peripheral device; or receiving communication signaling from the host based on the device identifier provided to the host; facilitating communication between the host and the peripheral device based on the communication signaling; configured to enable the host to operate with the peripheral device by Device.

2. The peripheral device is a first peripheral device, and the apparatus further includes a control circuit coupled to the interface circuit, the control circuit comprising: establishing a first configuration of the interface circuit to enable the host to operate with a first peripheral device; Detecting a second peripheral device coupled to the second connector or coupled to a third connector of the PCB configured to couple to another peripheral device; when coupled to the second connector or the third connector of the PCB, modifying at least one operational characteristic of the interface circuit to establish a second configuration of the interface circuit that enables the host to operate with the second peripheral device; It is configured as follows:

10. The apparatus of claim 1.

3. The control circuit further comprises: receiving a first peripheral device identifier from the first peripheral device via the second connector; providing the first peripheral identifier to the host; receiving from the host first configuration information useful for establishing the first configuration of the interface circuit to enable the host to operate with the first peripheral device; or receiving a second peripheral device identifier from the second peripheral device via the second connector or the third connector; providing the second peripheral identifier to the host; receiving, from the host, second configuration information useful for establishing the second configuration of the interface circuit to enable the host to operate with the second peripheral device; It is configured as follows:

3. The apparatus of claim 2.

4. The interface circuit a plurality of level shifters configured to convert the voltage level of each of the one or more signals provided by the host to one or more different voltage levels; the one or more signals having the different voltage levels are supplied to the peripheral device; The interface circuit one or more switches coupled to power rails provided by the host and configured to distribute or sequence power to the peripheral devices; 10. The apparatus of claim 1.

5. the second connector is a first peripheral connector; the device further includes a plurality of peripheral connectors including the first peripheral connector; the plurality of peripheral connectors are configured to couple the device with a plurality of respective peripheral devices; 10. The apparatus of claim 1.

6. further comprising a multiplexer circuit configured to switch power or communication paths between the first connector of the device and other connectors of the plurality of peripheral connectors to enable communication between the host and the respective peripherals coupled to the other peripheral connectors; 6. The apparatus of claim 5.

7. Each of the plurality of peripheral devices comprises a peripheral class or peripheral type; or the plurality of peripheral connectors are configured to provide respective power and communication interfaces for the peripheral classes or types; 7. The device according to claim 5 or claim 6.

8. The host includes a host PCB, the host PCB comprising: a system on chip (SoC); a system configuration module configured to determine at least the first configuration or the second configuration of the interface circuitry of the device; a debug module configured to receive from the device a measurement of the power distributed or signal level of the communication facilitated by the device; Including, 4. The apparatus of claim 3.

9. the system configuration module includes a system configuration module PCB configured to couple to the host PCB; or the debug module includes a debug module PCB configured to couple to the host PCB; 9. The apparatus of claim 8.

10. The system configuration module further comprises: identifying the device using the device identifier and determining the first configuration or the second configuration of the interface circuit based on the device identifier; or identifying the first peripheral, the class of the first peripheral, or the type of the first peripheral based on the first peripheral identifier, and determining the first configuration of the interface circuit based on the identification of the first peripheral, the class of the first peripheral, or the type of the first peripheral; or identifying the second peripheral, a class of the second peripheral, or a type of the second peripheral based on the second peripheral identifier, and determining the second configuration of the interface circuit based on the identification of the second peripheral, the class of the second peripheral, or the type of the second peripheral; It is configured as follows:

9. The apparatus of claim 8.

11. The control circuit receiving, from the system configuration module, first configuration information indicating the first configuration of the interface circuit; configuring the interface circuit based on the first configuration information to establish the first configuration of the interface circuit that enables the host to operate with the first peripheral device; or receiving, from the system configuration module, second configuration information indicating the second configuration of the interface circuit; configuring the interface circuit based on the second configuration information to establish the second configuration of the interface circuit that enables the host to operate with the first peripheral device; It is configured as follows:

9. The apparatus of claim 8.

12. For at least one of the first configuration and the first peripheral device, or the second configuration and the second peripheral device, the interface circuits correspond to nets in a hardware circuit diagram of the respective configurations of the interface circuits, the nets being useful for generating a circuit diagram of a system PCB including the SoC, the respective peripheral devices, and a portion of the interface circuits based on the respective configurations of the interface circuits between the SoC and the respective peripheral devices; 9. The apparatus of claim 8.

13. The interface circuit swapping the first peripheral with the second peripheral or another peripheral without removing power from the device; adding or removing the first peripheral device, the second peripheral device, or the other peripheral device without removing power from the device; Detecting the presence of the first peripheral device, the second peripheral device, or the other peripheral device when coupled to the device; or establishing a configuration of each of the interface circuits of the first peripheral device, the second peripheral device, or the other peripheral device based on the respective peripheral device identifier; configured to enable at least one of 9. The apparatus of claim 8.

14. a monitoring circuit configured to provide to said debug module a measurement of the signal level of communications distributed or facilitated by said device; further comprising:

9. The apparatus of claim 8.

15. A method for verifying a system including a host (106) and at least one peripheral device (110), comprising: The method comprises: a circuit on an interface printed circuit board (PCB) (108) for providing an interface PCB identifier to the host; the interface PCB is coupled between the host and the at least one peripheral device; The method comprises: The circuitry of the interface PCB receives power from the host based on a device identifier provided to the host (704); the circuitry of the interface PCB distributes (706) power received from the host to the peripheral device; or the circuitry of the interface PCB receiving (708) communication signaling from the host based on the interface PCB identifier provided to the host; the circuitry of the interface PCB facilitating communication between the host and the peripheral device based on the communication signaling (710); A method comprising:

16. The host debug module, a measure of the power delivered by said device; or A measurement of the signal level of facilitated communication on electrical paths that are not exposed to the outer layers of the PCB of the device. and further comprising a monitoring circuit configured to provide at least one of:

10. The apparatus of claim 1.

17. The method of claim 1, further comprising: a control circuit coupled to the interface circuit, the control circuit configured to establish a first configuration of the interface circuit to enable the host to operate with the peripheral device; the interface circuit corresponds to a net in a hardware circuit diagram of the first configuration of the interface circuit, the hardware circuit diagram being useful for generating a circuit diagram of a system PCB including the SoC, the peripheral device, and a portion of the interface circuit based on respective configurations of the interface circuit between the SoC and the peripheral device; 10. The apparatus of claim 1.

Images