Cell balance circuit, cell balance device, charge / discharge control circuit, charge / discharge control device, and battery device

Abstract

To provide a cell balance circuit and the like capable of cell balance operation as accurately as or more accurately than conventional arts, with a simpler structure than the conventional arts.SOLUTION: A cell balance circuit 15 is serially connected to a secondary battery including a battery pack serially connected to a first cell and a second cell from a positive electrode to a negative electrode in this order, adjusts respective voltage of the two cells, and includes: a switch circuit 16 capable of opening / closing routes respectively connected to the two cells; and a depletion type FET17 as a cell discharge resistor connected to the first cell and the second cell via the switch circuit 16. To voltage of the first cell and the second cell, overcharge detection voltage higher than a half of charging voltage and overcharge release voltage lower than a half of the charging voltage are set. A release condition in the overcharged state while a charger is connected is that voltage of the first cell and the second cell exceeding the overcharge detection voltage is equal to or lower than the overcharge release voltage.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a cell balance circuit, a cell balance device, a charge / discharge control circuit, a charge / discharge control device, and a battery device. [Background technology]

[0002] There are battery packs consisting of multiple rechargeable secondary battery cells connected in series. As secondary battery packs undergo repeated charging and discharging, differences in the voltages of the individual battery cells begin to occur. If the voltages of the individual battery cells in a battery pack differ significantly, the higher-voltage battery cells may quickly overcharge and stop charging when the battery pack is charged, and the lower-voltage battery cells may quickly overdischarge and stop discharging when the battery pack is discharged, resulting in only a small amount of charging or discharging. Therefore, it is preferable to adjust the voltages of the individual battery cells in a battery pack so that they are approximately uniform.

[0003] Therefore, from the viewpoint of keeping the voltage difference between battery cells within a predetermined range, there is a cell balancing technology that operates to equalize the voltages of battery cells in a battery pack (hereinafter referred to as "cell balancing operation") (see, for example, Patent Document 1).

[0004] The cell balancing operation disclosed in Patent Document 1 is an operation in which current flows from a battery cell with a relatively high voltage through a discharge path. The charge / discharge control circuit disclosed in Patent Document 1 measures and compares the voltage of each battery cell, and when a deviation of a predetermined voltage or more occurs, current flows from the battery cell with the relatively high voltage to lower the voltage of that battery cell. This cell balancing operation continues until the voltage difference between the high-voltage battery cell and the low-voltage battery cell falls within a predetermined range. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-124094 Summary of the Invention [Problem to be solved by the invention]

[0006] However, conventional cell balancing devices that perform the above-described cell balancing operation have a relatively large number of circuits, including a circuit that measures the voltage of each battery cell and a circuit that compares the measured voltages. The greater the number of circuits, the greater the amount of materials used and the overall device area. Furthermore, an increase in the number of circuits leads to an increase in the number of circuits to be tested. Thus, conventional cell balancing devices with a relatively large number of circuits leave room for improvement in terms of resource conservation and cost.

[0007] The present invention has been made in view of the above-mentioned circumstances, and has an object to provide a cell balancing circuit, a cell balancing device, a charge / discharge control circuit, a charge / discharge control device, and a battery device that are capable of performing cell balancing operations with accuracy equal to or greater than that of conventional devices, using a configuration simpler than conventional devices. [Means for solving the problem]

[0008] In order to solve the above-described problems, a cell balance circuit according to the present invention is a circuit connected in parallel to a secondary battery including a battery pack in which a first cell and a second cell are connected in series from a positive electrode to a negative electrode, and adjusts the individual voltages of the first cell and the second cell, a first switch capable of opening and closing a first path connecting the positive terminal of the first cell and the negative terminal of the first cell, and a second switch capable of opening and closing a second path connecting the positive terminal of the second cell and the negative terminal of the second cell, and a switch circuit that can open and close the paths of the first cell and the second cell via the switch circuit; Either cell and are alternatively connected When the first path is closed by closing the first switch and the second switch being open, the first cell is discharged, and when the second path is closed by closing the second switch and the first switch being open, the second cell is discharged. R common to the first cell and the second celland a cell discharge resistor, wherein an overcharge detection voltage for detecting an overcharged state and an overcharge release voltage for releasing the overcharged state are set for the voltages of the first cell and the second cell, respectively, the overcharge release voltage is set to a voltage lower than half a charging voltage which is an output voltage of a charger that charges the secondary battery, and the overcharge detection voltage is set to a voltage higher than half the charging voltage but lower than the charging voltage, and the condition for releasing the overcharged state in a charger connected state in which the charger is connected to an external positive terminal and an external negative terminal is that the voltage of one of the first cell and the second cell that has exceeded the overcharge detection voltage drops to or below the overcharge release voltage. Furthermore, in order to solve the above-mentioned problems, a cell balance device, a charge / discharge control circuit, a charge / discharge control device, and a battery device according to the present invention include the cell balance circuit. [Effects of the Invention]

[0009] According to the present invention, a cell balancing operation with accuracy equal to or higher than that of the conventional one can be performed with a configuration simpler than that of the conventional one. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic diagram showing an example of the configuration of a cell balance circuit, a charge / discharge control circuit, a charge / discharge control device, and a battery device according to a first embodiment of the present invention. [Figure 2] 2 is a schematic diagram showing a detailed configuration example of a charge / discharge control circuit according to the first embodiment. FIG. [Figure 3] 2 is a schematic diagram illustrating a detailed configuration example of a cell balance circuit according to the first embodiment. FIG. [Figure 4] FIG. 10 is a schematic diagram showing an example of the configuration of a cell balance circuit, a cell balance device, a charge / discharge control circuit, a charge / discharge control device, and a battery device according to a second embodiment of the present invention. [Figure 5] FIG. 10 is a schematic diagram showing a detailed configuration example of a charge / discharge control circuit according to a second embodiment. [Figure 6]FIG. 10 is a schematic diagram illustrating a detailed configuration example of a cell balance circuit and a cell balance device according to a second embodiment. [Figure 7] FIG. 10 is a schematic diagram illustrating a configuration example of a modified example of a cell balance circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE INVENTION A cell balancing circuit, a cell balancing device, a charge / discharge control circuit, a charge / discharge control device, and a battery device according to embodiments of the present invention will be described below with reference to the drawings.

[0012] [First embodiment] FIG. 1 is a schematic diagram showing an example of the configuration of a cell balance circuit, a charge / discharge control circuit, a charge / discharge control device, and a battery device according to the first embodiment.

[0013] The battery device 1 and the charge / discharge control circuit 10 are examples of the battery device and the charge / discharge control circuit according to the first embodiment. The battery device 1 includes a secondary battery 2 including a so-called two-cell battery pack, an external positive terminal P+ and an external negative terminal P-, a discharge control FET (Field Effect Transistor) 3, a charge control FET 4, and a charge / discharge control circuit 10 for controlling the charging and discharging of the secondary battery 2. For ease of explanation, the external positive terminal P+ and the external negative terminal P- may be collectively referred to as "external terminals" in the following description.

[0014] The charge / discharge control device 20 is an example of the charge / discharge control device according to the first embodiment. The charge / discharge control device 20 includes an external positive terminal P+, an external negative terminal P-, a discharge control FET 3, a charge control FET 4, and a charge / discharge control circuit 10. In other words, the charge / discharge control device 20 is a device obtained by omitting the secondary battery 2 from the battery device 1.

[0015] The secondary battery 2 is a so-called two-cell battery including a battery pack in which two battery cells (hereinafter simply referred to as "cells") are connected in series. A first cell 2_1 and a second cell 2_2 in the secondary battery 2 are connected in series in this order from the positive electrode 2a of the secondary battery 2 to the negative electrode 2b of the secondary battery 2.

[0016] The external positive terminal P+ and the external negative terminal P- are terminals for connection to external devices (not shown), such as a charger and a load. In the battery device 1, a path connecting the external positive terminal P+ and the external negative terminal P- (hereinafter referred to as an "external terminal path") is connected to, for example, the secondary battery 2, the overcurrent detection resistor 5, the discharge control FET 3, and the charge control FET 4 in this order from the external positive terminal P+ side.

[0017] The battery device 1 and the charge / discharge control device 20 are provided with a discharge control FET 3 and a charge control FET 4 on the external negative terminal P- side, i.e., on the low side. The discharge control FET 3 and the charge control FET 4 are both NMOS transistors, and their drains are connected to each other.

[0018] The discharge control FET3 includes a gate connected to the discharge control signal output terminal DO, a drain as one end connected to the drain of the charge control FET4, and a source as the other end connected to one end of the overcurrent detection resistor 5.

[0019] The charge control FET4 includes a gate connected to the charge control signal output terminal CO, a source as one end connected to the external negative terminal P−, and a drain as the other end connected to the drain of the discharge control FET3.

[0020] The charge / discharge control circuit 10 is configured, for example, as a single semiconductor chip, i.e., a semiconductor integrated circuit, and includes positive power supply terminals VDD and VDD2, a negative power supply terminal VSS, cell connection terminals VCa and VCb, a charge control signal output terminal CO, a discharge control signal output terminal DO, an external negative voltage input terminal VM, and an overcurrent detection terminal VINI.

[0021] The positive power supply terminal VDD is connected to the positive electrode 2a via a resistor R1, and is supplied with voltage from the positive electrode 2a of the secondary battery 2. The positive power supply terminal VDD2 is connected to the external positive electrode terminal P+ and the positive electrode 2a, and is supplied with voltage from the positive electrode 2a of the secondary battery 2. The negative power supply terminal VSS is connected to the negative electrode 2b, and is supplied with voltage from the negative electrode 2b.

[0022] The cell connection terminal VCa is connected to the junction of the first cell 2_1 and the second cell 2_2, i.e., the negative terminal of the first cell 2_1 and the positive terminal of the second cell 2_2, via a resistor R2. Here, one end of the resistors R1 and R2 connected to the first cell 2_1 to the n-th cell 2_n (the left end in FIG. 1) is referred to as the first end, and the other end connected to the positive power supply terminal VDD, the cell connection terminal VCa, and the negative power supply terminal VSS is referred to as the second end (the right end in FIG. 1).

[0023] A capacitor C1 for suppressing voltage fluctuations is connected between the junction between the second end of resistor R1 and the positive power supply terminal VDD and the junction between the negative electrode 2b and the negative power supply terminal VSS. A capacitor C2 for suppressing voltage fluctuations is connected between the junction between the second end of resistor R2 and the cell connection terminal VCa and the junction between the negative electrode 2b and the negative power supply terminal VSS.

[0024] The charge control signal output terminal CO is a terminal that outputs a charge control signal that is generated within the charge / discharge control circuit 10 and controls the stopping and permission of charging of the secondary battery 2 to the outside of the charge / discharge control circuit 10. The charge control signal output terminal CO is connected to the gate of the charge control FET4.

[0025] The discharge control signal output terminal DO is a terminal that outputs a discharge control signal that is generated within the charge / discharge control circuit 10 and controls the stopping and permission of discharging of the secondary battery 2 to the outside of the charge / discharge control circuit 10. The discharge control signal output terminal DO is connected to the gate of the discharge control FET3.

[0026] The external negative voltage input terminal VM is connected to the external negative terminal P− and the source of the charge control FET 4 via a resistor 6 .

[0027] The overcurrent detection terminal VINI is connected to one end of the overcurrent detection resistor 5 and the source of the discharge control FET3.

[0028] FIG. 2 is a schematic diagram showing a more detailed configuration example of the charge / discharge control circuit 10 as the charge / discharge control circuit according to the first embodiment.

[0029] The charge / discharge control circuit 10 includes positive power supply terminals VDD and VDD2, a negative power supply terminal VSS, cell connection terminals VCa and VCb, a charge control signal output terminal CO, a discharge control signal output terminal DO, an external negative voltage input terminal VM, and an overcurrent detection terminal VINI, as well as a battery voltage detection circuit 11, an overcurrent detection and release circuit 12, a control circuit 13, and a cell balance circuit 15.

[0030] The battery voltage detection circuit 11 is a circuit that detects the voltage between terminals included in the secondary battery 2. The battery voltage detection circuit 11 has a terminal connected to the positive power supply terminal VDD, a terminal connected to the negative power supply terminal VSS, a terminal connected to the cell connection terminal VCa, and a terminal connected to the control circuit 13.

[0031] The overcurrent detection and release circuit 12 has an overcurrent detection circuit for detecting an overcurrent state and an overcurrent release circuit for releasing the overcurrent state and transitioning from the overcurrent state to a normal state. The overcurrent detection and release circuit 12 also has a terminal connected to the positive power supply terminal VDD, a terminal connected to the overcurrent detection terminal VINI, a terminal connected to the external negative voltage input terminal VM, and a terminal connected to the control circuit 13.

[0032] The control circuit 13 has a terminal connected to the positive power supply terminal VDD, a terminal connected to the negative power supply terminal VSS, a terminal connected to the charge control signal output terminal CO, a terminal connected to the discharge control signal output terminal DO, a terminal connected to the external negative voltage input terminal VM, a terminal connected to the battery voltage detection circuit 11, a terminal connected to the overcurrent detection and release circuit 12, and a terminal connected to the cell balance circuit 15.

[0033] The control circuit 13 also has a first control circuit (not shown in FIG. 2) that controls charging and discharging of the secondary battery 2, and a second control circuit (not shown in FIG. 2) that adjusts the individual voltages of the first cell 2_1 and the second cell 2_2. The first control circuit generates control signals for controlling charging and discharging of the secondary battery 2 based on detection signals of the voltage of the secondary battery 2 and the voltages of the cells 2_1 and 2_2 from the battery voltage detection circuit 11, and supplies the control signals to the charge control signal output terminal CO and the discharge control signal output terminal DO. The second control circuit generates control signals for adjusting the individual voltages of the first cell 2_1 and the second cell 2_2 based on detection signals of the voltage of the secondary battery 2 and the voltages of the cells 2_1 and 2_2 from the battery voltage detection circuit 11, the voltage of the negative power supply terminal, and the voltage of the external negative voltage input terminal, and supplies the control signals to the cell balance circuit 15.

[0034] The cell balance circuit 15 is a circuit that performs a cell balancing operation to adjust the individual voltages of the first cell 2_1 and the second cell 2_2. The cell balance circuit 15 has a terminal connected to the positive power supply terminal VDD2, a terminal connected to the negative power supply terminal VSS, a terminal connected to the control circuit 13, and a terminal connected to the cell connection terminal VCb.

[0035] FIG. 3 is a schematic diagram showing a more detailed configuration example of the cell balance circuit 15 as the cell balance circuit according to the first embodiment.

[0036] The cell balance circuit 15 includes a switch circuit 16 and a depletion-type FET 17 as a cell discharge resistor.

[0037] The switch circuit 16 is provided between the positive power supply terminal VDD2, the negative power supply terminal VSS, the cell connection terminal VCb, and the depletion-type FET 17.

[0038] The switch circuit 16 has four switches 16_1, 16_2, 16_3, and 16_4, which is twice the number of two cells of the secondary battery 2. By having the switches 16_1 to 16_4, the switch circuit 16 is configured to be able to open and close a first path connecting the positive electrode terminal and negative electrode terminal of the first cell 2_1 and a second path connecting the positive electrode terminal and negative electrode terminal of the second cell 2_2.

[0039] Here, in the switches 16_1, 16_2, 16_3, and 16_4, the terminals connected to the positive power supply terminal VDD2, the negative power supply terminal VSS, and the cell connection terminal VCb, i.e., the positive terminals or negative terminals of the cells 2_1 and 2_2, are referred to as first terminals, and the terminals connected to the drain or source of the depletion-type FET 17 are referred to as second terminals.

[0040] Each of the switches 16_1 to 16_4 includes a first terminal, a second terminal, and a control terminal. Each of the switches 16_1 to 16_4 is configured to be able to switch between short-circuiting (closed state) and opening (open state) the first terminal and the second terminal in response to a control signal input to the control terminal.

[0041] Of the switches 16_1 to 16_4, the switches 16_1 and 16_2 have second terminals connected to the drain of the depletion-type FET 17. The remaining switches 16_3 and 16_4 have second terminals connected to the source of the depletion-type FET 17.

[0042] The switches 16_1 and 16_2 are switches that switch between connection and disconnection with the positive electrode terminals of the first cell 2_1 and the second cell 2_2, respectively. The switches 16_3 and 16_4 are switches that switch between connection and disconnection with the negative electrode terminals of the first cell 2_1 and the second cell 2_2, respectively.

[0043] The depletion-type FET 17 serving as a cell discharge resistor is, for example, an N-type depletion-type MOSFET. The depletion-type FET 17 has its gate and source connected (short-circuited).

[0044] Next, the operations of the cell balance circuit 15, the charge / discharge control circuit 10, the charge / discharge control device 20, and the battery device 1 configured as described above will be described.

[0045] Similar to conventional charge / discharge control circuits, charge / discharge control devices, and battery devices, the charge / discharge control circuit 10, the charge / discharge control device 20, and the battery device 1 perform switching operations between a normal state, a discharge inhibition state, a charge inhibition state, and an overcurrent detection state, i.e., charge / discharge control operations for the secondary battery 2. The overcurrent detection states include a discharge overcurrent detection state in which an overcurrent is detected when discharging the secondary battery 2, and a charge overcurrent detection state in which an overcurrent is detected when charging the secondary battery 2. Furthermore, the charge / discharge control circuit 10, the charge / discharge control device 20, and the battery device 1 perform cell balancing operations to adjust the individual voltages of the first cell 2_1 and the second cell 2_2.

[0046] The charge / discharge control circuit 10 (more specifically, the control circuit 13) includes an overcharge detection voltage V that starts the overcharge protection operation for each of the first cell 2_1 and the second cell 2_2. CU (>0) and the overcharge release voltage V that releases (stops) the overcharge protection operation CL (>0) is set in the charge / discharge control circuit 10 (more specifically, the control circuit 13), as a condition for canceling the overcharge protection operation, when the voltage of the secondary battery 2 reaches the overcharge release voltage V CL The conditions are set such that the voltage drops below 10 V and discharge from the secondary battery 2 to the load connected between the external terminals is started.

[0047] In a typical charge / discharge control circuit, the overcharge release voltage V CL is the overcharge detection voltage V CU On the other hand, in the charge / discharge control circuit 10, the overcharge detection voltage V CU is the charging voltage V, which is the output voltage of the charger connected between the external terminals. CH (>0) is higher than 1 / 2 the voltage (hereinafter simply referred to as the "reference voltage"), and the charging voltage V CH On the other hand, the overcharge release voltage V CL is set to a voltage lower than the reference voltage. That is, the overcharge release voltage VCL and overcharge detection voltage V CU is the charging voltage V CH The voltage is set within a range of less than the reference voltage.

[0048] The above-mentioned setting range is set to balance the voltages of the first cell 2_1 and the second cell 2_2 without overcharging, and a more preferable overcharge release voltage V CL and overcharge detection voltage V CU It is possible to set a more desirable overcharge release voltage V CL and overcharge detection voltage V CU The setting conditions will be explained later in the explanation of the cell balance operation.

[0049] First, we will explain the charge / discharge control operation of the secondary battery 2. In the charge / discharge control circuit 10, the charge / discharge control device 20, and the battery device 1, the battery voltage detection circuit 11 detects the voltage between its own terminals and supplies a signal indicating the detected voltage to the control circuit 13.

[0050] The overcurrent detection and release circuit 12 detects the presence or absence of an overcurrent based on the voltage input from the overcurrent detection terminal VINI, and supplies a signal indicating an overcurrent detected state or an overcurrent released state to the control circuit 13. The overcurrent detection and release circuit 12 detects an overcurrent and outputs an overcurrent detection signal when a predetermined time has elapsed since the state transitioned from an overcurrent non-detected state to an overcurrent detected state.

[0051] On the other hand, the overcurrent detection and release circuit 12 outputs a signal to release the overcurrent state based on the voltage input from the external negative voltage input terminal VM in the overcurrent detection state. A signal indicating the determination result by the overcurrent detection and release circuit 12 is supplied to the control circuit 13.

[0052] The control circuit 13 generates charge / discharge control signals that control the on / off of the discharge control FET3 and the charge control FET4 based on at least one of the signal output by the battery voltage detection circuit 11, the determination result by the overcurrent detection and release circuit 12, and the voltage Vm at the external negative voltage input terminal VM. The control circuit 13 supplies the generated charge / discharge control signals to the discharge control signal output terminal DO and the charge control signal output terminal CO, thereby controlling the on / off of the discharge control FET3 and the charge control FET4. The charge / discharge control signals are generated by a first control circuit of the control circuit 13.

[0053] Next, the cell balancing operation of the first cell 2_1 and the second cell 2_2 will be described. An operation start condition and an operation stop condition for the cell balancing operation are set in the control circuit 13. In the charge / discharge control circuit 10, the cell balancing operation starts when the operation start condition is met, and stops when the operation stop condition is met.

[0054] The cell balancing operation starts when a charger is connected to the external positive terminal P+ and the external negative terminal P- to start charging the secondary battery 2, and the overcharge detection voltage V CU In addition to the voltage rising above this level and being in an overcharged state where charging is prohibited, the following conditions are met: (I) The charger remains connected to the external positive terminal P+ and the external negative terminal P- (hereinafter referred to as the "charger connected state"); or (II) The charger is disconnected from the external positive terminal P+ and the external negative terminal P- and is not connected to the external positive terminal P+ and the external negative terminal P- (hereinafter referred to as the "charger disconnected state"), but discharge from the secondary battery 2 to the load connected to the external positive terminal P+ and the external negative terminal P- has not started. The purpose is to satisfy the following.

[0055] The control circuit 13 determines whether the battery is in an overcharged state and whether condition (I) or (II) is satisfied based on at least one of the voltage detected by the battery voltage detection circuit 11, the determination result by the overcurrent detection and release circuit 12, the voltage Vss at the negative power supply terminal VSS, and the voltage Vm at the external negative voltage input terminal VM.

[0056] When the charge / discharge control circuit 10 detects an overcharged state, the charge control FET4 is switched from on to off, and charging of the secondary battery 2 is stopped. Furthermore, if the cell balancing operation start condition of condition (I) or (II) is satisfied, transition to the cell balancing operation state is permitted.

[0057] That is, after the cell balancing operation start condition is satisfied, the charge / discharge control circuit 10 transitions between a cell balancing operation state and a cell balancing stop state according to the voltages of the first cell 2_1 and the second cell 2_2 detected by the battery voltage detection circuit 11. The cell balancing operation state is a state in which the depletion-type FET 17 is connected in parallel to the first cell 2_1 or the second cell 2_2. The cell balancing stop state is a state in which the depletion-type FET 17 is not connected to either the first cell 2_1 or the second cell 2_2.

[0058] Next, the relationship between the voltage of the first cell 2_1 and the voltage of the second cell 2_2 and the cell balancing operating state and the cell balancing stopped state will be described more specifically.

[0059] The voltage of the first cell 2_1 is the overcharge detection voltage V CU In the above case, when the overcharge state of the first cell 2_1 is detected, the depletion-type FET 17 is connected in parallel with the first cell 2_1 (hereinafter referred to as the "first cell discharging state"). CUIn the above case, if the overcharged state of the second cell 2_2 is detected, the depletion-type FET 17 is connected in parallel to the second cell 2_2 (hereinafter referred to as the "second cell discharging state"). Also, if the overcharged state of neither the voltage of the first cell 2_1 nor the voltage of the second cell 2_2 is detected, the cell balancing is stopped in which the depletion-type FET 17 is not connected to either the first cell 2_1 or the second cell 2_2.

[0060] The control signal for transitioning between the cell balancing operating state and the cell balancing stopped state, that is, the control signal for adjusting the individual voltages of the first cell 2_1 and the second cell 2_2, is generated by the second control circuit of the control circuit 13.

[0061] If an overcharged state of the first cell 2_1 is detected after the conditions for starting the cell balancing operation are satisfied, the second control circuit of the control circuit 13 generates a control signal for putting the charge / discharge control circuit 10 into the first cell discharging state and supplies the control signal to each control terminal of the switches 16_1 to 16_4. The switches 16_1 to 16_4 that have received the control signal for putting the charge / discharge control circuit 10 into the first cell discharging state are controlled to open or close (open or short), thereby switching the path within the switch circuit 16 and connecting the depletion-type FET 17 in parallel with the first cell 2_1.

[0062] More specifically, the switches 16_1 and 16_3 are closed, while the remaining switches 16_2 and 16_4 are opened, thereby connecting the cell balancing circuit 15 to the first cell 2_1 via the positive power supply terminal VDD2 and the cell connection terminal VCb. When the depletion-type FET 17 is connected in parallel to the first cell 2_1, a cell balancing current flows to reduce the voltage of the first cell 2_1.

[0063] When a cell balancing current flows to reduce the voltage of the first cell 2_1, the voltage of the first cell 2_1 decreases over time. Eventually, the voltage of the first cell 2_1 reaches the overcharge release voltage V CL and the overcharge release voltage V CLBelow this point, the second control circuit of the control circuit 13 supplies a control signal to each control terminal of the switches 16_1 to 16_4 to transition the charge / discharge control circuit 10 to a cell balancing suspended state in order to stop discharging the first cell 2_1.

[0064] The switches 16_1 to 16_4 receive a control signal for transitioning to the cell balancing stopped state and are switched between open and closed states so that no cell balancing current flows to either the first cell 2_1 or the second cell 2_2. In the charge / discharge control circuit 10, for example, the switch 16_4 is closed while the remaining switches 16_1, 16_2, and 16_3 are opened so that both the first cell 2_1 and the second cell 2_2 are open and the cell balancing circuit 15 is connected to the negative power supply terminal VSS.

[0065] When the discharge of the first cell 2_1 stops, the voltage of the first cell 2_1 drops to the overcharge release voltage V CL On the other hand, the voltage of the second cell 2_2 is determined by the configuration of the secondary battery 2 and the charging voltage V CH From the above relationship, the overcharge release voltage V CL Above reference voltage (=V CH This predetermined voltage is less than the overcharge detection voltage V CU The voltage is determined by the difference between the reference voltage and the overcharge release voltage V CL If the voltage drops below this level, the condition for canceling the overcharge protection operation is met, so the charge control FET4 transitions from off to on, and the charge / discharge control circuit 10 enters a cell balancing operation stop state.

[0066] In the case where an overcharged state of the second cell 2_2 is detected after the conditions for starting the cell balancing operation are met, the description of the first cell 2_1 is replaced with the first cell 2_1 and the first cell discharged state as the second cell 2_2 and the second cell discharged state, respectively.

[0067] That is, when an overcharged state of the second cell 2_2 is detected, the switches 16_1 to 16_4 are controlled to open or close (open or short), and the switches 16_2 and 16_4 are closed, while the remaining switches 16_1 and 16_3 are opened. By controlling the opening and closing of the switches 16_1 to 16_4, a cell balancing current flows to reduce the voltage of the second cell 2_2, and eventually the discharge of the second cell 2_2 stops. When the discharge of the second cell 2_2 stops, the voltage of the second cell 2_2 drops to the overcharge release voltage V CL The voltage of the first cell 2_1 is the overcharge release voltage V CL The voltage becomes a predetermined voltage that satisfies the condition of being equal to or greater than the reference voltage.

[0068] In this way, when the charger is connected to the external terminal, the charge / discharge control circuit 10 detects whether the overcharge detection voltage V CU The cell where the overcharge is detected has the overcharge release voltage V CL The cell balancing operation can be performed until the overcharge detection voltage V CU The cell where the overcharge is detected has the overcharge release voltage V CL When the overcharge detection voltage V reaches , the cell balancing operation stop condition and the condition for canceling the overcharge protection operation are met, so the charge control FET4 transitions from off to on, and the charge / discharge control circuit 10 enters a cell balancing operation stop state. CU If no overcharge is detected, the cell will be released from the overcharge release voltage V CL The voltage becomes a predetermined voltage that satisfies the condition of being equal to or greater than the reference voltage.

[0069] On the other hand, if an overcharge state is not detected in either the first cell 2_1 or the second cell 2_2, the second control circuit of the control circuit 13 generates a control signal for putting the charge / discharge control circuit 10 into a cell balancing stop state and supplies the control signal to each control terminal of the switches 16_1 to 16_4. In the cell balancing stop state, the open / closed states of the switches 16_1 to 16_4 and the connection relationship between the first cell 2_1 and the second cell 2_2 and the cell balancing circuit 15 are as described above.

[0070] Next, the more desirable overcharge release voltage V CL and overcharge detection voltage V CUIn cell balancing, if the voltage drop due to discharge is large, the time until the cell balancing operation is completed will be longer than when the voltage drop due to discharge is small. From the viewpoint of shortening the cell balancing operation time, the overcharge detection voltage V CU and overcharge release voltage V CL The smaller the difference, the better. However, the overcharge detection voltage V CU and overcharge release voltage V CL The difference is determined by design considerations that take into account the operational stability of overcharge detection and overcharge release, and therefore it may be difficult to make the difference excessively small.

[0071] On the other hand, the overcharge release voltage V CL and overcharge detection voltage V CU is the reference voltage and the overcharge release voltage V CL Difference with (V CH / 2-V CL ) and overcharge detection voltage V CU and the reference voltage (V CU -V CH / 2), it is preferable that the deviation between them is small. CU +V CL -V CH The closer to 0 | is, the better, and 0 (zero) is more preferable. This is because the absolute value of the difference between the two |V CU +V CL -V CH This is because the closer | is to 0, the smaller the difference between the voltage of the first cell 2_1 and the voltage of the second cell 2_2 can be made at the time of completion of the cell balancing operation.

[0072] In addition, the above-mentioned overcharge release voltage V CL and overcharge detection voltage V CU From the range of each possible value, the absolute value of the difference between the two |V CU +V CL -V CH | is the reference voltage (=V CH / 2), that is, the following formula (1) is satisfied. 0≦|V CU +V CL -V CH | <V CH / twenty one)

[0073] By expanding the absolute value of the above formula (1) and rearranging the formula, the following formula (2) can be derived. V CH / 2 <V CU +V CL <3V CH / twenty two) Equation (2) is the overcharge release voltage V CL and overcharge detection voltage V CU The sum of these is the charging voltage V CH The absolute value of the difference between the two |V CU +V CL -V CH | is small, the upper and lower limits of equation (2) are CH The range will be narrowed towards.

[0074] The more desirable absolute value of the difference between the two |V CU +V CL -V CH If | is 0, the overcharge release voltage V CL and overcharge detection voltage V CU The sum of these is the charging voltage V CH In other words, this is the case where the following formula (3) is satisfied. V CU +V CL =V CH ---(3)

[0075] According to this embodiment, the circuit for performing cell balancing operation only needs to include a second control circuit that generates a control signal for adjusting the individual voltages of the first cell 2_1 and the second cell 2_2, and a cell balancing circuit 15 that can flow a cell balancing current from the first cell 2_1 or the second cell 2_2 that is the switching destination via a cell discharge resistor. That is, the circuit for performing cell balancing operation of this embodiment has fewer circuits and a simpler configuration than conventional circuits for performing cell balancing operation that have a circuit for measuring the voltage of each battery cell and a circuit for comparing the measured voltages. On the other hand, the circuit for performing cell balancing operation of this embodiment can reduce the number of circuits and simplify the configuration, compared to conventional circuits for performing cell balancing operation that have a circuit for measuring the voltage of each battery cell and a circuit for comparing the measured voltages. On the other hand, the overcharge detection voltage V CUThe voltage after cell balancing of the cell where overcharge is detected is set to the target voltage, the overcharge release voltage V CL can be reduced to

[0076] Furthermore, in the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1 that include the cell balance circuit 15, the cell balance operation is performed, for example, by leaving the charger connected for a long period of time, or by leaving only the secondary battery 2 after charging without connecting any device to the external terminals. In this way, the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1 that include the cell balance circuit 15 can easily perform the cell balance operation, and can minimize variations in the voltage of the first cell 2_1 and the voltage of the second cell 2_2.

[0077] Furthermore, in the charge / discharge control circuit 10, the charge / discharge control device 20, and the battery device 1, which are provided with the cell balance circuit 15, the overcharge detection voltage V CU and overcharge release voltage V CL By setting the set value in a preferable range, the variation in the voltage of the first cell 2_1 and the voltage of the second cell 2_2 at the completion of the cell balancing operation can be reduced. In other words, the voltage of the first cell 2_1 and the voltage of the second cell 2_2 at the completion of the cell balancing operation can be made closer to each other.

[0078] More preferably, the overcharge detection voltage V CU and overcharge release voltage V CL The overcharge detection voltage V that satisfies the above formula (3) can be set. CU and overcharge release voltage V CL By setting the voltage of the first cell 2_1 and the voltage of the second cell 2_2 at the completion of the cell balancing operation, it is possible to make the voltage of the first cell 2_1 and the voltage of the second cell 2_2 equal to each other.

[0079] Furthermore, the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1, which are equipped with the cell balance circuit 15, can switch between a cell balancing operation state and a cell balancing stop state depending on the state of the secondary battery 2 (first cell 2_1 and second cell 2_2) or the connection to a charger. Furthermore, when transitioning to the cell balancing operation state, the transition is made after confirming that the above-mentioned cell balancing operation start conditions (I) or (II) are satisfied, so that unnecessary discharge of the secondary battery 2 due to cell balancing operation can be suppressed.

[0080] The cell balance circuit 15 and the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1 equipped with the cell balance circuit 15 are each equipped with a depletion-type FET 17 having a first end connected to the positive electrode terminals of the first cell 2_1 and the second cell 2_2 via a switch circuit 16, and a second end connected to the negative electrode terminals of the first cell 2_1 and the second cell 2_2 via the switch circuit 16. In the cell balance circuit 15 and the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1 equipped with the cell balance circuit 15, if there is one depletion-type FET 17, the first cell 2_1 and the second cell 2_2 can be selectively discharged by switching the opening and closing (opening or short-circuiting) of switches 16_1 to 16_4.

[0081] Therefore, in the cell balance circuit 15 and the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1 equipped with the cell balance circuit 15, the configuration of the cell discharge resistor can be simplified, and cell balance operation with the same or higher accuracy than conventional ones is possible.

[0082] [Second embodiment] FIG. 4 is a schematic diagram showing an example of the configuration of a cell balance device, a charge / discharge control circuit, a charge / discharge control device, and a battery device according to the second embodiment.

[0083] The battery device 61, the charge / discharge control device 60, and the charge / discharge control circuit 50 are examples of the battery device, the charge / discharge control device, and the charge / discharge control circuit, respectively, according to the second embodiment. The battery device 61 and the charge / discharge control device 60 differ from the battery device 1 and the charge / discharge control device 20, respectively, in that they include a charge / discharge control circuit 50 instead of the charge / discharge control circuit 10, but are otherwise similar.

[0084] Furthermore, the charge / discharge control circuit 50 differs from the charge / discharge control circuit 10 in that the first control circuit and the cell balance circuit 15 are formed on two different semiconductor chips 30 and 40, respectively, that the charge / discharge control circuit 50 is provided with a control circuit 33 having a first control circuit and a control circuit 43 having a second control circuit instead of the control circuit 13 having the first control circuit and the second control circuit, that the control circuit 43 and the cell balance circuit 15 are configured as independent cell balance devices 41, and that the semiconductor chip 30 further includes an output circuit 34 that connects the control circuit 33 and the control circuit 43. However, apart from the above differences, the charge / discharge control circuit 50 is configured similarly to the charge / discharge control circuit 10.

[0085] Therefore, in this embodiment, the differences between the charge / discharge control circuit 50 and the charge / discharge control circuit 10 will be mainly described, and descriptions that overlap with the cell balance circuit 15, the charge / discharge control circuit 10, the charge / discharge control device 20, and the battery device 1 will be omitted.

[0086] The charge / discharge control circuit 50 is formed in a distributed manner on a plurality of, for example, two, semiconductor chips 30, 40. That is, the charge / discharge control circuit 50 includes a circuit formed on the semiconductor chip 30 as the first semiconductor chip (see FIG. 5) and a circuit formed on the semiconductor chip 40 as the second semiconductor chip (see FIG. 6).

[0087] The semiconductor chip 30 is provided with a cell balance control signal terminal CB_CTL in addition to the positive power supply terminal VDD, negative power supply terminal VSS, cell connection terminal VCa, charge control signal output terminal CO, discharge control signal output terminal DO, external negative voltage input terminal VM, and overcurrent detection terminal VINI that the charge / discharge control circuit 10 has.

[0088] The semiconductor chip 40 is provided with a positive power supply terminal VDD corresponding to the positive power supply terminal VDD2 in the charge / discharge control circuit 10, a cell connection terminal VCb corresponding to the cell connection terminal VCb in the charge / discharge control circuit 10, a negative power supply terminal VSS, and a signal input terminal CTL.

[0089] In the semiconductor chip 30, the positive power supply terminal VDD, the negative power supply terminal VSS, the cell connection terminal VCa, the charge control signal output terminal CO, the discharge control signal output terminal DO, the external negative voltage input terminal VM, and the overcurrent detection terminal VINI are connected to the same terminals as in the charge / discharge control circuit 10. The cell balance control signal terminal CB_CTL is connected to the signal input terminal CTL.

[0090] In the semiconductor chip 40, the positive power supply terminal VDD is connected to the positive electrode 2a and the external positive electrode terminal P+. The cell connection terminal VCb is connected to the negative electrode terminal of the first cell 2_1 and the positive electrode terminal of the second cell 2_2. The negative power supply terminal VSS is connected to the negative electrode 2b.

[0091] FIG. 5 is a schematic diagram showing a more detailed configuration example of a circuit formed in a semiconductor chip 30, of a charge / discharge control circuit 50 as a charge / discharge control circuit according to the second embodiment.

[0092] FIG. 6 is a schematic diagram showing a detailed configuration example of a circuit formed in a semiconductor chip 40, that is, a cell balance circuit and a cell balance device according to the second embodiment, of a charge / discharge control circuit 50 as a charge / discharge control circuit according to the second embodiment.

[0093] The charge / discharge control circuit 50 includes a positive power supply terminal VDD, a negative power supply terminal VSS, a cell connection terminal VCa, a charge control signal output terminal CO, a discharge control signal output terminal DO, an external negative voltage input terminal VM, an overcurrent detection terminal VINI, a cell balance control signal terminal CB_CTL, a battery voltage detection circuit 11, an overcurrent detection and release circuit 12, a control circuit 33, an output circuit 34, a signal input terminal CTL, a control circuit 43, a cell balance circuit 15, and a cell connection terminal VCb.

[0094] The semiconductor chip 30 is formed with the following components of the charge / discharge control circuit 50: a positive power supply terminal VDD, a negative power supply terminal VSS, a cell connection terminal VCa, a charge control signal output terminal CO, a discharge control signal output terminal DO, an external negative voltage input terminal VM, an overcurrent detection terminal VINI, and a cell balance control signal terminal CB_CTL, a battery voltage detection circuit 11, an overcurrent detection and release circuit 12, a control circuit 33, and an output circuit 34.

[0095] The control circuit 33 has a terminal connected to the positive power supply terminal VDD, a terminal connected to the negative power supply terminal VSS, a terminal connected to the charge control signal output terminal CO, a terminal connected to the discharge control signal output terminal DO, a terminal connected to the external negative voltage input terminal VM, a terminal connected to the battery voltage detection circuit 11, a terminal connected to the overcurrent detection and release circuit 12, and a terminal connected to the output circuit 34.

[0096] The control circuit 33 also has a first control circuit (not shown) that generates control signals for controlling the charging and discharging of the secondary battery 2 and supplies them to the charge control signal output terminal CO and the discharge control signal output terminal DO, and a determination circuit (not shown) that determines the path between the terminals connected in the cell balance circuit 15, i.e., the path within the switch circuit 16.

[0097] The output circuit 34 is a circuit for outputting a signal indicating a path between terminals connected in the cell balancing circuit 15 from the semiconductor chip 30 to the semiconductor chip 40. The output circuit 34 has a terminal connected to the positive power supply terminal VDD, a terminal connected to the negative power supply terminal VSS, a terminal connected to the cell connection terminal VCa, a terminal connected to the control circuit 33, and a terminal connected to the cell balancing control signal terminal CB_CTL.

[0098] Meanwhile, a cell balance device 41 is formed on the semiconductor chip 40. The cell balance device 41 is an example of a cell balance device according to the second embodiment. The cell balance device 41 includes the positive power supply terminal VDD, the negative power supply terminal VSS, the cell balance circuit 15, the cell connection terminal VCb, the signal input terminal CTL, and the control circuit 43 of the charge / discharge control circuit 50.

[0099] In the cell balance device 41, the positive power supply terminal VDD is connected to the drain of the depletion-type FET 17 via the switch 16_1. Focusing on the switch 16_1, the switch 16_1 includes a first terminal connected to the positive power supply terminal VDD, a second terminal connected to the drain of the depletion-type FET 17, and a control terminal connected to the control circuit 43.

[0100] The negative power supply terminal VSS is connected via the switch 16_4 to the source of the depletion-mode FET 17. Focusing on the switch 16_4, the switch 16_4 includes a first terminal connected to the negative power supply terminal VSS, a second terminal connected to the source of the depletion-mode FET 17, and a control terminal connected to the control circuit 43.

[0101] The cell connection terminal VCb is connected to the drain of the depletion-type FET 17 via the switch 16_2, and is connected to the source of the depletion-type FET 17 via the switch 16_3.

[0102] A control circuit 43 serving as a cell balance control circuit or a second control circuit is connected to the signal input terminal CTL, and is also connected to the control terminals of the switches 16_1 to 16_4.

[0103] The cell balance circuit 15 is an example of a cell balance circuit according to the second embodiment. The cell balance circuit 15 in the charge / discharge control circuit 50 differs from the cell balance circuit 15 in the charge / discharge control circuit 10 in that it is formed on a semiconductor chip 40 different from the semiconductor chip 30 on which the first control circuit is formed, but is otherwise similar, and therefore the same reference numerals are used in this embodiment and description thereof will be omitted.

[0104] Next, the operations of the cell balance device 41, the charge / discharge control circuit 50, the charge / discharge control device 60, and the battery device 61 configured as described above will be described.

[0105] The charge / discharge control circuit 50, the charge / discharge control device 60, and the battery device 61 differ from the charge / discharge control circuit 10, the charge / discharge control device 20, and the battery device 1 in that the cell balance device 41 performs the cell balancing operation, respectively, but there is no substantial difference in that they perform the above-mentioned charge / discharge control operation and cell balancing operation of the secondary battery 2. Therefore, in this embodiment, the cell balancing operation in the charge / discharge control circuit 50, the charge / discharge control device 60, and the battery device 61 will be mainly described, and the charge / discharge control operation of the secondary battery 2 will be omitted from the description of the charge / discharge control operation of the charge / discharge control circuit 10, the charge / discharge control device 20, and the battery device 1.

[0106] In the cell balancing operation of the charge / discharge control circuit 50, the charge / discharge control device 60, and the battery device 61, the control circuit 33 first determines whether to enter a first cell discharging state, a second cell discharging state, or a cell balancing stopped state based on the voltage detected by the battery voltage detection circuit 11, the voltage Vss at the negative power supply terminal VSS, and the voltage Vm at the external negative voltage input terminal VM, and supplies a signal indicating the determination result to the output circuit 34.

[0107] The signal indicating the determination result is a signal representing the path between the terminals connected in the cell balance circuit 15, and can be, for example, a signal indicating the open / close state to be transitioned for each of the switches 16_1 to 16_4, or a signal indicating whether a transition of the open / close state is necessary to set the open / close state to be transitioned.

[0108] The output circuit 34 converts a signal indicating the determination result, i.e., a signal indicating the path between the terminals connected in the cell balancing circuit 15, into a format that can be transmitted from the cell balancing control signal terminal CB_CTL to the signal input terminal CTL of the semiconductor chip 40, and supplies it to the cell balancing control signal terminal CB_CTL.

[0109] The signal supplied to the cell balancing control signal terminal CB_CTL of the semiconductor chip 30 is transmitted to the signal input terminal CTL of the semiconductor chip 40 and supplied from the signal input terminal CTL to the control circuit 43. The control circuit 43 generates control signals for controlling the opening and closing of the switches 16_1 to 16_4 based on the supplied signal. The control circuit 43 supplies the generated control signals to the control terminals of the switches 16_1 to 16_4. The switch circuit 16 receives the control signal from the control circuit 43 and executes or stops the cell balancing operation.

[0110] As described above, the cell balancing circuit 15, and the cell balancing device 41, charge / discharge control circuit 50, charge / discharge control device 60, and battery device 61 that include the cell balancing circuit 15, are configured such that the control circuit 13 in the charge / discharge control circuit 10 is divided into the control circuit 33 and the control circuit 43, and the output circuit 34 that connects the control circuit 33 and the control circuit 43. Meanwhile, the operations of the cell balancing circuit 15, the cell balancing device 41, the charge / discharge control circuit 50, the charge / discharge control device 60, and the battery device 61 are substantially similar to the operations of the cell balancing circuit 15, and the charge / discharge control circuit 10, charge / discharge control device 20, and battery device 1 that include the cell balancing circuit 15. Therefore, the cell balancing circuit 15, the cell balancing device 41, the charge / discharge control circuit 50, the charge / discharge control device 60, and the battery device 61 can achieve the same effects as those of the charge / discharge control circuit 10, the charge / discharge control device 20, and the battery device 1.

[0111] Furthermore, in the charge / discharge control circuit 50, charge / discharge control device 60, and battery device 61, the cell balancing device 41 that performs cell balancing operations is formed on a semiconductor chip 40 that is different from the semiconductor chip 30 that controls charging and discharging of the secondary battery 2. Since the depletion-type FET 17 that generates heat during cell balancing operations is disposed outside the semiconductor chip 30, it is possible to provide a charge / discharge control circuit 50, charge / discharge control device 60, and battery device 61 that are less susceptible to the effects of heat generated during cell balancing operations.

[0112] It should be noted that the present invention is not limited to the above-described embodiments, and in the implementation stage, it can be implemented in various forms other than the above-described examples, and various omissions, substitutions, and modifications can be made within the scope that does not deviate from the gist of the invention.

[0113] For example, the above-described charge / discharge control circuits 10, 50, charge / discharge control devices 20, 60, and battery devices 1, 61 detect the overcharge detection voltage V CU The cell where the overcharge is detected has the overcharge release voltage V CL A condition for stopping the cell balancing operation may be set when a specific condition is met, even before the voltage drops to 0 V. The condition for stopping the cell balancing operation may be set to, for example, a timing at which it is preferable to suppress the discharge of the first cell 2_1 and the second cell 2_2.

[0114] An example of a timing when it is preferable to suppress the discharge of the first cell 2_1 and the second cell 2_2 is as follows: (i) Discharge from the secondary battery 2 to the load device has begun; and (ii) The charger is not connected Whether or not condition (i) or (ii) is satisfied is determined by the control circuit 13 or the control circuit 33 based on at least one of the voltage detected by the battery voltage detection circuit 11, the voltage Vss at the negative power supply terminal VSS, and the voltage Vm at the external negative voltage input terminal VM.

[0115] Such an overcharge detection voltage VCU The cell where the overcharge is detected has the overcharge release voltage V CL Even before the voltage drops to 0V, the charge / discharge control circuit 10, 50, the charge / discharge control device 20, 60, and the battery device 1, 61, in which the conditions for stopping the cell balancing operation are set, stop the cell balancing operation at a timing when it is desired to suppress the discharge of the first cell 2_1 and the second cell 2_2, thereby reducing energy loss associated with the cell balancing operation.

[0116] The charge / discharge control device 20 and the battery device 1 described above are exemplary configurations in which the discharge control FET 3 and the charge control FET 4 are provided on the external negative terminal P- side, i.e., the low side, of the path between the external terminals, but are not limited to this exemplary configuration. The charge / discharge control device and the battery device according to the embodiment may also be provided with the discharge control FET 3 and the charge control FET 4 on the external positive terminal P+ side, i.e., the high side.

[0117] The charge / discharge control circuit 10 described above is an example of a configuration including an overcurrent detection terminal VINI, but is not limited to this example of a configuration. Furthermore, the charge / discharge control device 20 and the battery device 1 described above are examples of a configuration including an overcurrent detection resistor 5 and an overcurrent detection terminal VINI, but are not limited to this example of a configuration. In the charge / discharge control circuit according to the embodiment, the overcurrent detection terminal VINI is an optional component and may be omitted. In the charge / discharge control device and the battery device according to the embodiment, the overcurrent detection resistor 5 and the overcurrent detection terminal VINI are optional components and may be omitted.

[0118] The above-described cell balance circuit 15 is not limited to the configurations exemplified in FIGS. 3 and 6, and other configurations such as the cell balance circuit 15A shown in FIG. 7 may be adopted depending on the configurations of the switch circuit 16 and the cell discharge resistors.

[0119] FIG. 7 is a schematic diagram showing an example of the configuration of a cell balance circuit 15A, which is a modified example of the cell balance circuit according to the embodiment of the present invention.

[0120] The cell balance circuit 15A is configured with a switch circuit 16A and depletion-type FETs 17A (17_1, 17_2) as cell discharge resistors instead of the switch circuit 16A and the depletion-type FET 17 in the cell balance circuit 15. As described above, in the above-described embodiment, the configuration of the switch circuit 16 is not limited to the configurations exemplified in Figures 3 and 6, and the configuration and the number of switches are not important as long as the paths connected to the first cell 2_1 and the second cell 2_2 via the cell discharge resistors can be opened or closed.

[0121] For example, if the cell discharge resistor is a depletion-type FET 17A including cascade-connected depletion-type FETs 17_1 and 17_2, a configuration including three switches 16_1, 16_2, and 16_3, such as the switch circuit 16A illustrated in FIG. 7, can switch between the first cell discharge state, the second cell discharge state, and the cell balancing stopped state. In the switch circuit 16A illustrated in FIG. 7, the first cell discharge state can be achieved by closing the switches 16_1 and 16_3 and opening the switch 16_2. The second cell discharge state can be achieved by closing the switches 16_2 and 16_3 and opening the switch 16_1. The cell balancing stopped state can be achieved by opening all the switches 16_1, 16_2, and 16_3, or by closing the switch 16_2 and opening the switches 16_1 and 16_3.

[0122] The switch circuit 16A may be configured to have two switches 16_1 and 16_2, omitting the switch 16_3. In the case of the switch circuit 16A having two switches 16_1 and 16_2, the first cell discharging state can be achieved by closing the switch 16_1 and opening the switch 16_2. The second cell discharging state can be achieved by closing the switch 16_2 and opening the switch 16_1. The cell balancing stopped state can be achieved by opening both the switches 16_1 and 16_2.

[0123] In the above-described embodiment, the cell discharge resistor is not limited to a single depletion-type FET 17, and any type and number of elements having a current limiting function may be used. The cell discharge resistor may be, for example, an on-resistance of a transistor or a resistive element. The cell discharge resistor may also be configured by connecting one or more elements selected from the depletion-type FET 17, the on-resistance of a transistor, and elements having a current limiting function such as a resistive element.

[0124] The above-described charge / discharge control circuit 10 has been described as an example in which the control circuit 13 has a first control circuit and a second control circuit and is provided outside the cell balance circuit 15, but is not limited to this example. For example, the first control circuit and the second control circuit of the control circuit 13 may be separated, and the cell balance circuit 15 may include the second control circuit.

[0125] When forming the cell balance device, charge / discharge control circuit, charge / discharge control device, and battery device according to the above-described embodiments, the charge / discharge control circuit 10 may be divided into the cell balance circuit 15 and the other components, the battery voltage detection circuit 11, the overcurrent detection and release circuit 12, and the control circuit 13, and each may be formed on a different semiconductor chip.

[0126] Furthermore, the above-described charge / discharge control circuit 50, charge / discharge control device 60, and battery device 61 are examples in which the cell balancing device 41 includes the control circuit 43, but this is not limiting. When forming the cell balancing device, charge / discharge control circuit, charge / discharge control device, and battery device according to this embodiment, the control circuit 43 does not necessarily have to be included in the cell balancing device 41. As long as a desired control signal can be supplied to the switch circuit 16 in the cell balancing device 41, the control circuit 43 as the second control circuit may be included outside the cell balancing device 41, for example, on the semiconductor chip 30.

[0127] These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0128] 1,61 Battery device 2 Secondary battery 2_1 First cell 2_2 Second cell 2a (secondary battery) positive electrode 2b (secondary battery) negative electrode 3 Discharge control FET 4 Charge control FET 10,50 Charge / discharge control circuit 13 Control circuit (first control circuit and second control circuit) 15,15A cell balance circuit 16,16A switch circuit 16_1, 16_2, 16_3, 16_4 switches 17, 17A, 17_1, 17_2 Depletion type FET (cell discharge resistor) 20,60 Charge / discharge control device 30,40 Semiconductor chips 33 Control circuit (first control circuit) 34 Output circuit 41 Cell balance device 43 Control circuit (cell balance control circuit or second control circuit) P+ External positive terminal P- External negative terminal

Claims

1. A circuit connected in parallel to a secondary battery including a battery pack in which a first cell and a second cell are connected in series from a positive electrode to a negative electrode, and which adjusts the individual voltages of the first cell and the second cell, a switch circuit including a first switch capable of opening and closing a first path connecting the positive electrode terminal of the first cell and the negative electrode terminal of the first cell, and a second switch capable of opening and closing a second path connecting the positive electrode terminal of the second cell and the negative electrode terminal of the second cell, and capable of opening and closing the first path and the second path based on control signals supplied to the first switch and the second switch; a cell discharge resistor common to the first cell and the second cell, which is selectively connected to either the first cell or the second cell via the switch circuit, and which discharges the first cell when the first switch is closed and the second switch is open, thereby closing the first path, and discharges the second cell when the second switch is closed and the first switch is open, thereby closing the second path; an overcharge detection voltage for detecting an overcharged state and an overcharge release voltage for releasing the overcharged state are set for the voltages of the first cell and the second cell, respectively; the overcharge release voltage is set to a voltage lower than half the charging voltage, which is the output voltage of a charger that charges the secondary battery; the overcharge detection voltage is set to a voltage higher than half the charging voltage and lower than the charging voltage, a cell balancing circuit characterized in that a condition for releasing the overcharged state in a charger-connected state in which the charger is connected to the external positive terminal and the external negative terminal is that the voltage of one of the first cell and the second cell, which has exceeded the overcharge detection voltage, drops to or below the overcharge release voltage.

2. 2. The cell balancing circuit according to claim 1, wherein the switch circuit switches the first cell and the second cell to a cell balancing stopped state in which they are not connected to the cell discharge resistors, when detecting at least one of a charger unconnected state in which a charger that charges the secondary battery is not connected to the external positive terminal and the external negative terminal, and a state in which the secondary battery is discharging to a device that serves as a load connected to the external positive terminal and the external negative terminal.

3. 3. The cell balance circuit according to claim 1, wherein the overcharge release voltage and the overcharge detection voltage are set so that a value equal to the charging voltage is included within a range that can be taken by the sum of the overcharge detection voltage and the overcharge release voltage.

4. A circuit connected in parallel to a secondary battery including a battery pack in which a first cell and a second cell are connected in series from a positive electrode to a negative electrode, and which adjusts the individual voltages of the first cell and the second cell, a switch circuit including a first switch capable of opening and closing a first path connecting the positive electrode terminal of the first cell and the negative electrode terminal of the first cell, and a second switch capable of opening and closing a second path connecting the positive electrode terminal of the second cell and the negative electrode terminal of the second cell, and capable of opening and closing the first path and the second path based on control signals supplied to the first switch and the second switch; a cell discharge resistor common to the first cell and the second cell, which is selectively connected to either the first cell or the second cell via the switch circuit, and discharges the first cell when the first switch is closed and the second switch is open, thereby closing the first path, and discharges the second cell when the second switch is closed and the first switch is open, thereby closing the second path; a cell balance control circuit that generates the control signal and supplies the generated control signal to the first switch and the second switch; a positive power supply terminal connected to a first end of the cell discharge resistor via the switch circuit; a negative power supply terminal connected to the second end of the cell discharge resistor via the switch circuit; a signal input terminal connected to the cell balance control circuit; an overcharge detection voltage for detecting an overcharged state and an overcharge release voltage for releasing the overcharged state are set for the voltages of the first cell and the second cell, respectively; the overcharge release voltage is set to a voltage lower than half the charging voltage, which is the output voltage of a charger that charges the secondary battery; the overcharge detection voltage is set to a voltage higher than half the charging voltage and lower than the charging voltage, a condition for releasing the overcharged state in a charger-connected state in which the charger is connected to the external positive terminal and the external negative terminal is that the voltage of one of the first cell and the second cell, which has exceeded the overcharge detection voltage, drops to or below the overcharge release voltage.

5. A charge / discharge control circuit for controlling the charge / discharge of the secondary battery, a positive power supply terminal to which a voltage from the positive electrode of the secondary battery is supplied; a negative power supply terminal to which a voltage from the negative electrode of the secondary battery is supplied; a cell connection terminal to which a voltage is supplied from a contact point between the first cell and the second cell; an external negative voltage input terminal connected to the external negative terminal; a charge control signal output terminal for outputting a charge control signal for controlling stopping and allowing charging of the secondary battery; a discharge control signal output terminal for outputting a discharge control signal for controlling stopping and allowing discharge of the secondary battery; a battery voltage detection circuit connected to the positive power supply terminal, the cell connection terminal, and the negative power supply terminal, respectively, for detecting the voltage of the secondary battery and the voltage of each cell based on the voltages supplied from the positive power supply terminal, the cell connection terminal, and the negative power supply terminal; a first control circuit that generates the charge control signal and the discharge control signal based on detection signals of the voltage of the secondary battery and the voltage of each cell from the battery voltage detection circuit; a second control circuit that generates control signals to be supplied to the first switch and the second switch based on detection signals of the voltage of the secondary battery and the voltage of each cell, the voltage of the negative power supply terminal, and the voltage of the external negative voltage input terminal; The cell balance circuit according to any one of claims 1 to 3; a signal output terminal connected to the output terminal of the cell balance circuit; A charge / discharge control circuit comprising:

6. the charge / discharge control circuit is formed on a plurality of semiconductor chips; The charge / discharge control circuit according to claim 5 , wherein the cell balance circuit is formed on a second semiconductor chip different from a first semiconductor chip on which the first control circuit is formed.

7. a charge / discharge control circuit according to claim 5 or 6; the external positive electrode terminal and the external negative electrode terminal; a charge control FET including a gate connected to the charge control signal output terminal and one end connected to the external negative terminal; a discharge control FET having a gate connected to the discharge control signal output terminal and one end connected to the other end of the charge control FET;

8. a charge / discharge control circuit according to claim 5 or 6; the secondary battery; the external positive electrode terminal and the external negative electrode terminal; a charge control FET including a gate connected to the charge control signal output terminal and one end connected to the external negative terminal; a discharge control FET having a gate connected to the discharge control signal output terminal and one end connected to the other end of the charge control FET;

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