Storage device and storage system

Abstract

To provide a storage device capable of transmitting a plurality of responses to one command to a host.SOLUTION: A controller of a storage device maintains one or more second type commands for enabling the storage device to transmit one of one or more preceding responses for a first type command to a host in a memory region without completing received one or more second type commands according to the reception from the host. The controller completes one second type command according to reception of the first type command from the host, and transmits a command completion response to the completed one second type command to the host as a first preceding response to the first type command. The controller transmits a command completion response for the completed first type command to the host according to completion of the first type command processing.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD OF THE INVENTION Embodiments of the present invention relate to techniques for controlling non-volatile memory. [Background technology]

[0002] In recent years, storage devices equipped with nonvolatile memories have become widespread. One such storage device is a solid-state drive (SSD) equipped with a NAND flash memory.

[0003] In communication between a storage device such as an SSD and a host, a logical interface standard may be used that allows the storage device to send one completion response to the host for one command issued by the host.

[0004] In storage devices that communicate with hosts in accordance with such logical interface standards, there is a demand for the realization of new technology that enables multiple responses to a single command to be sent to the host. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0050402 [Patent Document 2] US Patent Application Publication No. 2018 / 0335975 [Patent Document 3] U.S. Patent No. 10,705,974 Summary of the Invention [Problem to be solved by the invention]

[0006] A problem to be solved by one embodiment of the present invention is to provide a storage device and a storage system that are capable of sending multiple responses to a host in response to one command. [Means for solving the problem]

[0007] According to an embodiment, a storage device communicates with a host in accordance with a logical interface standard that allows one completion response to be sent by the storage device to the host for one command issued by the host. The storage device includes a non-volatile memory and a controller configured to send to the host one or more prior responses to a first-type command requesting the storage device to perform a predetermined operation, and a command completion response indicating that the first-type command has been completed. The one or more prior responses include at least a first prior response indicating acceptance of the first-type command. Each of the one or more prior responses is a response sent by the storage device to the host before the command completion response. In response to receiving one or more second-type commands from the host that enable one of the one or more prior responses to be sent by the storage device to the host, the controller maintains the received one or more second-type commands in a memory area within the storage device without completing them. In response to receiving the first type command from the host, the controller retrieves one second type command from the memory area, completes the retrieved one second type command, and transmits a command completion response for the completed one second type command to the host as the first preceding response to the first type command. In response to completing processing of the first type command, the controller transmits the command completion response for the completed first type command to the host. [Brief explanation of the drawings]

[0008] [Figure 1]FIG. 1 is a block diagram showing an example of the configuration of a storage system including a storage device according to an embodiment. [Figure 2] FIG. 2 is a diagram for explaining the division of roles between a host and a storage device according to the embodiment. [Figure 3] FIG. 2 is a block diagram showing an example of the configuration of a host and an example of the configuration of a storage device according to the embodiment. [Figure 4] FIG. 2 is a block diagram showing the relationship between a NAND interface and multiple NAND flash memory dies provided in a storage device according to an embodiment. [Figure 5] FIG. 2 is a diagram showing an example of the configuration of a block group managed in a storage device according to the embodiment. [Figure 6] A diagram showing operations performed in a storage device of an embodiment, including maintaining one or more second type commands in a pool that are sent in advance from a host, sending a completion response to one of the second type commands in the pool to the host as a prior response to a first type command sent from the host, and sending a completion response to the host indicating the completion of the first type command in response to the completion of the first type command. [Figure 7] A diagram showing an operation performed in a storage device of an embodiment, in which one second type command sent in advance from the host is maintained in a pool, an operation in which a completion response to the second type command in the pool is sent to the host as a preceding response to a first type command sent from the host, and an operation in which a completion response indicating the completion of the first type command is sent to the host in response to the completion of the first type command. [Figure 8] FIG. 10 is a diagram showing an example of the configuration of a write command issued as a first type command to a storage device according to the embodiment. [Figure 9] FIG. 10 is a diagram showing an example of the configuration of a flash address read command issued as a second type command to a storage device according to the embodiment. [Figure 10] FIG. 10 is a diagram showing an example of the configuration of a preceding response sent to a host by a storage device according to the embodiment. [Figure 11] FIG. 10 is a diagram showing another example of the configuration of a write command issued as a first type command to a storage device according to the embodiment. [Figure 12] FIG. 10 is a diagram showing another example of the configuration of a flash address read command issued as a second type command to the storage device according to the embodiment. [Figure 13] FIG. 10 is a diagram showing another example of the configuration of a preceding response sent to a host by a storage device according to the embodiment. [Figure 14] FIG. 4 is a diagram showing an example of the configuration of a read command issued to a storage device according to the embodiment. [Figure 15] FIG. 10 is a diagram showing an example of the configuration of a quality of service (QoS) domain create command issued to a storage device according to the embodiment. [Figure 16] FIG. 10 is a diagram showing the relationship between block addresses and offsets when block groups are used. [Figure 17] FIG. 2 is a diagram showing a plurality of QoS domains managed in a storage device according to an embodiment. [Figure 18] FIG. 1 is a block diagram showing the relationship between multiple QoS domains and a common flash block pool managed in a storage device according to an embodiment. [Figure 19] FIG. 2 is a block diagram illustrating a data write process executed by a storage device and a host according to the embodiment. [Figure 20] FIG. 10 is a diagram showing operations executed in a storage device according to an embodiment, in which one or more flash address read commands (FARs) sent in advance from a host are maintained in a FAR pool, an operation of sending a completion response to one of the flash address read commands in the FAR pool to the host as a preemptive response to a write command sent from the host, and an operation of sending a completion response to the host indicating completion of the write command in response to completion of the write command. [Figure 21]FIG. 10 is a diagram showing an operation executed in a storage device according to an embodiment, in which a single flash address read command (FAR) sent in advance from a host is maintained in a FAR pool, an operation in which a completion response to the flash address read command in the FAR pool is sent to the host as a preceding response to a write command sent from the host, and an operation in which a completion response indicating the completion of the write command is sent to the host in response to the completion of the write command. [Figure 22] FIG. 1 is a block diagram showing an operation executed in a storage device according to an embodiment, in which one or more flash address read commands (FARs) that specify the same memory resource are maintained in the same FAR pool, an operation of sending a preemptive response to a write command to a host using a flash address read command (FAR) maintained in the FAR pool that corresponds to a memory resource specified by a write command, and an operation of sending a completion response to the write command to a host. [Figure 23] FIG. 1 is a block diagram illustrating operations for maintaining one or more flash address read commands (FARs) that specify a superblock in a FAR pool corresponding to the superblock, sending a preemptive response to a write command that specifies the superblock to a host, and sending a completion response to the write command to a host. [Figure 24] 10 is a flowchart showing the procedure of processing for a flash address read command (FAR) executed in the storage device according to the embodiment. [Figure 25] 10 is a flowchart showing the procedure of processing for a write command, which is executed in a storage device according to the embodiment. [Figure 26] 10 is a flowchart showing the procedure of a process executed in the host. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment will be described with reference to the drawings. FIG. 1 is a block diagram showing an example of the configuration of a storage system including a storage device according to an embodiment of the present invention.

[0010] The storage system 1 includes a host (host device) 2 and a storage device 3. The host (host device) 2 is an information processing device configured to access one or more storage devices 3. The information processing device is, for example, a personal computer or a server computer.

[0011] In the following, a case where an information processing device such as a server computer is used as the host 2 will be mainly described.

[0012] A typical example of a server computer that functions as a host 2 is a server computer (hereinafter referred to as a server) in a data center.

[0013] In the case where the host 2 is realized by a server in a data center, the host 2 may be connected to a plurality of end user terminals (clients) 61 via a network 60. The host 2 can provide various services to these end user terminals 61.

[0014] Examples of services that can be provided by host 2 include (1) Platform as a Service (PaaS), which provides a system operating platform to each client (each end-user terminal 61), and (2) Infrastructure as a Service (IaaS), which provides infrastructure such as a virtual server to each client (each end-user terminal 61).

[0015] A plurality of virtual machines may be executed on the physical server functioning as the host 2. Each of these virtual machines running on the host 2 can function as a virtual server configured to provide various services to the client (end user terminal 61) corresponding to that virtual machine. An operating system and user applications used by the end user terminal 61 corresponding to that virtual machine are executed in each virtual machine.

[0016] A flash translation layer (host FTL) 301 is also executed in the host (server) 2. This host FTL 301 includes a lookup table (LUT), which is an address translation table that manages the mapping between each data identifier and each physical address of the nonvolatile memory in the storage device 3. By using this LUT, the host FTL 301 can know the data layout on the nonvolatile memory in the storage device 3.

[0017] The storage device 3 is a semiconductor storage device configured to write data to a nonvolatile memory and read data from the nonvolatile memory.

[0018] The storage device 3 can execute low-level abstraction. Low-level abstraction is a function for abstracting nonvolatile memory. The low-level abstraction includes a function to assist data placement. The function to assist data placement includes, for example, a function to assign a physical address indicating a physical storage location in nonvolatile memory where user data should be written in response to a write command sent from the host 2, and a function to notify the upper layer (host 2) of this assigned physical address.

[0019] The storage device 3 is connected to the host 2 via a cable or a network. Alternatively, the storage device 3 may be built into the host 2.

[0020] The communication between the host 2 and the storage device 3 is performed using a logical interface standard that allows the storage device 3 to send one completion response to the host 2 in response to one command issued by the host 2. The storage device 3 performs communication with the host 2 in accordance with this logical interface standard. This logical interface standard is, for example, NVM express TM (NVMe TM When the NVMe standard is used as this logical interface standard, the physical interface 50 connecting the storage device 3 and the host 2 may be, for example, a PCI Express TM (PCIe TM ), or Ethernet TM is used.

[0021] Next, we will explain the roles of the host 2 and the storage device 3. Figure 2 is a diagram showing the division of roles between the storage device 3 and the host 2.

[0022] A plurality of virtual machines 401 corresponding to a plurality of end users are executed on the host (server) 2. An operating system and user applications 402 used by the corresponding end user are executed on each virtual machine 401.

[0023] Additionally, the host (server) 2 executes multiple I / O services 403 corresponding to multiple user applications 402, respectively. These I / O services 403 may include a logical block address (LBA)-based block I / O service, a key-value store service, etc. Each I / O service 403 includes a lookup table (LUT) that manages the mapping between each user address tag and each physical address of the storage device 3.

[0024] Here, the user address tag refers to a data identifier that can identify the data to be accessed. An example of this user address tag is, but is not limited to, a logical address such as a logical block address (LBA). Alternatively, a key in a key-value store, or a hash value of this key, may be used as the user address tag.

[0025] The physical address of the storage device 3 is an address for specifying a storage location (physical storage location) within the nonvolatile memory included in the storage device 3.

[0026] In the LBA-based block I / O service, a LUT may be used that manages the mapping between each logical address (LBA) and each physical address of the storage device 3 .

[0027] On the other hand, in a key-value store service, a LUT may be used that manages the mapping between each key (or hash value of the key), each physical address of the storage device 3 where the data corresponding to these keys is stored, and the data length of each piece of data corresponding to these keys.

[0028] Each end user can choose which addressing method to use (LBA, a key in a key-value store, a hash value of this key, etc.).

[0029] The host (server) 2 may manage a plurality of write buffers (WB) 404 corresponding to a plurality of virtual machines 401, respectively. Write data from a certain user application 402 may be temporarily stored in the write buffer (WB) 404 for the virtual machine 401 corresponding to this user application 402.

[0030] The transmission of commands from the host (server) 2 to the storage device 3 and the return of command completion responses from the storage device 3 to the host (server) 2 are executed via an I / O queue 500. Commands sent from the host 2 to the storage device 3 include write commands and read commands. A write command is a command for writing data to nonvolatile memory in the storage device 3. A read command is a command for reading data to be read from the nonvolatile memory.

[0031] The storage device 3 manages multiple memory resources included in the nonvolatile memory within the storage device 3. The multiple memory resources are, for example, multiple areas obtained by logically dividing the nonvolatile memory. Each of the multiple areas is managed as a quality of service (QoS) domain 601. Each of these QoS domains 601 is a subset of multiple block groups included in the nonvolatile memory.

[0032] Each of the plurality of block groups includes one or more blocks (physical blocks) included in the nonvolatile memory, and is also referred to as a superblock.

[0033] Each of the multiple block groups belongs to only one QoS domain 601, and the same block group does not simultaneously belong to different QoS domains 601. This makes it possible to realize data allocation in which, for example, different QoS domains 601 are assigned to different end users, and data for different end users is written to different physical storage areas.

[0034] These QoS domains 601 are each identified by an identifier called a QoS domain ID. These QoS domain IDs are used as multiple identifiers for accessing these multiple areas (multiple QoS domains), respectively.

[0035] Alternatively, the multiple memory resources may be multiple block groups (superblocks) included in a non-volatile memory. In this case, data allocation can be achieved by writing data for different end users to different superblocks. Each superblock is identified by an identifier called a superblock ID.

[0036] The storage device 3 manages a common free block pool 602. The common free block pool is used to manage a collection of free superblocks that are shared by multiple QoS domains 601.

[0037] A free superblock is a superblock that is available (free) as a new write destination superblock. A free superblock is a superblock that does not store valid data. Valid data is the latest data associated with a user address tag such as an LBA. In other words, data that is linked as the latest data from the LUT of the host 2 is valid data. Invalid data is data that is not associated with a user address tag such as an LBA. For example, when updated data corresponding to a certain LBA is written to the storage device 3, the previous data corresponding to this LBA becomes invalid data.

[0038] For each QoS domain, the storage device 3 allocates one of the free superblocks in the common free block pool 602 as a destination superblock. The destination superblock is the superblock to which data should be written. For each QoS domain, the storage device 3 can also simultaneously allocate two or more destination superblocks from the free superblocks in the common free block pool 602.

[0039] In this case, multiple region identifiers called placement IDs are set for each QoS domain. For example, if placement ID 1 and placement ID 2 are set for QoS domain #1, the storage device 3 allocates one of the free superblocks in the common free block pool 602 as the destination superblock for placement ID 1 of QoS domain #1.

[0040] Furthermore, storage device 3 allocates another free superblock in the common free block pool 602 as a destination superblock for placement ID2 in QoS domain #1.

[0041] When a write command specifying QoS domain #1 and placement ID 1 is received from host 2, storage device 3 writes the data associated with this received write command to the destination superblock for placement ID 1 in QoS domain #1. On the other hand, when a write command specifying QoS domain #1 and placement ID 2 is received from host 2, storage device 3 writes the data associated with this received write command to the destination superblock for placement ID 2 in QoS domain #1.

[0042] This allows data associated with placement ID 1 of QoS domain #1 and data associated with placement ID 2 of QoS domain #1 to be written in different areas within QoS domain #1.

[0043] Next, the configuration of the host and the configuration of the storage device will be described. Fig. 3 is a block diagram showing an example of the configuration of the host and an example of the configuration of the storage device according to the embodiment.

[0044] The host 2 includes a processor 101 and a memory 102. The processor 101 is a CPU (Central Processing Unit) configured to control each component within the host 2. The processor 101 executes software (host software) loaded into the memory 102 from the storage device 3 or another storage device within the host 2. The host software includes an operating system, a file system, a device driver, an application program, and the like.

[0045] The memory 102 is a main memory provided in the host 2. The memory 102 is a volatile semiconductor memory in which stored contents are lost when the power supply is stopped. The memory 102 is, for example, a random access memory such as a DRAM (Dynamic Random Access Memory).

[0046] A portion of the storage area of ​​the memory 102 is used to store one or more submission queue / completion queue pairs (SQ / CQ pairs). Figure 3 illustrates an example in which a plurality of SQ / CQ pairs are stored in a portion of the storage area of ​​the memory 102. Each SQ / CQ pair includes at least one submission queue (SQ) and a completion queue (CQ) associated with the at least one submission queue (SQ).

[0047] The submission queue (SQ) is a queue used to issue commands to the storage device 3. The completion queue (CQ) is a queue used to receive a command completion response from the storage device 3 indicating completion of the command.

[0048] In the NVMe standard interface, at least one SQ / CQ pair is used to issue each command from host 2 to SSD 3 and to send each command completion from SSD 3 to host 2.

[0049] In this case, each command is stored in an arbitrary submission queue (SQ) by the host 2. When processing of a command is completed, a command completion response (also referred to as "command completion," "completion," or "completion message") indicating the completion of this command is stored by the controller 4 of the SSD 3 in a completion queue (CQ) associated with the submission queue (SQ) used to issue this command.

[0050] The SSD 3 includes a controller 4 and a non-volatile memory (for example, a NAND flash memory 5). The SSD 3 may also include a random access memory such as a DRAM 6.

[0051] The NAND flash memory 5 includes a memory cell array including a plurality of memory cells arranged in a matrix. The NAND flash memory 5 may be a flash memory with a two-dimensional structure or a flash memory with a three-dimensional structure.

[0052] The memory cell array of the NAND flash memory 5 includes a plurality of blocks BLK0 to BLKx-1. Each of the blocks BLK0 to BLKx-1 includes a plurality of pages (here, pages P0 to Py-1). Each page includes a plurality of memory cells connected to the same word line. Each of the blocks BLK0 to BLKx-1 is a unit of a data erase operation for erasing data. Each of the pages P0 to Py-1 is a unit of a data write operation and a data read operation.

[0053] The controller 4 is a memory controller configured to control the NAND flash memory 5. The controller 4 may be realized by a circuit such as a System-on-a-chip (SoC). The controller 4 is electrically connected to the NAND flash memory 5 via a NAND interface 13 that complies with, but is not limited to, the Toggle NAND flash interface or the Open NAND Flash Interface (ONFI).

[0054] In addition to the above-mentioned NAND interface 13, the controller 4 includes a host interface 11, a CPU 12, a DRAM interface 14, a direct memory access controller (DMAC) 15, a static RAM (SRAM) 16, and an ECC encoding / decoding unit 17. The host interface 11, CPU 12, NAND interface 13, DRAM interface 14, DMAC 15, SRAM 16, and ECC encoding / decoding unit 17 are interconnected via a bus 10.

[0055] The host interface 11 is a host interface circuit configured to communicate with the host 2. The host interface 11 is, for example, a PCIe controller. Alternatively, if the SSD 3 has a configuration in which a network interface controller is built in, the host interface 11 may be realized as part of the network interface controller.

[0056] The host interface 11 communicates with the host 2 in accordance with, for example, the NVMe standard. The host interface 11 includes an arbitration mechanism. This arbitration mechanism is a mechanism for selecting a submission queue from which a command is to be fetched from multiple submission queues present in the memory 102 of the host 2. The arbitration mechanism may be a round-robin arbitration mechanism or a weighted round-robin arbitration mechanism. Then, under the control of the CPU 12, the host interface 11 fetches one or more commands from the submission queue selected by the arbitration mechanism.

[0057] The CPU 12 is a processor configured to control the host interface 11, the NAND interface 13, the DRAM interface 14, the DMAC 15, the SRAM 16, and the ECC encoding / decoding unit 17. The CPU 12 performs various processes by executing a control program (firmware). The CPU 12 loads the control program (firmware) from a ROM or NAND flash memory 5 (not shown) into the SRAM 16 or the DRAM 6 in response to the supply of power to the storage device 3.

[0058] The NAND interface 13 is a NAND controller configured to control the NAND flash memory 5 under the control of the CPU 12. When the NAND flash memory 5 is composed of multiple NAND flash memory dies (NAND flash memory chips), the NAND interface 13 may be connected to each of these NAND flash memory dies via multiple channels (Ch).

[0059] The DRAM interface 14 is a DRAM controller configured to control the DRAM 6 under the control of the CPU 12 .

[0060] A portion of the storage area of ​​the DRAM 6 is used to store a flash address read (FAR) pool 31 and a block management table 32. The FAR pool 31 is used as a memory area for maintaining each specific command issued by the host 2 without completing it. The block management table 32 is used to manage information indicating the status of each of a plurality of superblocks. The information indicating the status of each superblock includes, for example, information indicating the number of times each superblock has been erased, information indicating whether each superblock is an active block or a free block, etc.

[0061] The internal buffer 161 is used as a storage area for temporarily storing data received from the host 2 and data to be transmitted to the host 2. The internal buffer 161 is allocated, for example, within the storage area of ​​the SRAM 16. Alternatively, the internal buffer 161 may be allocated within the storage area of ​​the DRAM 6.

[0062] The DMAC 15 executes data transfer between the memory 102 of the host 2 and the internal buffer 161 under the control of the CPU 12 .

[0063] When data is to be written to the NAND flash memory 5, the ECC encoding / decoding unit 17 encodes the data (data to be written) to add an error correction code (ECC) to the data as a redundant code. When data is read from the NAND flash memory 5, the ECC encoding / decoding unit 17 corrects errors in the read data using the ECC added to the data.

[0064] Next, we will explain the detailed configuration of the CPU 12. For each first type command, the CPU 12 executes a multi-phase completion response process in which it transmits to the host 2 one or more preceding responses to the first type command and a command completion response indicating that the first type command has been completed.

[0065] For example, a two-phase completion response process is executed in which a first preliminary response is sent by the controller 4 to the host 2 when a first type command is accepted, and a command completion response is sent by the controller 4 to the host 2 when processing of the first type command is completed.

[0066] Alternatively, a three-phase completion response process may be performed in which a first preceding response is sent by the controller 4 to the host 2 when the first type command is accepted, a second preceding response is sent by the controller 4 to the host 2 when processing of the first type command begins, and a command completion response is sent by the controller 4 to the host 2 when processing of the first type command is completed.

[0067] Alternatively, a four-phase completion response process may be performed in which a first preceding response is sent by the controller 4 to the host 2 when the first type command is accepted, a second preceding response is sent by the controller 4 to the host 2 when processing of the first type command is initiated, a third preceding response is sent by the controller 4 to the host 2 when processing of the first type command is interrupted, and a command completion response is sent by the controller 4 to the host 2 when processing of the first type command is completed.

[0068] By executing the multi-phase completion response processing, even if it takes a long time from when the first type command is accepted until the processing of the first type command is completed, the controller 4 can notify the host 2 of information regarding the processing of the first type command as one advance response to the first type command.

[0069] To realize the multi-phase completion response processing, the CPU 12 functions as a command fetch unit 21 and a command processing unit 22. A part or all of each of the command fetch unit 21 and the command processing unit 22 may be realized by dedicated hardware within the controller 4.

[0070] The command fetch unit 21 fetches a command issued by the host 2 from a submission queue (SQ). In this embodiment, if the fetched command is a first type command, the command fetch unit 21 transmits the fetched command to the command processing unit 22. A first type command is a specific type of command that requests the storage device 3 to execute a predetermined process.

[0071] If the fetched command is a second type command, the command fetch unit 21 does not complete the fetched command but keeps it in the FAR pool 31. The second type command is a command that enables one of one or more preceding responses to the first type command to be sent by the storage device 3 to the host 2.

[0072] Each of the one or more preceding responses is a response sent by the storage device 3 to the host 2 before the command completion response indicating that the first type command has been completed. The one or more preceding responses include at least a first preceding response indicating that the first type command has been accepted by the controller 4. Furthermore, the one or more preceding responses may include, for example, in addition to the first preceding response, a second preceding response indicating the start of processing of the first type command. Furthermore, the one or more preceding responses may include, in addition to the first preceding response and the second preceding response, a third preceding response indicating the interruption of processing of the first type command.

[0073] The host 2 issues one or more second type commands to the storage device 3 in advance before issuing the first type command to the storage device 3 in order to receive each of one or more previous responses to the first type command from the storage device 3.

[0074] In the controller 4, each of the one or more second type commands issued from the host 2 is not immediately completed, but is maintained in the FAR pool 31, which is a memory area in the storage device 3. Then, when a first type command is received from the host 2, the controller 4 completes one of the second type commands maintained in the FAR pool 31 in order to send a first preceding response to the host 2.

[0075] More specifically, when a first type command is received from the host 2, the command processing unit 22 acquires one second type command from the one or more second type commands from the FAR pool 31. Then, the command processing unit 22 completes the acquired one second type command and transmits a command completion response to the completed one second type command to the host 2 as a first preceding response to the first type command.

[0076] In this case, a command completion response to the second type command, including information representing the first preceding response, may be stored in one entry (completion queue entry) in the completion queue (CQ).

[0077] The size of one completion queue entry is 16 bytes. Therefore, when a configuration is used in which a command completion response to a second type command, including information representing the first preceding response, is stored in one completion queue entry, the maximum size of the information representing the first preceding response to a first type command is limited to a relatively small size.

[0078] In this embodiment, for example, a type of read command that involves data transfer from the controller 4 to the host 2 is used as the second type command. The second type command, which is a type of read command, includes a pointer that indicates a buffer area included in the memory 102 of the host 2 to which information should be transferred.

[0079] In this case, information regarding the processing of the first type command can be transferred as a first prior response to the buffer area specified by this pointer. The size of the buffer area included in memory 102 can be set to a sufficiently large size. Therefore, by transferring information regarding the processing of the first type command to the buffer area of ​​memory 102 as the first prior response, it is possible to increase the amount of information that can be notified to host 2 as the first prior response.

[0080] Then, when the processing of this first type command is completed, the command processing unit 22 transmits a command completion response indicating the completion of the first type command to the host 2. In this case, the command completion response indicating the completion of the first type command is stored in one completion queue entry.

[0081] Thus, in this embodiment, a second type command is issued in advance by the host 2 to the storage device 3, enabling the storage device 3 to send a preceding response to the first type command to the host 2. Then, when a first type command issued by the host 2 is received, the controller 4 of the storage device 3 completes one of the second type commands issued in advance, and sends a command completion response to the completed second type command to the host 2 as a first preceding response, which is one of the preceding responses to the first type command.

[0082] Next, a case where a kind of read command that accompanies data transfer from the controller 4 to the host 2 is used as the second type command will be described.

[0083] In this case, each of the one or more second type commands includes a pointer to a buffer area in memory 102 to which the information is to be transferred.

[0084] When a first type command is received from the host 2, the command processing unit 22 acquires one second type command from the one or more second type commands from the FAR pool 31. Then, the command processing unit 22 completes the acquired one second type command, and executes the following operations: (1) sending a command completion response for the completed one second type command to the host 2; and (2) transferring information related to the processing of the first type command to a buffer area in the memory 102 indicated by the pointer as a first preceding response.

[0085] That is, the command completion response to the second type command is stored in the completion queue (CQ), while information regarding the processing of the first type command is transferred to a buffer area in the memory 102 as a first preceding response.

[0086] In this way, by using a kind of read command that involves data transfer from the controller 4 to the host 2 as the second type command, it is possible to transfer a preceding response to the first type command to a buffer area in the memory 102 that has a size larger than the completion queue (CQ) entry. Therefore, it is possible to send various information related to the processing of the first type command to the host 2 as a preceding response to the first type command.

[0087] Next, a configuration using a plurality of FAR pools corresponding to a plurality of memory resources included in the NAND flash memory 5 will be described.

[0088] The multiple memory resources may be, for example, multiple areas in the NAND flash memory 5 identified by multiple QoS domain IDs, or may be, for example, multiple superblocks in the NAND flash memory 5 identified by multiple superblock IDs.

[0089] Each of the first type commands includes (1) a parameter that specifies the memory resource to be processed among the multiple memory resources included in the NAND flash memory 5, and (2) a parameter that specifies a process identifier (process ID) that indicates the process that has requested the execution of the processing corresponding to this first type command among the multiple processes executed by the host 2.

[0090] The controller 4 manages a plurality of FAR pools, which are a plurality of memory areas associated with a plurality of memory resources. The command fetch unit 21 receives a plurality of second type commands from the host 2, each of which includes a parameter specifying one of the plurality of memory resources and a parameter specifying a process identifier indicating one of the plurality of processes. The command fetch unit 21 maintains each of the received second type commands in one of the plurality of FAR pools based on the memory resource specified by each of the received second type commands, so that each second type command specifying the same memory resource is maintained in the same FAR pool.

[0091] That is, each second-type command specifying memory resource #1 is maintained in FAR pool #1 corresponding to memory resource #1. Similarly, each second-type command specifying memory resource #2 is maintained in FAR pool #2 corresponding to memory resource #2.

[0092] When a first type command is received from the host 2, the command processing unit 22 first selects, from a plurality of FAR pools, a FAR pool (here, the first FAR pool) corresponding to the processing target memory resource specified by the received first type command. The command processing unit 22 acquires, from the second type commands maintained in the selected first FAR pool, a second type command that specifies the same process identifier as the process identifier specified by the received first type command. This makes it possible to easily acquire a second type command that specifies the same resource identifier as the resource identifier specified by the received first type command and that specifies the same process identifier as the process identifier specified by the received first type command.

[0093] The command processing unit 22 then completes the acquired second type command and transmits a command completion response for the completed second type command to the host 2 as a first preceding response to the received first type command. If the acquired second type command includes a data pointer indicating a buffer area in the memory 102 of the host 2 to which information is to be transferred, the command processing unit 22 transfers information related to the processing of the received first type command to this buffer area in the memory 102 as a first preceding response to the received first type command. For example, the command processing unit 22 transmits a memory write request to the host 2. As a result, the command processing unit 22 stores information related to the processing of the received first type command in the buffer area in the memory 102 indicated by the data pointer via the processor 101 of the host 2. This makes it possible to prevent processes other than the process that requested the execution of the processing corresponding to the first type command from referencing information related to the processing of this first type command.

[0094] Furthermore, each of the one or more preceding responses also includes identification information included in the received first type command. When the received first type command includes a resource identifier for identifying a processing target memory resource among multiple memory resources included in the NAND flash memory 5, the identification information included in each of the one or more preceding responses to the received first type command includes the resource identifier included in the received first type command. Furthermore, the identification information included in each of the one or more preceding responses to the first type command includes at least one of a submission queue ID (SQID) that is an identifier for identifying the submission queue (SQ) from which the first type command was fetched, a command ID that is a command identifier for identifying the received first type command, or an arbitrary numeric value assigned to the first type command by the host 2.

[0095] If there is no second-type command that specifies the same process identifier as the process identifier specified by the received first-type command among the second-type commands maintained in the selected first FAR pool, the command processing unit 22 completes the received first-type command as an error. In this case, the command processing unit 22 transmits to the host 2 a command completion response to the first-type command that includes a status indicating an error in the received first-type command.

[0096] Next, an operation of completing each of the second type commands that are maintained in a specific FAR pool and are incomplete as an error will be described.

[0097] The controller 4 manages whether each of the multiple memory resources is in an available state or an unavailable state. For example, if each of the multiple memory resources is a superblock, a superblock that includes an unwritten area is in an available state. A superblock that is entirely filled with data, i.e., a superblock that does not include an unwritten area, is in an unavailable state.

[0098] The first memory resource transitions from an available state to an unavailable state when multiple first-type commands specifying the first memory resource are received and processed by the controller 4. For example, when multiple write commands specifying a superblock are received and processed by the controller 4, the superblock transitions from an available state to an unavailable state.

[0099] When the first memory resource transitions from an available state to an unavailable state, the command processing unit 22 completes, as an error, each of the incomplete second type commands that are maintained in one of the multiple FAR pools that corresponds to the first memory resource. In this case, for each of these second type commands, the command processing unit 22 transmits to the host 2 a command completion response for the second type command that includes a status indicating an error in the second type command.

[0100] Next, an example of a command used as the first type command will be described. In this embodiment, a write command (nameless write command: NLW command) of a type that specifies a target memory resource to which data (write data) is to be written, but does not specify a write destination location within the target memory resource, is used as the first type command.

[0101] This write command includes a parameter specifying a memory resource ID, a parameter specifying a data identifier such as a user address tag, and a parameter specifying a process ID. The parameter specifying the memory resource ID specifies one of multiple memory resources as the target memory resource to which data (write data) should be written. The parameter specifying the data identifier specifies the data identifier of the write data.

[0102] When a write command is received from the host 2, the command processing unit 22 assigns, to the received write command, a physical address (flash address) indicating a physical storage location within the memory resource to be processed where the write data should be written, i.e., a write destination location within the memory resource to be processed. The assigned physical address is represented by a resource identifier that identifies the memory resource to be processed and an offset from the beginning of the memory resource to be processed to the write destination location. Then, before starting a program operation to write the write data to the assigned physical address (also referred to as a write operation or flash write process), the command processing unit 22 transmits the assigned physical address and data identifier to the host 2 as a first advance response.

[0103] In this case, the command processing unit 22 acquires one second type command that specifies the same memory resource ID and process ID as the memory resource ID and process ID, respectively, specified by the received write command from the FAR pool 31. The command processing unit 22 completes the acquired one second type command and executes (1) an operation of sending a command completion response to the completed one second type command to the host 2, and (2) an operation of transferring the assigned physical address and data identifier to a buffer area in the memory 102 provided in the host 2 as a first preceding response.

[0104] Thereafter, the command processing unit 22 acquires write data associated with the received write command from the write buffer in the memory 102 of the host 2. For example, the command processing unit 22 transmits a memory read request to the host 2. This enables the command processing unit 22 to acquire the write data from the write buffer in the memory 102 of the host 2 via the processor 101 of the host 2. Then, the command processing unit 22 writes the acquired write data to the NAND flash memory 5 based on the assigned physical address. In this case, the write data is written to a write destination location in the resource to be processed, which is indicated by the assigned physical address.

[0105] Upon completion of writing the write data to the NAND flash memory 5, the command processing unit 22 transmits a command completion response indicating the completion of the write command to the host 2. In this case, the command completion response is stored in one entry in the completion queue (CQ).

[0106] Thus, in cases where a write command (nameless write command) is used as the first type command, the physical address (flash address) assigned to the write command and the data identifier of the write data are transferred to a buffer area in memory 102 of the host 2 as information related to the processing of the write command. That is, the physical address (flash address) assigned to the write command and the data identifier of the write data are transferred to a buffer area in memory 102 of the host 2 as a first preceding response to the write command. Therefore, the second type command for enabling the controller 4 to send a preceding response corresponding to the write command to the host 2 is referred to as a flash address read command (FAR command).

[0107] The first type command may be a maintenance command that causes the controller 4 to execute a maintenance operation on the NAND flash memory 5. The maintenance operation may be a garbage collection operation on the NAND flash memory 5.

[0108] Next, a description will be given of the configuration of the NAND flash memory 5. Fig. 4 is a block diagram showing the relationship between a NAND interface and a plurality of NAND flash memory dies provided in a storage device according to this embodiment.

[0109] The NAND flash memory 5 includes multiple NAND flash memory dies, each of which can operate independently.

[0110] 4 illustrates a case in which 16 channels Ch.1 to Ch.16 are connected to the NAND interface 13, and two NAND flash memory dies are connected to each of the 16 channels Ch.1 to Ch.16. In this case, the 16 NAND flash memory dies #1 to #16 connected to the channels Ch.1 to Ch.16 may be organized as bank #0, and the remaining 16 NAND flash memory dies #17 to #32 connected to the channels Ch.1 to Ch.16 may be organized as bank #1. A bank is a unit for operating multiple NAND flash memory dies in parallel by bank interleaving. In the configuration example of FIG. 4, a maximum of 32 NAND flash memory dies can be operated in parallel by using 16 channels and bank interleaving using two banks.

[0111] The erase operation may be performed in units of one block (physical block) or in units of a block group (superblock) including multiple blocks. One superblock may include, but is not limited to, a total of 32 physical blocks selected one by one from the NAND flash memory dies #1 to #32. Each of the NAND flash memory dies #1 to #32 may have a multi-plane configuration. For example, if each of the NAND flash memory dies #1 to #32 has a multi-plane configuration including two planes, one superblock may include a total of 64 physical blocks selected one by one from the 64 planes corresponding to the NAND flash memory dies #1 to #32.

[0112] FIG. 5 illustrates one superblock SB including 32 physical blocks (here, physical block BLK2 in NAND flash memory die #1, physical block BLK3 in NAND flash memory die #2, physical block BLK7 in NAND flash memory die #3, physical block BLK4 in NAND flash memory die #4, physical block BLK6 in NAND flash memory die #5, ..., physical block BLK3 in NAND flash memory die #32).

[0113] Next, the procedure of the multi-phase completion response process will be explained. Fig. 6 is a diagram showing an operation executed in the storage device 3 according to the embodiment, in which one or more second type commands transmitted in advance from the host 2 are maintained in a pool, an operation in which a completion response to one of the second type commands in the pool is transmitted to the host as a preceding response to a first type command transmitted from the host 2, and an operation in which, in response to the completion of the first type command, a completion response indicating the completion of the first type command is transmitted to the host.

[0114] First, the host 2 issues one or more second-type commands to the storage device 3 in advance via a submission queue (SQ) (step S11). FIG. 6 illustrates an example in which three second-type commands are issued in advance. By issuing multiple second-type commands to the storage device 3 in advance, even if multiple first-type commands are issued simultaneously by the host 2 to the storage device 3, the storage device 3 can return advance responses to each of the multiple first-type commands to the host 2. Note that if it is guaranteed that the number of first-type commands that the host 2 will issue simultaneously to the storage device 3 is one, the host 2 only needs to issue one second-type command to the storage device 3 in advance.

[0115] Each of the one or more second type commands issued in advance by the host 2 includes a parameter specifying a memory resource to be processed among a plurality of memory resources included in the NAND flash memory 5 of the storage device 3, and a parameter specifying a process identifier indicating a process associated with the second type command. When starting writing to a certain memory resource, the process identifier indicating the process that has requested to start writing to this memory resource can be used as the process associated with the second type command.

[0116] When one or more second type commands are received, the storage device 3 stores each of the received second type commands in a pool. The storage device 3 manages a pool for each memory resource included in the NAND flash memory 5. The storage device 3 determines a pool in which to store each of the received second type commands, based on a parameter included in each of the received second type commands that specifies the memory resource to be processed. The storage device 3 maintains each of the received second type commands in the determined pool without completing them.

[0117] Thereafter, the host 2 issues a first type command to the storage device 3 via the submission queue (SQ) (step S12). Like the second type command, the first type command includes a parameter specifying a memory resource to be processed among a plurality of memory resources included in the NAND flash memory 5, and a parameter specifying a process identifier indicating a process that has requested processing among a plurality of processes executed by the host 2.

[0118] In response to receiving the first type command, the storage device 3 acquires from the pool a second type command that specifies the same memory resource identifier and process identifier as those specified in the received first type command. In this case, the storage device 3 first selects a pool corresponding to the target memory resource indicated by the memory resource identifier specified in the first type command. Then, the storage device 3 acquires from the selected pool a second type command that specifies the same process identifier as the process identifier specified in the received first type command.

[0119] If the selected pool contains multiple second type commands that specify the same process identifier as the process identifier specified by the received first type command, the storage device 3 acquires the second type command that was last received from the host 2 among the multiple second type commands (last in, first out). Alternatively, the storage device 3 may acquire the second type command that was first received from the host 2 among the multiple second type commands (first in, first out).

[0120] Next, the storage device 3 completes the acquired second type command and transmits a completion response to the acquired second type command to the host 2 as a preceding response to the first type command received in step S12 (step S13). In step S13, the storage device 3 may store the command completion response to the second type command, including information indicating the preceding response to the first type command received in step S12, in one completion queue entry. Alternatively, in a case where a type of read command is used as the second type command, the storage device 3 executes an operation of transmitting a command completion response to the second type command to the host 2 and an operation of transferring information regarding the processing of the first type command to a buffer area in the memory 102 associated with the second type command as a preceding response to the first type command. The command completion response to the second type command is stored in a completion queue (CQ).

[0121] Upon receiving the command completion response to the second type command sent from the storage device 3 in step S13, the host 2 issues an additional second type command to the storage device 3 via the submission queue (SQ) in advance (step S14) before issuing the next first type command to the storage device 3. The additional second type command includes the same memory resource identifier and process identifier as the memory resource identifier and process identifier specified by the first type command issued to the storage device 3 in step S12. Because one second type command is completed to send the previous response, the number of uncompleted second type commands is reduced by one. By issuing the additional second type command, the number of uncompleted second type commands can be restored to the number of uncompleted second type commands before the previous response was sent.

[0122] When the storage device 3 completes the processing of the first type command, it transmits a command completion response to the first type command to the host 2 (step S15). The command completion response to the first type command transmitted in step S15 includes a status indicating whether the processing of the first type command was executed normally or not. The command completion response to the first type command is stored in a completion queue (CQ).

[0123] Through the above operations, the storage device 3 can send two responses, including a preceding response and a command completion response, to the host 2 in response to one first type command. Furthermore, if the second type command includes a pointer indicating a buffer area in the memory 102 to which information should be transferred, it is possible to increase the amount of information that can be notified to the host 2 as the first preceding response.

[0124] Furthermore, since the storage device 3 already stores one or more second type commands, it can send a preceding response to the host 2 more quickly than if it received a second type command after receiving a first type command.

[0125] Here, a case has been described in which multiple second type commands are issued in advance by the host 2, but the host 2 may also issue one second type command immediately before issuing a first type command.

[0126] Next, the procedure of multi-phase completion response processing when one second type command is issued immediately before issuing a first type command will be described. Fig. 7 is a diagram showing an operation executed in a storage device according to an embodiment, in which one second type command transmitted in advance from the host is maintained in a pool, an operation in which a completion response to the second type command in the pool is transmitted to the host as a preceding response to the first type command transmitted from the host, and an operation in which, in response to the completion of the first type command, a completion response indicating the completion of the first type command is transmitted to the host.

[0127] First, the host 2 issues one second type command to the storage device 3 in advance via a submission queue (SQ) (step S21). The second type command includes a parameter specifying a memory resource to be processed from among multiple memory resources included in the storage device 3, and a parameter specifying a process identifier indicating a process associated with the second type command. When starting writing to a certain memory resource, the process identifier indicating the process that requested the start of writing to this memory resource can be used as the process associated with the second type command. In the multi-phase completion response processing shown in FIG. 7, the host 2 issues a second type command to the storage device 3 immediately before issuing a first type command to the storage device 3. Therefore, this second type command includes the same resource identifier and process identifier as the resource identifier and process identifier specified by the corresponding first type command, respectively.

[0128] When a second type command is received, the storage device 3 stores the received second type command in a pool. The storage device 3 manages a pool for each memory resource included in the NAND flash memory 5. The storage device 3 determines a pool in which to store the received second type command based on a parameter that specifies the memory resource to be processed and that is included in the received second type command. The storage device 3 maintains the received second type command in the determined pool without completing it.

[0129] Thereafter, the host 2 issues a first type command to the storage device 3 via the submission queue (SQ) (step S22). Like the second type command, the first type command includes a parameter specifying a memory resource to be processed among a plurality of memory resources included in the NAND flash memory 5, and a parameter specifying a process identifier indicating a process that has requested processing among a plurality of processes executed by the host 2.

[0130] In response to receiving the first type command, the storage device 3 acquires from the pool a second type command that specifies the same memory resource identifier and process identifier as those specified in the received first type command. In this case, the storage device 3 first selects a pool corresponding to the target memory resource indicated by the memory resource identifier specified in the first type command. Then, the storage device 3 acquires from the selected pool a second type command that specifies the same process identifier as the process identifier specified in the received first type command.

[0131] Here, the storage device 3 acquires the second type command on a last-in, first-out basis, for example. In this case, the storage device 3 acquires, from among the second type commands maintained in the selected pool, the second type command that includes the same process identifier as the process identifier specified by the received first type command and that was last received from the host 2. In the multi-phase completion response processing shown in Fig. 7, the second type command issued immediately before the received first type command is acquired as the second type command that includes the same process identifier as the process identifier specified by the received first type command and that was last received from the host 2.

[0132] The storage device 3 then completes the acquired second type command and transmits a command completion response for the completed second type command to the host 2 as a preceding response to the first type command received in step S22 (step S23). In step S23, the storage device 3 may store the command completion response for the second type command, including information indicating the preceding response to the first type command received in step S22, in one completion queue entry. Alternatively, in a case where a type of read command is used as the second type command, the storage device 3 may perform an operation of transmitting a command completion response for the second type command to the host 2 and an operation of transferring information regarding the processing of the first type command to a buffer area in the memory 102 associated with the second type command as a preceding response to the first type command. The command completion response for the second type command is stored in a completion queue (CQ).

[0133] Upon receiving the command completion response to the second type command sent from the storage device 3 in step S23, the host 2 may issue an additional second type command to the storage device 3 in advance via the submission queue (SQ) before issuing the next first type command to the storage device 3 (step S24). The additional second type command includes the same memory resource identifier and process identifier as the memory resource identifier and process identifier specified by the first type command issued to the storage device 3 in step S22.

[0134] Alternatively, the host 2 may issue the next second type command to the storage device 3 via the submission queue (SQ) immediately before issuing the next first type command to the storage device 3. The next second type command includes the same resource identifier and process identifier as the resource identifier and process identifier specified by the next first type command. Furthermore, the timing at which the process of step S24 is executed is changed to immediately before issuing the next first type command to the storage device 3. Then, immediately before issuing the next first type command to the storage device 3, a next second type command corresponding to the next first type command is issued to the storage device 3.

[0135] When the storage device 3 completes the processing of the first type command, it transmits a command completion response to the first type command to the host 2 (step S25). The command completion response to the first type command transmitted in step S25 includes a status indicating whether the processing of the first type command was executed normally or not. The command completion response to the first type command is stored in a completion queue (CQ).

[0136] Next, a specific example of a command sent from the host 2 to the storage device 3 will be described.

[0137] FIG. 8 is a diagram showing an example of the configuration of a write command issued as a first type command to a storage device according to the embodiment.

[0138] The write command (nameless write command: NLW) is a write command used as a first type command. This write command may include a command ID, a QoS domain ID, a placement ID, a user address tag (UA tag), a process ID, a length, a data pointer, etc.

[0139] The command ID is an identifier for identifying this command (this write command). The QoS domain ID is an identifier that can uniquely identify the QoS domain where data should be written. A write command sent from the host 2 in response to a write request from an application corresponding to a certain end user includes a QoS domain ID that specifies the QoS domain corresponding to this end user. The placement ID is an identifier that can uniquely identify a storage area within the QoS domain where data should be written. In each QoS domain, data associated with different placement IDs is written to different destination superblocks currently assigned to that QoS domain. For this reason, the combination of the QoS domain ID and the placement ID is used as a parameter that specifies the destination superblock where data should be written. When the write command (NLW) is implemented using an existing write command specified in the NVMe standard, the namespace identifier field and stream identifier field included in the existing write command specified in the NVMe standard can be used as a field that specifies the QoS domain ID and a field that specifies the placement ID, respectively.

[0140] The UA tag is an identifier for identifying the write data to be written. This UA tag may be a logical address such as an LBA, a key in a key-value store, or a hash value of this key. The process ID is an identifier for uniquely identifying the process that requested the writing of the write data.

[0141] The length indicates the length of the write data to be written. This length (data length) may be specified by the number of LBAs or by bytes.

[0142] The data pointer is storage location information that indicates the storage location in the write buffer of the host 2 where the write data to be written is stored. A part of the storage area of ​​the memory 102 provided in the host 2 is used as the write buffer of the host 2. The data pointer is also referred to as the write buffer address.

[0143] FIG. 9 is a diagram showing an example of the configuration of a flash address read command issued as a second type command to the storage device 3 according to the embodiment.

[0144] The flash address read command (FAR) is used to notify the host 2 of the physical address assigned to the write command (NLW). This FAR is used as a second type command to enable the controller 4 to send a prior response corresponding to the write command (NLW) to the host 2. This FAR may include a command ID, a QoS domain ID, a placement ID, a process ID, a data pointer, and a size.

[0145] The command ID is an identifier for identifying this command (this FAR). The QoS domain ID is an identifier for identifying the QoS domain associated with this FAR. The placement ID is an identifier for identifying a storage area within the QoS domain associated with this FAR. The process ID is an identifier for identifying a process associated with this FAR.

[0146] The data pointer is a buffer address indicating the location (buffer area) in the memory 102 of the host 2 to which the read data associated with the command completion response to this FAR, i.e., the information associated with the preceding response to the write command (NLW), should be transferred. The size indicates the size of this buffer area.

[0147] FIG. 10 is a diagram showing an example of information transmitted as a preliminary response by the storage device 3 according to the embodiment to the host 2. In FIG.

[0148] When the write command (NLW) is accepted by the controller 4, the controller 4 transmits an address record request (ARR) shown in FIG. 10 to the host 2 as a preliminary response to the write command (NLW). The address record request (ARR) corresponds to the read data associated with the flash address read command (FAR). The address record request (ARR) is transmitted from the storage device 3 to the host 2 when a physical address in the NAND flash memory 5 is assigned to this write command (NLW).

[0149] The advance response, or Address Record Request (ARR), contains the UA tag, physical address, and identification information.

[0150] The UA tag is the UA tag included in the write command corresponding to this previous response. The physical address is the physical address assigned to the write command corresponding to this previous response. The physical address indicates the destination location where the data associated with the write command should be written. The physical address is represented by a superblock identifier indicating the superblock where the data should be written, and an offset from the beginning of this superblock to the destination location.

[0151] The identification information is identification information for identifying the write command corresponding to the preceding response, and is, for example, a QoS domain ID, a placement ID, a submission queue ID, or a command ID of the write command.

[0152] The write command (NLW) and the FAR may also include a superblock ID instead of the QoS domain ID and the placement ID.

[0153] FIG. 11 is a diagram showing another example of the structure of a write command issued as a first-type command to the storage device 3 according to this embodiment.

[0154] The write command (NLW) may include a command ID, a superblock ID, a user address tag (UA tag), a process ID, a length, a data pointer, and the like. The superblock ID is an identifier that can uniquely identify the superblock in which data is to be written.

[0155] FIG. 12 is a diagram showing another example of the configuration of a flash address read command issued as a second type command to the storage device 3 according to this embodiment.

[0156] This flash address read command (FAR) corresponds to the configuration of the write command (NLW) described in Fig. 11. This flash address read command (FAR) includes a command ID, a superblock ID, a process ID, a data pointer, and a size. The superblock ID is an identifier that identifies the superblock associated with this FAR.

[0157] FIG. 13 is a diagram showing another example of the configuration of information transmitted as a preliminary response by the storage device 3 according to this embodiment to the host 2. In FIG.

[0158] The address record request (ARR) shown in Fig. 13 corresponds to the configuration of the write command (NLW) described in Fig. 11. This preceding response, i.e., the address record request (ARR), includes a UA tag, a physical address, and identification information. The identification information is used to identify the write command associated with the preceding response. The identification information may be, for example, a superblock ID, a submission queue ID, or a command ID of the write command.

[0159] FIG. 14 is a diagram showing an example of the configuration of a read command issued to a storage device according to the embodiment.

[0160] The read command is a command that requests the storage device 3 to read data. This read command may include a command ID, a QoS domain ID, a physical address, a length, and a read buffer address.

[0161] The command ID is an identifier for identifying this command (this read command). The QoS domain ID is an identifier for identifying the QoS domain in which the data to be read is stored. The physical address indicates the physical memory location in which the data to be read is stored. The physical address is represented by a superblock identifier and an offset. The length indicates the length of the data to be read. The read buffer address indicates the location in the read buffer of the host 2 to which the read data should be transferred. A portion of the storage area of ​​the memory 102 provided in the host 2 is used as the read buffer of the host 2.

[0162] FIG. 15 is a diagram showing an example of the configuration of a QoS domain create command issued to a storage device according to the embodiment.

[0163] The QoS domain create command is a command for creating a QoS domain, and may include a command ID, a QoS domain ID, and a capacity.

[0164] The command ID is an identifier for identifying this command (this QoS domain create command). The QoS domain ID is an identifier for the QoS domain to be created. The capacity indicates the capacity to be reserved for the QoS domain to be created. The controller 4 reserves a number of free super-blocks corresponding to this capacity from the common free block pool 602, and in response to a write command specifying this QoS domain ID, assigns one of these reserved free super-blocks as the write destination super-block for this QoS domain.

[0165] FIG. 16 is a diagram showing the relationship between the identifiers of block groups (super blocks) and offsets.

[0166] For simplicity of illustration, it is assumed here that one superblock SB#1 is composed of four blocks BLK#11, BLK#21, BLK#31, and BLK#41. The identifier (superblock address) of superblock SB#1 is SB#1. The four blocks BLK#11, BLK#21, BLK#31, and BLK#41 may be blocks selected from four different NAND flash memory dies.

[0167] Each block BLK includes multiple pages (here, page 0 to page n). In the case where the page size (user data storage area of ​​each page) is 16K bytes and the sector size is 4K bytes, this block BLK is logically divided into 4×(n+1) areas.

[0168] The controller 4 writes data in the following order: page 0 of block BLK#11, page 0 of block BLK#21, page 0 of block BLK#31, page 0 of block BLK#41, page 1 of block BLK#11, page 1 of block BLK#21, page 1 of block BLK#31, page 1 of block BLK#41, and so on.

[0169] Offset +0 indicates the first 4KB region of page 0 of block BLK#11, offset +1 indicates the second 4KB region of page 0 of block BLK#11, offset +2 indicates the third 4KB region of page 0 of block BLK#11, and offset +3 indicates the fourth 4KB region of page 0 of block BLK#11.

[0170] Offset +4 indicates the first 4KB region of page 0 of block BLK#21, offset +5 indicates the second 4KB region of page 0 of block BLK#21, offset +6 indicates the third 4KB region of page 0 of block BLK#21, and offset +7 indicates the fourth 4KB region of page 0 of block BLK#21.

[0171] Similarly, offset +12 indicates the first 4KB region of page 0 of block BLK#41, offset +13 indicates the second 4KB region of page 0 of block BLK#41, offset +14 indicates the third 4KB region of page 0 of block BLK#41, and offset +15 indicates the fourth 4KB region of page 0 of block BLK#41.

[0172] Offset +16 indicates the first 4KB region of page 1 of block BLK#11, offset +17 indicates the second 4KB region of page 1 of block BLK#11, offset +18 indicates the third 4KB region of page 1 of block BLK#11, and offset +19 indicates the fourth 4KB region of page 1 of block BLK#11.

[0173] Offset +20 indicates the first 4KB area on page 1 of block BLK#21, offset +21 indicates the second 4KB area on page 1 of block BLK#21, offset +22 indicates the third 4KB area on page 1 of block BLK#21, and offset +23 indicates the fourth 4KB area on page 1 of block BLK#21.

[0174] Similarly, offset +28 indicates the first 4KB region of page 1 of block BLK#41, offset +29 indicates the second 4KB region of page 1 of block BLK#41, offset +30 indicates the third 4KB region of page 1 of block BLK#41, and offset +31 indicates the fourth 4KB region of page 1 of block BLK#41.

[0175] For example, when writing 4K bytes of data corresponding to a write command specifying a certain LBA (LBAx) to a location corresponding to offset +8, the controller 4 may return the UA tag (=LBAx), superblock address (=SB#1), offset (=+8), and length (=1) to the host 2 as an address record request ARR.

[0176] FIG. 17 is a diagram showing a plurality of QoS domains managed in the storage device 3 according to the embodiment.

[0177] Figure 17 shows a case where QoS domain #0, QoS domain #1, and QoS domain #2 have already been created. These QoS domains are represented by squares in Figure 17. The vertical width of the square representing a QoS domain represents the capacity of that QoS domain.

[0178] User application #0 can read / write access QoS domain #0 by using a read / write command that includes QoS domain ID #0 of QoS domain #0. Similarly, user application #1 can read / write access QoS domain #1 by using a read / write command that includes QoS domain ID #1 of QoS domain #1.

[0179] User application #2 and user application #3 can access QoS domain #2 for read / write access using read / write commands including QoS domain ID #2 of QoS domain #2.

[0180] FIG. 18 is a block diagram showing the relationship between a plurality of QoS domains and a common free block pool, which are managed in the storage device 3 according to this embodiment.

[0181] In addition to the common free block pool 602, the controller 4 can also manage an active block list (active block pool) corresponding to each placement ID.

[0182] The state of each superblock is roughly divided into active blocks (superblocks in a closed state) that store valid data, and free blocks that do not store valid data and can be used as write destination superblocks. For example, in placement ID #1 in QoS domain #0, each superblock that is an active block is managed by the active block pool 811 corresponding to placement ID #1. On the other hand, each free block that can be allocated to a write destination superblock for each placement ID is managed by the common free block pool 602.

[0183] When a write command specifying QoS domain #0 and placement ID #1 is received from host 2, controller 4 selects one superblock (free block) in the common free block pool 602 and assigns the selected superblock to placement ID #1 of QoS domain #0 as a write destination superblock. Furthermore, controller 4 determines a location (write destination location) within this write destination superblock. The write destination location within the write destination superblock is determined taking into consideration page write order constraints, defective pages, etc. Then, controller 4 writes the data associated with the write command to the write destination location within the write destination block.

[0184] When the entire write destination superblock of placement ID #1 is filled with user data, the controller 4 moves this write destination superblock to the active block pool 811 of placement ID #1 of QoS domain #0. Then, the controller 4 again selects one superblock (free block) in the common free block pool 602 and assigns the selected superblock as the new write destination superblock of placement ID #1 of QoS domain #0.

[0185] When a write command specifying QoS domain #0 and placement ID #2 is received from host 2, controller 4 selects one superblock (free block) in common free block pool 602 and assigns the selected superblock to placement ID #2 of QoS domain #0 as a write destination superblock. Furthermore, controller 4 determines a location (write destination location) within this write destination superblock. Then, controller 4 writes the data associated with the write command to the write destination location within the write destination block.

[0186] When the entire destination superblock of placement ID #2 is filled with user data, the controller 4 moves this destination superblock to the active block pool 812 of placement ID #2 of QoS domain #0. Then, the controller 4 again selects one superblock (free block) in the common free block pool 602 and assigns the selected superblock as the new destination superblock of placement ID #2 of QoS domain #0.

[0187] FIG. 19 is a block diagram for explaining a data write process executed by the storage device 3 and the host 2 according to this embodiment.

[0188] (1) In the host 2, the host FTL 301 is executed. This host FTL 301 manages the mapping between each UA tag, such as an LBA, and each physical address in the NAND flash memory 5 using an LUT. In response to a write request from a user application, the host FTL 301 sends a write command to the storage device 3, specifying a pair of a QoS domain ID and a placement ID (or a superblock ID), a process ID, a UA tag, a data pointer, and a length. The host FTL 301 only needs to specify the QoS domain ID and the placement ID (or the superblock ID) as resource identifiers of the memory resource to be processed, and does not need to specify a write destination location within the memory resource to be processed. This eliminates the need for the host FTL 301 to manage bad blocks, bad pages, and the like within the storage device 3.

[0189] (2) The controller 4 of the storage device 3 selects one superblock from the common free block pool 602 shared by multiple QoS domains 601. The controller 4 assigns this selected superblock as a destination superblock for the placement ID specified by the received write command. The common free block pool 602 may only manage free blocks other than bad blocks. For example, a block with the minimum number of program / erase cycles may be selected from the common free block pool 602. The controller 4 then determines this destination superblock as the superblock to which data should be written and further determines a destination location within this destination superblock to which the data should be written. Note that if a destination superblock for this placement ID has already been assigned, the controller 4 simply assigns this already assigned destination superblock as the superblock to which data should be written, and does not need to perform an operation to assign a superblock from the common free block pool 602 as the destination superblock for this placement ID.

[0190] (3) The controller 4 sends a preceding response to the host 2 including the UA tag of the write data, a block address indicating the determined write destination superblock, and an offset indicating the determined write destination location, thereby notifying the host 2 of the physical address where the write data associated with this write command will be written.

[0191] (4) The controller 4 acquires the write data from the write buffer 404 of the host 2 based on the write buffer address included in the write command. The acquisition of the write data from the write buffer 404 may be performed using the DMA controller 15. Then, the controller 4 executes a data write operation to write the write data to a destination location in the destination superblock.

[0192] (5) After the writing of the write data is completed and the write data can be read from the NAND flash memory 5, the controller 4 sends a command completion response to the write command to the host 2 as a release request to release the area in the write buffer 404 where the write data is stored. In response to this command completion response, the host 2 releases the area in the write buffer 404 where the write data is stored. This released area in the write buffer 404 can be used for storing other write data, etc. Next, a specific example of the multi-phase completion response processing described with reference to Fig. 6 will be described. Hereinafter, it is assumed that a write command is used as the first type command, and a flash address read command (FAR) is used as the second type command. Fig. 20 is a diagram showing operations executed in the storage device 3 according to the embodiment, such as maintaining one or more flash address read commands (FAR) transmitted in advance from the host 2 in a FAR pool, transmitting a completion response for one of the FARs in the FAR pool to the host 2 as a preceding response to the write command transmitted from the host 2, and transmitting a completion response indicating the completion of the write command to the host 2 in response to the completion of the write command.

[0193] First, the host 2 issues one or more FARs to the storage device 3 in advance via a submission queue (SQ) (step S31). The FAR includes a command ID, a process ID, a data pointer, and a size. The FAR also includes either a pair of a QoS domain ID and a placement ID, or a superblock ID, as a resource identifier. The following describes the case where the FAR includes a superblock ID as a resource identifier.

[0194] When one or more FARs are received, the storage device 3 stores each of the received FARs in a pool. The storage device 3 manages a FAR pool for each superblock (write destination superblock) included in the NAND flash memory 5. The storage device 3 determines the FAR pool in which to store each of the received FARs based on a parameter specifying a superblock ID included in each of the received FARs. The storage device 3 maintains each of the received FARs in the determined FAR pool without completing it.

[0195] Thereafter, the host 2 sends a write command (NLW) to the storage device 3 (step S32). The write command (NLW) includes a command ID, a UA tag, a process ID, a length, and a data pointer. The write command (NLW) also includes either a pair of a QoS domain ID and a placement ID, or a superblock ID, as a resource identifier. The following describes a case where the write command (NLW) includes a superblock ID as a resource identifier.

[0196] In response to receiving the write command (NLW), the storage device 3 assigns to the received write command (NLW) a physical address indicating a physical storage location (destination location) in the NAND flash memory 5 where the data associated with the received write command (NLW) should be written.

[0197] The storage device 3 acquires a FAR that specifies the same superblock ID and process ID as those specified by the received write command (NLW). In this case, the storage device 3 first selects a pool corresponding to the write destination superblock indicated by the superblock ID specified by the received write command (NLW). Then, the storage device 3 acquires, from the selected pool, a FAR that specifies the same process ID as the process ID specified by the received write command (NLW).

[0198] The storage device 3 then completes the acquired FAR. The storage device 3 transmits a command completion response for the completed FAR to the host 2 as a preceding response to the received write command (NLW) (step S33). In step S33, the storage device 3 transmits the command completion response for the completed FAR to the host 2. Also in step S33, the storage device 3 transfers the ARR to the read buffer specified by the data pointer of the completed FAR. The ARR includes the physical address assigned to the received write command (NLW), the UA tag specified by the received write command (NLW), and the identification information included in the received write command (NLW).

[0199] Upon receiving the completion response to the FAR sent from the storage device 3 in step S33, the host 2 issues an additional FAR to the storage device 3 via the submission queue (SQ) in advance (step S34) before issuing to the storage device 3 the next write command (NLW) that specifies the same superblock ID as the superblock ID specified by the write command (NLW) issued in S32. The additional FAR includes the same superblock ID and process ID as the superblock ID and process ID specified by the write command (NLW) issued to the storage device 3 in step S32.

[0200] The storage device 3 obtains the write data associated with the write command (NLW) received in step S32 from the write buffer of the host 2. The storage device 3 executes a program operation to write the write data to a write destination location in the NAND flash memory 5 based on the physical address assigned to the received write command (NLW). When this program operation ends, the storage device 3 transmits a command completion response to the received write command (NLW) to the host 2 (step S35). The command completion response to the write command (NLW) transmitted in step S35 includes a status indicating whether or not the write process of the data associated with the write command (NLW) has been executed successfully. The command completion response to the write command (NLW) is stored in the completion queue (CQ).

[0201] Through the above operations, the storage device 3 can send two responses to the write command (NLW), including an advanced response and a command completion response, to the host 2. Furthermore, because the FAR includes a pointer indicating the buffer area in the memory 102 to which information should be transferred, it is possible to notify the host 2 of an ARR having a relatively large size as an advanced response to the write command (NLW).

[0202] Next, a specific example of the multi-phase completion response processing described with reference to Fig. 7 will be described. Hereinafter, it is assumed that a write command is used as the first type command, and a flash address read command (FAR) is used as the second type command. Fig. 21 is a diagram showing the following operations executed in the storage device 3 according to the embodiment: maintaining one flash address read command (FAR) transmitted in advance from the host 2 in the FAR pool 31; transmitting a completion response for one FAR in the FAR pool 31 to the host 2 as a preceding response to the write command transmitted from the host 2; and transmitting a completion response indicating the completion of the write command to the host 2 in response to the completion of the write command.

[0203] First, the host 2 transmits one FAR to the storage device 3 (step S41). The FAR includes a command ID, a QoS domain ID, a placement ID, a process ID, a data pointer, and a size. The FAR may also include a superblock ID as a resource identifier instead of the QoS domain ID and the placement ID. The following assumes that the FAR includes a superblock ID as a resource identifier. In the multi-phase completion response process shown in FIG. 21, the host 2 issues a FAR to the storage device 3 immediately before issuing a write command (NLW) to the storage device 3. Therefore, this FAR includes the same resource identifier (superblock ID) and process ID as those specified by the corresponding write command (NLW).

[0204] When a FAR is received, the storage device 3 stores the received FAR in a FAR pool. The storage device 3 manages a FAR pool for each superblock (write destination superblock) included in the NAND flash memory 5. The storage device 3 determines the FAR pool in which to store the received FAR based on the superblock ID included in the received FAR. The storage device 3 maintains the received FAR in the determined FAR pool without completing it.

[0205] Thereafter, the host 2 issues a write command (NLW) to the storage device 3 via the submission queue (SQ) (step S42). The write command (NLW) includes a command ID, a UA tag, a process ID, a length, and a data pointer. The write command (NLW) also includes either a pair of a QoS domain ID and a placement ID, or a superblock ID, as a resource identifier. The following describes a case where the write command (NLW) includes a superblock ID as a resource identifier.

[0206] In response to receiving the write command (NLW), the storage device 3 assigns to the received write command (NLW) a physical address indicating a physical storage location (destination location) in the NAND flash memory 5 where the data associated with the received write command (NLW) should be written.

[0207] The storage device 3 acquires a FAR that specifies the same superblock ID and process ID as the superblock ID and process ID specified by the received write command (NLW). In this case, the storage device 3 first selects a pool corresponding to the write destination superblock indicated by the superblock ID specified by the received write command (NLW). The storage device 3 then acquires a FAR from the selected pool that specifies the same process ID as the process ID specified by the received write command (NLW). In the multi-phase completion response processing shown in Fig. 21, the FAR issued immediately before the received write command (NLW) is acquired as the FAR that specifies the same superblock ID and process ID as the superblock ID and process ID specified by the received write command (NLW).

[0208] The storage device 3 then completes the acquired FAR. The storage device 3 transmits a command completion response for the completed FAR to the host 2 as a preceding response to the received write command (NLW) (step S43). In step S43, the storage device 3 transmits the command completion response for the completed FAR to the host 2. Also in step S43, the storage device 3 transfers the ARR to the read buffer specified by the data pointer of the completed FAR. The ARR includes the physical address assigned to the received write command (NLW), the UA tag specified by the received write command (NLW), and the identification information included in the received write command (NLW).

[0209] Upon receiving the completion response to the FAR sent from the storage device 3 in step S43, the host 2 may issue an additional FAR to the storage device 3 via the submission queue (SQ) in advance (step S44) before issuing to the storage device 3 the next write command (NLW) that specifies the same superblock ID as the superblock ID specified by the write command (NLW) issued in S42. The additional FAR includes the same superblock ID and process ID as the superblock ID and process ID specified by the write command (NLW) issued to the storage device 3 in step S42.

[0210] Alternatively, the host 2 may issue the next FAR to the storage device 3 via the submission queue (SQ) immediately before issuing the next write command (NLW) to the storage device 3. The next FAR includes the same superblock ID and process ID as the superblock ID and process ID specified by the next write command (NLW). Furthermore, the timing at which step S44 is executed is changed to immediately before issuing the next write command (NLW) to the storage device 3. Then, immediately before issuing the next write command (NLW) to the storage device 3, the next FAR corresponding to the next write command (NLW) is issued to the storage device 3.

[0211] The storage device 3 obtains the write data associated with the write command (NLW) received in step S42 from the write buffer of the host 2. The storage device 3 executes a program operation to write the write data to a write destination location in the NAND flash memory 5 based on the physical address assigned to the received write command (NLW). When this program operation ends, the storage device 3 transmits a command completion response to the received write command (NLW) to the host 2 (step S45). The command completion response to the write command (NLW) transmitted in step S45 includes a status indicating whether or not the write process of the data associated with the write command (NLW) has been executed successfully. The command completion response to the write command (NLW) is stored in the completion queue (CQ).

[0212] FIG. 22 is a block diagram showing an operation executed in a storage device 3 according to an embodiment, in which one or more flash address read commands (FARs) specifying the same memory resource are maintained in the same FAR pool 31, an operation of sending a preemptive response to the write command to the host using a FAR maintained in the FAR pool 31 corresponding to the memory resource specified by the write command, and an operation of sending a completion response to the write command to the host.

[0213] First, the host 2 stores in a submission queue (SQ) a command to be sent to the storage device 3. The command stored in the submission queue may be any command, such as a write command, a flash address read command (FAR), or a read command.

[0214] The command fetch unit 21 of the storage device 3 fetches a command from a submission queue (SQ). If the fetched command is a FAR, the command fetch unit 21 identifies a write destination superblock based on the superblock ID included in the fetched FAR. The FAR pool corresponding to the identified write destination superblock is determined as the FAR pool in which the fetched FAR should be stored.

[0215] For example, if the identified write destination superblock is write destination superblock SB#1, the command fetch unit 21 stores the fetched FAR in the FAR pool 31-1 corresponding to the write destination superblock SB#1. Also, if the identified write destination superblock is write destination superblock SB#2, the command fetch unit 21 stores the fetched FAR in the FAR pool 31-2 corresponding to the write destination superblock SB#2.

[0216] If the fetched command is a write command (NLW), the command fetch unit 21 transmits the write command (NLW) to the command processing unit 22. In response to receiving the write command, the command processing unit 22 determines a physical address indicating a storage area in the NAND flash memory 5 where the data associated with the write command (NLW) should be written. Then, the command processing unit 22 acquires the superblock ID and process ID included in the write command (NLW).

[0217] For example, when the write command (NLW) includes the superblock SB#2, the command processing unit 22 acquires, from the FAR pool 31-2, a FAR that includes the same process ID as the process ID included in the write command (NLW).

[0218] The command processing unit 22 completes the acquired FAR. Then, the command processing unit 22 transmits a command completion response (FAR completion) for the completed FAR to the host 2 as a preceding response (first preceding response) for the received write command (NLW). In this case, the command processing unit 22 executes an operation of storing the command completion response (FAR completion) for the completed FAR in the completion queue (CQ) and an operation of transferring an ARR corresponding to the received write command (NLW) to a position in the read buffer 701 indicated by the data pointer of the completed FAR.

[0219] The ARR corresponding to the received write command (NLW) includes the physical address assigned to the received write command (NLW), the UA tag included in the received write command (NLW), and identification information for identifying the received write command (NLW).

[0220] The host 2 processes a command completion response (FAR completion) for the completed FAR. This allows the host 2 to recognize that the ARR for the write command (NLW) for writing data to the memory resource (e.g., superblock) specified by this FAR has been stored in the read buffer by the storage device 3 as a previous response. The host 2 then processes the ARR and updates the LUT so that the physical address included in the ARR is associated with the UA tag included in the ARR.

[0221] After transmitting a command completion response (FAR completion) for the completed FAR to the host 2 as a preceding response (first preceding response), the command processing unit 22 acquires write data associated with the received write command (NLW) from the write buffer 404 of the host 2 and writes the data to the NAND flash memory 5. Then, the command processing unit 22 transmits a command completion response for the received write command (NLW) to the host 2. The command completion response is stored in the completion queue (CQ).

[0222] FIG. 23 is a block diagram illustrating the operations of maintaining one or more flash address read commands (FARs) that specify a certain superblock in a FAR pool corresponding to the superblock, sending a preemptive response to a write command that specifies the superblock to a host 2, and sending a completion response to the write command to a host 2.

[0223] When the controller 4 receives a FAR transmitted from the host 2, it acquires the superblock ID included in the received FAR. If the superblock ID included in the received FAR indicates SB#1, the controller 4 stores the FAR in the FAR pool 31-1 associated with SB#1. The FAR pool 31-1 maintains the stored FAR.

[0224] Then, upon receiving a write command (NLW) including a superblock ID indicating SB#1, the command processing unit 22 executes a flash address allocation process. In the flash address allocation process, the command processing unit 22 determines a write destination location in SB#1 where data associated with the write command (NLW) should be stored. Then, the command processing unit 22 assigns a physical address (superblock ID, offset) indicating the determined write destination location to the write command (NLW).

[0225] Furthermore, the command processing unit 22 acquires a FAR from the FAR pool 31-1. At this time, the command processing unit 22 acquires, from the FAR pool 31-1, a FAR that includes the same process ID as the process ID included in the received write command (NLW).

[0226] The controller 4 transmits the physical address assigned to the write command (NLW), the UA tag included in the write command (NLW), and identification information for identifying the write command (NLW) as read data associated with the acquired FAR to the host 2. Then, the controller 4 transmits a command completion response for the FAR to the host 2. In other words, the controller 4 transmits the command completion response for the FAR and the read data (ARR) associated with the FAR to the host 2 as a preceding response to the write command (NLW).

[0227] Then, the command processing unit 22 executes a flash write process to write data associated with the write command (NLW) to the NAND flash memory 5. Thereafter, the controller 4 transmits to the host 2 a command completion response to the write command (NLW).

[0228] FIG. 24 is a flowchart showing the procedure of processing executed in the storage device 3 according to this embodiment in response to a flash address read command (FAR).

[0229] When a command is received from the host 2, that is, when a command issued by the host 2 is fetched from the submission queue (SQ), the controller 4 determines whether the received command is a FAR (step S51).

[0230] If the received command is not a FAR (No in step S51), the controller 4 ends the processing for the FAR.

[0231] If the received command is a FAR (Yes in step S51), the controller 4 classifies the received FAR into one of multiple FAR groups based on the resource identifier included in the received FAR (step S52). Here, the resource identifier included in the FAR may be, for example, a QoS domain ID, a pair of a QoS domain ID and a placement ID, or a superblock ID. Furthermore, the multiple FAR groups are associated with multiple memory resources (for example, multiple write destination superblocks or multiple QoS domains).

[0232] The controller 4 determines whether the FAR pool corresponding to the FAR group into which the FAR received in step S51 is classified, among the plurality of FAR pools corresponding to the plurality of FAR groups, is full (step S53).

[0233] If the FAR pool corresponding to the FAR group into which the received FAR is classified is full (Yes in step S53), the controller 4 completes the oldest FAR among the incomplete FARs already maintained in this FAR pool as an error (step S54). In step S54, the controller 4 stores a command completion response in the completion queue (CQ), which includes the command ID of the oldest incomplete FAR, the submission queue ID from which the oldest incomplete FAR was fetched, a status indicating an error, and the like.

[0234] The number of new commands fetched from the submission queue at one time is one or more. Therefore, N (N>1) new FARs belonging to the same FAR group may be fetched from the submission queue. In this case, the controller 4 completes the oldest N FARs among the incomplete FARs maintained in this FAR pool as errors.

[0235] In this way, if the number of FARs to be maintained in a certain FAR pool exceeds the upper limit of the number of FARs that can be maintained in each FAR pool, controller 4 completes the excess number of FARs that are already maintained in this FAR pool and are incomplete as an error.

[0236] If the FAR pool 31 corresponding to the FAR group into which the received FAR is classified is not full (No in step S55), or if the processing of step S54 is completed, the controller 4 stores the FAR received in step S51 in the FAR pool corresponding to the FAR group into which this FAR is classified (step S55).

[0237] This operation allows the controller 4 to maintain the FARs received from the host 2 in one of multiple FAR pools rather than completing them.

[0238] FIG. 25 is a flowchart showing the procedure of processing for a write command (NLW) executed in the storage device 3 according to this embodiment.

[0239] When a command is received from the host 2, that is, when a command issued by the host 2 is fetched from the submission queue (SQ), the controller 4 determines whether the received command is a write command (NLW) (step S61).

[0240] If the received command is not a write command (NLW) (No in step S61), the controller 4 ends the process for the write command (NLW).

[0241] If the received command is a write command (NLW) (Yes in step S61), the controller 4 determines a write destination location in the NAND flash memory 5 where data associated with the received write command (NLW) should be written (step S62). In step S62, the controller 4 determines a write destination location in the memory resource indicated by the resource identifier specified by the received write command (NLW). Then, the controller 4 assigns a physical address indicating the determined write destination location (superblock ID of the write destination superblock, and an offset from the beginning of the write destination superblock to the write destination location) to the received write command (NLW).

[0242] Next, the controller 4 selects a FAR group associated with the resource identifier specified by the received write command (NLW) (step S63). The controller 4 determines whether a FAR including the same process identifier as the process identifier specified by the write command (NLW) exists in the FAR pool 31 corresponding to the selected FAR group (step S64).

[0243] If a FAR including the same process identifier as the process identifier specified by the received write command (NLW) exists in the FAR pool 31 corresponding to the selected FAR group (Yes in step S64), the controller 4 acquires the FAR including the same process identifier as the process identifier specified by the received write command (NLW) from the FAR pool 31 corresponding to the selected FAR group (step S65). In step S65, the controller 4 acquires the FAR including the same process identifier as the process identifier specified by the received write command (NLW) and that was last received from the host 2 from the FAR pool 31 corresponding to the selected FAR group.

[0244] The controller 4 completes the acquired FAR and transmits a command completion response for the completed FAR to the host 2 as a preceding response to the received write command (NLW) (step S66). In step S66, the controller 4 executes an operation of transmitting the command completion response for the completed FAR to the host 2 and an operation of transferring the ARR for the received write command (NLW) to a location in the read buffer of the host 2. In the operation of transferring the ARR to a location in the read buffer of the host 2, for example, the controller 4 transmits a memory write request to the host 2 that specifies a location in the read buffer of the host 2. As a result, the controller 4 stores the ARR at a location in the read buffer of the host 2 via the processor 101 of the host 2.

[0245] The controller 4 acquires data associated with the received write command (NLW) from the write buffer of the host 2. Then, the controller 4 executes a write operation to write the acquired data to the NAND flash memory 5 (step S67). When the write operation is completed, the controller 4 transmits a command completion response to the received write command (NLW) to the host 2 (step S68).

[0246] If a FAR including the same process identifier as the process identifier specified by the received write command (NLW) does not exist in the FAR pool 31 corresponding to the selected FAR group (No in step S64), the controller 4 completes the received write command (NLW) as an error (step S69). In step S69, the controller 4 transmits to the host 2 a command completion response for the received write command (NLW), including a status indicating an error in the received write command (NLW). This notifies the host 2 that the write command (NLW) has been completed as an error.

[0247] FIG. 26 is a flowchart showing the procedure of the process executed in the host 2.

[0248] First, when writing to a memory resource in the NAND flash memory 5 is to be started, the host 2 identifies this memory resource as a write-destination resource (write-destination memory resource) (step S101). For example, when a process corresponding to a certain application is started, a memory resource in the NAND flash memory 5 allocated to this process (application) may be determined as the memory resource where writing is to be started, i.e., as the write-destination resource. The resource identifier of the write-destination resource may be represented by a pair of a QoS domain ID and a placement ID, or may be represented by a superblock ID. Then, the host 2 stores one or more FARs in a submission queue (SQ), each of which includes the resource identifier of the write-destination resource and the process ID of the process to which this write-destination resource is allocated (step S102). In this way, one or more FARs are issued in advance to the storage device 3 via the submission queue (SQ).

[0249] The host 2 waits until a write request (UA tag, length, data pointer) is issued from this process (application) (step S103).

[0250] If a write request is not issued from the application (No in step S103), the host 2 waits until a write request is issued from the application. If a write request is issued from this process (application) (Yes in step S103), the host 2 stores a write command (NLW) in the submission queue (SQ) based on the write request (step S104). The write command (NLW) includes a resource identifier of the write destination resource, a process ID that identifies the process that issued the write request, a UA tag included in the write request, a length included in the write request, a data pointer included in the write request, etc. In this way, the host 2 generates a write command (NLW) by adding the resource identifier and process ID to the write request from this process (application). Then, the host 2 issues the generated write command (NLW) to the storage device 3 via the submission queue (SQ).

[0251] Upon receiving a write command (NLW) issued by the host 2, the storage device 3 selects one FAR that specifies the same resource identifier and process ID as the resource identifier and process ID specified by the write command (NLW), and completes the selected one FAR. Then, the storage device 3 transmits a command completion response for the completed FAR to the host 2 as a preceding response to the received write command (NLW). In this case, the storage device 3 executes an operation of storing the command completion response for the completed FAR in a completion queue (CQ) and an operation of transferring an ARR associated with the received write command (NLW) to a location in the read buffer specified by the completed FAR.

[0252] The host 2 determines whether or not a command completion response (prior response) for the FAR has been received from the storage device 3 (step S105). If a command completion response (prior response) for the FAR has not been received from the storage device 3 (No in step S105), the host 2 waits until a command completion response (prior response) for the FAR is received from the storage device 3. If a command completion response for the FAR has been received, more specifically if the received command completion response for the FAR includes a status indicating success of the FAR (Yes in step S105), the host 2 acquires an ARR from the read buffer specified by the completed FAR, and updates the LUT so that the physical address indicated by the acquired ARR is associated with the UA tag indicated by the acquired ARR (step S106).

[0253] The host 2 stores the additional FAR in the submission queue (SQ) (step S107). The additional FAR includes the resource identifier of the write destination resource identified in step S101 and the process ID of the process to which this write destination resource is assigned. In this way, the host 2 supplements one FAR that specifies the write destination resource identified in step S101.

[0254] The host 2 determines whether or not a command completion response to the write command (NLW) issued in step S104 has been received (step S108).

[0255] If a command completion response to the write command (NLW) is not received (No in step S108), the host 2 waits until it receives a command completion response to the write command (NLW).

[0256] When a command completion response to the write command (NLW) is received (Yes in step S108), the host 2 releases the area in the write buffer where the write data associated with the write command (NLW) is stored (step S109).

[0257] As described above, according to this embodiment, in response to receiving one or more second type commands from the host 2, each of which enables one of one or more preceding responses to be sent by the storage device 3 to the host 2, the controller 4 maintains the received one or more second type commands in the FAR pool, which is a memory area within the storage device 3, without completing the received one or more second type commands. In response to receiving a first type command from the host 2, the controller 4 obtains one second type command from the memory area, completes the obtained one second type command, and sends a command completion response for the completed one second type command to the host 2 as a first preceding response to the received first type command. Then, in response to completing processing of the first type command, the controller 4 sends a command completion response for the completed first type command to the host 2.

[0258] Therefore, even when communication with the host 2 is performed in accordance with a logical interface standard that returns only one response for one command, two or more responses can be returned for a first type command, including one or more preceding responses and a command completion response.

[0259] Furthermore, each of the one or more second type commands includes a pointer indicating a buffer area in memory 102 provided in host 2 to which information should be transferred. The controller 4 executes an operation of sending a command completion response for one completed second type command to host 2, and an operation of transferring a first preceding response for the first type command to the buffer area in memory 102 specified by the pointer. By transferring the first preceding response to the buffer area in memory 102 in this way, it is possible to increase the amount of information that can be notified to the host 2 as the first preceding response.

[0260] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0261] 1...storage system, 2...host, 3...storage device, 4...controller, 5...NAND flash memory, 6...DRAM, 10...bus, 11...host interface, 12...CPU, 13...NAND interface, 14...DRAM interface, 15...DMAC, 16...SRAM, 17...ECC encoding / decoding unit, 21...command fetch unit, 22...command processing unit, 31...FAR pool, 32...block management table, 101...processor, memory...102.

Claims

1. A storage device that communicates with a host in accordance with a logical interface standard that allows the storage device to transmit one completion response to one command issued by the host, a non-volatile memory; a controller configured to send to the host one or more prior responses to a first type command requesting the storage device to perform a predetermined operation, and a command completion response indicating that the first type command has been completed; the one or more previous responses include at least a first previous response indicating that the first type command has been accepted, and each of the one or more previous responses is a response sent by the storage device to the host before the command completion response; The controller In response to receiving one or more second type commands from the host, the one or more second type commands being used to enable one of the one or more previous responses to be sent by the storage device to the host, maintaining the received one or more second type commands in a memory area within the storage device without completing the received one or more second type commands; In response to receiving the first type command from the host, acquire one second type command from the memory area among the one or more second type commands, complete the acquired one second type command, and send a command completion response to the completed one second type command to the host as the first preceding response to the first type command; the storage device being configured, in response to completing processing of the first type command, to send the command completion response for the completed first type command to the host.

2. each of the one or more second type commands includes a pointer to a buffer area in a memory located at the host to which information is to be transferred; The controller 2. The storage device according to claim 1, further comprising: an operation of transmitting the command completion response for the completed second type command to the host; and an operation of transferring information regarding the processing of the first type command as the first preceding response to the buffer area in the memory provided in the host.

3. the first type command includes a parameter specifying a memory resource to be processed among a plurality of memory resources included in the nonvolatile memory, and a parameter specifying a process identifier indicating a process that has requested execution of processing corresponding to the first type command among a plurality of processes executed by the host; The controller managing a plurality of memory areas corresponding to the plurality of memory resources; receiving a plurality of second type commands from the host, each of the second type commands including a parameter specifying one of the plurality of memory resources and a parameter specifying a process identifier indicating one of the plurality of processes; maintain each of the received second type commands in one memory area among the plurality of memory areas based on a memory resource specified by each of the received second type commands such that each second type command specifying the same memory resource is maintained in the same memory area; In response to receiving the first type command from the host, selecting a memory area from the plurality of memory areas that corresponds to the memory resource to be processed that is specified by the received first type command; acquiring, from among the second-type commands maintained in the selected memory area, a second-type command that specifies a process identifier identical to the process identifier specified by the received first-type command; 2. The storage device of claim 1, configured to complete the acquired second type command and send a command completion response to the completed second type command to the host as the first preceding response to the received first type command.

4. 4. The storage device of claim 3, wherein the controller is configured to complete the received first-type command as an error if the one or more second-type commands maintained in the selected memory area do not include a second-type command that specifies a process identifier that is identical to the process identifier specified by the received first-type command.

5. The controller managing whether each of the plurality of memory resources is in an available state or an unavailable state; 4. The storage device according to claim 3, wherein when a plurality of first-type commands specifying a first memory resource among the plurality of memory resources are received and processed by the controller, causing the first memory resource to transition from the available state to the unavailable state, each of the incomplete second-type commands maintained in one memory area among the plurality of memory areas corresponding to the first memory resource is completed as an error.

6. the nonvolatile memory includes a plurality of blocks, each of which is a unit of a data erase operation; the controller is configured to manage a plurality of block groups, each of which includes one or more blocks; 4. The storage device according to claim 3, wherein each of the plurality of memory resources is one of the plurality of block groups.

7. the first type command is a write command for writing data to the nonvolatile memory, 4. The storage device of claim 3, wherein the write command includes a parameter that specifies one of the plurality of memory resources as the target memory resource to which the data is to be written, and a parameter that specifies a data identifier for identifying the data.

8. each of the one or more second type commands includes a pointer to a buffer area in a memory located at the host to which information is to be transferred; The controller In response to receiving the write command from the host, assigning, to the write command, a physical address indicating a physical storage location within the target memory resource to which data associated with the write command should be written; completing the one second-type command obtained; 8. The storage device of claim 7, configured to perform the operations of: sending the command completion response for the completed one second type command to the host; and transferring the assigned physical address and the data identifier to the buffer area in the memory provided in the host as the first preceding response.

9. the nonvolatile memory includes a plurality of blocks, each of which is a unit of a data erase operation; the controller is configured to manage a plurality of block groups, each of which includes one or more blocks; each of the plurality of memory resources is one block group among the plurality of block groups; the availability state of each of the plurality of memory resources indicates a state in which new data can be written to the corresponding block group; The storage device of claim 5 , wherein the unavailable state of each of the plurality of memory resources indicates that the entire corresponding block group is filled with data.

10. The storage device of claim 1 , wherein each of the one or more previous responses includes identification information included in the first type command.

11. the first type command includes a resource identifier for identifying a memory resource to be processed among a plurality of memory resources included in the nonvolatile memory; The storage device of claim 10 , wherein the identification information included in each of the one or more previous responses includes the resource identifier included in the first type command.

12. 11. The storage device of claim 10, wherein the identification information included in each of the one or more previous responses includes at least one of an identifier for identifying a submission queue from which the first type command was fetched, a command identifier for identifying the first type command, or an arbitrary numerical value assigned to the first type command by the host.

13. The controller obtain, from among the second type commands maintained in the selected memory area, a second type command that includes the same process identifier as the process identifier included in the received first type command and that was last received from the host; 4. The storage device of claim 3, further configured to complete the acquired second type command and send a command completion response for the completed second type command to the host as the first preceding response to the received first type command.

14. The controller 4. The storage device according to claim 3, wherein, when the number of second type commands to be maintained in one of the plurality of memory areas exceeds an upper limit of the number of commands that can be maintained in each of the plurality of memory areas, the storage device is configured to complete, as an error, the number of second type commands that exceeds the upper limit, among the incomplete second type commands that are already maintained in the one memory area.

15. The controller 15. The storage device according to claim 14, wherein the storage device is configured to complete one or more of the oldest second type commands that are already maintained in the one memory area and are incomplete as an error.

16. the logical interface standard is the NVM express standard, The storage device according to claim 1 , wherein the controller is configured to communicate with the host in accordance with the NVM express standard.

17. A storage system including a host and a storage device, wherein communication between the host and the storage device is performed in accordance with a logical interface standard that allows one completion response to be sent by the storage device to the host for one command issued by the host, The storage device a non-volatile memory; a controller configured to send to the host one or more prior responses to a write command to write data to the non-volatile memory and a command completion response indicating that the write command has been completed; the write command includes a parameter specifying a data identifier for identifying the data, the one or more previous responses include at least a first previous response indicating that the write command has been accepted, and each of the one or more previous responses is a response sent by the storage device to the host before the command completion response; The host issuing one or more second type commands to the storage device to enable one of the one or more prior responses to be sent by the storage device to the host; each of the one or more second type commands includes a pointer to a buffer area in a memory located at the host to which information is to be transferred; configured to issue the write command to the storage device after issuing the one or more second type commands to the storage device; The controller storing the one or more second-type commands in a memory area within the storage device in response to receiving the one or more second-type commands from the host; In response to receiving the write command from the host, assigning to the write command a physical address indicating a physical storage location within the non-volatile memory to which data associated with the write command should be written; obtaining one second-type command from the memory area; and completing the one second-type command obtained; performing an operation of transmitting the command completion response to the one completed second type command to the host, and an operation of transferring the assigned physical address and the data identifier as the first preceding response to the buffer area in the memory provided in the host; obtaining the data associated with the write command from the memory of the host, and writing the obtained data to the non-volatile memory based on the assigned physical address; the storage system being configured to transmit the command completion response, indicating completion of the write command, to the host upon completion of writing the data to the nonvolatile memory.

18. the write command includes a parameter specifying a target memory resource to which the data associated with the write command should be written, among a plurality of memory resources included in the nonvolatile memory, and a parameter specifying a process identifier indicating a process that has requested processing on the target memory resource, among a plurality of processes executed by the host; The controller managing a plurality of memory areas corresponding to the plurality of memory resources; receiving a plurality of second type commands from the host, each of the second type commands including a parameter specifying one of the plurality of memory resources and a parameter specifying a process identifier indicating one of the plurality of processes; maintain each of the received second type commands in one memory area among the plurality of memory areas based on a memory resource specified by each of the received second type commands such that each second type command specifying the same memory resource is maintained in the same memory area; In response to receiving the write command from the host, selecting a memory area corresponding to the processing target memory resource designated by the received write command from the plurality of memory areas; acquiring a second-type command that specifies a process identifier that is the same as the process identifier specified by the received write command from among the second-type commands maintained in the selected memory area; completing the one second-type command obtained; The host is configured to perform an operation of transmitting the command completion response to the one completed second type command to the host, and an operation of transferring the assigned physical address and the data identifier as the first preceding response to the buffer area in the memory provided in the host, 18. The storage system of claim 17, wherein the host is configured to issue a new second type command to the storage device after issuing the write command to the storage device, the new second type command including a parameter specifying the memory resource to be processed and a parameter specifying a process identifier indicating one of the plurality of processes.

19. The host maintaining an address translation table that manages mapping between each data identifier and each physical address of the non-volatile memory; 18. The storage system according to claim 17, further configured to update the address translation table so that the physical address transmitted from the storage device is associated with the data identifier transmitted from the storage device.

Images