Conversion method, restoration method, conversion device, and restoration device

Abstract

To provide a conversion method and the like capable of reducing power consumption during a memory access with a simple method while maintaining image quality.SOLUTION: First video data is in one or more display line composed by a plurality of pixels being arranged. A conversion method includes: acquisition steps (S11 and S12) of acquiring maximal value and minimum value of gradation value of the plurality of pixels on the basis of the first video data; a determination step (S14) of determining second bit accuracy to be bit accuracy after conversion of the first video data and equal to the first bit accuracy or lower on the basis of the calculated representative value, maximal value and minimum value; a conversion step (S15) of converting the first video data of the first bit accuracy into second video data of the second bit accuracy on the basis of the representative value and the gradation value of the plurality of pixels; and a writing step (S16) of writing the representative value, the second bit accuracy, and the second video data to the memory in association with one another.SELECTED DRAWING: Figure 11

Description

[Technical Field]

[0001] The present disclosure relates to a conversion method, a restoration method, a conversion device, and a restoration device. [Background technology]

[0002] Conventionally, various methods have been considered for reducing the amount of data when saving video data. For example, Patent Document 1 discloses a technique for reducing the amount of video data using an encoding table. By reducing the amount of data, it is possible to reduce the power consumption when writing video data to memory (when accessing memory). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-96457 Summary of the Invention [Problem to be solved by the invention]

[0004] However, the technology of Patent Document 1 has the problem that the processing becomes complicated and the hardware resources increase. It is desirable to reduce the amount of data by a simple method. There is also a method of lowering the bit precision of the video data, but this has the problem of degrading the image quality.

[0005] Therefore, the present disclosure provides a conversion method, a restoration method, a conversion device, and a restoration device that can reduce power consumption during memory access in a simple manner while maintaining image quality. [Means for solving the problem]

[0006] A data conversion method according to one embodiment of the present disclosure is a method for converting first video data of a first bit precision and writing the first video data to a memory, the first video data being video data for one or more display lines configured with a plurality of pixels lined up, the method including: an acquisition step of acquiring a representative value, a maximum value, and a minimum value of gradation values ​​of the plurality of pixels based on the first video data; a determination step of determining a second bit precision, which is the bit precision after conversion of the first video data, based on the acquired maximum value and minimum value, the second bit precision being equal to or less than the first bit precision; a conversion step of converting the first video data of the first bit precision into second video data of the determined second bit precision based on the representative value and the gradation values ​​of the plurality of pixels; and a write step of associating the representative value, the second bit precision, and the second video data and writing them to the memory.

[0007] A data restoration method according to one embodiment of the present disclosure is a restoration method for restoring first video data from second video data of a second bit precision equal to or less than the first bit precision into which first video data of a first bit precision has been converted, wherein the first video data is video data for one or more display lines each consisting of a plurality of pixels arranged side by side, and the second video data, the second bit precision, and a representative value of the gradation values ​​of the plurality of pixels calculated based on the first video data are stored in a memory in correspondence with each other, the method including: a reading step for reading the second video data, the second bit precision, and the representative value from the memory; a dividing step for dividing the second video data into data corresponding to each of the plurality of pixels based on the second bit precision; and a restoration step for restoring the second video data to the first video data of the first bit precision based on the representative value and a value corresponding to the gradation value of the pixel indicated by each of the divided data.

[0008] A data conversion device according to one embodiment of the present disclosure is a conversion device that converts first video data to a first bit precision and writes the first video data to a memory, the first video data being video data for one or more display lines each consisting of a plurality of pixels arranged side by side, and includes: an acquisition unit that acquires a representative value, a maximum value, and a minimum value of gradation values ​​of the plurality of pixels based on the first video data; a determination unit that determines a second bit precision, which is the bit precision after conversion of the first video data, based on the acquired maximum value and minimum value, the second bit precision being equal to or less than the first bit precision; a conversion processing unit that converts the first video data to second video data with the determined second bit precision based on the representative value and the gradation values ​​of each of the plurality of pixels; and a writing unit that associates the representative value, the second bit precision, and the second video data and writes them to the memory.

[0009] A data restoration device according to one embodiment of the present disclosure is a restoration device that restores first video data from second video data of a second bit precision equal to or less than the first bit precision into which first video data of a first bit precision has been converted, wherein the first video data is video data for one or more display lines each consisting of a plurality of pixels arranged side by side, and the second video data, bit precision information indicating the second bit precision, and a representative value of the gradation values ​​of the plurality of pixels calculated based on the first video data are stored in correspondence with each other in a memory, and the data restoration device includes: a reading unit that reads the second video data, the bit precision information, and the representative value from the memory; a dividing unit that divides the second video data into data corresponding to each of the plurality of pixels based on the second bit precision; and a restoration processing unit that restores the second video data to the first video data of the first bit precision based on the gradation value of the pixel indicated by each of the divided data and the representative value. [Effects of the Invention]

[0010] According to one aspect of the present disclosure, it is possible to realize a conversion method or the like that can reduce power consumption during memory access in a simple manner while maintaining image quality. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic diagram showing a configuration example of a display device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram schematically showing the configuration of a pixel circuit according to the embodiment. [Figure 3] FIG. 3 is a block diagram illustrating a functional configuration of a control device included in the display device according to the embodiment. [Figure 4] FIG. 4 is a block diagram illustrating a functional configuration of a conversion unit according to the embodiment. [Figure 5] FIG. 5 is a diagram showing an example of gradation values ​​for one line. [Figure 6] FIG. 6 is a table showing the relationship between the maximum difference value and bit precision according to the embodiment. [Figure 7] FIG. 7 is a diagram showing an image of data before and after conversion when the maximum difference value is 12. [Figure 8] FIG. 8 is a diagram illustrating a data structure of the integrated information according to the embodiment. [Figure 9] FIG. 9 is a block diagram illustrating a functional configuration of a restoration unit according to the embodiment. [Figure 10] FIG. 10 is a diagram showing an image of data before and after restoration when the maximum difference value is 12. [Figure 11] FIG. 11 is a flowchart illustrating a first example of the operation of the control device according to the embodiment. [Figure 12] FIG. 12 is a diagram illustrating an example of bit precision determined by the average value and the maximum difference value according to the embodiment. [Figure 13] FIG. 13 is a flowchart illustrating a second example of the operation of the control device according to the embodiment. [Figure 14] FIG. 14 is a diagram showing a configuration in which the control device according to the embodiment stores video data in an external memory. [Figure 15] FIG. 15 is a diagram for explaining power reduction in the application example. [Figure 16] FIG. 16 is a diagram showing a configuration in which the control device according to the embodiment stores video data in an internal memory. DETAILED DESCRIPTION OF THE INVENTION

[0012] (Background to this disclosure) Conventionally, video signals (video data) input from an external device are temporarily stored in a memory such as a frame memory in order to convert them into a format for internal use. For example, when high-speed operation is required, such as for a high-resolution video signal such as 4K, where one frame period is 144 Hz, a large amount of data must be processed at high speed, posing a problem of increased power consumption due to increased memory access. Therefore, there is a need to reduce the power consumption due to memory access.

[0013] It is also known that reducing the amount of video data and shortening the time required to access memory can reduce the amount of power consumed by memory access. It is desirable to reduce the amount of data in a simple manner while maintaining image quality.

[0014] As in Patent Document 1, it is possible to reduce the amount of video data using an encoding table, but as described in the "Problem to be solved by the invention," there is a problem that the processing becomes complicated and hardware resources increase.

[0015] As a method for reducing data volume other than that described in Patent Document 1, for example, it is possible to reduce the data volume by uniformly lowering the bit precision of the video data (for example, from 10 bits to 8 bits), but this has the problem of degrading image quality.Also, for example, there is a method for increasing the compression rate by performing entropy coding, but the compression rate may deteriorate depending on the correspondence between the code and the assigned gradation data (gradation value).

[0016] As such, while conventional methods may be able to reduce power consumption, they also have issues such as deterioration in image quality, increased complexity of processing, and in some cases, a deterioration in compression ratio, making it difficult to reduce power consumption in a simple manner while maintaining image quality.

[0017] Therefore, in this disclosure, a conversion method, restoration method, etc. that can reduce power consumption during memory access in a simple manner while maintaining image quality will be described.

[0018] Hereinafter, the embodiments will be specifically described with reference to the drawings.

[0019] Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, components, component placement and connection configurations, steps, and step sequences shown in the following embodiments are merely examples and are not intended to limit the present disclosure. For example, terms indicating relationships between elements, such as "identical," as well as numerical values ​​and numerical ranges, are not expressions that express only the strict meaning, but also expressions that include a substantially equivalent range, for example, a difference of a few percent (e.g., about 10%). Furthermore, among the components in the following embodiments, components not described in independent claims are described as optional components.

[0020] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0021] (Embodiment) A conversion method, a restoration method, etc. according to this embodiment will be described below with reference to Fig. 1 to Fig. 16. In this embodiment, a case where an organic electroluminescence (EL) element is used in a display device will be described as an example.

[0022] [1. Display device configuration] First, the configuration of a display device including a control device according to one embodiment of the present disclosure will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing an example configuration of a display device 1 according to the present embodiment.

[0023] 1, the display device 1 includes a display panel 10 and a control device 20. The display device 1 is driven by, for example, a progressive drive method for an organic EL light-emitting panel.

[0024] [1-1. Display panel configuration] The display panel 10 includes a display section 12 having a plurality of pixel circuits 30, and also includes a gate drive circuit 14 and a source drive circuit 16 as peripheral circuits of the display section 12. The display section 12, gate drive circuit 14, source drive circuit 16, scanning lines 40, and signal lines 42 are mounted on a panel substrate (not shown) made of, for example, glass or a resin such as acrylic.

[0025] The display unit 12 displays an image based on a video signal (R, G, B) (see FIG. 2) input from outside to the display device 1. As shown in FIG. 1, the display unit 12 includes a plurality of pixel circuits 30 arranged in a matrix, with row-like scanning lines 40 and column-like signal lines 42 wired thereto. In the display unit 12, an initialization operation, a writing operation, and a light-emitting operation are performed row-by-row for the plurality of pixel circuits 30. Note that, in the following, an example will be described in which the bit precision (number of bits) of the video signal (R, G, B) input from outside to the display device 1 is 10 bits, but the present invention is not limited to this.

[0026] The display panel 10 has a plurality of pixel circuits 30 arranged in a matrix. More specifically, each of the plurality of pixel circuits 30 is arranged at a position where a scanning line 40 and a signal line 42 intersect. Details will be described later.

[0027] The scanning lines 40 are arranged for each row of the pixel circuits 30. One end of the scanning line 40 is connected to the pixel circuit 30, and the other end of the scanning line 40 is connected to the gate drive circuit .

[0028] The signal line 42 is arranged for each column of the pixel circuits 30. One end of the signal line 42 is connected to the pixel circuit 30, and the other end of the signal line 42 is connected to the source drive circuit 16.

[0029] The gate drive circuit 14 is also called a scanning line drive circuit and is configured by, for example, a shift register. The gate drive circuit 14 is connected to the scanning lines 40 and outputs gate control signals to the scanning lines 40 to control the on / off of each transistor in the pixel circuit 30. In the present embodiment, the gate drive circuit 14 outputs, for example, a control signal WS, a control signal REF, a control signal INI, and a quenching signal EN to the gate (gate electrode) of each transistor in the pixel circuit 30 as gate control signals that control the on / off of each transistor in the pixel circuit 30. The control signal WS, the control signal REF, the control signal INI, and the quenching signal EN are examples of control signals.

[0030] The source driving circuit 16 is also called a signal line driving circuit. The source driving circuit 16 is connected to a signal line 42 and outputs a video signal, which is supplied from the control device 20 on a frame-by-frame basis, to the signal line 42, thereby supplying the video signal to each pixel circuit 30. The source driving circuit 16 writes luminance information based on the video signal to each pixel circuit 30 in the form of a current value or a voltage value through the signal line 42. The video signal input to the source driving circuit 16 is, for example, digital serial data (video signals (R, G, B)) for each of the three primary colors of RGB. The video signals (R, G, B) input to the source driving circuit 16 are converted into row-by-row parallel data (an example of an output video signal) within the source driving circuit 16. The row-by-row parallel data is further converted into row-by-row analog data within the source driving circuit 16, which is output to the signal line 42 as a video signal.

[0031] [1-2. Pixel circuit configuration] The plurality of pixel circuits 30 are arranged, for example, in N rows and M columns. N and M vary depending on the size and resolution of the display screen. For example, in a resolution called HD (High Definition), when pixel circuits 30 corresponding to the three primary colors of RGB are adjacent in a row, N is at least 1080 rows and M is at least 1920 × 3 columns. In this embodiment, each pixel circuit 30 has an organic EL element as a light-emitting element.

[0032] The configuration of the pixel circuit 30 will be further described with reference to Fig. 2. Fig. 2 is a circuit diagram that schematically shows the configuration of the pixel circuit 30 according to the present embodiment.

[0033] 2, the pixel circuit 30 includes a light-emitting element 32, a drive transistor 33, switch transistors 34, 36, and 37, a selection transistor 35, and a pixel capacitor 38. In FIG. 2, the pixel capacitor 38 is also represented as Cs.

[0034] The light-emitting element 32 has a cathode connected to a power supply Vcath (negative power supply line) and an anode connected to the source of the drive transistor 33. When a current corresponding to the signal voltage of a video signal flows through the light-emitting element 32 from the drive transistor 33, the light-emitting element 32 emits light at a luminance corresponding to the signal voltage. The light-emitting element 32 is, for example, an organic EL element such as an OLED (Organic Light Emitting Diode). For example, a pixel circuit 30 (pixel) constituting a display panel 10 that displays an image is composed of a light-emitting element 32 that emits light by current driving, including an organic EL element. Note that the light-emitting element 32 is not limited to an organic EL element, but may be a self-emitting element such as an inorganic EL element or a QLED (Quantum-dot Light Emitting Diode), or may not be a self-emitting element as long as it is an element controlled by current driving.

[0035] The gate of the driving transistor 33 is connected to one electrode of the pixel capacitor 38, the drain is connected to the source of the switch transistor 34, and the source is connected to the anode of the light-emitting element 32. In FIG. 2, the source is also connected to the other electrode of the pixel capacitor 38. The driving transistor 33 converts a signal voltage applied between the gate and source into a current (also referred to as a drain-source current) corresponding to the signal voltage. When the driving transistor 33 is turned on, it supplies a drain-source current to the light-emitting element 32, causing the light-emitting element 32 to emit light. The driving transistor 33 is configured, for example, with an n-type thin film transistor (n-type TFT (Thin Film Transistor)).

[0036] The switch transistor 34 has a gate connected to the scanning line 40, one of its source and drain connected to a power supply Vcc, and the other of its source and drain connected to the drain of the drive transistor 33. The switch transistor 34 is turned on or off in response to a light-off signal EN supplied from the scanning line 40. When the switch transistor 34 is turned on, it connects the drive transistor 33 to the power supply Vcc, causing a current to be supplied between the drain and source of the drive transistor 33 to the light-emitting element 32. The switch transistor 34 is formed, for example, by a p-type thin film transistor (p-type TFT).

[0037] The selection transistor 35 has a gate connected to a scanning line 40, one of a source and a drain connected to a signal line 42, and the other of the source and drain connected to one electrode of a pixel capacitor 38. The selection transistor 35 is turned on or off in response to a control signal WS supplied from the scanning line 40. When the selection transistor 35 is turned on, it applies the signal voltage of the video signal supplied from the signal line 42 to the electrode of the pixel capacitor 38, causing a charge corresponding to the signal voltage to accumulate in the pixel capacitor 38. The selection transistor 35 is formed, for example, by an n-type thin film transistor (n-type TFT).

[0038] The switch transistor 36 has a gate connected to a scanning line 40, one of a source and a drain connected to a power supply Vref, and the other connected to one electrode of a pixel capacitor 38. The switch transistor 36 is turned on or off in response to a control signal REF supplied from the scanning line 40. When the switch transistor 36 is turned on, it sets the electrode of the pixel capacitor 38 to the voltage (reference voltage) of the power supply Vref. The switch transistor 36 is formed, for example, by an n-type thin film transistor (n-type TFT).

[0039] The switch transistor 37 has a gate connected to a scanning line 40, one of a source and a drain connected to the source of the switch transistor 34 and the drain of the drive transistor 33, and the other connected to a power supply Vini. The switch transistor 37 is turned on or off in response to a control signal INI supplied from the scanning line 40. When the drive transistor 33 is on and the switch transistor 34 is on, cutting off the connection to the power supply Vcc, the switch transistor 37 is turned on to set the anode of the light-emitting element 32 to the voltage (reference voltage) of the power supply Vini. The switch transistor 37 is formed, for example, by an n-type thin film transistor (n-type TFT).

[0040] The pixel capacitor 38 is a capacitor having one electrode connected to the gate of the drive transistor 33, the source of the selection transistor 35, and the source of the switch transistor 36, and the other electrode connected to the source of the drive transistor 33. The pixel capacitor 38 accumulates charge corresponding to the signal voltage supplied from the signal line 42. For example, the pixel capacitor 38 stably maintains the voltage between the gate and source electrodes of the drive transistor 33 after the selection transistor 35 and the switch transistor 36 are turned off. In this way, when the selection transistor 35 and the switch transistor 36 are turned off, the pixel capacitor 38 applies a voltage between the gate and source of the drive transistor 33 in accordance with the signal potential due to the accumulated charge.

[0041] The EL capacitance 39 is a parasitic capacitance inherent in the EL element, and after this capacitance is charged and the voltage between the electrodes rises, a current starts to flow toward the EL element, causing the EL element to start emitting light.

[0042] The conductivity types of the drive transistor 33, selection transistor 35, switch transistor 36, and switch transistor 37 are not limited to those described above, and n-type and p-type TFTs may be mixed as appropriate. The conductivity type of the switch transistor 34 is not limited to those described above, and it may be an n-type TFT. Each transistor is not limited to a polysilicon TFT, and may be composed of an amorphous silicon TFT or the like.

[0043] [1-3. Control device configuration] The configuration of the control device 20 will be further described with reference to Fig. 3. Fig. 3 is a block diagram showing the functional configuration of the control device 20 included in the display device 1 according to this embodiment.

[0044] The control device 20 is formed on, for example, an external system circuit board (not shown) disposed outside the display panel 10. The control device 20 functions as, for example, a TCON (Timing Controller) and controls the overall operation of the display device 1. Specifically, the control device 20 outputs gate control signals generated based on a vertical synchronization signal VS, a horizontal synchronization signal HS, and a video period signal DE supplied from the outside to the gate drive circuit 14. The control device 20 also supplies digital serial data of video signals (R, G, B) to the source drive circuit 16.

[0045] In this embodiment, the control device 20 controls at least the light-emitting period and the light-extinction period of a frame period, which is a period during which the same image is continuously displayed. The control device 20 distributes (divides) the light-extinction period of the frame period by configuring each frame period into multiple sub-frame periods in which the light-emitting period and the light-extinction period are repeated at regular intervals.

[0046] Furthermore, when the frame period, which is the period during which the same image continues to be displayed, fluctuates within a certain range for each frame or is temporarily stable, but the exact frame period is not known in advance, the control device 20 of the present disclosure may change the frame length of the subframes so as to reconstruct the frame period with n (n is an integer of 2 or more) subframes, regardless of the input frame period, and perform control to display the image.

[0047] As shown in FIG. 3, the control device 20 includes a conversion unit 110, a synchronization control unit 120, a line buffer 130, a restoration unit 140, and a duty control unit 150.

[0048] The conversion unit 110 converts the video signals (R, G, B) received from the outside so as to reduce the amount of data of the video signals (R, G, B) for each line and output the reduced data to the line buffer 130. The conversion unit 110 generates information (integrated information, described later) by converting the number of bits corresponding to the bit precision of the video signals (R, G, B) for each line received from the outside into a smaller number of bits, and outputs the information to the line buffer 130 (writes it into the line buffer 130). The conversion unit 110 outputs information generated by sequentially converting the number of bits of the video signals (R, G, B) for each line to the line buffer 130. The conversion unit 110 generates integrated information from the video signals (R, G, B) based on a vertical synchronization signal VS, a horizontal synchronization signal HS, and a video period signal DE from the outside so that the video signals (R, G, B) are displayed on the display unit 12 at desired timing, and outputs the integrated information to the line buffer 130. Details of the conversion unit 110 will be described later. Hereinafter, converting the number of bits according to the bit precision to a smaller number of bits will also be referred to simply as converting the bit precision. The smaller number of bits will also be referred to as the bit precision after conversion.

[0049] Since the conversion unit 110 writes the integrated information in which the data amount of the video signals (R, G, B) has been reduced to the line buffer 130, the access time to the line buffer 130 can be reduced compared to when the video signals (R, G, B) for each line received from the outside are written to the line buffer 130. This leads to a reduction in the power required to write the video signals (R, G, B).

[0050] The video signals (R, G, B) received from the outside for each line are video data for a display line configured by a plurality of pixels arranged side by side, and are an example of first video data. The bit precision (10 bits in this embodiment) of the video signals (R, G, B) is an example of first bit precision.

[0051] The synchronization control unit 120 is a control unit for controlling the timing at which the video signals (R, G, B) are displayed on the display unit 12. The synchronization control unit 120 receives a vertical synchronization signal VS, a horizontal synchronization signal HS, and a video period signal DE from the outside, and outputs them to the duty control unit 150 and the line buffer 130.

[0052] The line buffer 130 is a buffer that temporarily stores information based on the video signal (R, G, B). In this embodiment, the line buffer 130 stores the information converted by the conversion unit 110 and outputs it to the restoration unit 140 at a predetermined timing.

[0053] The line buffer 130 has a capacity capable of temporarily holding information based on, for example, several lines of video signals (R, G, B). The line buffer 130 is an example of a memory.

[0054] The restoration unit 140 reads the integrated information from the line buffer 130 and converts the video signals (R, G, B) for each line, whose bit precision has been converted, back to the original bit precision. The restoration unit 140 performs a process of restoring the video signals (R, G, B) for each line received from the outside from the integrated information. The restoration unit 140 will be described in detail later.

[0055] Since the restoration unit 140 reads out the integrated information from the line buffer 130, the access time to the line buffer 130 can be reduced compared to when the video signals (R, G, B) for each line received from the outside are read out from the line buffer 130. This leads to a reduction in the power required to read out the video signals (R, G, B). Furthermore, since the restoration unit 140 can restore the video signals (R, G, B) for each line received from the outside from the integrated information, degradation of image quality is less likely to occur.

[0056] The duty control unit 150 generates a gate control signal for controlling the gate drive circuit 14 so that the video signals (R, G, B) are displayed on the display unit 12 at desired timing. The duty control unit 150 outputs the generated gate control signal to the gate drive circuit 14. In this embodiment, the duty control unit 150 detects the reception of the vertical synchronization signal VS or the video period signal DE.

[0057] Furthermore, duty control unit 150 may generate gate control signals for executing multiple subframe periods in which light-emitting periods and extinction periods are repeated at regular intervals. When duty control unit 150 detects a signal indicating the start of a frame period, it generates a gate control signal for executing an initialization period during the extinction period in the subframe period following the subframe period executed upon detection. Otherwise, i.e., when duty control unit 150 does not detect a signal indicating the start of a frame period, it generates a gate control signal for repeatedly executing subframe periods consisting of light-emitting periods and extinction periods at regular intervals.

[0058] The duty control unit 150 generates a gate control signal for controlling the emission and extinction of the light-emitting element 32 based on the input length of the sub-frame period, the initialization parameter, and the extinction parameter, the presence or absence of a signal indicating the start of the frame period, and the count value (timer value) from the start of the extinction period of the sub-frame period, and outputs the signal to the gate drive circuit 14.

[0059] [1-3-1. Configuration of the conversion unit] Next, the conversion unit 110 will be further described with reference to Figures 4 to 8. Figure 4 is a block diagram showing the functional configuration of the conversion unit 110 according to this embodiment.

[0060] As shown in FIG. 4, the conversion unit 110 includes a preprocessing buffer 111, a calculation unit 112, an extraction unit 113, a determination unit 114, and a conversion processing unit 115.

[0061] The pre-processing buffer 111 is a buffer that temporarily stores video signals (R, G, B) for each line received from the outside. The pre-processing buffer 111 stores the video signals (R, G, B) until the bit precision after conversion is determined by the determination unit 114.

[0062] The calculation unit 112 calculates a representative value of the video signal (R, G, B) for each line based on the video signal (R, G, B) for that line. It can also be said that the calculation unit 112 calculates a representative value of the gradation values ​​for that line based on the gradation values ​​of each of the multiple pixels that make up that line. The calculation unit 112 calculates one representative value for each line. The representative value may be equal to or greater than the minimum gradation value for that line and equal to or less than the maximum gradation value for that line. Hereinafter, an example will be described in which the representative value is the average value of the gradation values ​​of the multiple pixels in that line, but this is not limiting and the representative value may be the maximum, minimum, median, mode, etc. of the gradation values ​​of the multiple pixels. The representative value may also be calculated based on the gradation values ​​of the multiple pixels in a previous frame (the video signal (R, G, B) for each line). For example, the representative value may be the average, maximum, minimum, median, mode, etc. of the gradation values ​​of the multiple pixels in the most recent frame (e.g., the previous frame).

[0063] Fig. 5 is a diagram showing an example of gradation values ​​for one line. Fig. 5 shows a display of a video signal for one line and a graph showing the relationship between pixel positions and gradation values. In this line, an image is displayed that is bright in the center and dark on the left and right.

[0064] As shown in FIG. 5, the calculation unit 112 calculates the average value of the gradation values ​​of the line based on the gradation value of each pixel. For example, the calculation unit 112 may calculate the average value by adding up the gradation values ​​of each pixel in one line and dividing the sum by the number of pixels in that line. Furthermore, in order to prevent the processing in an arithmetic circuit (for example, a multiplier or divider) from becoming complicated, if the number of pixels in one line is not a power of two, the calculation unit 112 may calculate the average value using the gradation values ​​of dummy pixels so that the number of pixels in one line becomes a power of two. For example, if the number of pixels in one line is 900 pixels, the calculation unit 112 may calculate the average value using the gradation values ​​of the 900 pixels and the gradation values ​​of 124 dummy pixels. The gradation values ​​of the 124 dummy pixels may be, for example, an average value calculated by the calculation unit 112 or a predetermined fixed value. The fixed value may be a value based on the bit precision of the video signal (R, G, B) received from outside, or may be, for example, the median value of the bit precision. If the bit precision of the video signal (R, G, B) is 10 bits, the median value of the bit precision is 512. Note that the method by which the calculation unit 112 calculates the average value is not limited to the above, and any existing method may be used. The calculation unit 112 functions as an acquisition unit that acquires a representative value of the gradation values ​​of each pixel in one line indicated by the video signal (R, G, B).

[0065] 4 again, extraction unit 113 extracts the maximum and minimum values ​​of the video signals (R, G, B) for each line based on the video signals (R, G, B) for that line. Extraction unit 113, for example, extracts the largest gradation value from among the gradation values ​​of each of the multiple pixels that make up that line, sets the extracted gradation value as the maximum value for that line, and extracts the smallest gradation value from among the gradation values ​​of each of the multiple pixels that make up that line, and sets the extracted gradation value as the minimum value for that line.

[0066] 5, the extraction unit 113 determines the gradation value of the pixel near the center to be the maximum value and the gradation value of the pixel on the right edge to be the minimum value. The extraction unit 113 functions as an acquisition unit that acquires the maximum and minimum gradation values ​​of each pixel in one line indicated by the video signal (R, G, B).

[0067] 4 again, the determination unit 114 determines the bit precision after conversion of the video signal (R, G, B) of the line based on the average value calculated by the calculation unit 112 and the maximum and minimum values ​​of the gradation values ​​extracted by the extraction unit 113. The bit precision after conversion is an example of second bit precision, and is equal to or lower than the bit precision of the video signal (R, G, B). Furthermore, the bit precision after conversion is common to one line.

[0068] In this way, the determination unit 114 dynamically determines the bit precision after conversion based on the video signal (R, G, B) of the line of the frame. The bit precision after conversion may differ for each line, for example.

[0069] FIG. 6 is a table showing the relationship between the maximum difference value and bit precision according to this embodiment.

[0070] The determination unit 114 determines the bit precision based on, for example, the maximum value, the average value, and the minimum value and the table shown in Fig. 6. The determination unit 114 calculates a first difference obtained by subtracting the average value from the maximum value and a second difference obtained by subtracting the minimum value from the average value, sets the larger of the first difference and the second difference as the maximum difference, and determines the bit precision after conversion from the table in Fig. 6.

[0071] If the maximum difference value is 512 or greater, the determination unit 114 determines that the bit precision after conversion will be 10 bits, i.e., no bit conversion will be performed, if the maximum difference value is 256 or greater and less than 512, the determination unit 114 determines that the bit precision after conversion will be 9 bits, and if the maximum difference value is 128 or greater and less than 256, the determination unit 114 determines that the bit precision after conversion will be 8 bits. Similarly, if the maximum difference value is less than 128, the determination unit 114 determines the bit precision after conversion based on the table shown in Fig. 6. In this way, the determination unit 114 determines that the minimum bit precision that can express the maximum difference will be the bit precision after conversion.

[0072] 6 shows an example in which the bit precision is in 1-bit increments, but is not limited to this. The table only needs to include a bit precision of 1 or more that is smaller than 10 bits and the maximum difference value when converted to the bit precision. The table may also be a table in 2-bit increments, for example.

[0073] The determination unit 114 may determine the bit precision after conversion of the video signal (R, G, B) of the line based on at least the maximum and minimum gradation values. For example, when the maximum or minimum gradation value is used as the representative value, the determination unit 114 may determine the bit precision after conversion by using the difference obtained by subtracting the minimum value from the maximum value as the maximum difference value. Furthermore, the determination unit 114 may determine whether a sign bit is included or not, and include the determination result in the bti precision information indicating the bit precision after conversion.

[0074] The conversion processing unit 115 generates integrated information including video data (converted data, described later) to be stored in the line buffer 130 based on the video signal (R, G, B) for each line received from the outside and stored in the pre-processing buffer 111, the bit precision after conversion determined by the determination unit 114, and the average value calculated by the calculation unit 112, and outputs the generated information to the line buffer 130. The conversion processing unit 115 converts the video signal (R, G, B) into converted data with the determined bit precision based on the gradation value of each pixel and the average value calculated by the calculation unit 112. The conversion processing unit 115 generates integrated information including the converted data of each pixel by using the difference between the gradation value of each pixel and the average value calculated by the calculation unit 112 as the converted data of each pixel. Such integrated information may be information in which the amount of data is reduced from the video signal (R, G, B) for each line received from the outside.

[0075] FIG. 7 is a diagram showing an image of data before and after conversion when the maximum difference is 12. Before conversion, one box represents the data of one pixel, and after conversion, a set of a sign bit and a difference represents the data of one pixel. FIG. 5 shows an image of video data for six pixels. The numbers in the boxes represent the bit precision of the video data. The video data before conversion has 10 bits, which is the bit precision of the video signal (R, G, B) received from outside. Note that when the maximum difference is 12, the determination unit 114 determines that the bit precision after conversion will be 4 bits.

[0076] The conversion processing unit 115 generates converted data for each pixel by using the difference between the gradation value and the average value as the converted gradation value of that pixel. Since this difference is at most 12, it can be expressed in 4 bits. In this way, the conversion processing unit 115 converts the gradation value expressed in 10 bits into a 4-bit gradation value that indicates the difference from the average value. The conversion processing unit 115 uniformly converts the 10-bit gradation value for each pixel into 4 bits. This makes it possible to convert 10-bit video data (video signals (R, G, B)) into 4-bit data.

[0077] Furthermore, the conversion processing unit 115 may add a sign bit to the converted gradation value (difference). The sign bit is a bit that indicates whether the difference between each of the multiple pixels is a positive value or a negative value. Note that if the maximum or minimum value is used as the representative value, the sign bit does not need to be included.

[0078] FIG. 8 is a diagram showing the data structure of the integrated information according to this embodiment.

[0079] 8, the integrated information includes header information and converted data. The header information includes an average value and bit precision. The integrated information is information that combines the header information and converted data including one line's worth of sign bits and differences into a single data set.

[0080] The average value is the average value (10 bits) calculated by the calculation unit 112 from one line of video signal (R, G, B) (10 bits) received from an external device. In other words, the average value corresponds to the average value used when converting from 10 bits to 4 bits in FIG. 7, and is a gradation value indicated by the bit precision of one line of video signal (R, G, B). Bit precision indicates the bit precision of the gradation value of each pixel in the converted data, and is also referred to as bit precision information. In the example of FIG. 7, the bit precision indicated by the bit precision information is 4 bits. The bit precision information is used when restoring the difference (converted gradation value) to the original 10-bit gradation value. The bit precision information is, for example, information of bit precision capable of expressing the bit precision (10 bits in this embodiment) of the external video signal (R, G, B). If the bit precision of the video signal (R, G, B) is 10 bits, the bit precision information is 4 bits. The bit precision information is indicated as 4 bits, regardless of the bit precision after conversion.

[0081] The converted data is a data portion indicating the difference between each pixel, and is configured by arranging the sign bit and the difference shown in Fig. 7. The converted data is an example of second video data.

[0082] The conversion processing unit 115 generates the integrated information shown in FIG.

[0083] As described above, the conversion unit 110 can calculate an average value from one line of video signal (R, G, B) received from the outside and reduce the data amount of the video signal using the average value. In other words, the conversion unit 110 can reduce the data amount of the video signal (R, G, B) and write it to the line buffer 130 without using an encoding table or the like. This allows the time required for the conversion unit 110 to access the line buffer 130 to write the integrated information to the line buffer 130 to be shorter than when writing the video signal itself (uncompressed signal), and as a result, the power consumed by the line buffer 130 can be reduced.

[0084] [1-3-2. Configuration of the restoration section] Next, the restoration unit 140 will be further described with reference to Figures 9 and 10. Figure 9 is a block diagram showing the functional configuration of the restoration unit 140 according to this embodiment.

[0085] As shown in FIG. 9, the restoration unit 140 includes a division unit 141, a post-processing latch 142, an average value holding unit 143, a bit precision holding unit 144, and a restoration processing unit 145.

[0086] The division unit 141 divides the integrated information read from the line buffer 130 into an average value, bit precision, and converted data, outputs the average value to the average value holding unit 143, outputs the bit precision to the bit precision holding unit 144, and outputs the converted data to the post-processing latch 142.

[0087] The post-processing latch 142 is a buffer that temporarily holds the converted data acquired from the division unit 141. The post-processing latch 142 holds the converted data until the data is restored in the restoration processing unit 145.

[0088] The average value holding unit 143 temporarily holds the average value obtained from the dividing unit 141 .

[0089] The bit precision storage unit 144 temporarily stores the bit precision acquired from the division unit 141 .

[0090] The restoration processing unit 145 generates video data to be displayed on the display unit 12 and outputs it to the source driving circuit 16. The restoration processing unit 145 performs processing to restore the converted data to a video signal (R, G, B) received from outside, based on the converted data held in the post-processing latch 142, the average value held in the average value holding unit 143, and the bit precision held in the bit precision holding unit 144. It can also be said that the restoration processing unit 145 reconverts the bit precision (e.g., 4 bits) of the converted data into the bit precision (e.g., 10 bits) of the video signal (R, G, B) received from outside.

[0091] Fig. 10 is a diagram showing an image of data before and after restoration when the maximum difference value is 12. Fig. 10 shows an image of video data for 6 pixels. The numbers in the boxes indicate the bit precision of the video data. The video data before restoration is converted data that has been bit-converted by conversion unit 110, and is represented by 4 bits.

[0092] The restoration processing unit 145 restores the 10-bit gradation value of each pixel by adding or subtracting the average value and the difference for each pixel included in the converted data. The restoration processing unit 145 restores the 4-bit difference for each pixel to a uniform 10-bit gradation value. When the sign bit indicates a positive value, the restoration processing unit 145 restores the 10-bit gradation value of the pixel by adding the average value and the difference. When the sign bit indicates a negative value, the restoration processing unit 145 restores the 10-bit gradation value of the pixel by subtracting the difference from the average value. The video data restored in this way is the video signal (R, G, B) (video data) for each line received from the outside, so there is no degradation in the image quality of the displayed video.

[0093] As described above, the restoration unit 140 can restore the video signal (R, G, B) using the integrated information. That is, the restoration unit 140 can restore data without using a restoration table or the like. Furthermore, the integrated information is compressed data, and the time required for the restoration unit 140 to access the line buffer 130 in order to read the integrated information from the line buffer 130 can be shortened compared to when reading the video signal itself (uncompressed signal), thereby reducing the power consumed by the line buffer 130.

[0094] [2. Operation of the control device] The operation of the control device 20 configured as above will be described with reference to Figs. 11 to 13. First, the operation of the conversion unit 110 will be described with reference to Figs. 11 and 12. Fig. 11 is a flowchart showing a first example of the operation (conversion method) of the control device 20 according to this embodiment. Fig. 11 shows the processing in the conversion unit 110, and more specifically, shows a method of converting the first video data with first bit precision and writing it to the line buffer 130. Below, an example will be described in which the calculation unit 112 calculates an average value as a representative value.

[0095] 11, when conversion unit 110 acquires one line of video data (video signals (R, G, B)), it calculates an average value of gradation values ​​from the acquired video data (S11). Calculation unit 112 calculates an average value of gradation values ​​of one line based on the gradation values ​​of each of a plurality of pixels in the line, and outputs the calculated average value to determination unit 114.

[0096] Next, based on the video data for one line, extraction unit 113 extracts the maximum and minimum gradation values ​​for that line (S12). Based on the gradation values ​​of each of the multiple pixels in that line, calculation unit 112 extracts the maximum and minimum gradation values ​​for that line, and outputs the extracted maximum and minimum values ​​to determination unit 114.

[0097] Steps S11 and S12 are an example of an acquisition step.

[0098] Next, the determination unit 114 calculates the difference in gradation values ​​for the line based on the maximum, average, and minimum values ​​(S13). The determination unit 114 calculates a first difference by subtracting the average value from the maximum value, and calculates a second difference by subtracting the minimum value from the average value. In step S13, the determination unit 114 calculates the two differences based on the average values.

[0099] Next, the determination unit 114 determines the bit precision after conversion of the video data based on the calculated differences (first difference and second difference) (S14). The determination unit 114 determines the bit precision after conversion based on the maximum difference value, which is the larger of the first difference and the second difference. The determination unit 114 determines, for example, the smallest bit precision among the bit precisions that can express the maximum difference value as the bit precision after conversion.

[0100] The determining unit 114 outputs the determined bit precision after conversion to the conversion processing unit 115. The determining unit 114 may also output the average value acquired from the calculation unit 112 to the conversion processing unit 115. Step S14 is an example of a determining step.

[0101] 12 is a diagram showing an example of bit precision determined by the average value and the maximum difference value according to the present embodiment. Note that "+1" in the bit precision in FIG. 12 indicates the sign bit.

[0102] As shown in FIG. 12, when the average value of the gradation values ​​is 700 and the maximum difference value is 700 (for example, the minimum value is 0), and when the average value of the gradation values ​​is 512 and the maximum difference value is 512 (for example, the minimum value is 0), the determination unit 114 determines that the bit precision after conversion will be 10 bits, that is, that the bit precision will not be converted.

[0103] Furthermore, if the average value of the gradation values ​​is 761 and the maximum difference value is 262 (for example, the maximum value is 1023), the determination unit 114 determines the bit precision after conversion to be 9 bits. Furthermore, if the average value of the gradation values ​​is 861 and the maximum difference value is 162 (for example, the maximum value is 1023), the determination unit 114 determines the bit precision after conversion to be 8 bits. When the bit precision after conversion is 8 bits, it will be less than 10 bits including the sign bit, making it possible to reduce the amount of data.

[0104] Furthermore, if the average value of the gradation values ​​is 996 and the maximum difference value is 27 (for example, the maximum value is 1023), the determination unit 114 determines the bit precision after conversion to be 5 bits. Furthermore, if the average value of the gradation values ​​is 1016 and the maximum difference value is 7 (for example, the maximum value is 1023), the determination unit 114 determines the bit precision after conversion to be 3 bits.

[0105] In this way, the smaller the maximum difference value in one line, the smaller the bit precision determined by the determination unit 114 after conversion. In other words, the smaller the maximum difference value in one line, the more the determination unit 114 determines the bit precision that will result in a greater effect in reducing the amount of data. This makes it possible to significantly reduce the amount of data, i.e., achieve a high compression rate, especially when displaying video that contains many similar gradations, such as natural images.

[0106] 11 again, next, the conversion processing unit 115 converts the video data stored in the pre-processing buffer 111 based on the determined bit precision (S15). The conversion processing unit 115 calculates the difference between the gradation value of each pixel and the average value, and converts the bit precision of the video data by using this difference as the converted gradation value of the pixel. Step S15 is an example of a conversion step.

[0107] Next, the conversion processing unit 115 generates integrated information including the average value, bit precision information, and converted data, and outputs the generated integrated information to the line buffer 130, thereby writing the integrated information to the line buffer 130 (S16). In step S16, the conversion processing unit 115 writes the representative value, bit precision information, and converted data to the line buffer in association with each other. This reduces the time required to access the line buffer 130 for writing, compared to writing the 10-bit video data itself to the line buffer 130. Step S16 is an example of a writing step. The conversion processing unit 115 also functions as a writing unit that writes the average value, second bit precision, and second video data to the line buffer 130 in association with each other.

[0108] The conversion unit 110 may perform the process shown in FIG. 11 for each line, or may perform the process shown in FIG. 11 for each two or more lines. When the process shown in FIG. 11 is performed for each line, the bit precision after conversion can be determined according to the maximum and minimum gradation values ​​for each line, thereby more effectively reducing the amount of data. Furthermore, for example, when the conversion unit 110 performs the process shown in FIG. 11 for each two lines, the maximum, average, and minimum values ​​are obtained from the gradation values ​​of each pixel included in the two lines. This allows only one piece of header information to be added to the converted data for two lines, thereby reducing the amount of data for the header information.

[0109] As described above, the processing is performed in the conversion unit 110, but the power consumed in this processing is sufficiently small compared to the line buffer 130 having a buffer of multiple lines.

[0110] Next, the operation of the restoration unit 140 will be described with reference to Fig. 13. Fig. 13 is a flowchart showing a second example of the operation (restoration method) of the control device 20 according to this embodiment. Fig. 13 shows the processing in the restoration unit 140, and specifically shows a restoration method for restoring first video data from second video data with a second bit precision equal to or less than the first bit precision into which first video data with a first bit precision has been converted. Below, an example in which the representative value is an average value will be described.

[0111] As shown in Fig. 13, the restoration unit 140 reads out the integrated information from the line buffer 130 at a desired timing (S21). The restoration unit 140 reads out the converted data, the bit precision of the converted data (second bit precision), and a representative value. The integrated information read out here includes converted data in which the bit precision of the video data has been converted by the conversion unit 110, and therefore the time required to access the line buffer 130 for reading can be shortened compared to when reading out the 10-bit video data itself. Step S21 is an example of a reading step.

[0112] Next, the dividing unit 141 divides the integrated information into three parts: an average value, bit precision information, and converted data, thereby extracting an average value and bit precision information from the integrated information (S22). The dividing unit 141 outputs the average value to the average value holding unit 143, outputs the bit precision to the bit precision holding unit 144, and outputs the converted data to the post-processing latch 142.

[0113] The bit precision holding unit 144 holds the bit precision and outputs the bit precision to the restoration processing unit 145 at a desired timing.

[0114] Next, the restoration processing unit 145 divides the converted data based on the bit precision acquired from the bit precision storage unit 144 (S23). The restoration processing unit 145 divides the converted data into data corresponding to each pixel. As shown before restoration in FIG. 10, the restoration processing unit 145 divides the converted data into sets of a sign bit and a difference. One set is data corresponding to one pixel. Step S23 is an example of a division step.

[0115] Next, the restoration processing unit 145 restores the video data from the converted data based on the average value (S24). The restoration processing unit 145 restores the original video data (video signal (R, G, B) before conversion) from the converted data based on the data of each pixel divided in step S23 and the average value. Each divided data is a value corresponding to the gradation value and average value of the pixel, and indicates the difference between the gradation value with first-bit precision and the representative value for the pixel. The restoration processing unit 145 restores the original video data by calculating the difference and average value for each pixel. The restoration processing unit 145 restores the gradation value (10 bits) of the pixel by adding or subtracting the difference (4 bits) of the pixel to or from the average value (10 bits). Step S24 is an example of a restoration step.

[0116] In addition, if the converted data includes a sign bit, the restoration processing unit 145 takes the value obtained by adding the difference of the pixel and the average value as the gradation value of the pixel with the first bit precision (10 bits) if the sign bit indicates a positive value, and takes the value obtained by subtracting the difference of the pixel from the average value as the gradation value of the pixel with the first bit precision (10 bits) if the sign bit indicates a negative value.

[0117] Next, the restoration processing unit 145 outputs the restored video data to the subsequent stage (S25). The restoration processing unit 145 outputs the restored video data to the source driving circuit 16 at a desired timing.

[0118] As described above, the processing is performed in the restoration unit 140, but the power consumed in this processing is sufficiently small compared to the line buffer 130 having a buffer of multiple lines.

[0119] [3. Application Examples] An application example of the above conversion method will be described with reference to Figures 14 to 16. Figure 14 is a diagram showing a configuration in which control device 20 according to this embodiment stores video data in an external memory (for example, DRAM (Dynamic Random Access Memory) 230).

[0120] 14, an ASIC (Application Specific Integrated Circuit) 220 and a DRAM 230 are mounted on a substrate 210. The mounting substrate, which is the substrate 210 on which the ASIC 220 and the DRAM 230 are mounted, may be used in any electrical device that processes video signals. The mounting substrate may be used, for example, in a display device such as a television, an imaging device such as a camera, a recording / playback device such as a recorder, or a mobile terminal such as a smartphone.

[0121] The ASIC 220 is an example of a semiconductor integrated circuit (IC: Integrated Circuit) mounted on the substrate 210, and includes a pre-processing buffer 221, a conversion unit 222, a memory control unit 223, a DRAM control unit 224, an input / output unit 225, and a restoration unit 228. In FIG. 14, the pre-processing buffer 221 is illustrated as an external configuration of the conversion unit 222.

[0122] 3, and is a buffer that temporarily stores video signals (R, G, B) for each line received from the outside. The capacity of the pre-processing buffer 221 is smaller than the capacity of the DRAM 230. In other words, the power consumption required for writing and reading to and from the pre-processing buffer 221 is smaller than the power consumption required for writing and reading to and from the DRAM 230.

[0123] 3 except for the pre-processing buffer 111, and performs processing to convert the bit precision of one line of video signals (R, G, B) stored in the pre-processing buffer 221 into bit precision according to the gradation values ​​of the one line of video signals (R, G, B). The processing performed by the conversion unit 222 may be processing shown in FIG.

[0124] The memory control unit 223 controls the integrated information generated by the conversion unit 222. In the example of Fig. 14, the memory control unit 223 instructs the DRAM control unit 224 to write and read the integrated information to and from the DRAM 230.

[0125] The DRAM control unit 224 controls writing and reading of data to and from the DRAM 230. Based on instructions from the memory control unit 223, the DRAM control unit 224 controls writing of integrated information to and reading of integrated information from the DRAM 230.

[0126] The input / output unit 225 is a part that electrically connects the DRAM control unit 224 and the DRAM 230, and is, for example, a connection terminal.

[0127] The restoration unit 228 corresponds to the restoration unit 140 shown in FIG. 3, and performs processing to restore the video signal (R, G, B) for each line received from the outside from the integrated information read out from the DRAM 230.

[0128] The DRAM 230 is an external memory provided outside the ASIC 220, and corresponds to the line buffer 130 shown in Fig. 3. The capacity of the DRAM 230 is larger than that of the pre-processing buffer 221.

[0129] Although the example has been shown in which the functions of the conversion unit 110 and the restoration unit 140 shown in Fig. 3 are realized by the ASIC 220 mounted on one substrate 210, the functions of the conversion unit 110 and the restoration unit 140 shown in Fig. 3 may be realized by separate ASICs. Also, the function of the restoration unit 140 may be realized by a device external to the mounting substrate.

[0130] Fig. 15 is a diagram for explaining power reduction in an application example. Fig. 15 schematically shows the power consumed in writing (writing) and reading (reading) one line of video data in the pre-processing buffer 221, and the power consumed in writing (writing) and reading (reading) in the DRAM 230. The horizontal axis of Fig. 15 represents time, and the vertical axis represents power.

[0131] The dashed-dotted line frame in Fig. 15 indicates the amount of power consumed by a conventional mounting board. The conventional mounting board has a configuration in which the conversion unit 222 is removed from the mounting board shown in Fig. 14. In other words, the dashed-dotted line in Fig. 15 indicates the amount of power consumed when writing and reading one line of video signal (R, G, B) (10 bits) once to the pre-processing buffer 221 and once to the DRAM 230. Note that the amount of power consumed when writing and reading to the pre-processing buffer 221 is the same for both the mounting board shown in Fig. 14 and the conventional mounting board.

[0132] As shown in Fig. 15, in this embodiment, the video signals (R, G, B) are converted in the conversion unit 222, and the integrated information with reduced data volume is written to the DRAM 230, and the integrated information is read from the DRAM 230, thereby shortening the access time to the DRAM 230. This makes it possible to reduce the amount of power consumption by the amount shown in Fig. 15. The amount of power consumption reduction differs depending on the bit precision of the converted data, and increases as the bit precision decreases (i.e., the compression rate increases).

[0133] For example, if the DRAM access time when writing or reading video data with a bit precision of 10 bits to or from the DRAM 230 is 100%, when the bit precision is 9 bits (e.g., when the bit precision of the converted data is 8 bits and the bit precision of the sign bit is 1 bit), the DRAM access time is 90%, when the bit precision is 6 bits (e.g., when the bit precision of the converted data is 5 bits and the bit precision of the sign bit is 1 bit), the DRAM access time is 60%, and when the bit precision is 4 bits (e.g., when the bit precision of the converted data is 3 bits and the bit precision of the sign bit is 1 bit), the DRAM access time is 40%. In other words, when the bit precision is 9 bits, the DRAM access time is reduced by 10%, when the bit precision is 6 bits, the DRAM access time is reduced by 40%, and when the bit precision is 4 bits, the DRAM access time is reduced by 60%. The mounting board of this application example can reduce the amount of power consumption corresponding to the reduction in DRAM access time.

[0134] Another application example of the conversion method will be described with reference to FIG. 16. FIG. 16 is a diagram showing a configuration in which control device 20 according to this embodiment stores video data in an internal memory (for example, SRAM (Static Random Access Memory) 227). Note that components that are the same as or similar to those on the mounting board shown in FIG. 14 are given the same reference numerals, and descriptions thereof will be omitted. As shown in FIG. 16, ASIC 220a has an SRAM control unit 226 and an SRAM 227 in addition to ASIC 220 shown in FIG. 14.

[0135] The memory control unit 223 further instructs the SRAM control unit 226 to write and read the integrated information to and from the SRAM 227 .

[0136] The SRAM control unit 226 controls writing and reading of data to and from the SRAM 227. The SRAM control unit 226 controls writing of integrated information to and reading of integrated information from the SRAM 227 based on instructions from the memory control unit 223.

[0137] The SRAM 227 is an internal memory built into the ASIC 220a, and corresponds to the line buffer 130 shown in Fig. 3. The capacity of the SRAM 227 is larger than that of the pre-processing buffer 221.

[0138] The restoration unit 228 performs a process of restoring the video signal (R, G, B) for each line received from the outside from the integrated information read out from the SRAM 227 or the DRAM 230.

[0139] Writing and reading the integrated information to and from the built-in SRAM 227 in this manner can shorten the access time to the SRAM 227. Furthermore, if the SRAM 227 has a function that allows simultaneous writing and reading, the conversion method of the present disclosure can more effectively reduce the amount of power consumed.

[0140] [4. Effects etc.] As described above, the conversion method according to the present embodiment is a method for converting first video data having a first bit precision and writing the converted data to the line buffer 130 (an example of a memory). The first video data is video data for one or more display lines each including a plurality of pixels arranged side by side. The conversion method includes the following steps: acquiring, based on the first video data, an average value (an example of a representative value), a maximum value, and a minimum value of the gradation values ​​of the plurality of pixels; determining, based on the acquired maximum and minimum values, a second bit precision (S14) that is the bit precision after conversion of the first video data and is equal to or less than the first bit precision; converting, based on the average value and the gradation values ​​of the plurality of pixels, the first video data having the first bit precision into second video data having the determined second bit precision; and writing, based on the average value and the gradation values ​​of the plurality of pixels, the second bit precision, and the corresponding second video data, to the line buffer 130 (S16).

[0141] As a result, the video data to be saved has reduced bit precision, allowing the amount of data to be reduced when saved, thereby shortening the time required to access memory when writing the video data to be saved. Furthermore, since the original video data can be restored using the difference and the representative value, image quality can be maintained. Furthermore, since conversion is performed based on the gradation values ​​of the original video data, conversion can be performed using a simple method without using a special conversion table such as an encoding table. Therefore, the conversion method according to this embodiment makes it possible to reduce power consumption when writing to memory using a simple method while maintaining image quality.

[0142] In addition, in the determination step, a first difference between the maximum value and the average value and a second difference between the average value and the minimum value are calculated, and a second bit precision is determined based on the calculated first difference and second difference.

[0143] This makes it possible to determine the second bit precision after conversion simply by calculating the first difference and the second difference.

[0144] In addition, in the determining step, the bit precision capable of expressing the larger difference between the first difference and the second difference is determined as the second bit precision.

[0145] This makes it possible to eliminate data loss due to conversion, and therefore to reduce power consumption when writing to memory access while maintaining image quality more reliably.

[0146] In the converting step, the difference between the grayscale value of each of the plurality of pixels and the average value is calculated, and the difference between each of the plurality of pixels is used as second video data.

[0147] This makes it possible to obtain the converted data simply by calculating the difference.

[0148] Moreover, the second video data further includes a sign bit indicating whether the difference for each of the plurality of pixels is a positive value or a negative value.

[0149] This makes it possible to more reliably restore the original video data when restoring the video data.

[0150] In the writing step, the average value associated with the second bit precision and the second video data is a grayscale value with the first bit precision.

[0151] This makes it possible to restore video data with the first bit precision using the representative value and the converted data, thereby making it possible to store data that maintains image quality.

[0152] The average value is the average or median value of the gradation values ​​of a plurality of pixels.

[0153] This allows the amount of data to be reduced by using only the frame video data.

[0154] The average value may also be calculated based on the first video data of a plurality of pixels in a past frame.

[0155] This allows a representative value for a series of frames in which the brightness of the displayed image does not change significantly to be calculated in advance.

[0156] As described above, the restoration method according to the present embodiment is a restoration method for restoring first video data from second video data with a second bit precision equal to or less than the first bit precision into which first video data with a first bit precision is converted. The first video data is video data for one or more display lines each including a plurality of pixels arranged side by side, and the second video data, the second bit precision, and a representative value of the gradation values ​​of the plurality of pixels calculated based on the first video data are stored in line buffer 130 (an example of a memory) in association with each other. The restoration method includes a reading step (S21) of reading the second video data, the second bit precision, and an average value (an example of the representative value) from line buffer 130, a dividing step (S23) of dividing the second video data into data corresponding to each of the plurality of pixels based on the second bit precision, and a restoration step (S24) of restoring the second video data to first video data with the first bit precision based on the average value and a value corresponding to the gradation value and average value of the pixel indicated by each divided data.

[0157] As a result, the amount of data in the read integrated information is reduced compared to the original video data, thereby shortening the time required to access memory when reading the data. Furthermore, since the read information includes the difference and the representative value, it is possible to restore the video data to the video data before conversion, thereby maintaining image quality. Therefore, according to the restoration method, it is possible to reduce power consumption when reading from memory in a simple manner while maintaining image quality.

[0158] In addition, each divided data indicates the difference between the gradation value of the first bit precision at the pixel and the average value, and in the restoration step, the first video data is restored by calculating the difference and the average value for each of the multiple pixels.

[0159] This makes it possible to restore the original video data simply by calculating the representative value and the gradation value.

[0160] In addition, the second video data includes a sign bit indicating whether the difference between the gradation value of the pixel in the first video data and the average value is a positive value or a negative value, and in the restoration step, if the sign bit indicates a positive value, the value obtained by adding the difference of the pixel to the average value is used as the gradation value of the pixel with first-bit precision, and if the sign bit indicates a negative value, the value obtained by subtracting the difference of the pixel from the average value is used as the gradation value of the pixel with first-bit precision.

[0161] This allows the video data to be properly restored even if the sign bit is included.

[0162] As described above, the conversion unit 110 (an example of a storage device) according to this embodiment is a conversion device that converts first video data with first bit precision and converts the first video data to be written to the line buffer 130 (an example of a memory). The first video data is video data for one or more display lines each configured with a plurality of pixels lined up. The conversion unit 110 includes an acquisition unit (e.g., a calculation unit 112 and an extraction unit 113) that acquires the average value (an example of a representative value), maximum value, and minimum value of the gradation values ​​of multiple pixels based on the first video data; a determination unit 114 that determines a second bit precision, which is the bit precision after conversion of the first video data, based on the acquired maximum and minimum values, and which is equal to or lower than the first bit precision; a conversion processing unit 115 that converts the first video data of the first bit precision into second video data of the determined second bit precision based on the average value and the gradation values ​​of each of the multiple pixels; and a conversion processing unit 115 (an example of a writing unit) that associates the average value, the second bit precision, and the second video data and writes them to the line buffer 130.

[0163] This provides the same effect as the above conversion method.

[0164] As described above, the restoration unit 140 (an example of a restoration device) according to this embodiment is a restoration device that restores first video data from second video data with a second bit precision equal to or less than the first bit precision into which first video data with a first bit precision is converted. The first video data is video data for one or more display lines each including a plurality of pixels arranged side by side. The second video data, bit precision information indicating the second bit precision, and an average value (an example of a representative value) of the gradation values ​​of the plurality of pixels calculated based on the first video data are stored in association with each other in a memory. The restoration unit 140 includes a division unit 141 (an example of a read unit) that reads the second video data, the bit precision information, and the average value from the memory, a division unit 141 that divides the second video data into data corresponding to each of the plurality of pixels based on the second bit precision, and a restoration processing unit 145 that restores the second video data to first video data with the first bit precision based on the average value and the gradation value of the pixel indicated by each of the divided data.

[0165] This provides the same effect as the restoration method described above.

[0166] (Other embodiments) Although the control device according to one or more aspects has been described above based on each embodiment, the present disclosure is not limited to these embodiments. As long as it does not deviate from the spirit of the present disclosure, various modifications conceivable by a person skilled in the art to the present embodiment and configurations constructed by combining components of different embodiments may also be included in the present disclosure.

[0167] For example, in the above embodiment, an example has been described in which the semiconductor integrated circuit is an ASIC, but this is not limited thereto and other semiconductor integrated circuits having at least one of the functions of a conversion unit and a restoration unit may be used. The semiconductor integrated circuit may be, for example, an FPGA (Field Programmable Gate Array). An FPGA is a programmable semiconductor integrated circuit.

[0168] Furthermore, in the above embodiment, an example has been described in which the determination unit determines the bit precision after conversion based on the table shown in FIG. 6, but the method of determining the bit precision after conversion is not limited to this, and for example, the bit precision after conversion may be calculated by a predetermined calculation using the maximum and minimum values.

[0169] In the above embodiments, each component may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component. Each component may be realized by a program execution unit such as a CPU (Central Processing Unit) or a processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0170] The order in which the steps in the flowchart are executed is merely an example for specifically explaining the present disclosure, and an order other than the above may be used. Also, some of the steps may be executed simultaneously (in parallel) with other steps, or some of the steps may not be executed.

[0171] The division of functional blocks in the block diagram is an example, and multiple functional blocks may be realized as a single functional block, one functional block may be divided into multiple blocks, or some functions may be moved to another functional block.Furthermore, the functions of multiple functional blocks having similar functions may be processed in parallel or in time-sharing by a single piece of hardware or software.

[0172] Furthermore, the control device according to the above embodiments may be realized as a single device (for example, a single IC chip) or may be realized by multiple devices (for example, multiple IC chips). For example, the conversion unit and the restoration unit may be separate devices (a conversion device and a restoration device) that are connected to each other so that they can communicate with each other.

[0173] Furthermore, each component of the control device described in the above embodiments may be implemented as software or, typically, as an LSI, an integrated circuit. These components may be integrated individually on a single chip, or some or all of them may be integrated on a single chip. While LSI is used here, it may also be referred to as an IC, system LSI, super LSI, or ultra LSI depending on the level of integration. Furthermore, the integration method is not limited to LSI; it may also be implemented using dedicated circuits or general-purpose processors. Field-programmable gate arrays (FPGAs), which can be programmed after LSI fabrication, or reconfigurable processors, which allow the connection or settings of circuit cells within an LSI to be reconfigured, may also be used. Furthermore, if an integrated circuit technology that can replace LSI emerges due to advances in semiconductor technology or other derivative technologies, that technology may naturally be used to integrate the components.

[0174] A system LSI is an ultra-multifunctional LSI manufactured by integrating multiple processing units on a single chip, and is specifically a computer system consisting of a microprocessor, ROM (Read Only Memory), RAM (Random Access Memory), etc. Computer programs are stored in the ROM. The system LSI achieves its functions when the microprocessor operates in accordance with the computer program.

[0175] Furthermore, one aspect of the present disclosure may be a computer program that causes a computer to execute each of the characteristic steps included in either the conversion method shown in FIG. 11 or the restoration method shown in FIG.

[0176] Furthermore, for example, the program may be a program to be executed by a computer. Another aspect of the present disclosure may be a computer-readable non-transitory recording medium on which such a program is recorded. For example, such a program may be recorded on a recording medium and distributed or circulated. For example, the distributed program may be installed in a device having another processor, and the program may be executed by the processor, thereby causing the device to perform each of the above processes.

[0177] Furthermore, these general or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a non-transitory recording medium such as a computer-readable CD-ROM, or as any combination of the system, method, integrated circuit, computer program, or recording medium. The program may be pre-stored in the recording medium, or may be supplied to the recording medium via a wide area communication network including the Internet. [Industrial Applicability]

[0178] The present disclosure is particularly useful in technical fields such as television systems, game consoles, and personal computer displays, where high speed and high resolution display are required. [Explanation of symbols]

[0179] 1 Display device 10 Display panel 12 Display section 14 Gate drive circuit 16 Source driver circuit 20 Control device 30 pixel circuit 32 Light-emitting element 33 Drive transistor 34, 36, 37 Switch transistor 35 Select transistor 38 pixel capacity 39EL capacity 40 scan lines 42 Signal line 110, 222 conversion unit 111, 221 Pretreatment buffer 112 Calculation part (acquisition part) 113 Extraction part (acquisition part) 114 Decision Section 115 Conversion processing unit (writing unit) 120 Synchronization control section 130 Line buffer (memory) 140, 228 Restoration Department 141 Division 142 Post-processing latch 143 Average value holding unit 144 bit precision holding section 145 Restoration Processing Unit 150 Duty control section 210 Substrate 220, 220a ASIC 223 Memory control unit 224 DRAM control unit 225 Input / output section 226 SRAM control section 227 SRAM 230 DRAM

Claims

1. A method for converting first video data having a first bit precision and writing the converted first video data into a memory, the method comprising: the first video data is video data for one or more display lines each including a plurality of pixels arranged side by side; an acquisition step of acquiring a representative value, a maximum value, and a minimum value of the grayscale values ​​of the plurality of pixels based on the first video data; a determining step of determining a second bit precision, which is a bit precision after conversion of the first video data, based on the acquired maximum value and the acquired minimum value, the second bit precision being equal to or less than the first bit precision; a conversion step of converting the first video data with the first bit precision into second video data with the determined second bit precision based on the representative value and the gradation values ​​of the plurality of pixels; a writing step of writing the representative value, the second bit precision, and the second video data in association with each other into the memory. How to convert.

2. In the determining step, a first difference between the maximum value and the representative value and a second difference between the representative value and the minimum value are calculated, and the second bit precision is determined based on the calculated first difference and second difference. The conversion method according to claim 1 .

3. In the determining step, a bit precision capable of expressing a larger difference between the first difference and the second difference is determined as the second bit precision. The conversion method according to claim 2 .

4. In the converting step, a difference between the gradation value of each of the plurality of pixels and the representative value is calculated, and the difference of each of the plurality of pixels is used as the second video data. The conversion method according to any one of claims 1 to 3.

5. The second video data further includes a sign bit indicating whether the difference in each of the plurality of pixels is a positive value or a negative value. The conversion method according to claim 4.

6. In the writing step, the representative value associated with the second bit precision and the second video data is a gradation value with the first bit precision. The conversion method according to any one of claims 1 to 5.

7. The representative value is the average value or the median value of the gradation values ​​of the plurality of pixels. The conversion method according to any one of claims 1 to 6.

8. The representative value is calculated based on the first video data of the plurality of pixels in a past frame. The conversion method according to any one of claims 1 to 6.

9. A restoration method for restoring first video data from second video data having a second bit precision equal to or less than the first bit precision, the second video data being converted from the first video data having a first bit precision, the method comprising: the first video data is video data for one or more display lines each including a plurality of pixels arranged side by side; the second video data, the second bit precision, and a representative value of the gradation values ​​of the plurality of pixels calculated based on the first video data are stored in a memory in association with each other; a reading step of reading the second video data, the second bit precision, and the representative value from the memory; a dividing step of dividing the second video data into data corresponding to each of the plurality of pixels based on the second bit precision; and a restoration step of restoring the second video data to the first video data with the first bit precision based on the representative value and a value corresponding to the representative value and the gradation value of the pixel indicated by each divided data. How to restore.

10. each of the divided data indicates a difference between the gradation value with the first bit precision and the representative value for the pixel; In the restoring step, the first video data is restored by calculating the difference and the representative value for each of the plurality of pixels. The restoration method according to claim 9.

11. the second video data includes a sign bit indicating whether a difference between the gradation value of the pixel in the first video data and the representative value is a positive value or a negative value; In the restoration step, if the sign bit indicates a positive value, the value obtained by adding the difference of the pixel and the representative value is set as the gradation value of the pixel with first-bit precision, and if the sign bit indicates a negative value, the value obtained by subtracting the difference of the pixel from the representative value is set as the gradation value of the pixel with first-bit precision. The restoration method according to claim 10.

12. A conversion device that converts first video data having a first bit precision and writes the converted first video data into a memory, comprising: the first video data is video data for one or more display lines each including a plurality of pixels arranged side by side; an acquisition unit that acquires a representative value, a maximum value, and a minimum value of the grayscale values ​​of the plurality of pixels based on the first video data; a determination unit that determines a second bit precision, which is a bit precision after conversion of the first video data, based on the acquired maximum value and the acquired minimum value, and which is equal to or less than the first bit precision; a conversion processing unit that converts the first video data with the first bit precision into second video data with the determined second bit precision based on the representative value and the gradation values ​​of each of the plurality of pixels; a writing unit that writes the representative value, the second bit precision, and the second video data in association with each other into the memory. Conversion device.

13. 1. A restoration device that restores first video data from second video data having a second bit precision equal to or less than the first bit precision into which the first video data having a first bit precision is converted, the restoration device comprising: the first video data is video data for one or more display lines each including a plurality of pixels arranged side by side; the second video data, bit precision information indicating the second bit precision, and a representative value of the gradation values ​​of the plurality of pixels calculated based on the first video data are stored in a memory in association with each other; a reading unit that reads the second video data, the bit precision information, and the representative value from the memory; a division unit that divides the second video data into data corresponding to each of the plurality of pixels based on the second bit precision; a restoration processing unit that restores the second video data to the first video data with the first bit precision based on the gradation value of the pixel indicated by each divided data and the representative value. Restoration device.

Images