Processors and endian conversion methods

Abstract

To provide means to, in a processor having a CPU, a plurality of peripheral circuits, and an endian conversion circuit disposed between the CPU and the plurality of peripheral circuits, prevent a value intended by a creator of software from being interpreted by the peripheral circuits as a value different from the value when the peripheral circuits interpret a write value as a plural-byte value, making creation of the software easy.SOLUTION: An endian conversion circuit has a table showing a relation between addresses and connection destination types. The endian conversion circuit uses type information taken out of the table using the address of an access destination to separately control a data conversion circuit and a byte enable conversion circuit in the endian conversion circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a processor having an endian conversion circuit provided between a CPU and a peripheral circuit, and an endian conversion method. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 8-202646 (Patent Document 1) is a background art in this technical field. This publication describes an endian conversion circuit (converter) for facilitating connection between a CPU (main processor) and a peripheral circuit (I / O device) when the two have different endian formats. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-202646 Summary of the Invention [Problem to be solved by the invention]

[0004] The endian conversion circuit in Patent Document 1 rearranges data when the endian is different between the CPU and the peripheral circuit. For example, when the CPU sends a 4-byte hexadecimal number 00000001 to the peripheral circuit, circuitIf a 4-byte value is written to a 4-byte address, it is converted to 01000000. This is to accommodate the fact that addresses for 4-byte values ​​are assigned differently in little endian and big endian. Specifically, little endian assigns addresses from the lowest byte to the highest byte, while big endian assigns addresses from the highest byte to the lowest byte. Therefore, in order to store the same data at the same address when interpreted in byte units, the order of the data must be reversed. However, if interpreted as a 4-byte value, a different value will be written. If the peripheral circuit interprets the written value as a 4-byte value, it will be interpreted as a value different from the value intended by the software creator. This is not limited to 4 bytes; in general, when a written value is interpreted in units greater than 1 byte, it will be interpreted as a value different from the value intended by the software creator.

[0005] The present disclosure aims to provide a means for facilitating software creation in a processor having a CPU, multiple peripheral circuits, and an endian conversion circuit provided between the CPU and the multiple peripheral circuits, by preventing a written value from being interpreted as a value different from the value intended by the software creator when the peripheral circuit interprets the value as a multi-byte value.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of representative aspects of this disclosure is as follows.

[0008] In order to solve the above problem, in one embodiment of a processor, the endian conversion circuit has a table showing the relationship between addresses and connection destination types, and the processor separately controls the data conversion circuit and byte enable conversion circuit within the endian conversion circuit using type information extracted from the table using the address of the access destination. [Effects of the Invention]

[0009] According to the processor of the above embodiment, when the endianness of the CPU and the peripheral circuitry are different, the byte enable is converted by the byte enable conversion circuit in accordance with the difference in how addresses are assigned to multi-byte data, and the data is converted by the data conversion circuit taking into account how many bytes the peripheral circuitry interprets the numerical values ​​in, thereby enabling the peripheral circuitry to correctly interpret the values ​​intended by the software creator.

[0010] Problems, configurations, and effects other than those described above will become apparent from the following description of the embodiments. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a first example of a configuration diagram of a processor to which the present invention is applied. [Figure 2] 2 is an example of a timing chart of the bus 111 and the bus 114 in FIG. [Figure 3A] 2 is an example of little-endian byte enable operations on bus 111 and bus 114 in FIG. 1. [Figure 3B] 2 is an example of big endian byte enable operations for the bus 111 and the bus 114 in FIG. 1. [Figure 4A] 1. FIG. 4 is a diagram showing a first example of an attribute information table of the control circuit 102 of FIG. [Figure 4B] 1. FIG. 4 is a diagram showing a first example of a control signal generation rule for the control circuit 102 of FIG. [Figure 5] 2 is a first example of the control circuit 102 of FIG. [Figure 6] 2 is an example of the byte enable conversion circuit 104 in FIG. 1. [Figure 7] 2 illustrates an example of the operation of the byte enable conversion circuit 104 of FIG. 1. [Figure 8] 1. This is an example of the data conversion circuit 103 in FIG. [Figure 9] 2 illustrates an example of the operation of the data conversion circuit 103 in FIG. [Figure 10] 1. A first example of the operation of the bus 111 and the bus 114 in FIG. [Figure 11A] 1. FIG. 4 is a diagram showing a second example of the attribute information table of the control circuit 102 of FIG. [Figure 11B] 1. FIG. 4 is a diagram showing a second example of a control signal generation rule for the control circuit 102 of FIG. [Figure 12] 2 is a second example of the operation of the bus 111 and the bus 114 in FIG. [Figure 13] 2 is a second example of the control circuit 102 of FIG. 1. [Figure 14] FIG. 2 is a second example of a configuration diagram of a processor to which the present invention is applied. [Figure 15A] FIG. 15 is a diagram showing an attribute information table of the control circuit 1402 of FIG. [Figure 15B] FIG. 15 is a diagram showing a control signal generation rule of the control circuit 1402 of FIG. [Figure 16] FIG. 10 is a third example of a configuration diagram of a processor to which the present invention is applied. [Figure 17] This is an example of the delay circuit 1601 in FIG. [Figure 18] 17 is an example of a timing chart of the bus 111 and the bus 114 in FIG. 16. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments and examples will be described with reference to the drawings. However, in the following description, the same components will be assigned the same reference numerals, and repeated description may be omitted. Note that the drawings may be more schematic than the actual embodiment to clarify the description, but they are merely examples and do not limit the interpretation of the present invention.

[0013] The processor according to the embodiment has the following configuration.

[0014] That is, the processor (100) has a CPU (101), a plurality of peripheral circuits (105-108), and an endian conversion circuit (109) provided between the CPU (101) and the plurality of peripheral circuits (105-108). The endian conversion circuit (109) has a table (AIT) that stores type information (endian attribute, type attribute) indicating the relationship between an address and a type of connection destination, a byte enable conversion circuit (104), and a data conversion circuit (103). The endian conversion circuit (109) separately controls the byte enable conversion circuit (104) and the data conversion circuit (103) using type information (endian attribute, type attribute) extracted from the table (AIT) using the output address of the access destination output from the CPU (101).

[0015] The endian conversion method according to the embodiment has the following configuration.

[0016] An endian conversion method for a processor (100) having a CPU (101), a plurality of peripheral circuits (105-108), and an endian conversion circuit (109) provided between the CPU (101) and the plurality of peripheral circuits (105-108), the endian conversion circuit (109) having a table (AIT) that stores type information (endian attribute, type attribute) indicating the relationship between an address and a type of connection destination, a byte enable conversion circuit (104), and a data conversion circuit (103), comprising: a) a step of extracting type information (endian attribute, type attribute) from a table (AIT) using an output address of an access destination output from the CPU (101); b) separately controlling the byte enable conversion circuit (104) and the data conversion circuit (103) based on the extracted type information (endian attribute, type attribute).

[0017] According to the processor and endian conversion method of the above embodiment, when the endianness of the CPU and peripheral circuits differ, the byte enable is converted by the byte enable conversion circuit in accordance with the difference in how addresses are assigned to multi-byte data, and the data is converted by the data conversion circuit taking into account how many bytes the peripheral circuits interpret the numerical values ​​in, thereby enabling the peripheral circuits to correctly interpret the values ​​intended by the software creator.

[0018] Hereinafter, the embodiments will be described in detail with reference to the drawings. [Example]

[0019] FIG. 1 is a first example of a configuration diagram of a processor to which the present invention is applied.

[0020] The processor 100 of this embodiment includes a CPU 101, an endian conversion circuit 109, a first peripheral circuit (ROM) 105, a second peripheral circuit (RAM) 106, a third peripheral circuit (first IO circuit) 107, a fourth peripheral circuit (second IO circuit) 108, a first bus (hereinafter referred to as the bus) 111, and a second bus (hereinafter referred to as the bus) 114. The CPU 101 is connected to the bus 111, and the first peripheral circuit (ROM) 105, the second peripheral circuit (RAM) 106, the third peripheral circuit (first IO circuit) 107, and the fourth peripheral circuit (second IO circuit) 108 are connected to the bus 114. The endian conversion circuit 109 is connected between the bus 111 and the bus 114. The ROM is a non-volatile memory such as a read-only memory, and the RAM is a volatile memory such as a random access memory.

[0021] The endian conversion circuit 109 includes a control circuit 102 , a data conversion circuit 103 , and a byte enable conversion circuit 104 .

[0022] The CPU 101 executes the following processing in accordance with a program stored in the first peripheral circuit (ROM) 105. The CPU 101 first receives input information from the third peripheral circuit (first IO circuit: IO1) 107 and the fourth peripheral circuit (second IO circuit: IO2) 108 via buses 114 and 111, performs predetermined processing, and then writes output information to the third peripheral circuit (first IO circuit) 107 and the fourth peripheral circuit (second IO circuit) 108 via the buses 111 and 114. The second peripheral circuit (RAM) 106 is used to save the progress of the processing.

[0023] When the third peripheral circuit (first IO circuit) 107 receives a request to take in input information from the CPU 101 via the buses 111 and 114, it outputs the input information taken in from the signal line 115 to the CPU 101 via the buses 114 and 111. When the third peripheral circuit (first IO circuit) 107 receives a request to write output information from the CPU 101 via the buses 111 and 114, it stores the write value internally and outputs it to the signal line 115.

[0024] The operation of the fourth peripheral circuit (second IO circuit) 108 is similar to the operation of the third peripheral circuit (first IO circuit) 107.

[0025] The control circuit 102 receives information on the access address and access size from the CPU 101 via the bus 111 , generates control signals for the byte enable conversion circuit 104 and the data conversion circuit 103 , and outputs them to signal lines 112 and 113 .

[0026] The byte enable conversion circuit 104 performs a predetermined conversion on the byte enable of the bus 111 in accordance with the control signal (first signal) received from the signal line 112 and outputs the result to the bus 114.

[0027] The data conversion circuit 103 performs a predetermined conversion on the write data on the bus 111 in accordance with the control signal (second signal) received from the signal line 113, and outputs the converted data to the bus 114. The data conversion circuit 103 also performs a predetermined conversion on the read data on the bus 114 in accordance with the control signal received from the signal line 113, and outputs the converted data to the bus 111.

[0028] Fig. 2 is an example of a timing chart of the bus 111 and the bus 114 in Fig. 1. Since the operations of the bus 111 and the bus 114 are similar, the two are not distinguished from each other in the description.

[0029] clk is the clock signal (1 bit), req is the request signal (1 bit), wr is the write signal (1 bit), size[2:0] is the size signal (size information) (3 bits), be[3:0] is the byte enable signal (4 bits), adr[31:2] is the address signal (30 bits), wd[31:0] is the write data (32 bits), rdv is the read data valid signal (1 bit), rd[31:0] is the read data (32 bits). size[2:0] indicates that it is composed of 3-bit signals: size[2], size[1], and size[0], where size[2] is the most significant bit and size[0] is the least significant bit. Similarly, be[3:0] is composed of four bits from be[3] to be[0], adr[31:2] is composed of 30 bits from adr

[31] to adr[2], wd[31:0] is composed of 32 bits from wd

[31] to wd[0], and rd[31:0] is composed of 32 bits from rd

[31] to rd[0]. In all cases, the larger the number in [], the more significant the bit. req, wr, size[2:0], be[3:0], adr[31:2], and wd[31:0] are signals from the CPU 101 to the peripheral circuits 105-108, while rdv and rd[31:0] are signals from the peripheral circuits 105-108 to the CPU 101. Although the address space is 32 bits, since the write and read data are 4 bytes, the lower two bits of the address are not transmitted. Instead, byte enable indicates which byte of the 4 bytes is valid. The operation of byte enable will be described later. The size signal is one of three binary numbers: 001, 010, or 100, which indicate that 1 byte, 2 bytes, or 4 bytes will be transferred (data transfer size), respectively.

[0030] Each of the buses 111 and 114 includes a data bus including 32 data signal lines for transferring data such as wd[31:0] and rd[31:0], and adr[31:2]. etc.An address bus including 30 address signal lines for transferring address signals, and a bus for transferring request signals (req: 1 bit), write signals (wr: 1 bit), size signals (size[2:0]: 3 bits) and byte enable signals (be[3:0]: 4 bits). 9 of and a control bus including four control signal lines.

[0031] The first cycle (cycle=1) is the write data transfer. When writing, req and wr are set to 1, and valid values ​​(sz1, be1, a1, d1) are output to size[2:0], be[3:0], adr[31:2], and wd[31:0], respectively.

[0032] Cycles 3 to 6 are read data transfers. During a read, req is 1 and wr is 0. Also, in the first cycle (cycle 3), valid values ​​(sz2, be2, a2) are output to size[2:0], be[3:0], and adr[31:2]. The number of read cycles is not fixed, and the transfer ends in the cycle when rdv becomes 1. A valid value (d2) is output to rd[31:0] in the cycle when rdv becomes 1. Although omitted in Figures 1 and 2, peripheral circuits 105 to 108 output values ​​for rdv and rd[31:0], respectively. Regarding rdv, the outputs of the four peripheral circuits are ORed on bus 114. Figure 2 shows the state after the OR is taken. Regarding rd[31:0], the output value of the peripheral circuit that output a 1 to rdv on bus 114 is selected. Figure 2 shows the state after selection. If there is no peripheral circuit that outputs 1 to rdv, the value of rd[31:0] is ignored.

[0033] 3A and 3B are examples of byte enable operations of the bus 111 and the bus 114 in FIG. 1. FIG. 3A is an example of little endian byte enable operations of the bus 111 and the bus 114 in FIG. 1. FIG. 3B is an example of big endian byte enable operations of the bus 111 and the bus 114 in FIG. 1. )and The behavior differs depending on whether it is big endian or little endian, so they are listed separately. Little endian can be said to be the first endian, and big endian is the second endian, which is different from the first endian.

[0034] As mentioned above, there are three cases for the size of the data to be transferred: 1 byte, 2 bytes, and 4 bytes.

[0035] When transferring one byte (8 bits) (when the size signal: size[2:0] is 001), there are four possible cases (Figure 3A: be[3:0]: 0001, 0010, 0100, 1000; Figure 3B: be[3:0]: 1000, 0100, 0010, 0001) depending on which of the four bytes the data is output to. (In other words, if bus 111 and bus 114 each include 32 data lines DL31-DL0 as data buses, there are four possible cases depending on which of the data line groups DL31-DL24, DL23-DL16, DL15-DL8, and DL7-DL0 the one-byte data is output to.) In little endian, the address of the lower byte is small and the address of the upper byte is large. On the other hand, in big endian, the address of the lower byte is large and the address of the upper byte is small.

[0036] When transferring 2 bytes (16 bits) (when the size signal: size[2:0] is 010), only addresses that are multiples of 2 are allowed. Therefore, there are two cases depending on whether the data is in the upper 2 bytes or the lower 2 bytes of the 4-byte data (Figure 3A). :be[3:0]:0011,1100, FIG. 3B:1100,0011) (that is, when each of bus 111 and bus 114 includes 32 data lines DL31-DL0 as a data bus, there are two cases depending on which of the data line groups DL31-DL16 and DL15-DL0 the 2-byte data is output to). A 2-byte transfer of address 4n corresponds to the overlapping of 1-byte transfers of addresses 4n and 4n+1, and a 2-byte transfer of address 4n+2 corresponds to the overlapping of 1-byte transfers of addresses 4n+2 and 4n+3.

[0037] When transferring 4 bytes (32 bits) (size signal: size[2:0] is 100), all 4 bytes of data are valid, so all bits of the byte enable are 1 (be[3:0]:1111), and the byte enable value is the same for little endian and big endian.

[0038] Figures 4A and 4B show a first example of the operation of the control circuit 102 of Figure 1. Figure 4A is a diagram showing a first example of an attribute information table AIT of the control circuit 102 of Figure 1. Figure 4B is a diagram showing a first example of a control signal generation rule CSGR of the control circuit 102 of Figure 1.

[0039] The operation of the control circuit 102 is described by the attribute information table AIT and the control signal generation rule CSGR. The attribute information table AIT stores the address range and attribute information of each peripheral circuit.

[0040] The attribute information table AIT is stored in the address (adr[31:2]) of the bus 111 at the lower 2 bits. 0It takes as input the data (a concatenation of the data) and outputs attribute information for the corresponding peripheral circuit. Attribute information can also be described as peripheral circuit type information. There are two types of attribute information: endian and type. Endian is 0 for little endian and 1 for big endian. When type is 0 (first type), it indicates that data is interpreted as a collection of 1 byte of data regardless of the value of the size signal (size[2:0]) on bus 111. When type is 1 (second type), it indicates that data of 2 bytes or more is interpreted as data of the size indicated by the value of the size signal (size[2:0]) on bus 111.

[0041] The control signal generation rule CSGR indicates a rule for generating values ​​to be output to the signal lines 112 and 113, using as input the endian, type, and size signal (size[2:0]) of the bus 111 output from the attribute information table AIT. Although not specified in this table, it is assumed that the endian of the CPU is little endian.

[0042] The value of the control signal on the signal line 112 is 0 (first value) when the endian attribute is 0, and 1 (second value) when it is 1. This indicates that when the endian of the CPU and the peripheral circuit are the same, byte enable conversion is not performed, and when they are different, byte enable conversion is performed.

[0043] The signal line 113 (the value of the control signal) takes on three values: 00 (first value) indicates no data conversion, 01 (second value) indicates conversion in byte units, and 10 (third value) indicates conversion in 2-byte units. Details of the conversion will be described later. The signal line 113 becomes 00 when the endian attribute is 0. This indicates that no data conversion is performed when the endianness of the CPU and peripheral circuits is the same. Furthermore, the signal line 113 always becomes 01 (conversion in byte units) when the endian attribute is 1 and the type attribute is 0. On the other hand, when the endian attribute is 1 and the type attribute is 1, the output value differs depending on the value of the size signal (size[2:0]) of the bus 111. When size[2:0] is 001 (1 byte), the output value is 01 (conversion in 1 byte units), when size[2:0] is 010 (2 bytes), the output value is 10 (conversion in 2 byte units), and when size[2:0] is 100 (4 bytes), the output value is 00 (no conversion).

[0044] FIG. 5 is a first example of the control circuit 102 of FIG.

[0045] The control circuit 102 of this embodiment includes fixed value output circuits 501, 502, 505, 506, and 507, comparison circuits 503 and 504, AND circuits 508, 509, 510, 513, and 514, and OR circuits 511 and 512.

[0046] The fixed value output circuit 501 outputs a fixed value F0000000 in hexadecimal notation to a signal line 521 .

[0047] The fixed value output circuit 502 outputs the hexadecimal fixed value F8000000 to a signal line 522 .

[0048] Comparator circuit 503 compares the address of bus 111 (adr[31:2] with two low-order 0 bits) with the value of signal line 521, and outputs the result to signal line 523. The output value is 0 if the address is smaller than the fixed hexadecimal value F0000000, and 1 if the address is equal to or greater than the fixed value F0000000.

[0049] Comparator circuit 504 compares the address on bus 111 (adr[31:2] with two low-order 0 bits) with the value on signal line 522, and outputs the result to signal line 524. The output value is 0 if the address is smaller than the fixed hexadecimal value F8000000, and 1 if the address is equal to or greater than the fixed value F8000000.

[0050] The fixed value output circuit 505 outputs the fixed binary value 10 to the signal line 525 . The fixed value output circuit 506 outputs a fixed binary value of 11 to a signal line 526 . The fixed value output circuit 507 outputs the fixed binary value 01 to the signal line 527 . When the value of signal line 523 is 0, AND circuit 508 outputs the value of signal line 525 to signal line 528. This corresponds to the first row of the attribute information table AIT in FIG. 4A. AND circuit 508 also outputs 00 to signal line 528 when the value of signal line 523 is 1. In this case, the value of signal line 528 does not affect the output of OR circuit 511.

[0051] AND circuit 509 outputs the value of signal line 526 to signal line 529 when the value of signal line 523 is 1 and the value of signal line 524 is 0. This corresponds to the second row of the attribute information table AIT in FIG. 4A. AND circuit 509 also outputs 00 to signal line 529 when the value of signal line 523 is 0 or the value of signal line 524 is 1. In this case, the value of signal line 529 does not affect the output of OR circuit 511.

[0052] When the value of signal line 524 is 1, AND circuit 510 outputs the value of signal line 527 to signal line 530. This corresponds to the third row of the attribute information table AIT in FIG. 4A. AND circuit 510 also outputs 00 to signal line 530 when the value of signal line 524 is 0. In this case, the value of signal line 530 does not affect the output of OR circuit 511.

[0053] OR circuit 511 takes the OR of the three values ​​on signal lines 528, 529, and 530 and outputs the result to signal line 531. Since two of the three values ​​on signal lines 528, 529, and 530 are 00, the operation of OR circuit 511 essentially selects one of the three values ​​on signal lines 528, 529, and 530. The value output to signal line 531 corresponds to the output of attribute information table AIT in FIG. 4A.

[0054] The value of the endian attribute on the signal line 531 is output to the signal line 112 as is.

[0055] OR circuit 512 outputs 1 to signal line 532 when the type attribute of signal line 531 is 0 or when bit 0 of the size signal (size[2:0]) of bus 111 is 1 (corresponding to 1 byte), and outputs 0 otherwise.

[0056] AND circuit 513 outputs 1 to bit 0 of signal line 113 when the endian attribute of signal line 531 and the value of signal line 532 are both 1. This operation corresponds to the case where 01 is output to signal line 113 in the second and third lines of the control signal generation rule CSGR in Figure 4B. AND circuit 513 also outputs 0 when the endian attribute of signal line 531 or the value of signal line 532 is 0.

[0057] The AND circuit 514 outputs 1 to bit 1 of the signal line 113 when the endian attribute and type attribute of the signal line 531 are both 1 and bit 1 of the size signal (size[2:0]) of the bus 111 is 1 (corresponding to 2 bytes). This operation corresponds to the case where 10 is output to the signal line 113 on the fourth line of the control signal generation rule CSGR in FIG. 4B. The AND circuit 514 also outputs 0 to bit 1 of the signal line 113 when the endian attribute, type attribute of the signal line 531, or bit 1 of the size signal (size[2:0]) of the bus 111 is 0.

[0058] FIG. 6 is an example of the byte enable conversion circuit 104 of FIG.

[0059] The byte enable conversion circuit 104 is made up of selection circuits 601, 602, 603, and 604.

[0060] When the value of the signal line 112 is 0, the selection circuit 601 selects bit 3 (be[3]) of the byte enable signal of the bus 111 and outputs it to bit 3 (be[3]) of the byte enable signal of the bus 114. When the value of the signal line 112 is 1, the selection circuit 601 also selects bit 0 (be[0]) of the byte enable signal of the bus 111 and outputs it to bit 3 (be[3]) of the byte enable signal of the bus 114 as the endian-converted byte enable signal.

[0061] The selection circuits 602, 603, and 604 operate in the same way, selecting the left input when the value of the signal line 112 is 0, and the right input when the value of the signal line 112 is 1, and outputting them as byte enable signals after endian conversion.

[0062] FIG. 7 shows an example of the operation of the byte enable conversion circuit 104 of FIG.

[0063] When the signal line 112 is 0, the byte enable conversion circuit 104 outputs the same value as the input.

[0064] When the signal line 112 is 1, the byte enable conversion circuit 104 outputs the input with the upper and lower digits reversed in order.

[0065] Figure 8 is an example of the data conversion circuit 103 in Figure 1. Data conversion is performed on write data (wd[31:0]) and read data (rd[31:0]), but only the write data conversion circuit is shown in Figure 8. The read data conversion circuit has the same configuration.

[0066] The data conversion circuit 103 comprises selection circuits 801, 802, 803, and 804.

[0067] When the value of the signal line 113 is 00, the selection circuit 801 selects bits 31 to 24 (wd[31:24]) of the write data on the bus 111 and outputs them to bits 31 to 24 (wd[31:24]) of the write data on the bus 114 without endian conversion. When the value of the signal line 113 is 01, the selection circuit 801 also selects bits 7 to 0 (wd[7:0]) of the write data on the bus 111 and outputs them to bits 31 to 24 (wd[31:24]) of the data on the bus 114 as endian-converted data. When the value of the signal line 113 is 10, the selection circuit 801 also selects bits 15 to 8 (wd[15:8]) of the write data on the bus 111 and outputs them to bits 31 to 24 (wd[31:24]) of the write data on the bus 114 as endian-converted data.

[0068] The operation of the selection circuits 802, 803, and 804 is similar; when the value of the signal line 113 is 00, the left input is selected and output; when the value of the signal line 113 is 01, the center input is selected; and when the value of the signal line 113 is 10, the right input is selected and output.

[0069] FIG. 9 shows an example of the operation of the data conversion circuit 103 in FIG.

[0070] When the signal line 113 is 00, the data conversion circuit 103 outputs the same value as the input.

[0071] When the signal line 113 is 01, the data conversion circuit 103 outputs the input in byte (8 bits) units with the upper and lower bits reversed in order.

[0072] When the signal line 113 is 10, the data conversion circuit 103 outputs the data with the upper 16 bits (bits 31 to 16) swapped with the lower 16 bits (bits 15 to 0).

[0073] Fig. 10 shows a first example of the operation of the bus 111 and the bus 114 in Fig. 1. Although Fig. 10 does not show the operation of read data, it is the same as the operation of write data.

[0074] The first peripheral circuit (ROM) 105 and the second peripheral circuit (RAM) 106 interpret write data in byte units regardless of the access size. Therefore, endian conversion is performed so that data at the same address becomes the same byte by byte. For example, when the access size is 4 bytes, the least significant byte (s) of bus 111 is output to the most significant byte of bus 114. This is because the least significant byte of bus 111 corresponds to address 4n, while the most significant byte of bus 114 corresponds to address 4n.

[0075] The third peripheral circuit (first IO circuit) 107 interprets data in units of the same size as the access size. Therefore, endian conversion is performed so that the data order is preserved in units of the access size. For example, if the access size is 2 bytes and the address is 4n, the data is shifted from low to high while preserving the data order (rs). This ensures that the data interpretation by the CPU 101 and the data interpretation by the third peripheral circuit (first IO circuit) 107 are the same.

[0076] Since the fourth peripheral circuit (second IO circuit) 108 has the same endian format as the CPU 101, endian conversion is not performed. [Example]

[0077] Figures 11A and 11B show a second example of the operation of the control circuit 102 of Figure 1. Figure 11A is a diagram showing a second example of the attribute information table of the control circuit 102 of Figure 1. Figure 11B is a diagram showing a second example of the control signal generation rule of the control circuit 102 of Figure 1.

[0078] The difference between the operation of the control circuit 102 in FIGS. 4A and 4B and that in FIGS. 11A and 11B is that a register size output is added to the attribute information table AIT in FIG. 11A, and the output of the control signal generation rule CSGR in FIG. 11B differs depending on the value of the register size attribute. The register size attribute indicates the size of the unit by which the accessed peripheral circuit interprets the write value. As described in the explanation of FIG. 10, in the operation of the control circuit 102 in FIGS. 4A and 4B, when accessing the third peripheral circuit (first IO circuit) 107, data is interpreted in units of the same size as the access size. In such an operation, for example, if the third peripheral circuit (first IO circuit) 107 accesses an address that interprets data in 1-byte units, a problem occurs in that the interpretation differs from that of the CPU 101. To address such problems, the operation of the control circuit 102 in Figures 11A and 11B determines the output of the signal line 113 depending on the register size attribute (how many bytes the data is interpreted in) of the third peripheral circuit (first IO circuit) 107.

[0079] 11A, the area of ​​the third peripheral circuit (first IO circuit) 107 is divided into three, and one byte is output for the register size attribute from addresses F0000000 to F1FFFFFF, two bytes for the register size attribute from addresses F2000000 to F3FFFFFF, and four bytes for the register size attribute from addresses F4000000 to F7FFFFFF. In the first peripheral circuit (ROM) 105, the second peripheral circuit (RAM) 106, and the fourth peripheral circuit (second IO circuit) 107, the value of the register size attribute is ignored by the control signal generation rule of FIG. 11B, so the output value of the register size attribute may be any of one byte, two bytes, and four bytes.

[0080] In the control signal generation rule CSGR of FIG. 11B, the operation when accessing the third peripheral circuit (first IO circuit) 107 is different from that of FIG. 4B. When the register size attribute is 1 byte, the output to the signal line 113 is 01 regardless of the value of the size signal (size[2:0]) of the bus 111. This is the same as FIG. 4B when size[2:0] is 001 (1 byte), but the operation when size[2:0] is 010 (2 bytes) and 100 (4 bytes) is different from that of FIG. 4B. When the register size attribute is 2 bytes, the operation when size[2:0] is 001 (1 byte) and 010 (2 bytes) is the same as FIG. 4B, but the operation when size[2:0] is 100 (4 bytes) is different from that of FIG. 4B, and the output to the signal line 113 is 10. The operation when the register size attribute is 4 bytes is the same as FIG. 4B.

[0081] Figure 12 is a second example of the operation of the bus 111 and the bus 114 in Figure 1. Figure 12 corresponds to a second example of the operation of the control circuit 102 in Figures 11A and 11B. The operations when accessing the first peripheral circuit (ROM) 105, the second peripheral circuit (RAM) 106, and the fourth peripheral circuit (second IO circuit) 108 are the same as those in Figure 10, so they are omitted, and only the operation when accessing the third peripheral circuit (first IO circuit) 107 is described. In Figure 12, size = 1 indicates the operation when the register size attribute is 1 byte, size = 2 indicates the operation when the register size attribute is 2 bytes, and size = 4 indicates the operation when the register size attribute is 4 bytes.

[0082] When the register size attribute is 1 byte, the operation differs from that shown in FIG. 10 when the access size is 2 bytes or 4 bytes. In either case, the same data is output to bytes with the same address in byte units. For example, when the access size is 4 bytes, the least significant byte (s) of bus 111 is output to the most significant byte of bus 114. This is because the least significant byte of bus 111 corresponds to address 4n, while the most significant byte of bus 114 corresponds to address 4n. When the register size attribute is 1 byte, the third peripheral circuit (first IO circuit) 107 interprets data in byte units, and this operation ensures that the CPU 101 and the third peripheral circuit (first IO circuit) 107 interpret data in byte units.

[0083] When the register size attribute is 2 bytes, the operation differs from that shown in Figure 10 when the access size is 4 bytes. The lower two bytes (rs) of bus 111 are output to the upper two bytes of bus 114 while preserving the data order. Because the lower two bytes of bus 111 correspond to addresses 4n and 4n+1, data is shifted to the area of ​​the same address on bus 114, but because the data order is preserved, it is guaranteed that the CPU 101 and the third peripheral circuit (first IO circuit) 107 will interpret the data in the same way. Similarly, the upper two bytes (pq) of bus 111 are output to the lower two bytes of bus 114 while preserving the data order. [Example]

[0084] FIG. 13 shows a second example of the control circuit 102 of FIG.

[0085] The difference between the control circuit 102 in FIG. 5 and the control circuit 102A in FIG. 13 is that the fixed value output circuits 501, 502, 505, 506, and 507 in FIG. 5 are replaced with memory circuits 1301, 1302, 1305, 1306, and 1307, and values ​​can be rewritten from the bus 111.

[0086] When the request signal (req) of the bus 111 is 1, the write signal (wr) is 1, the size signal (size[2:0]) is 100 (4 bytes), and the address signal (adr[31:2]) is a predetermined value, the write control circuit 1311 outputs a write control signal for the memory circuits 1301, 1302, 1305, 1306, and 1307 to one of signal lines 1321, 1322, 1325, 1326, and 1327. The write control signal consists of a write enable and write data, and the write data is output by selecting a portion of the write data (wd[31:0]) of the bus 111.

[0087] 13, it becomes possible to set the contents (stored values) of the attribute information table AIT of Fig. 4A from the CPU 101. That is, it has a function of rewriting the stored values ​​of the table AIT in accordance with a request from the CPU 101, or a process of rewriting the stored values ​​of the table AIT in accordance with a request from the CPU 101. This makes it possible to use the same control circuit 102A even if the configuration of the peripheral circuit changes. [Example]

[0088] FIG. 14 is a second example of a configuration diagram of a processor to which the present invention is applied.

[0089] 1 and the processor 1400 of FIG. 14 differ in that the CPU 1401 supports both little endian and big endian operation and outputs information about the current endian operation to the control circuit 1402 via a signal line 1411. In other words, the CPU 1401 has a function for changing the endian to little endian or big endian. The endian conversion circuit 1409 changes the rules for endian conversion in accordance with the information about the endian of the CPU 1401 received from the signal line 1411. The processor 1400 includes a step of changing the endian of the CPU 1401, a step of transmitting the information about the endian of the CPU 1401 to the signal line 1411 between the CPU 1401 and the endian conversion circuit 1409, and a step of changing the rules for endian conversion of the endian conversion circuit 1409 in accordance with the information about the endian of the CPU 1401 received from the signal line 1411.

[0090] The control circuit 1402 takes into consideration not only the built-in table AIT but also information about the endian of the CPU 1401 taken in from a signal line 1411, and generates signals to be output to signal lines 112 and 113. Details will be described later.

[0091] Figures 15A and 15B show examples of the operation of the control circuit 1402 of Figure 14. Figure 15A is a diagram showing an attribute information table AIT of the control circuit 1402 of Figure 14. Figure 15B is a diagram showing a control signal generation rule CSGR of the control circuit 1402 of Figure 14.

[0092] The attribute information table AIT in FIG. 15A is the same as the attribute information table AIT in FIG. 4A.

[0093] 15B differs from the control signal generation rule CSRG of FIG. 4B in that it takes the value of signal line 1411 into consideration. When the value of signal line 1411 is 0, the operation is the same as that of FIG. 4B. When the value of signal line 1411 is 1 and the endian attribute is 0, the endian of the CPU 1401 and the peripheral circuit are different, so endian conversion of the byte enable is required, and signal line 112 becomes 1. On the other hand, signal line 113 becomes 01 when the type attribute is 0, and becomes 01, 10, 00, or 00 depending on the value of the size signal (size[2:0]) of bus 111 when the type attribute is 1. Note that in the attribute information table AIT of FIG. 15A, there is no case where the endian attribute is 0 and the type attribute is 0, so this case is not shown in FIG. 15B. If the value of the signal line 1411 is 1 and the endian attribute is also 1, the endian of the CPU 1401 and the peripheral circuits are the same, so there is no need to perform endian conversion, and 0 is output to the signal lines 112 and 113 . [Example]

[0094] FIG. 16 is a third example of a configuration diagram of a processor to which the present invention is applied.

[0095] 1 and the processor 1600 of FIG. 16 differ in that the endian conversion circuit 1609 includes a delay circuit 1601. In the processor 100 of FIG. 1, the control circuit 102, the data conversion circuit 103, and the byte enable conversion circuit 104 take time to process, which increases the transfer time from the CPU 101 to the peripheral circuits (105, 106, 107, 108), potentially leading to a decrease in the operating frequency. To address this issue, the present embodiment uses the delay circuit 1601 to divide the transfer from the CPU 101 to the peripheral circuits (105, 106, 107, 108) into two clock cycles, thereby shortening the transfer time per clock cycle and preventing a decrease in the operating frequency. Note that the transfer of read data from the peripheral circuits (105, 106, 107, 108) to the CPU 101 is delayed by one clock cycle or more from the start of the transfer, and because the operation of the control circuit 102 has been completed by that point and the impact of the decrease in operating frequency due to the endian conversion circuit is minor, the transfer of read data is not divided into two clock cycles in this embodiment. However, because the transfer time is lengthened due to the processing time of the data conversion circuit 103, the transfer of read data may also be divided into clock cycles to eliminate this impact.

[0096] When the value received from the signal line 112 is 0, the delay circuit 1601 outputs the byte enable received from the signal line 1611 and the write data received from the signal line 1612 to the bus 114 as is. When the value received from the signal line 112 is 1, the delay circuit 1601 delays the byte enable received from the signal line 1611 and the write data received from the signal line 1612 by one clock cycle and outputs them to the bus 114. The delay circuit 1601 also outputs the read data received from the bus 114 to the signal line 1612 as is. The delay circuit 1601 also outputs the read data valid signal received from the bus 114 to the bus 111 as is. In other words, the endian conversion circuit 1609 has a function or step of delaying the byte enable and data by one clock cycle using the delay circuit 1601 when endian conversion is required.

[0097] FIG. 17 is an example of the delay circuit 1601 in FIG.

[0098] The delay circuit 1601 is made up of memory circuits 1701, 1702, 1703, and 1705, AND circuits 1704, 1709, 1710, and 1711, selection circuits 1706, 1707, and 1708, and an OR circuit 1712.

[0099] The memory circuit 1701 delays the byte enable signal received from the signal line 1611 by one clock cycle and outputs it to the signal line 1721 .

[0100] The memory circuit 1702 delays the write data (wd[31:0]) received from the signal line 1612 by one clock cycle and outputs it to a signal line 1722 .

[0101] The memory circuit 1703 outputs the write signal (wr), size signal (size[2:0]), and address signal (adr[31:2]) received from the bus 111 to a signal line 1723 with a delay of one clock cycle.

[0102] The AND circuit 1704 takes an AND of the byte enable conversion valid signal received from the signal line 112 and the request signal (req) received from the bus 111 and outputs the AND to a signal line 1724 .

[0103] The memory circuit 1705 outputs the state of the signal line 1724 to a signal line 1725 with a delay of one clock cycle.

[0104] When the value of signal line 1725 is 1, selection circuit 1706 outputs the value of signal line 1721 as the byte enable signal (be[3:0]) of bus 114. When the value of signal line 1725 is 0, selection circuit 1706 also outputs the byte enable signal (be[3:0]) of bus 111 as the byte enable signal (be[3:0]) of bus 114.

[0105] When the value of signal line 1725 is 1, selection circuit 1707 outputs the value of signal line 1722 as write data (wd[31:0]) on bus 114. When the value of signal line 1725 is 0, selection circuit 1707 also outputs the write data (wd[31:0]) on bus 111 as write data (wd[31:0]) on bus 114.

[0106] When the value of signal line 1725 is 1, selection circuit 1708 outputs the value of signal line 1723 as the write signal (wr), size signal (size[2:0]), and address signal (adr[31:2]) of bus 114. When the value of signal line 1725 is 0, selection circuit 1708 also outputs the write signal (wr), size signal (size[2:0]), and address signal (adr[31:2]) of bus 111 as the write signal (wr), size signal (size[2:0]), and address signal (adr[31:2]) of bus 114.

[0107] The AND circuit 1709 takes an AND of the write signal (wr) on the signal line 1723 and the value of the signal line 1725 and outputs it to a signal line 1729 .

[0108] An AND circuit 1710 takes the inverted value of the signal line 1725 and the value of the signal line 1724, and outputs the result to a signal line 1730. As a result, the signal line 1730 becomes 1 for only one cycle when the signal line 1724 rises.

[0109] The AND circuit 1711 takes the inverted value of the signal line 1730 and the AND of the request signal (req) on the bus 111 and outputs it to the signal line 1731. As a result, the signal on the signal line 1731 becomes a signal that delays the rising edge of the request signal (req) on the bus 111 by one cycle only when the signal line 112 is 1.

[0110] An OR circuit 1712 takes an OR of the value of a signal line 1729 and the value of a signal line 1731 and outputs the OR as a request signal (req) on the bus 114 .

[0111] FIG. 18 is an example of a timing chart of the bus 111 and the bus 114 in FIG.

[0112] In the first cycle (cycle=1), write data is transferred on the bus 111. Since the signal line 112 is 1, the same write data is transferred on the bus 114. is the second cycle will be held.

[0113] In the third to seventh cycles, read data transfer is performed on bus 111. Because signal line 112 is 1, the start of the same read data transfer on bus 114 is delayed to the fourth cycle, but the data transfer ends in the seventh cycle, the same as on bus 111. This is because the delay circuit 1601 in Fig. 17 has circuits that delay the request signal (req), write signal (wr), size signal (size[2:0]), byte enable signal (be[3:0]), and address signal (adr[31:2]) by one cycle, but does not have circuits that delay the read data valid signal (rdv) and read data (rd[31:0]) by one cycle.

[0114] The invention made by the inventor has been specifically described above based on examples, but it goes without saying that the present invention is not limited to the above-described embodiments and examples, and various modifications are possible. [Explanation of symbols]

[0115] 100: Processor 101:CPU 103: Data conversion circuit 104: Byte enable conversion circuit 105: First peripheral circuit (ROM) 106: Second peripheral circuit (RAM) 107: Third peripheral circuit (first IO circuit: IO1) 108: Fourth peripheral circuit (second IO circuit: IO2) 109: Endian conversion circuit 501, 502, 505, 506, 507: Fixed value output circuit (corresponding to a table showing the relationship between addresses and connection types) 1301, 1302, 1305, 1306, 1307: Memory circuits (corresponding to a table showing the relationship between addresses and connection types) 1311: Write control circuit 1400: Processor 1401:CPU 1409: Endian conversion circuit 1411: Signal line that transmits CPU endian information 1600: Processor 1601: Delay circuit 1609: Endian conversion circuit

Claims

1. A CPU and a plurality of peripheral circuits; an endian conversion circuit provided between the CPU and the plurality of peripheral circuits; the endian conversion circuit has a table storing type information indicating the relationship between an address and a type of connection destination, a byte enable conversion circuit, and a data conversion circuit; the endian conversion circuit separately controls the byte enable conversion circuit and the data conversion circuit using the type information retrieved from the table using the output address of the access destination output from the CPU; the data conversion circuit is capable of not performing endian conversion of the data or performing endian conversion of the data based on the type information; the byte enable conversion circuit is provided to convert a byte enable signal indicating which bytes of the data are valid, and is capable of not converting the byte enable signal or converting the byte enable signal in accordance with the endian conversion of the data based on the type information; the endian conversion circuit has a delay circuit that delays the byte enable signal and the data by one clock cycle when endian conversion is required; A processor characterized by:

2. 10. The processor of claim 1, The table further includes size information regarding the size at which the destination interprets the data; the endian conversion circuit separately controls the byte enable conversion circuit and the data conversion circuit using the type information and the size information extracted from the table; A processor characterized by:

3. 10. The processor of claim 1, the endian conversion circuit has a function of rewriting the stored values ​​of the table in accordance with a request from the CPU; A processor characterized by:

4. 10. The processor of claim 1, The CPU has a function of changing the endian, a signal line for transmitting information about the endian of the CPU between the CPU and the endian conversion circuit; the endian conversion circuit changes the rules of endian conversion in accordance with the information about the endian of the CPU received from the signal line; A processor characterized by:

5. A CPU and a plurality of peripheral circuits; an endian conversion circuit provided between the CPU and the plurality of peripheral circuits; the endian conversion circuit has a table storing type information indicating the relationship between an address and a type of connection destination, a byte enable conversion circuit, and a data conversion circuit; the endian conversion circuit separately controls the byte enable conversion circuit and the data conversion circuit using the type information retrieved from the table using the output address of the access destination output from the CPU; the data conversion circuit is capable of not performing endian conversion of the data or performing endian conversion of the data based on the type information; the byte enable conversion circuit is provided to convert a byte enable signal indicating which bytes of the data are valid, and is capable of not converting the byte enable signal or converting the byte enable signal in accordance with the endian conversion of the data based on the type information; The first bus and a second bus; the CPU is connected to the first bus and outputs, to the first bus, one byte or multiple bytes of first endian data, an address signal of an access destination, a size signal indicating the size of the data, and the byte enable signal indicating which bytes of the data are valid; the plurality of peripheral circuits are connected to the second bus; the endian conversion circuit is provided between the first bus and the second bus, The plurality of peripheral circuits include: a memory that interprets data in a second endian format different from the first endian format on a byte-by-byte basis; a first IO circuit that interprets the second endian data for each data size indicated by the value of the size signal; a second IO circuit that interprets the data in the first endian format as data of a size indicated by the value of the size signal; The table is the type information of the memory includes an address range of the memory, an endian attribute indicating the second endian, and a type attribute indicating a first type for interpreting data byte by byte regardless of the value of the size signal; With respect to the first IO circuit, an address range of the first IO circuit, and the type information of the first IO circuit includes an endian attribute indicating the second endian and a type attribute indicating a second type to be interpreted for each data of a size indicated by a value of the size signal, With respect to the second IO circuit, an address range of the second IO circuit, and the type information of the second IO circuit includes an endian attribute indicating the first endian and a type attribute indicating the second type, The endian conversion circuit generates a first signal that controls the byte enable conversion circuit and a second signal that controls the data conversion circuit based on the endian attribute, the type attribute, and the size signal output from the table using the address signal of the access destination output from the CPU.

6. 6. The processor of claim 5, the first signal is set to a first value when the endian attribute indicates the first endian, and the byte enable signal is output to the second bus without performing endian conversion using the byte enable conversion circuit; the first signal is set to a second value when the endian attribute indicates the second endian, and the processor performs endian conversion of the byte enable signal using the byte enable conversion circuit and outputs the converted byte enable signal to the second bus.

7. 6. The processor of claim 5, The second signal is a) when the endian attribute indicates the first endian, a first value is set, and the data is output to the second bus without performing endian conversion using the data conversion circuit; b) if the endian attribute indicates the second endian and the type attribute is the first type, a second value is set, and the data is output to the second bus without performing endian conversion using the data conversion circuit; c) when the endian attribute indicates the second endian and the type attribute is the second type, c1) when the size signal indicates 1 byte, the second value is set, endian conversion of the data is performed using the data conversion circuit, and the converted data is output to the second bus; c2) when the size signal indicates 2 bytes, a third value is set, and endian conversion of the data is performed using the data conversion circuit, and the converted data is output to the second bus; c3) When the size signal indicates 4 bytes, the first value is set, and the data is output to the second bus without endian conversion using the data conversion circuit.

8. 1. An endian conversion method for a processor having a CPU, a plurality of peripheral circuits, and an endian conversion circuit provided between the CPU and the plurality of peripheral circuits, the endian conversion circuit having a table storing type information indicating a relationship between an address and a type of a connection destination, a byte enable conversion circuit, and a data conversion circuit, a) extracting the type information from the table using an output address of an access destination output from the CPU; b) separately controlling the byte enable conversion circuit and the data conversion circuit based on the extracted type information; the data conversion circuit is capable of not performing endian conversion of the data or performing endian conversion of the data based on the type information; the byte enable conversion circuit is provided to convert a byte enable signal indicating which bytes of the data are valid, and is capable of not converting the byte enable signal or converting the byte enable signal in accordance with the endian conversion of the data based on the type information; The endian conversion method further comprises a step of delaying the byte enable and data by one clock cycle using a delay circuit when endian conversion is required.

9. 9. The endian conversion method according to claim 8, The table further includes size information regarding the size at which the destination interprets the data; The step a) includes a step of retrieving the size information from the table; In the step b), the byte enable conversion circuit and the data conversion circuit are controlled separately based on the type information and the size information.

10. 9. The endian conversion method according to claim 8, an endian conversion method comprising the step of rewriting the stored values ​​of the table in the endian conversion circuit in accordance with a request from the CPU;

11. 9. The endian conversion method according to claim 8, changing the endian of the CPU; transmitting information about the endian of the CPU to a signal line between the CPU and the endian conversion circuit; and changing the rules of endian conversion of the endian conversion circuit in accordance with information about the endian of the CPU received from the signal line.

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