Data input device and input data processing method

Abstract

A data input device capable of high-speed transmission and a method for processing input data are provided. [Solution] The detection circuit is connected to the input circuit and the training circuit and is used to set a second delay setting based on the first delay setting and the clock cycle of the first clock signal, the second delay setting including a second data delay amount and a second clock delay amount; the data delay line is connected to the input circuit and the detection circuit and outputs a second data signal based on the first data signal and the second data delay amount; and the clock delay line is connected to the input circuit and the detection circuit and outputs a second clock signal based on the first clock signal and the second clock delay amount.

Description

[Technical Field]

[0001] The present invention relates to a data input device and a method for processing input data, and more particularly to a data input device and a method for processing input data that are capable of high-speed transmission. [Background technology]

[0002] Circuits such as memory circuits typically use a clock signal as a timing reference for their operations. Summary of the Invention [Problem to be solved by the invention]

[0003] However, the phase of the clock signal may shift due to changes in temperature, voltage, etc., which may result in an increase in the error rate of the memory circuit when sampling input data. [Means for solving the problem]

[0004] In view of the above problems, the present invention has the following configuration. That is, in a data input device including an input circuit, a training circuit, a detection circuit, a data delay line, and a clock delay line, the input circuit is adapted to receive a first data signal and a first clock signal; the training circuit is connected to the input circuit and is used to set a first delay setting based on the first data signal and the first clock signal, the first delay setting including a first data delay amount and a first clock delay amount; the detection circuit is connected to the input circuit and the training circuit, and is used to set a second delay setting based on the first delay setting and a clock cycle of the first clock signal, the second delay setting including a second data delay amount and a second clock delay amount; the data delay line is connected to the input circuit and the detection circuit, and outputs a second data signal based on the first data signal and the second data delay amount; The clock delay line is connected to the input circuit and the detection circuit, and outputs a second clock signal based on the first clock signal and the second clock delay amount.

[0005] Additionally, the clock cycle includes a plurality of delay unit time grids, and the detection circuit sets the second delay setting based on the first delay setting and the number of the plurality of delay unit time grids included in the clock cycle.

[0006] Furthermore, when the setting of the first delay setting is completed, the detection circuit detects the number of the delay unit time grids included in the clock cycle at that time and records it as a first number, and also detects the number of the delay unit time grids included in the clock cycle in real time thereafter.When the detection circuit determines that the number of the delay unit time grids included in the clock cycle is different from the first number, the detection circuit sets the recorded and detected number of the delay unit time grids included in the clock cycle as a second number, and also sets the second delay setting based on the first delay setting, the first number, and the second number.

[0007] Further, each of the first data delay amount, the first clock delay amount, the second data delay amount, and the second clock delay amount includes a plurality of the delay unit time grids; The detection circuit adjusts the number of the plurality of delay unit time grids of the first data delay amount based on the first number and the second number to obtain the second data delay amount, and the detection circuit adjusts the number of the plurality of delay unit time grids of the first clock delay amount based on the first number and the second number to obtain the second clock delay amount.

[0008] and the detection circuit adjusts the number of the plurality of delay unit time grids of the first data delay amount to obtain the second data delay amount based on a ratio between the second number and the first number; The detection circuit adjusts the number of the plurality of delay unit time grids of the first clock delay amount based on a ratio between the second number and the first number to obtain the second clock delay amount.

[0009] Further, the detection circuit multiplies the number of the plurality of delay unit time grids of the first data delay amount by a ratio between the second number and the first number to obtain the second data delay amount, and the detection circuit multiplies the number of the plurality of delay unit time grids of the first clock delay amount by a ratio between the second number and the first number to obtain the second clock delay amount.

[0010] Also, the delay unit time grid corresponds to a delay unit, and the delay unit is a buffer.

[0011] Also, a first data signal and a first clock signal are received; setting a first delay setting based on the first data signal and the first clock signal, the first delay setting including a first data delay amount and a first clock delay amount; setting a second delay setting based on the first delay setting and a clock cycle of the first clock signal, the second delay setting including a second data delay amount and a second clock delay amount; outputting a second data signal based on the first data signal and the second data delay amount; A second clock signal is output based on the first clock signal and the second clock delay amount.

[0012] Also, the clock cycle includes a plurality of delay unit time grids, and setting the second delay setting based on the first delay setting and the clock cycle of the first clock signal includes: setting the second delay setting based on the first delay setting and the number of the plurality of delay unit time grids included in the clock cycle.

[0013] Further, the step of setting the second delay setting based on the first delay setting and the clock cycle of the first clock signal includes: When the setting of the first delay setting is completed, the number of the plurality of delay unit time grids included in the clock cycle at that time is detected and recorded as a first number; At the same time, the number of the plurality of delay unit time grids included in the clock cycle is detected in real time thereafter; When the number of the plurality of delay unit time grids included in the clock cycle is different from the first number, the number of the plurality of delay unit time grids included in the recorded and detected clock cycle is set to a second number; Setting the second delay setting based on the first delay setting, the first number, and the second number.

[0014] Further, each of the first data delay amount, the first clock delay amount, the second data delay amount, and the second clock delay amount includes a plurality of the delay unit time grids; setting the second delay setting based on the first delay setting, the first number, and the second number, adjusting a number of the plurality of delay unit time grids of the first data delay amount according to the first number and the second number to obtain the second data delay amount; and adjusting the number of the plurality of delay unit time grids of the first clock delay amount based on the first number and the second number to obtain the second clock delay amount.

[0015] Further, the step of setting the second delay setting based on the first delay setting, the first number, and the second number includes: adjusting the number of the plurality of delay unit time grids of the first data delay amount according to a ratio between the second number and the first number to obtain the second data delay amount; and adjusting the number of the plurality of delay unit time grids of the first clock delay amount based on a ratio of the second number to the first number to obtain the second clock delay amount.

[0016] Further, the step of setting the second delay setting based on the first delay setting, the first number, and the second number includes: multiplying the number of the plurality of delay unit time grids of the first data delay amount by a ratio of the second number to the first number to obtain the second data delay amount; Multiplying the number of the plurality of delay unit time grids of the first clock delay amount by a ratio of the second number to the first number to obtain the second clock delay amount.

[0017] Also, the delay unit time grid corresponds to a delay unit, and the delay unit is a buffer. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a schematic diagram of an embodiment of a data input device and output circuit. [Figure 2] 1 is a flowchart illustrating an embodiment of a method for processing input data according to the present invention. [Figure 3A] 10 is a schematic diagram of an embodiment when an output circuit outputs a first data signal and a first clock signal. FIG. [Figure 3B] 2 is a schematic diagram of an embodiment when an input circuit receives a first data signal and a first clock signal. [Figure 4A] FIG. 1 is a schematic diagram of an embodiment of a training process of a training circuit. [Figure 4B] FIG. 1 is a schematic diagram of an embodiment of a training process of a training circuit. [Figure 4C] FIG. 1 is a schematic diagram of an embodiment of a training process of a training circuit. [Figure 5]4 is a schematic diagram of an embodiment of a first data signal and a first clock signal after a training process and after being affected by temperature and voltage. [Figure 6] FIG. 2 is a schematic diagram of an embodiment of a clock cycle. [Figure 7] 10 is a flowchart of an embodiment of step S03. DETAILED DESCRIPTION OF THE INVENTION

[0019] The detailed features and advantages of the present application will be described in detail in the following embodiments, and the contents thereof are sufficient for those skilled in the art to understand and practice the technical contents of the present application. Based on the contents described in the specification, patent scope, and drawings of the present application, those skilled in the art can easily understand the objectives and advantages associated with the present application.

[0020] An embodiment of the present invention will be described with reference to Figure 1. A data input device 1 includes an input circuit 10, a training circuit 11, a detection circuit 12, a data delay line 13, and a clock delay line 14.

[0021] The training circuit 11 is connected to the input circuit 10, the detection circuit 12, the data delay line 13, and the clock delay line 14. The detection circuit 12 is connected to the input circuit 10, the training circuit 11, the data delay line 13, and the clock delay line 14.

[0022] In some embodiments, the data input device 1 may be applied to a transmission interface. For example, the data input device 1 may be applied to any transmission interface, including, but not limited to, a memory transmission interface such as a dynamic random access memory (DRAM) or a die-to-die transmission interface. The data input device 1 may also be realized in the form of a chip through an integrated circuit manufacturing process.

[0023] Next, a description will be given with reference to Figures 1 and 2. Here, Figure 2 is a flowchart illustrating an embodiment of a method for processing input data according to the present invention. An input circuit 10 is used to receive a first data signal D1 and a first clock signal CK from an output circuit 2 (step S01). A description will be given with reference to Figure 3A. Here, Figure 3A is a schematic diagram of an embodiment when the output circuit outputs the first data signal and the first clock signal. In some embodiments, the first data signal D1 includes a plurality of data.

[0024] For convenience of explanation, in Fig. 3A, the first data signal D1 includes only three pieces of data: data D01, data D11, and data D21, but the number of pieces of data included in the first data signal D1 is not limited to these.

[0025] In this embodiment, when the first data signal D1 and the first clock signal CK are output from the output circuit 2, the positive edge and / or negative edge of the first clock signal CK coincides (is located, hits) with the center position of each data included in the first data signal D1.

[0026] FIG. 3A shows an embodiment in which the positive edge of the first clock signal CK coincides with the center position of each data included in the first data signal D1.

[0027] Referring to Figure 3B, which is a schematic diagram of an embodiment when an input circuit receives a first data signal D1 and a first clock signal CK, in some embodiments, when the input circuit 10 receives the first data signal D1 and the first clock signal CK, a skew T1 occurs between the first data signal D1 and the first clock signal CK.

[0028] The skew T1 prevents the positive edge of the first clock signal CK from hitting the exact center of each data point in the first data signal D1. In the embodiment of Figure 3B, the skew T1 causes the first data signal D1 to be faster than the first clock signal CK, causing the first positive edge of the first clock signal CK to hit data point D11 instead of data point D01 as expected.

[0029] In some embodiments, the output circuit 2 may be a memory circuit, or in some embodiments, the output circuit 2 may be a volatile storage medium, a non-volatile storage medium, or a combination thereof.

[0030] The volatile storage medium is, for example, a random access memory such as a random access memory (RAM), a static random access memory (SRAM), or a dynamic random access memory (DRAM).

[0031] The nonvolatile storage medium may be a ROM, a programmable read-only memory (PROM), an EPROM, an EEPROM, a one-time PROM (OTPROM), or a flash memory. Here, the type of the output circuit 2 is not limited.

[0032] In some embodiments, the first clock signal CK may be a global clock generated by a clock source (such as, but not limited to, an oscillator) or may be delayed through a clock tree, although the present application is not limited thereto.

[0033] In various embodiments, the transmission speed of the first data signal D1 and the first clock signal CK may be, but is not limited to, 16 Gbps or 32 Gbps.

[0034] In this embodiment, the skew T1 is caused by the physical metal lines between the output circuit 2 and the input circuit 10.

[0035] In several embodiments, the training circuit 11 is used to perform a training process to set a first delay setting A (step S02) based on the first data signal D1 and the first clock signal CK to correct the skew T1.

[0036] The first delay setting A includes a first data delay amount A1 and a first clock delay amount A2. Please refer to Figures 4A to 4C, where Figures 4A to 4C are schematic diagrams of embodiments of the training process of the training circuit, respectively.

[0037] In some embodiments, in the training process of the training circuit 11, as shown in FIG. 4C , in order to make the positive edge or negative edge of the first clock signal CK hit the center position of the current data D01 of the first data signal D1, taking the positive edge of the first clock signal CK as an example, the data input device 1 can use the training circuit 11 to detect the relationship between the first data signal D1 and the first clock signal CK, and set the first data delay amount A1 and the first clock delay amount A2 accordingly.

[0038] Among these, the data pattern of the first data signal D1 input to the training process is known to the training circuit 11.

[0039] For example, if the data pattern of the first data signal D1 is "010" and the current data D01 is "1", the relationship between the first data signal D1 and the first clock signal CK can be shown in FIG. 4A.

[0040] First, the training circuit 11 may first adjust the left index G1 and the right index G2 to the boundary of the current data D01.

[0041] Among these, the training circuit 11 can determine whether the current data D01 has been adjusted to the left boundary based on whether the data sampled at the left index G1 is "0" or not, and also determines whether the current data D01 has been adjusted to the right boundary based on whether the data sampled at the right index G2 is "0" or not.

[0042] After the left index G1 and the right index G2 are respectively adjusted to the boundaries of the current data D01, as shown in FIG. 4B, the training circuit 11 can obtain the data width of the current data D01 based on the distance between the left index G1 and the right index G2, and can determine the center position of the current data D01 based on the data width.

[0043] Thereafter, the training circuit 11 sets the first data delay amount A1 and the first clock delay amount A2 based on the determined center position, thereby completing the training process of the data input device 1.

[0044] 4(c), the training circuit 11 increases the delay amount (first data delay amount A1) of the first data signal D1. In some embodiments, the initial values ​​of the first data delay amount A1 and the first clock delay amount A2 are both 0 seconds (s).

[0045] In FIG. 3B and FIGS. 4A to 4C, the first data signal D1 is faster than the skew T1 of the first clock signal CK, but the present invention is not limited to this.

[0046] In some embodiments, the skew T1 may cause the first clock signal CK to be faster than the first data signal D1.

[0047] In several embodiments, if the skew T1 causes the first clock signal CK to be faster than the first data signal D1, the training circuit 11 increases the delay of the first clock signal CK (i.e., the first clock delay A2).

[0048] By executing the training process through the training circuit 11, the training circuit 11 can know the time length of the skew T1, and at the same time, the first data delay amount A1 or the first clock delay amount A2 increases according to the time length of the skew T1.

[0049] For example, if the time length of the skew T1 shown in FIG. 3B is 200 picoseconds (ps), then the first data signal D1 is faster than the first clock signal CK, and therefore when the training circuit 11 executes the training process, the training circuit 11 sets the first data delay amount A1 to 200 ps.

[0050] In several embodiments, after the training circuit 11 acquires the first delay setting A, the training circuit 11 transmits a first data delay amount A1 to the data delay line 13 and transmits a first clock delay amount A2 to the clock delay line 14.

[0051] The data delay line 13 outputs the first data signal D1 after increasing the delay amount based on the first data delay amount A1 to a data processing unit (not shown) based on the first data signal D1 and the first data delay amount A1.

[0052] The clock delay line 14 outputs the first clock signal CK to the data processing unit after increasing the delay amount in accordance with the first clock delay amount A2 based on the first clock signal CK and the first clock delay amount A2.

[0053] At this time, the positive edge and / or negative edge of the first clock signal CK output by the clock delay line 14 strikes exactly at the center position of each data included in the first data signal D1 output by the data delay line 13.

[0054] However, in several embodiments, during operation of the data input device 1, after the skew T1 is corrected by the training circuit 11, the generated first clock signal CK and the first clock signal CK may generate a new skew T2 due to the influence of fluctuations in temperature, voltage, etc.

[0055] Next, reference will be made to Fig. 5, which is a schematic diagram of an embodiment of the first data signal and the first clock signal after a training process and after being affected by temperature and voltage. When skew T2 exists, the positive edge of the first clock signal CK corrected by skew T1 does not correctly coincide with the center position of each data included in the first data signal D1 corrected by skew T1.

[0056] 5, the skew T2 causes the first clock signal CK after correcting the skew T1 to be faster than the first data signal D1 after correcting the skew T1, so that the positive edge of the first clock signal CK after correcting the skew T1 cannot correctly arrive at the expected data.

[0057] In other words, the first data delay amount A1 and the first clock delay amount A2 set by the training circuit 11 at this time to correct the skew T1 cannot cope with the influence caused by the skew T2.

[0058] In several embodiments, the detection circuit 12 is used to set a second delay setting B (step S03) based on the first delay setting A and the clock cycle T of the first clock signal CK to correct the skew T2.

[0059] The second delay setting B includes a second data delay amount B1 and a second clock delay amount B2, see Figure 6, which is a schematic diagram of an embodiment of a clock cycle.

[0060] In this embodiment, the clock cycle T includes a plurality of delay unit time grids d, and the detection circuit 12 is used to set the second delay setting B based on the first delay setting A and the number of delay unit time grids d included in the clock cycle T.

[0061] In some embodiments, the delay unit time grid d corresponds to a delay unit.

[0062] The number of delay unit time grids d included in a clock cycle T represents the time required for a signal to pass through a number of delay units, where the time length of the clock cycle T corresponds to the number of delay unit time grids d included in the clock cycle T.

[0063] For example, assume that the number of delay unit time grids d included in a clock cycle T is 100. The length of the clock cycle T is the time required for a signal to pass through 100 delay units. In some embodiments, the delay units are buffers.

[0064] 7 will be described next. In some embodiments, when the detection circuit 12 executes step S03, the detection circuit 12 first detects the number of delay unit time grids d included in the clock cycle T at that time when the first delay setting A in the training circuit 11 is completed, and records this as a first number (step S031). Then, the number of delay unit time grids d included in the clock cycle T is detected in real time.

[0065] When the detection circuit 12 detects that the number of delay unit time grids d included in the clock cycle T is different from the first number, the detection circuit 12 records that the number of delay unit time grids d included in the detected clock cycle T is a second number (step S032).

[0066] Next, the detection circuit 12 sets the second delay setting B based on the first delay setting A, the first number, and the second number (step S033).

[0067] For example, assuming that the training circuit 11 has completed the first delay setting A, the number of delay unit time grids d included in the clock cycle T is 100, and the detection circuit 12 detects and records 100 as the first numerical value. After recording 100 as the first number, the detection circuit 12 detects the number of delay unit time grids d included in the clock cycle T in real time.

[0068] When the detection circuit 12 detects that the number of delay unit time grids d included in the clock cycle T is 80, since 80 is different from the first number (i.e., 100), the detection circuit 12 records that the detected 80 is the second number.

[0069] Then, the detection circuit 12 sets the second delay setting B based on the first delay setting A, the first number (ie, 100), and the second number (ie, 80).

[0070] The number of delay unit time grids d included in the clock cycle T varies depending on the time (i.e., the values ​​of the first number and the second number are different) because the delay units are affected by fluctuations in temperature, voltage, etc.

[0071] For example, suppose the first number is 100 and the second number is 80, this means that the length of a clock cycle T will vary from the time it takes for a signal to pass through 100 delay units to the time it takes for a signal to pass through 80 delay units.

[0072] In other words, this increases the time required for a signal to pass through a single delay unit, and the reason it takes longer to pass through a single delay unit is because the delay unit is affected by changes in temperature, voltage, etc.

[0073] In this case, if the length of the clock cycle T is 200 ps, ​​since the time length of the clock cycle T is fixed, the time required for a signal to pass through a single delay unit is 2 ps (200 ps / 100 = 2 ps) when the number of multiple delay unit time grids d included in the clock cycle T is a first number, and the time required for a signal to pass through a single delay unit is 2.5 ps (200 ps / 80 = 2.5 ps) when the number of multiple delay unit time grids d included in the clock cycle T is a second number.

[0074] In some embodiments, the first data delay amount A1, the first clock delay amount A2, the second data delay amount B1, and the second clock delay amount B2 also include a plurality of delay unit time grids d.

[0075] Similarly, the number of delay unit time grids d included in the first data delay amount A1, the first clock delay amount A2, the second data delay amount B1, and the second clock delay amount B2 indicates that the time lengths of the first data delay amount A1, the first clock delay amount A2, the second data delay amount B1, and the second clock delay amount B2 are the time required for a signal to pass through a number of delay units corresponding to the number of delay unit time grids d included in the first data delay amount A1, the first clock delay amount A2, the second data delay amount B1, and the second clock delay amount B2.

[0076] In several embodiments, the training circuit 11 sets the first data delay amount A1 and the first clock delay amount A2 by setting the number of delay unit time grids d included in the first data delay amount A1 and the first clock delay amount A2.

[0077] 3B as an example, if the time length of the skew T1 shown in FIG. 3B is 200 ps, ​​then the first data signal D1 is faster than the first clock signal CK. Therefore, if the time required for the signal to pass through one delay unit after the training circuit 11 executes the training process is 2 ps, the training circuit 11 sets the number of delay unit time grids d included in the first data delay amount A1 to 100. Therefore, the time length of the first data delay amount A1 is 200 ps.

[0078] In particular, when the delay unit is affected by fluctuations in temperature, voltage, etc., the time required for a signal to pass through a single delay unit changes, and the skew generated by the number of multiple delay unit time grids d included in the first data delay amount A1 and the first clock delay amount A2 set by the training circuit 11 becomes skew T2.

[0079] As in the above example, when the delay unit is affected by fluctuations in temperature, voltage, etc., and the time required for a signal to pass through a single delay unit increases from 2 ps to 2.5 ps, the number of delay unit time grids d included in the first data delay amount A1 is 100. Therefore, the time length of the first data delay amount A1 becomes 250 ps (2.5 ps × 100 = 250 ps) instead of the originally planned 200 ps. As a result, the first data signal D1 corrected with the skew T1 is delayed too much, and the first clock signal CK corrected with the skew T1 is 50 ps faster than the first data signal D1 corrected with the skew T1. Here, the difference of 50 ps caused by changes in temperature, voltage, etc. is the skew T2.

[0080] In some embodiments, when the detection circuit 12 performs step S033, the detection circuit 12 adjusts the number of delay unit time grids d of the first data delay amount A1 based on the first number and the second number to obtain the second data delay amount B1.

[0081] Then, the detection circuit 12 adjusts the number of delay unit time grids d of the first clock delay amount A2 based on the first number and the second number to obtain the second clock delay amount B2.

[0082] For example, when the first number is 100, the second number is 80, the time length of the clock cycle T is 200 ps, ​​and the number of delay unit time grids d in the first data delay amount A1 is 100, the time required for a signal to pass through one delay unit increases from 2 ps (200 ps / 100 = 2 ps) to 2.5 ps (200 ps / 80 = 2.5 ps). Therefore, if the number of delay unit time grids d included in the first data delay amount A1 is 100, the length of the first data delay amount A1 will be 250 ps (2.5 ps x 100 = 250 ps) instead of the originally planned 200 ps.

[0083] Therefore, in order to maintain the time length of the delay amount at 200 ps, ​​the detection circuit 12 adjusts the number of delay unit time grids d of the first data delay amount A1 to 80, and to maintain a delay of 200 ps (2.5 ps x 80 = 200), the first data delay amount A1 containing 80 delay unit time grids d is the second data delay amount B1.

[0084] In some embodiments, when the detection circuit 12 performs step S033, the detection circuit 12 adjusts the number of delay unit time grids d of the first data delay amount A1 based on the ratio between the second number and the first number to obtain the second data delay amount B1.

[0085] Then, the detection circuit 12 adjusts the number of delay unit time grids d of the first clock delay amount A2 based on the ratio between the second number and the first number to obtain the second clock delay amount B2.

[0086] In some embodiments, the detection circuit 12 obtains the second data delay amount B1 by multiplying the number of the plurality of delay unit time grids d of the first data delay amount A1 by the ratio between the second number and the first number.

[0087] Then, the detection circuit 12 multiplies the number of the plurality of delay unit time grids d of the first clock delay amount A2 by the ratio between the second number and the first number to obtain the second clock delay amount B2.

[0088] For example, if the first number is 100, the second number is 80, and the number of delay unit time grids d included in the first data delay amount A1 is 100, the detection circuit 12 multiplies the number of delay unit time grids d included in the first data delay amount A1 (i.e., 100) by the ratio of the second number to the first number (i.e., 0.8) based on the ratio between the second number and the first number (i.e., 80 / 100=0.8) to obtain a second data delay amount B1 in which the number of delay unit time grids d included is 80 (100×0.8=80).

[0089] In FIG. 5, the skew T2 causes the first data signal D1 after correcting the skew T1 to be excessively delayed, so that the first clock signal CK after correcting with the skew T1 is faster than the first data signal D1 after correcting with the skew T1, but the present invention is not limited to this.

[0090] In some embodiments, the skew T2 may cause the first clock signal CK to be excessively delayed after correcting for the skew T1, and the first data signal D1 after correcting for the skew T1 is faster than the first clock signal CK after correcting for the skew T1.

[0091] In some embodiments, the data delay line 13 is used to output a second data signal D2 that is provided to a data processing unit (not shown) based on the first data signal D1 and the second data delay amount B1 (step S04).

[0092] The clock delay line 14 is used to output a second clock signal CK2 to be supplied to the data processing unit based on the first clock signal CK and the second clock delay amount B2 (step S05).

[0093] At this time, the positive edge and / or negative edge of the second clock signal CK2 output from the clock delay line 14 hits the center position of each data included in the second data signal D2 output from the data delay line 13 accurately.

[0094] In short, the data input device 1 of the present invention can execute any of the input data processing methods of the embodiments for the first data signal D1 and the first clock signal CK, and the positive edge and / or negative edge of the second clock signal CK2 can coincide with the center position of each data contained in the second data signal D2.

[0095] Furthermore, even if there is skew T2 due to changes in temperature, voltage, etc., the data input device 1 that executes the input data processing method of this embodiment can correct the skew T2 again without interrupting data transmission, thereby achieving high-speed data transmission.

[0096] As described above, the technical content of the present application has been described by showing preferred embodiments. However, these embodiments are not intended to limit the technical scope of the present application, and any slight changes or modifications made by those skilled in the art without departing from the spirit of the present application should be interpreted as being included in the technical scope, and the technical scope of the present application is determined based on the claims. [Explanation of symbols]

[0097] 1. Data input device 2 Output circuit 10 Input circuit 11 Training Circuit 12 Detection circuit 13 Data Delay Line 14 Clock Delay Line A First Delay Setting B Second delay setting A1 First data delay amount A2 First clock delay amount B1 Second data delay amount B2 Second clock delay D1 First data signal CK First clock signal D2 Second data signal CK2 Second clock signal Steps S01 to S05, S031 to S033 D01, D11, D21 data T1, T2 skew G1, G2 indicators T clock cycles d delay unit time grid

Claims

1. A data input device including an input circuit, a training circuit, a detection circuit, a data delay line, and a clock delay line, the input circuit is adapted to receive a first data signal and a first clock signal; the training circuit is connected to the input circuit and is used to set a first delay setting based on the first data signal and the first clock signal, the first delay setting including a first data delay amount and a first clock delay amount; the detection circuit is connected to the input circuit and the training circuit and is used to set a second delay setting based on the first delay setting and a clock cycle of the first clock signal, the second delay setting including a second data delay amount and a second clock delay amount; the data delay line is connected to the input circuit and the detection circuit, and outputs a second data signal based on the first data signal and the second data delay amount; the clock delay line is connected to the input circuit and the detection circuit, and outputs a second clock signal based on the first clock signal and the second clock delay amount; the clock cycle includes a plurality of delay unit time grids, and the detection circuit sets the second delay setting based on the first delay setting and the number of the plurality of delay unit time grids included in the clock cycle; When the setting of the first delay setting is completed, the detection circuit detects the number of the plurality of delay unit time grids included in the clock cycle at that time and records it as a first number, and also detects the number of the plurality of delay unit time grids included in the clock cycle in real time thereafter, and when the detection circuit determines that the number of the plurality of delay unit time grids included in the clock cycle is different from the first number, the detection circuit sets the recorded and detected number of the plurality of delay unit time grids included in the clock cycle as a second number, and also sets the second delay setting based on the first delay setting, the first number, and the second number.

2. 2. The data input device of claim 1, wherein the first data delay amount, the first clock delay amount, the second data delay amount, and the second clock delay amount each include a plurality of the delay unit time grids, and the detection circuit adjusts the number of the plurality of delay unit time grids of the first data delay amount based on the first number and the second number to obtain the second data delay amount, and the detection circuit adjusts the number of the plurality of delay unit time grids of the first clock delay amount based on the first number and the second number to obtain the second clock delay amount.

3. 3. The data input device of claim 2, wherein the detection circuit adjusts the number of the plurality of delay unit time grids of the first data delay amount to obtain the second data delay amount based on the ratio between the second number and the first number, and the detection circuit adjusts the number of the plurality of delay unit time grids of the first clock delay amount based on the ratio between the second number and the first number to obtain the second clock delay amount.

4. 4. The data input device of claim 3, wherein the detection circuit multiplies the number of the plurality of delay unit time grids of the first data delay amount by a ratio of the second number to the first number to obtain the second data delay amount, and the detection circuit multiplies the number of the plurality of delay unit time grids of the first clock delay amount by a ratio of the second number to the first number to obtain the second clock delay amount.

5. 5. The data input device of claim 4, wherein the delay unit time grid corresponds to a delay unit, the delay unit being a buffer.

6. receiving a first data signal and a first clock signal; setting a first delay setting based on the first data signal and the first clock signal, the first delay setting including a first data delay amount and a first clock delay amount; setting a second delay setting based on the first delay setting and a clock cycle of the first clock signal, the second delay setting including a second data delay amount and a second clock delay amount; outputting a second data signal based on the first data signal and the second data delay amount; outputting a second clock signal based on the first clock signal and the second clock delay amount; the clock cycle includes a plurality of delay unit time grids, and setting the second delay setting based on the first delay setting and the clock cycle of the first clock signal comprises: setting the second delay setting based on the first delay setting and the number of the plurality of delay unit time grids included in the clock cycle; When the setting of the first delay setting is completed, the number of the plurality of delay unit time grids included in the clock cycle at that time is detected and recorded as a first number, and at the same time, the number of the plurality of delay unit time grids included in the clock cycle thereafter is detected in real time; When the number of the plurality of delay unit time grids included in the clock cycle is different from the first number, the number of the plurality of delay unit time grids included in the recorded and detected clock cycle is set to a second number; A method of processing input data comprising: setting the second delay setting based on the first delay setting, the first number, and the second number.

7. each of the first data delay amount, the first clock delay amount, the second data delay amount, and the second clock delay amount includes a plurality of the delay unit time grids; setting the second delay setting based on the first delay setting, the first number, and the second number, adjusting a number of the plurality of delay unit time grids of the first data delay amount based on the first number and the second number to obtain the second data delay amount; 7. The method for processing input data according to claim 6, further comprising adjusting a number of the plurality of delay unit time grids of the first clock delay amount based on the first number and the second number to obtain the second clock delay amount.

8. setting the second delay setting based on the first delay setting, the first number, and the second number, adjusting a number of the plurality of delay unit time grids of the first data delay amount based on a ratio of the second number to the first number to obtain the second data delay amount; 8. The method for processing input data according to claim 7, further comprising adjusting a number of the plurality of delay unit time grids of the first clock delay amount based on a ratio between the second number and the first number to obtain the second clock delay amount.

9. setting the second delay setting based on the first delay setting, the first number, and the second number, multiplying the number of the plurality of delay unit time grids of the first data delay amount by a ratio of the second number to the first number to obtain the second data delay amount; 9. The method for processing input data according to claim 8, further comprising multiplying the number of the plurality of delay unit time grids of the first clock delay by a ratio of the second number to the first number to obtain the second clock delay.

10. 10. The method of claim 9, wherein the delay unit time grid corresponds to a delay unit, the delay unit being a buffer.

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