DDR5 Client PMIC Power-Up Sequence and State Transition

Abstract

To provide an apparatus for implementing double data-rate fifth generation (DDR5) client power management integrated circuit (PMIC) power up sequence and state transitions.SOLUTION: A power management integrated circuit (PMIC) 100 includes multiple registers 102a to 102n, and a host interface being one or more of multiple pins pin1 to pin28. One 102i of the multiple registers may be a power state entry register configured to control entry to a low power state. One of the multiple pins may be an enable pin VR_EN27. The PMIC enters the low power state in response to setting the power state entry register to a first value and providing the enable pin with a signal at a first level. The PMIC exits the low power state in response to providing the enable pin with the signal at a second level, and enters an idle state after exiting the low power state.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates generally to computer memories, and more particularly to a method and / or apparatus for implementing a DDR5 client PMIC power-up sequence and state transitions. [Background technology]

[0002] Consumers are seeking to reduce the power consumption of computing devices. As computing devices become more portable, power consumption becomes increasingly important to ensure long battery life. In particular, portable computing devices such as laptops, notebooks, and netbook computers face pressing current demands in certain situations. Each component of a computing device needs to be optimized to reduce power consumption.

[0003] DDR5 SODIMM / UDIMM implements different power states to minimize power consumption. A power state (or P-state) is a voltage-frequency pair that sets the speed and power consumption of a component. Lower operating voltages will result in lower power consumption. Generally, operating in a higher P-state will result in lower power consumption.

[0004] A power management integrated circuit (PMIC) can control the power state of a DDR5 SODIMM / UDIMM. However, to keep the package size of the power management integrated circuit small, the number of available pins is limited. DDR5 client PMICs and SODIMM / UDIMMs have only one pin to control the power state. Conventional PMICs for DDR5 client PMICs and SODIMM / UDIMMs do not allow seamless transitions from specific power states (i.e., P1 and P3a states) without requiring additional pins.

[0005] It would be desirable to implement a DDR5 client PMIC power-up sequence and state transitions. Summary of the Invention

[0006] The present invention relates to an apparatus including a plurality of registers and a host interface having a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry into a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing a signal of a first level to the enable pin. The apparatus may be configured to exit the low power state in response to providing a signal of a second level to the enable pin. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control the state of a plurality of regulators. [Brief explanation of the drawings]

[0007] Embodiments of the present invention will become apparent from the following detailed description and the accompanying claims and drawings. [Figure 1] FIG. 1 illustrates an exemplary embodiment of an unbuffered memory module. [Figure 2] FIG. 2 is a block diagram illustrating the memory module of FIG. [Figure 3] FIG. 3 illustrates an exemplary embodiment of a buffered memory module. [Figure 4] FIG. 4 is a block diagram illustrating the memory module of FIG. [Figure 5] FIG. 5 is a diagram showing the pin layout of the power management integrated circuit. [Figure 6] FIG. 6 is a diagram illustrating an I2C / I3C bus between a host memory controller and a memory module. [Figure 7] FIG. 7 is a state diagram illustrating entry into and exit from a quiescent power state. [Figure 8] FIG. 8 is a timing diagram showing the power-up sequence when the VR_EN pin is high after the VIN_Bulk ramp and there is no bus command. [Figure 9] FIG. 9 is a timing diagram showing the power-up sequence when the VR_EN pin is high and there is no bus command before the VIN_Bulk ramp. [Figure 10] FIG. 10 is a timing diagram showing the power-up sequence when the VR_EN pin is high during the VIN_Bulk ramp and there is no bus command. [Figure 11] FIG. 11 is a timing diagram showing the power-up sequence of a PMIC with bus commands. [Figure 12] FIG. 12 is a timing diagram illustrating the power-down sequence when the VR_EN pin is high with the low power status register at a low value in the program mode of operation. [Figure 13] FIG. 13 is a timing diagram illustrating the power-down sequence when the VR_EN pin is low with the low power status register at a low value in the program mode of operation. [Figure 14] FIG. 14 is a timing diagram illustrating the power-down sequence when the VR_EN pin is high with the low power status register at a high value in the program mode of operation. [Figure 15] FIG. 15 is a timing diagram illustrating the power-down sequence when the VR_EN pin is low with the low power status register at a high value in the program mode of operation. [Figure 16] FIG. 16 is a timing diagram showing the power-down sequence when the VR_EN pin is high with the low power state register at a low value in the secure mode of operation. [Figure 17] FIG. 17 is a timing diagram illustrating a disable or enable command on the bus during a secure mode of operation. [Figure 18] FIG. 18 is a timing diagram showing the power-down sequence when the VR_EN pin is high and the low power status register is at a high or low value in the secure mode of operation. [Figure 19] FIG. 19 is a timing diagram showing the power down sequence using the VR_EN pin with the low power state register at a high value in the secure mode of operation. DETAILED DESCRIPTION OF THE INVENTION

[0008] Embodiments of the present invention include providing a DDR5 client PMIC power-up sequence and state transition that can (i) seamlessly transition from a low-power P1 state to an idle P3a state, (ii) utilize existing pins for the PMIC circuitry, (iii) use the VR_EN pin and registers to control entry into and exit from low-power states, (iv) support secure and programmable modes of operation, (v) support only a bidirectional PWR_GR_OOD pin or an output-only PWR_GOOD pin, (vi) support a VR disable command with a VR_EN pin or a VR disable command on the I2C / I3C bus, (vii) be implemented as part of a DDR5 unbuffered memory module, (viii) be implemented as a buffered memory module, (ix) be implemented as part of a registered double data rate fifth generation memory module, and / or (x) be implemented as one or more integrated circuits.

[0009] Embodiments of the present invention may be configured to be implemented in double data rate fifth generation (DDR5) random access memory (RAM) modules. Low-power hardware and / or hardware for mobile devices may have a limited power budget. Power states (e.g., P-states) may be implemented to limit power consumption under certain operating conditions. Embodiments of the present invention may be configured to control the power states (e.g., entry and exit) of DDR5 memory and operate according to the strict current requirements of the various P-states.

[0010] Embodiments of the present invention may be configured to enable seamless transitions from the P1 state to the P3a state. Transitions between P states can reduce power consumption (e.g., to help meet the power requirements of a notebook computer). In one example, a quiescent power state (e.g., P-state P1) can have a current requirement of approximately 25 uA, and an idle state (e.g., P-state P3a) can have a current requirement of approximately 100 uA. Embodiments of the present invention may be configured to utilize existing pins (e.g., pins that already have existing functionality) to transition between the P1 and P3a states. Reusing pins can ensure that the present invention meets package size requirements and / or can reduce layout complexity. Only one pin (e.g., the VR_EN pin) may be available to control the power state. For example, the VR_EN pin or a VR enable command on the I2C / I3C bus can be used to turn on an output rail.

[0011] In one example, embodiments of the present invention may be implemented in an unbuffered dual in-line memory module (UDIMM). For example, in the case of a notebook computer, embodiments of the present invention may be implemented in a small outline dual in-line memory module (SODIMM). In one example, a DDR5 SODIMM may have one pin (e.g., VR_EN) for controlling the power state. In another example, embodiments of the present invention may be implemented in a registered dual in-line memory module (RDIMM). The type of memory module implemented may vary according to the design criteria of a particular implementation.

[0012] Embodiments of the present invention may be configured to support secure and / or programmable modes of operation. The present invention may support bidirectional operation on a pin (e.g., PWR_GOOD) and / or output-only operation on the PWR_GOOD pin. The present invention may also be configured to support a VR disable command using the VR_EN pin and / or a VR disable command on the I2C / I3C bus.

[0013] Referring to FIG. 1, a diagram illustrating an exemplary embodiment of an unbuffered memory module is shown. In various embodiments, a memory system includes several circuits 50a-50n. The circuits 50a-50n may be implemented as memory modules (or boards). In one example, the circuits 50a-50n may be implemented as dual in-line memory modules (DIMMs). In some embodiments, the circuits 50a-50n may be implemented as double data rate fifth generation (DDR5) SDRAM modules.

[0014] In various embodiments, circuits 50a-50n may include several blocks (or circuits) 72a-72n, block (or circuit) 100, and / or various other blocks, circuits, pins, connectors, and / or traces. Circuits 72a-72n may implement memory devices. In one example, circuits 72a-72n may be implemented as synchronous dynamic random access memory (SDRAM) devices (or chips, or modules). Circuit 100 may be implemented as a power management integrated circuit (PMIC). In one example, PMIC 100 may conform to the JEDEC DDR5 specification. The type, arrangement, and / or number of components of memory modules 50a-50n may be varied to meet the design criteria of a particular implementation.

[0015] The memory modules 50a-50n are shown connected to a block (or circuit) 20. The circuit 20 may implement a memory controller (e.g., a host controller). The circuit 20 may be located within another device, such as a computing engine. Various connectors (or pins or traces) 60 may be implemented to connect the memory modules 50a-50n to the memory controller 20. In some embodiments, the connectors (or pins or traces) 60 may have a 288-pin configuration. In one example, the memory controller 20 may be a component of a computer motherboard (or mainboard). In another example, the memory controller 20 may be a component of a microprocessor. In yet another example, the memory controller 20 may be a component of a central processing unit (CPU).

[0016] In one example, some of the connectors (or pins or traces) 60 may be part of the memory modules 50a-50n, and some of the connectors (or pins or traces) 60 may be part of the motherboard and / or memory controller 20. The memory modules 50a-50n may be connected to a computer motherboard (e.g., by pins, traces, and / or connectors 60) to transfer data between components of the computer device and the memory modules 50a-50n. In some embodiments implementing UDIMMs, the connectors (or pins or traces) 60 may implement a 64-bit bus or a 72-bit bus. In one example, the memory controller 20 may be implemented on a northbridge of a motherboard and / or as a component of a microprocessor (e.g., an Intel CPU, an AMD CPU, an ARM CPU, etc.). The implementation of the memory controller 20 may vary according to the design criteria of a particular implementation.

[0017] In various embodiments, the circuits 50a-50n may be implemented as DDR5 SDRAM memory modules. In one example, the circuits 50a-50n may have a memory module density of 128 gigabytes (GB), 512 GB, 1 terabyte (TB), or more per module. In embodiments implementing DDR5 standard SDRAM memory modules, the circuits 50a-50n may operate at frequencies between 1.2 and 3.2 gigahertz (GHz) and / or higher.

[0018] In an embodiment implementing DDR5 standard SDRAM memory modules, circuits 50a-50n may have a data rate range of 3.2 GT / s to 4.6 GT / s. In an exemplary embodiment implementing DDR5 SDRAM memory modules, circuits 50a-50n may operate at up to 8 GT / s. The operating parameters of memory modules 50a-50n may vary according to the design criteria of a particular implementation.

[0019] In one example, memory modules 50a-50n may be implemented in accordance with the fifth generation (DDR5) standard (e.g., a standard currently under development by JEDEC). References to the DDR5 standard may refer to the latest working and / or draft version of the DDR5 specification published by JEDEC or distributed to committee members as of March 2019. All appropriate sections of the DDR5 standard are incorporated herein by reference. JEDEC specifications may refer to DDR5 SDRAM specifications and / or specifications for future generations of DDR SDRAM (e.g., DDR6).

[0020] Referring to FIG. 2, a block diagram illustrating memory module 50a of FIG. 1 is shown. Memory module 50a may be representative of memory modules 50b-50n. Memory module 50a is shown in communication with memory controller 20. Memory controller 20 is shown as part of block (or circuit) 10. Circuit 10 may be a motherboard (or mainboard) or other electronic component or computing engine or host device that communicates with memory module 50a.

[0021] Memory module 50a may include one or more blocks (or circuits) 80a-80n and / or PMIC 100. Circuits 80a-80n may implement data paths for memory module 50a. In the illustrated example, memory module 50a may include five data paths (e.g., 80a-80e) on one side of memory module 50a and four data paths (e.g., 80k-80n) on the other side of memory module 50a. Circuits 82a-82n may each be implemented as a memory channel. Memory channels 82a-82n may each include multiple blocks (or circuits) 84a-84n. Circuits 84a-84n may be implemented as random access memory (RAM) chips. For example, RAM chips 84a-84n may implement volatile memory such as dynamic RAM (DRAM). The RAM chips 84a-84n may be SDRAM devices 72a-72n (e.g., the chips 84a-84n may comprise one or more circuits 72a-72n disposed within one of the memory channels 82a-82n). In some embodiments, the RAM chips 84a-84n may be physically located on both sides (e.g., the front and back) of the circuit board of the memory modules 50a-50n. The amount of memory on the memory module 50a may vary according to the design criteria of a particular implementation.

[0022] The memory controller 20 may generate a clock signal (e.g., CLK), a number of control signals (e.g., ADDR / CMD), and / or a number of commands. The signal CLK and / or the signal ADDR / CMD may be provided to the memory channels 82a-82n. In one example, the signals ADDR / CMD and CLK may be transmitted on the common bus 52 and the common bus 54, respectively. Commands may be provided to the PMIC 100 via a bus 90. A data bus 30 may be connected between the memory controller 20 and the data paths 80a-80n. The bus 30 may include traces, pins, and / or connections between the memory controller 20 and the memory channels 82a-82n. The memory controller 20 may generate and / or receive data signals (e.g., DQa-DQn) and data strobe signals (e.g., DQSa-DQSn) that may be provided / received from the data bus 30. Portions of signals DQa-DQn and DQSa-DQSn may be provided to respective data paths 80a-80n. For example, signals DQa-DQn may be DQ signals defined in the JEDEC specification, and signals DQSa-DQSn may be DQS signals defined in the JEDEC specification. In the illustrated example, signals DQa-DQn may each have a corresponding signal DQSa-DQSn, although in some embodiments, one DQS signal may strobe multiple (e.g., four) DQ signals.

[0023] Bus 90 may be implemented as a host interface bus. Host interface bus 90 may be bidirectional. Host interface bus 90 may be configured to communicate commands and / or other data to other components of PMIC 100 and / or memory module 50a. In some embodiments, host interface bus 90 may implement the I2C protocol. In some embodiments, host interface bus 90 may implement the I3C protocol. The protocol implemented by host interface bus 90 may vary according to the design criteria of a particular implementation.

[0024] Referring to Figure 3, a diagram illustrating an exemplary embodiment of a buffered memory module is shown. The buffered memory module shown in connection with Figure 3 may have a similar implementation to the unbuffered memory module shown in connection with Figure 1.

[0025] In various embodiments, circuits 50a-50n may include SDRAM devices 72a-72n, PMIC 100, multiple blocks (or circuits) 70a-70n, block (or circuit) 74, and / or various other blocks, circuits, pins, connectors, and / or traces. Circuits 70a-70n may be implemented as data buffers. Circuit 74 may be implemented as a registered clock driver (RCD). In another example, RCD circuit 74 may be implemented as an RCD circuit that complies with JEDEC specifications (e.g., the DDR5 standard). For example, in an embodiment implementing circuits 50a-50n as DDR5-compliant SDRAM modules, memory modules 50a-50n may include circuits 72a-72n arranged in columns of ten SDRAM devices (or chips, or modules), circuits 70a-70n may be arranged in columns corresponding to circuits 72a-72n, RCD circuit 74 may be arranged such that circuits 72a-72n are arranged in groups of five on either of two sides of RCD circuit 74, and power management integrated circuit (PMIC) 100 may conform to the JEDEC DDR5 specification. In an embodiment implementing a DDR5 standard SDRAM memory module, there may be five memory modules on each side of RCD circuit 74. In some embodiments, connector (or pins or traces) 60 may implement an 80-bit bus. The number, type, and / or arrangement of components of circuits 50a-50n may vary according to the design criteria of a particular implementation.

[0026] Referring to FIG. 4, a block diagram illustrating the memory module of FIG. 3 is shown. Memory module 50a may include data paths 80a-80n, RCD circuit 74, and / or PMIC 100. For example, data path 80a may include memory channel 82a and / or data buffer 70a. Data paths 80b-80n may have similar implementations. In the illustrated example, memory module 50a may include five data paths (e.g., 80a-80e) on one side of RCD circuit 74 and five data paths (e.g., 80j-80n) on the other side of RCD circuit 74.

[0027] The RCD circuit 74 may be configured to communicate with the memory controller 20, the data buffers 70a-70n, the memory channels 82a-82n, and / or the PMIC 100. The RCD circuit 74 may decode commands (e.g., control words) received from the memory controller 20. The signal CLK and / or the signal ADDR / CMD may be provided to the RCD circuit 74. For example, the RCD circuit 74 may receive a register command word (RCW). In another example, the RCD circuit 74 may receive a buffer control word (BCW). The RCD circuit 74 may be configured to bridge command and address lines between the DRAM chips 84a-84n, the data buffers 70a-70n, and / or the RCD circuit 74 and the memory controller 20. For example, an RCW may flow from the memory controller 20 to the RCD circuit 74. The RCW may be used to configure the RCD circuit 74.

[0028] The RCD circuit 74 can be used in both LRDIMM and RDIMM configurations. The RCD circuit 74 can implement a 32-bit 1:2 command / address register. For example, the RCD circuit 74 can have two sets of command / address outputs (e.g., A and B). The RCD circuit 74 can support a high-speed bus (e.g., a BCOM bus between the RCD circuit 74 and the data buffers 70a-70n). The RCD circuit 74 can perform automatic impedance calibration. The RCD circuit 74 can perform command / address parity checking. The RCD circuit 74 can control register RCW readback. In one example, the RCD circuit 74 can implement a serial communications bus (e.g., a 1 MHz inter-integrated circuit (I2C) bus, etc.). However, other types of management bus protocols (e.g., a sideband interface, etc.) may be implemented to meet the design criteria of a particular implementation. In some embodiments, the RCD circuit 74 can implement a 12.5 MHz inter-integrated circuit (I3C) bus. The inputs to the RCD circuit 74 may be pseudo-differential using an external and / or internal reference voltage. The clock, command / address, control, and / or data buffer control outputs of the RCD circuit 74 may be enabled in groups and independently driven at different strengths.

[0029] The RCD circuit 74 may receive the signal CLK and / or the signal ADDR / CMD from the memory controller 20. Various digital logic components of the RCD circuit 74 may be used to generate signals based on the signal CLK and / or the signal ADDR / CMD and / or other signals (e.g., RCW). The RCD circuit 74 may also be configured to generate a signal (e.g., CLK') and a signal (e.g., ADDR' / CMD'). The signal CLK' and / or the signal ADDR' / CMD' may be provided to each of the memory channels 82a-82n. In one example, the signals ADDR' / CMD' and CLK' may be transmitted on the common bus 52 and the common bus 54, respectively. In another example, the RCD circuit 74 may implement a single ADDR / CMD input and two ADDR' / CMD' outputs to support a 1:2 command / address architecture. The RCD circuit 74 may generate one or more signals (e.g., DBC). The signal DBC is provided to the data buffers 70a-70n. The signal DBC may implement a data buffer control signal, which may be transmitted on a common bus 56 (e.g., a data buffer control bus).

[0030] The data buffers 70a-70n may be configured to receive commands and data from the bus 56. The data buffers 70a-70n may be configured to generate / receive data to / from the bus 30. The bus 30 may include traces, pins, and / or connections between the memory controller 20 and the data buffers 70a-70n. The bus 58 may transmit data between each of the data buffers 70a-70n and its respective memory channel 82a-82n. The data buffers 70a-70n may be configured to buffer data on the buses 30 and 58 for write operations (e.g., data transfer from the memory controller 20 to the corresponding memory channel 82a-82n). The data buffers 70a-70n may be configured to buffer data on the buses 30 and 58 for read operations (e.g., data transfer from the corresponding memory channel 82a-82n to the memory controller 20).

[0031] The data buffers 70a-70n may exchange data with the DRAM chips 84a-84n in small units (e.g., 4-bit nibbles for x4 DRAMs, 8-bit bytes for x8 DRAMs). In various embodiments, the DRAM chips 84a-84n may be arranged in multiple (e.g., two) sets. In a two-set / two-DRAM chip (e.g., 84a-84b) implementation, each set may include a single DRAM chip (e.g., 84a or 84b). Each DRAM chip 84a-84b may be connected to a respective data buffer 70a-70n via an upper nibble and a lower nibble, i.e., byte. In a two-set / four-DRAM chip (e.g., 84a-84d) implementation, each set may include two DRAM chips (e.g., 84a-84b or 84c-84d). The first set may be connected to a respective data buffer 70a-70n via an upper nibble. Other sets may be connected to respective data buffers 70a-70n via the lower nibble. In the case of a two set / eight DRAM chip (e.g., 84a-84h) implementation, each set may include four DRAM chips 84a-84h. A set of four DRAM chips (e.g., 84a-84d) may be connected to respective data buffers 70a-70n via the upper nibble. Another set of four DRAM chips (e.g., 84e-84h) may be connected to respective data buffers 70a-70n via the lower nibble. Other numbers of sets, other numbers of DRAM chips, and other data unit sizes may be implemented to meet the design criteria of a particular implementation.

[0032] An interface 102 is shown. 102 can be configured to enable communication between the RCD circuit 74 and the PMIC 100. For example, the interface 102 can implement a register clock driver / power management integrated circuit interface (e.g., an RCD-PMIC interface). The interface 102 can include one or more signals and / or connections. Some of the signals and / or connections implemented by the interface 102 can be unidirectional. Some of the signals and / or connections implemented by the interface 102 can be bidirectional. The interface 102 can be enabled by the host memory controller 20. In one example, the memory controller 20 can enable the interface 102 for the RCD using a signal ADDR / CMD. In another example, the memory controller 20 can enable the interface 102 for the PMIC 100 by providing an enable command. In some embodiments, the bus 90 can communicate with the RCD circuit 74.

[0033] Referring to FIG. 5, a diagram illustrating a pinout diagram for a power management integrated circuit is shown. A top view of the microchip package of the PMIC 100 is shown. In one example, the microchip package of the PMIC 100 may be implemented as a quad flat no-lead (QFN) package. For example, the QFN package of the PMIC 100 may be approximately 4 mm by 3 mm in size. The amount of space available for the PMIC 100 on the circuits 50a-50n may be limited.

[0034] A number of pins of the PMIC 100 are shown. The PMIC 100 can be implemented to have 28 pins (e.g., pin 1 through pin 28). The amount of space available for the PMIC 100 can be limited, so the size of the PMIC 100 can be constrained to certain specifications. The pinout of the PMIC 100 is based on design criteria defined by the JEDEC DDR5 specification. In some embodiments, the pinout of the PMIC 100 may be predefined according to the JEDEC DDR5 specification. For example, size constraints may prevent the addition of more pins to the PMIC 100.

[0035] In general, pins pin1-pin28 may each have a predefined function. One or more of pins pin1-pin28 of PMIC 100 may be a host interface. PMIC 100 may be configured to implement entry and / or exit of the P1 and P3a states using available pins pin1-pin28. PMIC 100 may be configured to add additional functionality to one or more of pins pin1-pin28 while enabling the predetermined function of each of pins pin1-pin28.

[0036] In the illustrated example, pin pin2, pin pin6, and pin pin20 may each communicate a signal (e.g., VIN_BULK_A, VIN_BULK_B, and VIN_BULK_C may each together be the signal VIN_BULK). Pin pin13 may carry a signal (e.g., VOUT_1.8V). Pin pin15 may carry a signal (e.g., VOUT_1.0V). Pin pin3 may communicate a signal (e.g., SWA). Pin pin5 may communicate a signal (e.g., SWB). Pin pin19 may communicate a signal (e.g., SWC). Pin pin9 may carry a signal (e.g., PID). Pin pin23 may carry a signal (e.g., GSI_n). Pin pin25 may carry a signal (e.g., PWR_GOOD). Pin pin27 may carry a signal (e.g., VR_EN). The pinout of the PMIC 100 may be varied according to the design criteria of a particular implementation and / or according to the DDR5 standard JEDEC specification.

[0037] The PMIC 100 may include blocks (or circuits) 102a-102n. The circuits 102a-102n may each implement a register. Each of the registers 102a-102n may include a location. In one example, location 104 is shown in register 102i. Register 102i may be a power state entry register. The PMIC 100 may further include blocks (or circuits) 106a-106n. The circuits 106a-106n may each implement a regulator. The PMIC 100 may include other components (not shown). The number, type, and / or arrangement of components of the PMIC 100 may vary according to the design criteria of a particular implementation.

[0038] The registers 102a-102n may be configured to provide highly volatile storage. The registers 102a-102n may have read-only, read / write-only, or reservable characteristics. A subset of the registers 102a-102n may comprise an area accessible to the host controller 20. For example, the host controller 20 may be configured to read from and write to a subset of the registers 102a-102n. The subset of the registers 102a-102n may allow a DIMM vendor (e.g., a vendor of the circuits 50a-50n) to program the PMIC 100. The subset of the registers 102a-102n may be a PMIC vendor (e.g., a vendor of the PMIC 100) specific area. Registers 102a-102n may be configured to provide various functions of PMIC 100, such as error logging, status information (real-time and periodic), masking, power state entries, current thresholds, voltage settings, temperature readings, power measurements, etc. The functionality of registers 102a-102n may be varied according to the design criteria of a particular implementation.

[0039] Registers 102a-102n may be 8-bit registers. In one example, registers 102a-102n may comprise eight memory locations (or register values). Register value 104 is a representative example of a register value (or memory location) for registers 102a-102n. In the illustrated example, register 102i may be the R1A register, and register value 104 may be the R1A[4] value (e.g., bit 4 of bits 0:7 of register R1A). The value stored in register value 104 may be configured to enable additional functionality for one or more of pins pin1-pin28. Register value 104 may be configured to enable a low-power (e.g., quiescent) state for PMIC 100. Register value 104 may be configured to control entry into and / or exit from low-power and idle power states.

[0040] Register 102i may be one of a subset of registers 102a-102n accessible by host controller 20. Register value 104 may be a read / write value (e.g., host controller 20 may read from or write to register value 104). Register value 104 may be a PMIC quiescent state entry enable value (e.g., QUIESCENT_STATE_EN). In one example, when register value 104 has a low (e.g., logic 0) value, the quiescent state may be disabled. In one example, when register value 104 has a high (e.g., logic 1) value, the quiescent state may be enabled.

[0041] Regulators 106a-106n may comprise switching regulators and / or low dropout (LDO) regulators. In one example, regulator 106a may be a SWA regulator, regulator 106b may be a SWB regulator, and regulator 106c may be a SWC regulator. Regulators 106a-106c may be switch-node output buck regulators connected to a power inductor. In another example, regulator 106d may be a 1.8V LDO regulator, and regulator 106e may be a 1.0V LDO regulator. The number and / or type of regulators implemented may be modified or varied according to the design criteria of a particular implementation.

[0042] The signal VIN_BULK may be a 5V power input supply to the PMIC 100 for one or more of the regulators 106a-106n. In one example, the signal VIN_BULK_A may be the input supply for the SWA regulator 106a, the signal VIN_BULK_B may be the input supply for the SWB regulator 106b, and the signal VIN_BULK_C may be the input supply for the SWC regulator 106c. The signal VOUT_1.8V may be a 1.8V output for the LDO regulator 106d. The signal VOUT_1.0V may be a 1.0V output for the LDO regulator 106e. The signal SWA may be an output for the SWA regulator 106a, the signal SWB may be an output for the switch regulator 106b, and the signal SWC may be an output for the switch regulator 106c. The signal PID may receive IDs for the I2C and I3C buses. The signal GSI_n may provide a general status interrupt output. Signal GSI_n may be an open-drain output configured to communicate events to host controller 20.

[0043] The signal PWR_GOOD may be an open-drain output configured to indicate the power status of the PMIC 100. For example, the signal PWR_GOOD may be asserted high when VIN_BULK and all enabled regulators 106a-106n remain within tolerance thresholds configured by the corresponding registers 102a-102n. In one example, the signal PWR_GOOD may be asserted low when VIN_BULK is below a threshold or when any of the enabled regulators 106a-106n exceeds a tolerance threshold. The signal PWR_GOOD may also be configured as an I / O. For example, in low-power operation, the pin 25 for the signal PWR_GOOD can operate as an I / O. In another example, the pin 25 for the signal PWR_GOOD may be output-only.

[0044] The signal VR_EN may be a PMIC enable input signal. In one example, when the signal VR_EN is asserted high, the PMIC 100 can turn on one of the regulators 106a-106n. In one example, when the signal VR_EN is asserted low, the PMIC 100 can turn off one of the regulators 106a-106n. The pin 27 may be an enable pin for the host interface of the PMIC 100. The enable pin 27 may be an input configured to control the status of one or more of the regulators 106a-106n.

[0045] If the mask bits of registers 102a-102n are not set, the PMIC 100 can assert signal GSI_n and signal PWR_GOOD when certain events occur. In one example, various events can cause the PMIC 100 to internally generate a VR disable command (e.g., overvoltage or undervoltage on signal VIN_BULK, overvoltage or undervoltage on signals SWA-SWC, critical temperatures, etc.). For events that do not trigger a VR disable command, the PMIC 100 can operate normally. The host controller 20 may be configured to read the status registers 102a-102n to determine and / or isolate the cause of the assertion of signal GSI_n or signal PWR_GOOD. The PMIC 100 can continue to assert signal GSI_n or signal PWR_GOOD until the host controller 20 clears or masks the appropriate register 102a-102n.

[0046] In some embodiments, in the low-power (e.g., quiescent) P1 state, the VIN_BULK current may be approximately 25 μA (VIN_BULK is 5 V). All circuitry within the PMIC 100, including all regulators 106a-106n, may be turned off. The signal VR_EN may be set to a static low state or a static high state. The signal GSI_n may be pulled high. Access to the I2C or I3C interface may be disabled and the bus may be pulled high. The signal PID may be pulled either high or low.

[0047] In some embodiments, in the idle power P3a state, the current on VIN_BULK may be approximately 100 μA (VIN_BULK is 5 V). All output and / or LDO regulators 106a-106n may be turned on with an output load of 0 A. Signal VR_EN may be set to a static low state or a static high state. Signal GSI_n may be pulled high. Access to the I2C or I3C interface may be enabled and the bus may be pulled high. Signal PID may be pulled either high or low.

[0048] The PMIC 100 can be configured to operate in a secure mode of operation or a programmable mode of operation. Whether the PMIC 100 operates in the secure mode of operation or the programmable mode of operation can be determined by the values ​​of one of the registers 102a-102n. In one example, one of the register values ​​for one of the registers 102a-102n (e.g., register value R2F[2]) can be used to determine which mode of operation is enabled for the PMIC 100. The mode of operation of the PMIC 100 can be selected after a VR enable command provided by the host controller 20 (e.g., either using the signal VR_EN at pin 27 or by providing a command on the I2C / I3C bus) is registered.

[0049] In a programmable mode of operation, when the host controller 20 issues a VR enable command (e.g., using the signal VR_EN or the I2C / I3C bus), the PMIC 100 may be configured to modify any of the registers 102a-102n based on commands provided by the host controller 20. The host controller 20 may modify or change any of the registers 102a-102n that are part of the host subset of registers 102a-102n. The PMIC 100 may operate in response to the programming of the registers 102a-102n by the host controller 20.

[0050] In the secure mode of operation, the PMIC 100 may be configured to not allow the host controller 20 to modify some of the registers 102a-102n (e.g., secure registers). For example, in the secure mode of operation, some of the registers 102a-102n may be modified and some of the registers 102a-102n may not be modified or changed by the host controller 20. The PMIC 100 may be configured to ignore requests from the host controller 20 corresponding to some of the registers 102a-102n. For example, registers R15-R2F, registers R32-R34, registers R40-R6F, and / or registers R70-RFF may be modified while the PMIC 100 is operating in the secure mode of operation, while the registers 102a-102n (e.g., secured registers) are not modified. Generally, in the secure mode of operation, the PMIC 100 may write-protect some of the registers 102a-102n, but in the secure mode of operation (or the programmable mode of operation), there may be no restrictions on read operations of the registers 102a-102n.

[0051] The host controller 20 can power cycle the PMIC 100 to allow writing to the secured registers when the PMIC 100 enters the secure mode of operation. Power cycling the PMIC 100 may involve the complete removal of the VIN_BULK signal to the PMIC 100 (e.g., no input to pins 2, 6, and 20). The secure mode of operation can only be entered when a VR enable command is provided by the host controller 20. For example, register R2F[2] may default to zero when the PMIC 100 powers up (e.g., corresponding to the secure mode of operation), but the PMIC 100 can allow the host controller 20 (from the host subset) to modify any of the registers 102a-102n before the VR enable command is provided.

[0052] Some of the registers 102a-102n may store threshold values. In one example, one or more of the registers 102a-102n may store threshold voltages for signals SWA, SWB, and / or SWC. The PMIC 100 may actively monitor the output voltage of each enabled regulator 106a-106n. In a programmable mode of operation, if the PMIC 100 detects that any of the switching regulators (e.g., regulators 106a-106c) has an overvoltage condition, the PMIC 100 may generate a VR disable command, disable the switching regulators 106a-106c, update the registers 102a-102n, assert the signal GSI_n, and assert the signal PWR_GOOD (the LDO regulators 106d-106e may remain active). PMIC 100 may allow host controller 20 to access registers 102a-102n to determine the cause of the overvoltage condition and clear the appropriate registers. Once host controller 20 clears the appropriate registers and issues a VR_ENABLE command, switching regulators 106a-106c may be re-enabled by host controller 20. In the secure mode of operation, if PMIC 100 detects that any of switching regulators 106a-106c is in an overvoltage condition, PMIC 100 may respond similarly to the programming mode of operation, except that host controller 20 may power cycle PMIC 100.

[0053] Referring to FIG. 6, a diagram illustrating an I2C / I3C bus between the host memory controller 20 and memory modules 50a-50h is shown. A system bus 350 is shown. The system bus 350 may implement the I2C or I3C protocol. In one example, the system bus 350 may correspond to the host interface bus 90 shown in connection with FIG. 2. Generally, the system bus 350 may communicate with eight DIMMs per bus (e.g., memory modules 50a-50h).

[0054] Each of the memory modules 50a-50h may include a respective hub 200a-200h and / or several devices 352a-352n. The hubs 200a-200h may implement a serial presence detect (SPD) hub. Each of the SPD hubs 200a-200h may allow the memory controller 20 to access information about the memory modules 50a-50h. For example, each SPD hub 200a-200h may provide access to the amount of memory installed, when to use it, etc. In one example, the SPD hubs 200a-200h may communicate using an I2C protocol. In another example, the SPD hubs 200a-200h may communicate using an I3C protocol. The SPD hubs 200a-200n may be configured to provide enable commands from the host memory controller 20 to the PMIC 100.

[0055] In the illustrated example, SPD hub 200a and slave devices 352a-352d are shown as representative examples corresponding to memory module 50a. In one example, slave devices 352a-352d may be PMIC 100, RCD circuit 74, and two temperature sensors. A portion 350' of system bus 350 is shown on memory module 50a communicating between SPD hub 200a and slave devices 352a-352d. In some embodiments, system bus 350 can communicate with at least five devices per memory module 50a-50h (e.g., for receiving power measurement readouts, PMIC 100 status, temperature readouts, SPD status, and / or RCD circuit 74 status).

[0056] In one example of a system bus 350 implementing the I3C protocol (e.g., operating at 12.5 MHz), the total amount of time for a basic periodic read (e.g., excluding packet error checking (PEC), IBI checks, and / or software overhead) can be approximately 464 μs. For example, using only the system bus 350, the signal PMIC current / power read time is approximately 128 μs (e.g., 8×16) for one PMIC per DIMM and 256 μs (e.g., 2×8×16) for two PMICs per DIMM. In another example, using only the system bus 350, the PMIC general status read time is approximately 128 μs (e.g., 8×16) for one PMIC per DIMM and 256 μs (e.g., 2×8×16) for two PMICs per DIMM. In yet another example, using only the system bus 350, the temperature sensor (TS) read time can be 128 μs with two temperature sensors per DIMM (e.g., 8×2×8) and 48 μs with one SPD TS per DIMM (8×6). In yet another example, using only the system bus 350, the SPD read time can be approximately 80 μs with one SPD per DIMM (e.g., two registers (MR48 and MR52) may be read in addition to the SPD TS). Furthermore, using only the system bus 350 can further include the RCD read time. In another example, using an I2C bus protocol (e.g., operating at 1 MHz), the total time for a basic periodic read can be approximately 5.5 ms.

[0057] The PMIC 100 may be configured to provide measured power and / or current consumption per rail (e.g., on each voltage regulator module). In one example, the memory controller 20 may access the power data and utilize that information to adjust the access patterns of the DRAM modules 72a-72n. The system bus 350 may be configured to allow the memory controller 20 to access the power data (e.g., via an I2C / I3C protocol).

[0058] Upon power-up, the PMIC 100 may operate in the I2C operating mode by default. In the I2C operating mode, the PMIC 100 has a maximum speed limited to 1 MHz, in-band interrupts are not supported, bus 350 reset is supported, parity checking is not supported (other than the supported CCC), and packet error checking is not supported. The PMIC 100 may operate in the I2C operating mode until the host controller 20 provides a command to enter the I3C operating mode. In one example, the host controller 20 may issue a SETAASA CCC command to enter the I3C operating mode. In the I3C operating mode, the PMIC 100 may have a maximum operating speed of up to 12.5 MHz, support in-band interrupts, support bus 350 reset, enable parity checking by default, and support packet error checking but disable it by default.

[0059] Referring to FIG. 7, a state diagram illustrating entry into and exit from quiescent power states is shown. State diagram 380 is shown. State diagram 380 may include power states 382-392. Power state 382 may be the P0 state. Power state 384 may be the P2_B power state. Power state 386 may be the P3 (or P3a) power state. Power state 388 may be the P1 power state. State 390 may be the P2_A1 power state. Power state 392 may be the P2_A2 power state. Power states 382-392 may be power states in which PMIC 100 may be configured to operate. PMIC 100 may include other power states (not shown). The number and / or type of power states implemented by PMIC 100 may be modified or changed according to the design criteria of a particular implementation.

[0060] In the P0 power state 382, ​​the signal VIN_BULK is disabled and the R_GOOD signal is a logic low value. For example, there may be no input on pins pin2, pin6, and pin20. The P0 power state 382 may be a power cycle of the PMIC 100. From the P0 power state 382, ​​the PMIC 100 can move to a P2_B power state 384.

[0061] In the P2_B power state 384, all switching regulators 106a-106c are off, and all LDO regulators 106d-106e are on. In the P2_B power state 384, the signal PWR_GOOD may be a logic low value, and the signal VR_EN may be a logic low value (or a high-impedance state). In the P2_B power state 384, the register value R32[7] may be zero. The P2_B power state 384 may be a transition state from the P0 power state 382 and / or the P1 power state 388 prior to a VR enable command. When the signal VR_EN transitions high or a VR enable command is present on the I2C / I3C bus 90, the P2_B power state 384 can transition to the P3 power state 386.

[0062] In the P3 power state 386, all switching regulators 106a-106c may be on. In one example, the P3 power state 386 may be a regulation mode of operation and / or a VIN_BULK link monitoring mode of operation. In the P3 power state 386, the register value R32[7] may be 1. In one example, in the P3 power state 386, the PMIC 100 may have a current of approximately 100 μA at 5V VIN_BULK.

[0063] In the P3 power state 386, when the VR_EN pin transitions from high to low, the R32[5] register is set to 0, and the register value 104 is set to 0, the signal PWR_GOOD goes low and the PMIC 100 transitions to the P2_A1 power state 390. In the P3 power state 386, when the VR_EN pin transitions from high to low, the R32[5] register is set to 0, and the register value 104 is set to 1, the signal PWR_GOOD goes low and the PMIC 100 transitions to the P1 power state 388. In the P3 power state 386, if the VR_EN pin transitions from high to low and the R32[5] register is set to 1, the PMIC 100 may be in an improper configuration (e.g., simultaneous use of the signals PWR_EN and PWR_GOOD as I / O types may be improper because the VR_EN pin may be intended to turn the output rail on and off only if the signal PWR_GOOD is configured as an I / O, and the signal PWR_GOOD may be connected to GND if configured as an I / O). If the VR_EN pin transitions from low to high in the P3 power state 386, the signal PWR_GOOD is in a high-impedance state and the PMIC 100 remains in the P3 power state 386 (e.g., assume the PMIC entered the P3 power state 386 from a VR enable command on the I2C / I3C bus 90).

[0064] In the P3 power state 386, if a VR enable command is present on the I2C / I3C bus 90, the R2F[2] register is set to 1, the register value 104 is set to 0, the signal PWR_GOOD is in a high-impedance state, and the PMIC 100 transitions to the P2_A1 power state 390. In the P3 power state 386, if a VR enable command is present on the I2C / I3C bus 90, the R2F[2] register is set to 1, the register value 104 is set to 1, the signal PWR_GOOD is in a high-impedance state, and the PMIC 100 transitions to the P1 power state 388. In the P3 power state 386, if a VR enable command is present on the I2C / I3C bus 90, the R2F[2] register is set to 0, the signal PWR_GOOD is in a high-impedance state, and the PMIC 100 remains in the P3 power state 386. In the P3 power state 386, if a VR disable command is present on the I2C / I3C bus 90, the signal PWR_GOOD is in a high impedance state and the PMIC 100 remains in the P3 power state 386 (for example, assume that the PMIC 100 enters the P3 power state 386 and the VR_EN pin transitions high).

[0065] In the P3 power state 386, if the signal PWR_GOOD is input low and the R32[5] register is set to 0, the signal PWR_GOOD is in a high-impedance state and the PMIC 100 can remain in the P3 power state 386 (e.g., the signal PWR_GOOD I / O type can be configured as output only, and the signal PWR_GOOD input can be low, but internally the output signal PWR_GOOD can be in a high-impedance state). In the P3 power state 386, if the signal PWR_GOOD is input low and the R32[5] register is set to 1, the signal PWR_GOOD is low and the PMIC 100 remains in the P2_A1 power state 390.

[0066] In the P3 power state 386, if there is an internal VR disable event and the R2F[2] register is set to 0, the signal PWR_GOOD is low, the PMIC 100 transitions to the P2_A1 power state 390, and the PMIC 100 requires a power cycle. In the P3 power state 386, if there is an internal VR disable event and the R2F[2] register is set to 1, the signal PWR_GOOD is low, the PMIC 100 transitions to the P2_A1 power state 390, and the PMIC 100 does not require a power cycle (e.g., the PMIC 100 may re-enable the output regulators 106a-106n with a VR enable command, assuming the event is no longer present and the status registers are cleared). In the P3 power state 386, if the signal VIN_BULK is invalid, the PMIC 100 may transition to the P0 power state 382.

[0067] In the P1 power state 388, the register value 104 can be set to 1. The P1 power state 388 can only have entry from the P3 power state 386. In the P1 power state 388, if the VR_EN pin transitions from low to high and the register value 104 is set to 1, the signal PWR_GOOD is in a high-impedance state, no power cycle is required, and the PMIC 100 transitions to the P3 power state 386. In the P1 power state 388, if a VR enable or VR disable command is set on the I2C / I3C bus 90 and the register value 104 is set to 1, the signal PWR_GOOD has no change and the PMIC 100 remains in the P1 power state 388. In one example, in the P1 power state 388, the PMIC 100 can have a current of approximately 25 μA at 5V VIN_BULK. For example, in the P1 power state 388, the PMIC 100 may consume less power than in the P3 power state 386.

[0068] The P2_A1 power state 390 may be a state without a fault event. The P2_A1 power state 390 can be transitioned to from the P3 power state 386 after a VR enable command. In the P2_A1 power state 390, all switching regulators 106a-106c may be off. In the P2_A1 power state 390, all LDO regulators 106e-106f may be on. In the P2_A1 power state 390, the signal PWR_GOOD is low or high, the input signal VR_EN is low or high, and register R32[7] is set to 0.

[0069] In the P2_A1 power state 390, if the VR_EN pin transitions from high to low, there is no change (e.g., the PMIC 100 is already in the P2_A1 power state 390 and the VR_EN pin has no meaning). In the P2_A1 power state 390, if the VR_EN pin transitions from low to high and register R32[5] is set to 1, the PMIC 100 may be in an improper configuration. In the P2_A1 power state 390, if the VR_EN pin transitions from low to high, register R32[5] is set to 0, and register value 104 is set to 0, signal PWR_GOOD goes to a high-impedance state and the PMIC 100 transitions to the P3 power state 386. In general, the P2_A1 power state 390 may not be entered in the absence of an event (e.g., register value 104 is set to 1).

[0070] In the P2_A1 power state 390, if a VR disable command is present on the I2C / I3C bus 90, there may be no change (e.g., the PMIC 100 is already in the P2_A1 power state 390 via the VR_EN pin, and the VR disable command may have no effect). In the P2_A1 power state 390, if a VR enable command is present on the I2C / I3C bus 90 and register R2F[2] is set to 0, there may be no change. In the P2_A1 power state 390, if a VR enable command is present on the I2C / I3C bus 90 and register R2F[2] is set to 1, the signal PWR_GOOD is in a high-impedance state, the PMIC 100 transitions to the P3 power state 386, and no power cycle is required.

[0071] In the P2_A1 power state 390, if there is an internal VR disable event and register R2F[2] is set to 0, signal PWR_GOOD is set low, a power cycle is required, and the PMIC 100 transitions to the P2_A2 power state 392. In the P2_A1 power state 390, if there is an internal VR disable event and register R2F[2] is set to 1, signal PWR_GOOD may be set low, a power cycle may not be required, and the PMIC 100 may transition to the P2_A2 power state 392 (e.g., the PMIC 100 may re-enable the output regulators 106a-106n with a VR enable command, assuming the event is no longer present, the status registers are cleared, and a power cycle may be required if there is a thermal shutdown, regardless of the settings of registers 102a-102n). In power state P2_A1, if signal VIN_BULK is invalid, PMIC 100 can transition to P0 power state 382.

[0072] The P2_A2 power state 392 may be a fault event state. The P2_A2 power state 392 may be transitioned to from the P3 power state 386 after a VR enable command. In the P2_A2 power state 392, all switching regulators 106a-106c may be off. In the P2_A2 power state 392, all LDO regulators 106e-106f may be on. In the P2_A2 power state 392, the signal PWR_GOOD is low, the input signal VR_EN is low or high, and register R32[7] may be set to 0.

[0073] In the P2_A2 power state 392, if the VR_EN pin transitions from high to low, there may be no change (e.g., the PMIC 100 may already be in the P2_A2 power state 392 and the VR_EN pin may have no meaning). In the P2_A2 power state 392, if the VR_EN pin transitions from low to high and register R2F[2] is set to 0, the signal PWR_GOOD is set low, the PMIC 100 requires a power cycle, and the PMIC 100 remains in the P2_A2 power state 392. In the P2_A2 power state 392, if the VR_EN pin transitions from low to high, register R2F[2] is set to 1, and register value 104 is set to 0, the signal PWR_GOOD goes to a high impedance state, no power cycle is required, and the PMIC 100 transitions to the P3 power state 386. In the P2_A2 power state 392, if the VR_EN pin transitions from low to high, register R2F[2] is set to 1, register R32[5] is set to 0, and register value 104 is set to 0, signal PWR_GOOD is in a high impedance state, no power cycle is required, and the PMIC 100 can transition to the P3 power state 386. In the P2_A2 power state 392, if the VR_EN pin transitions from low to high, register R2F[2] is set to 1, register R32[5] is set to 1, and register value 104 is set to 0, the PMIC 100 may be improperly configured.

[0074] In the P2_A2 power state 392, if a VR enable command is present on the I2C / I3C bus 90 and register R2F[2] is set to 0, then signal PWR_GOOD may be set low, a power cycle may be required, and the PMIC 100 may remain in the P2_A2 power state 392. In the P2_A2 power state 392, if a VR enable command is present on the I2C / I3C bus 90, register R2F[2] is set to 1, and register value 104 is set to 0, then signal PWR_GOOD is in a high impedance state, a power cycle is not required, and the PMIC 100 may transition to the P3 power state 386. In the P2_A2 power state 392, if a VR enable command is present on the I2C / I3C bus 90, register R2F[2] is set to 1, and register value 104 is set to 1, the signal PWR_GOOD is in a high impedance state, no power cycle is required, and the PMIC 100 can transition to the P3 power state 386.

[0075] In the P2_A2 power state 392, if there is an internal VR disable event and register R2F[2] is set to 0, there may be no change and a power cycle may be required. In the P2_A2 power state 392, if there is an internal VR disable event and register R2F[2] is set to 1, there may be no change and a power cycle may not be required. In the P2_A2 power state 392, if the signal VIN_BULK is invalid, the PMIC 100 may transition to the P0 power state 382.

[0076] The P1 power state 388 may be a quiescent power state. In the quiescent power state 388, the signal VIN_BULK may be nominally 5 V and may have a current requirement of 25 μA. In the quiescent power state 388, all circuits within the PMIC 100 may be off, including the switch regulators 106 a-c and the LDO regulators 106 d-e. In the quiescent power state 388, the signal VR_EN may be at a static low level or a static high level. In the quiescent power state 388, I2C / I3C interface access is not permitted (e.g., access to the bus 90 may be disabled) and may be pulled high, and the signal PID may be at a static low level or a high level. The quiescent power state 388 may be applicable only when the register value 104 is set to a logic one (or high) value. When the PMIC 100 enters the quiescent power state 388, the PMIC 100 can store the settings of register bits R32[5], R2F[2] and register value 104 in non-volatile memory as long as the signal VIN_BULK is valid. In one example, the non-volatile memory can be accessed via the host controller 20. The pin 25 for the signal PWR_GOOD can be configured to have bidirectional operation when the PMIC 100 is in the program operating mode and in the quiescent power state 388.

[0077] The P3 / P3a power state 386 may be an idle power state. In the idle power state 386, the signal VIN_BULK may be nominally 5 V and have a current requirement of 100 μA. In the idle power state 386, all circuits within the PMIC 100, including the switch regulators 106a-106c and the LDO regulators 106d-106e, may be on with a 0 A load. In the idle power state 386, the signal VR_EN may be static low or high. In the idle power state 386, I2C / I3C interface access may be allowed (e.g., access to the bus 90 may be enabled), but the bus 90 may be pulled high, and the signal PID may be static low or high. The idle power state 386 may be applicable only when the register value 104 is set to a logic 0 (or low) value. The P3a power state may be the same state as the P3 power state, but the load on all switch output regulators 106a-106c and LDO regulators 106d-106e is 0 A. For example, in the quiescent power state 388, the PMIC 100 will consume less power than when in the idle power state 386.

[0078] The register 102i may be a power state entry register. The power state entry register 102i may be an R1A register. The power state entry register R1A may include 8 bits (e.g., 8 storage locations). One of the storage locations (e.g., R1A[4]) may be a register value 104. The R1A register may be configured to control entry into the quiescent (e.g., low) P1 power state 388.

[0079] The [0] bit of register R1A may be a VOUT_1.0V_POWER_GOOD_THRESHOLD_VOLTAGE storage location, which may provide the VOUT_1.0V LDO output threshold voltage for the Power Good state. In one example, a value of 0 for the [0] bit of register R1A may be −10% from the setting of register R51[2:1], and a value of 1 may be −15% from the setting of register R51[2:1].

[0080] Bit [1] of register R1A can be an OUTPUT_POWER_SELECT storage location that can provide a switch output power selection (e.g., only applicable if register R1B[6] is set to 1). In one example, a value of 0 for bit [1] of register R1A can report individual power for each rail on R0C, R0E, and R0F, and a value of 1 can report total power on each rail in R0C.

[0081] Bit [2] of register R1A may be a VOUT_1.8_POWER_GOOD_THRESHOLD_VOLTAGE storage location that may provide the LDO threshold voltage for a power good condition. In one example, a value of 0 for bit [2] of register R1A indicates a voltage of 1.6V, and a value of 1 may be reserved. Bit [3] of register R1A may be reserved.

[0082] Bit [4] of register R1A may be register value 104. Register value 104 may be a QUIESCENT_STATE_EN storage location that can provide an enable bit for entering the quiescent power state 388. Register value 104 must be set before issuing a VR enable command. In one example, a value of 0 for register value 104 can disable the quiescent power state 388, and a value of 1 can enable the quiescent power state 388 (e.g., a VR disable command (e.g., in programmable mode only, the VR_EN pin transitioning low or register R32[7] being set to 0) can place the PMIC 100 in the quiescent power state 388).

[0083] Bit [5] of register R1A may be a VIN_BULK_POWER_GOOD_THRESHOLD_VOLTAGE storage location, which may provide the VIN_BULK input supply (falling) threshold voltage for the power good condition. In one example, a value of 0 for bit [5] of register R1A may indicate a voltage of 4.0V, and a value of 1 for bit [5] of register R1A may indicate a voltage of 3.75V. Bits [6:7] of register R1A may be reserved.

[0084] The default value of the bits in register R1A may be 0. In one example, by default, register value 104 may be a 0 value. When register value 104 has a value of 0, PMIC 100 may disable quiescent power state 388 (e.g., PMIC 100 may not enter quiescent power state 388). Register value 104 may be changed to a value of 1 to enable quiescent power state 388. Register value 104 may be changed by a command from host controller 20. In one example, the command from host controller 20 to change register value 104 may be a transition of signal VR_EN. In another example, the command from host controller 20 to change register value 104 may be a VR enable command or a VR disable command on bus 90.

[0085] In some embodiments, the host controller interface (e.g., pins pin1-pin28) of the PMIC 100 may be defined by the DDR5 specification. Each of pins pin1-pin28 may have a specific function. Signal VR_EN may have a predefined function. The PMIC 100 may add a predefined function to pin pin28. For example, the PMIC 100 may reuse pin pin28 and register value 104 to control entry into and exit from the quiescent power state 388. The PMIC 100 may be configured to operate within the requirements of the DDR5 specification (and later generations) to add functionality to the quiescent power state 388. The combination of pin pin28 for signal VR_EN and register value 104 for controlling entry into and exit from the quiescent power state 388 may allow the PMIC 100 to control the state of regulators 106a-106n without increasing the number of pins pin1-pin28 in the host controller interface of the PMIC 100.

[0086] Referring to FIG. 8, a timing diagram illustrating a power-up sequence when the VR_EN pin is high after the VIN_Bulk ramp and there is no bus command is shown. A timing diagram 420 is shown. The timing diagram 420 may include waveforms 422 through 438. Waveform 422 may represent the signal VIN_BULK. Waveform 424 may represent the signal VOUT_1.8V. Waveform 426 may represent the signal VOUT_1.0V. Waveform 428 may represent a command on the I2C / I3C bus 90. Waveform 430 may represent the signal VR_EN. Waveform 432 may represent the signal SWC. Waveform 434 may represent the signal SWB. Waveform 436 may represent the signal SWA. Waveform 438 may represent the signal PWR_GOOD.

[0087] Vertical lines 440-450 are shown. The vertical lines 440-450 may correspond to specific timing and / or responses by the PMIC 100. In one example, the vertical line 440 may represent a sequence of events and / or actions. The vertical line 440 may correspond to a low-to-high transition of the VIN_BULK waveform 422. The vertical line 442 may correspond to a low-to-high transition of the VOUT_1.8V waveform 424. The time between the lines 440 and 442 may be t1.8V_READY. The vertical line 444 may correspond to a low-to-high transition of the VOUT_1.0V waveform 426. The time between the lines 442 and 444 may be t1.0V_READY.

[0088] Line 448 may correspond to the low-to-high transition of the VR_EN waveform 430. Line 446 may precede line 448. The time between line 442 and line 446 may be tMANAGEMENT_READY. The time between line 440 and line 448 may be tVIN_BULK_TO_VR_ENABLE. There may be no VR enable command on the I2C / I3C bus 90.

[0089] At time 448, the SWC waveform 432 may transition from low to high, then the SWB waveform 434 may transition from low to high, the SWA waveform 436 may transition from low to high, and then the PWR_GOOD waveform 438 may transition from low to high. For example, changing (e.g., providing an input to) the VR_EN waveform 430 may change the state of the regulators 106a-106n. The PWR_GOOD waveform 438 may be in an indeterminate state 452 before time 440. Line 450 may correspond to the low-to-high transition of the PWR_GOOD waveform. The time between line 448 and line 450 may be tPMIC_PWR_GOOD_OUT.

[0090] Signal VIN_BULK (e.g., signals VIN_BULK_A, VIN_BULK_B, and VIN_BULK_C) may be one input power supply for PMIC 100. The input power supply may be received from a host platform (e.g., host controller 20). The VIN_BULK power supply may be used by PMIC 100 for all three switched output regulators 106a-106c and two LDO output regulators 106d-106e. Signal VOUT_1.8V (e.g., an LDO output) may be separate and independent from signal SWC (e.g., a switched output for a DRAM VPP rail). Signal VOUT_1.0V (e.g., an LDO output) may be separate and independent from signals SWA or SWB.

[0091] When PMIC 100 is powered up, the VIN_BULK power supply is allowed to reach a minimum threshold voltage of approximately 4.25V before being detected as enabled by PMIC 100. After the VIN_BULK power supply reaches the minimum threshold voltage, PMIC 100 can update register R08[7] when signal VIN_BULK falls below the threshold setting in bit [5] of register R1A.

[0092] When the VIN_BULK power supply becomes valid (e.g., at time 440), the PWR_GOOD waveform 438 can transition from an indeterminate state 452 to a low value, and the PMIC 100 can drive the VOUT_1.8V waveform 424 high (e.g., within t1.8V_READY) and the VOUT_1.0V waveform 426 high (e.g., within t1.0V_READY). The PMIC 100 can drive the signal PWR_GOOD low only when the VIN_BULK waveform 422 reaches a minimum threshold voltage. The PWR_GOOD waveform 438 can be pulled up either on the platform or on the host controller 20 (e.g., from 1.8V to 3.3V). The pull-up voltage for the PWR_GOOD waveform 438 is only available after VIN_BULK is valid and stable. The PMIC 100 may enable the I2C / I3C bus 90 interface function within tMANAGEMENT_READY. The host controller 20 may not attempt to access the registers 102a-102n until the tMANAGEMENT_READY timing requirement is met.

[0093] During power-up, the host controller 20 ramps up the VIN_BULK waveform 422, holds the VIN_BULK waveform 422 stable, and can hold the VR_EN pin at a static low or high for a minimum amount of time, tVIN_VULK_to_VR_ENABLE. In general, there may be no timing relationship requirements on the VR_EN waveform 430 as long as it is held at a static level (either low or high). If the VR_EN waveform 430 is held low during the ramp-up of the VIN_BULK waveform 422, the VR_EN waveform 430 can transition to high only once. The VR_EN waveform 430 may not be allowed to transition low during the ramp-up of the VIN_BULK waveform 422 once it goes high. If the VR_EN waveform 430 is held high or transitions high during the ramp-up of the VIN_BULK waveform 422, the PMIC 100 can turn on the output rail. If the VR_EN waveform 430 is held low during the ramp-up of the VIN_BULK waveform 422, the host controller 20 can assert the signal VR_EN high to turn on the output rails of the PMIC 100. The host controller 20 may issue a VR enable command by setting register R32[7] to 1 via the I2C / I3C bus 90 to turn on the output rails of the PMIC 100. The exemplary power-up initialization sequences shown in connection with FIGS. 8-12 may be representative examples. The particular ramp-up sequence may be configurable via registers 102a-102n corresponding to the power-on sequence configuration.

[0094] After the VR enable command is registered on the I2C / I3C bus 90 or the signal VR_EN is registered high, the PMIC 100 can perform a number of steps during tPMIC_PWR_GOOD_OUT. The PMIC 100 can check that the power good status of the VIN_BULK waveform 422 is valid. The PMIC 100 can power up using a power-on sequence configuration (e.g., described by register R40 and / or register R42) and configure the internal registers 102a-102n to be programmed into the DIMM vendor memory space registers. The PMIC 100 can then power up all enabled output switch regulators 106a-106c and prepare for normal operation. The PMIC 100 can then update a status register (e.g., R08) and allow the PWR_GOOD waveform 438 to float within the time tPMIC_PWR_GOOD_OUT. If the PWR_GOOD waveform 438 is not allowed to float within the time tPMIC_PWR_GOOD_OUT, the host controller 20 can access the status registers of the PMIC 100 for more information. The PMIC 100 may not acknowledge requests from the host controller 20 on the I2C / I3C bus 90 after a VR enable command until the time tPMIC_PWR_GOOD_OUT expires.

[0095] 9, a timing diagram illustrating a power-up sequence when the VR_EN pin is high and there is no bus command before the VIN_Bulk ramp is shown. Timing chart 480 is shown. Timing chart 480 may include waveforms 422-438. Waveforms 422-438 may be similar to waveforms 422-438 shown in connection with FIG. 8.

[0096] Vertical lines 482-490 are shown. The vertical lines 482-490 may correspond to particular timings and / or responses by the PMIC 100. The vertical line 482 may correspond to a low-to-high transition of the VIN_BULK waveform 422. The vertical line 484 may correspond to a low-to-high transition of the VOUT_1.8V waveform 424. The time between the line 482 and the line 484 may be t1.8V_READY. The vertical line 486 may correspond to a low-to-high transition of the VOUT_1.0V waveform 426. The time between the line 484 and the line 486 may be t1.0V_READY.

[0097] The low-to-high transition of the VR_EN waveform 430 may occur before time 482 (e.g., before the ramp-up of the VIN_BULK waveform 422). Line 488 may be after line 486. The time between line 484 and line 488 may be tMANAGEMENT_READY. Line 490 may correspond to the low-to-high transition of the PWR_GOOD waveform 438 (and the low-to-high transition of the SWC waveform 432, the low-to-high transition of the SWB waveform 434, and the low-to-high transition of the SWA waveform 436). The PWR_GOOD waveform 438 may be in an indeterminate state 492 before time 482 (e.g., before VIN_BULK ramps up). The time from time 482 to time 490 may be tVIN_BULK_TO_PWR_GOOD_OUT. There may be cases where there is no VR enable command on the I2C / I3C bus 90.

[0098] 10, a timing diagram illustrating a power-up sequence when the VR_EN pin is high during the VIN_BULK ramp and there is no bus command is shown. Timing chart 520 is shown. Timing chart 520 may include waveforms 422-438. Waveforms 422-438 may be similar to waveforms 422-438 shown in connection with FIG. 8.

[0099] Vertical lines 522-530 are shown. The vertical lines 522-530 may correspond to particular timings and / or responses by the PMIC 100. The vertical line 522 may correspond to a low-to-high transition of the VIN_BULK waveform 422. The vertical line 524 may correspond to a low-to-high transition of the VOUT_1.8V waveform 424. The time between the line 522 and the line 524 may be t1.8V_READY. The vertical line 526 may correspond to a low-to-high transition of the VOUT_1.0V waveform 426. The time between the line 524 and the line 526 may be t1.0V_READY.

[0100] The low-to-high transition of the VR_EN waveform 430 may occur at time 522 (e.g., during the ramp-up of the VIN_BULK waveform 422). Line 528 may be after line 526. The time between line 524 and line 528 may be tMANAGEMENT_READY. Line 530 may correspond to the low-to-high transition of the PWR_GOOD waveform 438 (and after the low-to-high transitions of the SWC waveform 432, the SWB waveform 434, and the SWA waveform 436). The PWR_GOOD waveform 438 may be in an indeterminate state 532 before time 522 (e.g., before VIN_BULK ramps up). The time from time 522 to time 530 may be tVIN_BULK_TO_PWR_GOOD_OUT. There may be no VR enable command on the I2C / I3C bus 90.

[0101] 11, a timing diagram illustrating a power-up sequence of a PMIC with a bus command is shown. Timing chart 580 is shown. Timing chart 580 may include waveforms 422-438. Waveforms 422-438 may be similar to waveforms 422-438 shown in connection with FIG. 8.

[0102] Vertical lines 582-592 are shown. Vertical lines 582-592 may correspond to particular timings and / or responses by the PMIC 100. Vertical line 582 may correspond to a low-to-high transition of the VIN_BULK waveform 422. Vertical line 584 may correspond to a low-to-high transition of the VOUT_1.8V waveform 424. The time between line 582 and line 584 may be t1.8V_READY. Vertical line 586 may correspond to a low-to-high transition of the VOUT_1.0V waveform 426. The time between line 584 and line 586 may be t1.0V_READY.

[0103] Line 588 may be after line 586. The time between line 584 and line 588 may be tMANAGEMENT_READY. Line 590 may correspond to a VR enable command 596 on the I2C / I3C bus 90. The VR enable command 596 may be asserted after the ramp-up of the VIN_BULK waveform 422. After the VR enable command 596, the SWC waveform 432 may transition from low to high, the SWB waveform 434 may transition from low to high, and the SWA waveform 436 may transition from low to high. The PWR_GOOD waveform 438 may transition from low to high after the VR enable command 596 and the transition of the waveforms 432-436 at time 592. The PWR_GOOD waveform 438 may be in an indeterminate state 594 before time 582 (e.g., before VIN_BULK ramps up). The time from time 582 to time 590 may be tVIN_BULK_TO_VR_ENABLE. The time between time 590 and time 592 may be tPMIC_PWR_GOOD_OUT. A section 598 of the VR_EN waveform 430 is shown after the VR enable command 596. After the VR enable command 596, the VR_EN pin going high may have no effect on the operation of the PMIC 100.

[0104] 12, a timing diagram illustrating a power-down sequence when the VR_EN pin is high with the low power status register at a low value in a program mode of operation is shown. A timing chart 620 is shown. The timing chart 620 may include waveforms 422-438. The waveforms 422-438 may be similar to the waveforms 422-438 shown in connection with FIG. 8.

[0105] Vertical lines 622-632 are shown. The vertical lines 622-632 may correspond to particular timings and / or responses by the PMIC 100. The vertical line 622 may correspond to a low-to-high transition of the VIN_BULK waveform 422. The vertical line 624 may correspond to a low-to-high transition of the VOUT_1.8V waveform 424. The time between the line 622 and the line 624 may be t1.8V_READY. The vertical line 626 may correspond to a low-to-high transition of the VOUT_1.0V waveform 426. The time between the line 624 and the line 626 may be t1.0V_READY.

[0106] Line 628 may be after line 586. The time between line 624 and line 628 may be tMANAGEMENT_READY. Line 630 may correspond to the low-to-high transition of the VR_EN waveform 430. The VR_EN waveform 430 may transition to high after the ramp-up of the VIN_BULK waveform 422. After time 630, the SWC waveform 432 may transition from low to high, the SWB waveform 434 may transition from low to high, and the SWA waveform 436 may transition from low to high. The PWR_GOOD waveform 438 may transition from low to high after the transition of the waveforms 432-436 at time 630 and line 632. The PWR_GOOD waveform 438 may be in an indeterminate state 634 before time 622 (e.g., before VIN_BULK ramps up). The time from time 622 to time 630 may be tVIN_BULK_TO_VR_ENABLE. The time between time 630 and time 632 may be tPMIC_PWR_GOOD_OUT. A VR enable command 636 is shown after time 630 when the VR_EN waveform 430 is asserted high. The VR enable command 636 may have no effect on the operation of the PMIC 100 after the signal VR_EN pin is asserted.

[0107] 13, a timing diagram illustrating a power-down sequence when the VR_EN pin is low with the low power status register at a low value in the program mode of operation is shown. Timing chart 650 is shown. Timing chart 650 may include waveforms 422-438. Waveforms 422-438 may be similar to waveforms 422-438 shown in connection with FIG. 8.

[0108] Vertical lines 652-654 are shown. The vertical lines 652-654 may correspond to particular timings and / or responses by the PMIC 100. The vertical line 652 may correspond to a high-to-low transition of the VR_EN waveform 430. The vertical line 654 may correspond to a low-to-high transition of the VR_EN waveform 430.

[0109] The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may each be at a high value. There may be no VR disable command on the bus 90. The register value 104 may be set to 0.

[0110] After time 652, when the VR_EN waveform 430 transitions low, the PWR_GOOD waveform 438 may transition low. Next, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, and then the SWC waveform 432 may transition from high to low. For example, changing the VR_EN waveform 430 (e.g., providing an input) may change the state of the regulators 106a-106n. After time 654, when the VR_EN waveform 430 returns high, the SWC waveform 432 may transition from low to high, then the SWB waveform 434 may transition from low to high, then the SWA waveform 436 may transition from low to high, and then the PWR_GOOD waveform 438 may transition from low to high. For example, changing the VR_EN waveform 430 (e.g., providing an input) may change the state of the regulators 106a-106n.

[0111] Regardless of how regulators 106a-106n are turned on (e.g., using signal VR_EN or a VR enable command on bus 90), regulators 106a-106n may be powered down based on the operating mode (e.g., programmable operating mode or secure operating mode) of PMIC 100. In the programmable operating mode, when register value 104 is set to 0, PMIC 100 can allow host controller 20 to power down any or all of regulators 106a-106n using three different methods.

[0112] In one method, when PMIC 100 is in a programmable operating mode and register value 104 is set to 0, host controller 20 can use a VR disable command (e.g., with register R32[7] set to 0 or signal VR_EN transitioning low) to power down regulators 106a-106n. PMIC 100 can execute one or more power-off sequences according to a configuration (e.g., defined by register R58 and / or defined by register R5A) to preserve the voltage relationships as configured in registers 102a-102n.

[0113] In one example, the PMIC 100 can control the signal PWR_GOOD by providing a VR disable command using the VR_EN pin (e.g., setting the signal VR_EN low). The PMIC 100 can then assert the signal PWR_GOOD low. The host controller 20 can re-enable the output regulators 106a-106n by asserting the signal VR_EN high. The PMIC 100 can perform one or more power-on sequences according to the registers 102a-102n and float the signal PWR_GOOD after the timing parameter tPMIC_PWR_GOOD_OUT is satisfied. The PMIC 100 may not need to be power-cycled.

[0114] In another example, the signal PWR_GOOD can be controlled by the host controller 20, with the PMIC 100 providing a VR disable command using the bus 90 (e.g., with register value R32[7] set to 0). The PMIC 100 can leave the signal PWR_GOOD floating because a fault condition may not exist (e.g., the VR disable command may be an intentional command from the host controller 20). The host controller 20 can re-enable the regulators 106a-106n by issuing a VR enable command on the bus 90 (e.g., with register value R32[7] set to 1). The PMIC 100 can perform one or more power-on sequences according to the registers 102a-102n and continue to float the signal PWR_GOOD until time tPMIC_PWR_GOOD_OUT. The PMIC 100 may then assume normal control of the signal PWR_GOOD (e.g., as shown in connection with FIG. 14).

[0115] In general, simultaneous use of signals VR_EN and VR enable (or VR disable) commands on bus 90 may not be permitted. For example, if signal VR_EN transitions low first, signal PWR_GOOD may follow low and remain low for any subsequent commands on bus 90.

[0116] In another method of controlling the power-down of regulators 106a-n, PMIC 100 can configure one or more bits of registers 102a-n (e.g., bits [6, 4:3] of register R2F) in any particular sequence desired by host controller 20. PMIC 100 cannot execute a power-off sequence without instructions from host controller 20. PMIC 100 can keep signal PWR_GOOD floating because the power-down may be an intentional command from host controller 20 (e.g., not a fault condition). Host controller 20 can re-enable any of disabled regulators 106a-n by configuring one or more bits of registers 102a-n (e.g., bits [6, 4:3] of register R2F) in any particular sequence desired by host controller 20.

[0117] In yet another method for controlling the power-down of the regulators 106a-106n, the registers 102a-102n (e.g., register R32[5] set to 1) can drive the signal PWR_GOOD low. The PMIC 100 can maintain the voltage relationship configured by the registers 102a-102n and execute one or more power-down sequences according to the registers 102a-102n to drive the signal PWR_GOOD low. The PMIC 100 can preserve the contents of all registers 102a-102n (e.g., including the MTP error log register). The host controller 20 can re-enable the regulators 106a-106n by issuing a VR enable command on the bus 90, and the PMIC 100 can execute one or more power-on sequences and float the signal PWR_GOOD after the tPMIC_PWR_GOOD timing parameter is met. The PMIC 100 may not require a power cycle.

[0118] The PMIC 100 can be configured to generate an internal VR disable command at any time in response to one or more events. The PMIC 100 can execute one or more power-off sequences according to the registers 102a-102n to preserve the voltage relationships configured in the registers 102a-102n. The PMIC 100 can then assert the signal PWR_GOOD low. The host controller 20 can re-enable the regulators 106a-106n with a VR enable command (via the signal VR_EN or bus 90), and the PMIC 100 can float the signal PWR_GOOD. The PMIC 100 may not require a power cycle.

[0119] 14, a timing diagram illustrating a power-down sequence when the VR_EN pin is high with the low power status register at a high value in the program mode of operation is shown. A timing chart 680 is shown. The timing chart 680 may include waveforms 422-438. The waveforms 422-438 may be similar to the waveforms 422-438 shown in connection with FIG. 8.

[0120] Vertical lines 682-684 are shown. Vertical lines 682-684 may correspond to particular timing and / or responses by PMIC 100. Vertical line 682 may correspond to a VR disable command on bus 90. Vertical line 684 may correspond to a VR enable command on bus 90.

[0121] The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may each be at a high value. The VR_EN waveform 430 may be held at a static high value. The register value 104 may be set to 0.

[0122] After time 682, when a VR disable command 686 is provided on bus 90, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, and then the SWC waveform 432 may transition from high to low. After time 684, when a VR enable command 688 is provided on bus 90, the SWC waveform 432 may transition from low to high, then the SWB waveform 434 may transition from low to high, and then the SWA waveform 436 may transition from low to high (e.g., may power the switching regulators 106a-106c back on). The PWR_GOOD waveform 438 may be held high regardless of the VR disable command 686 and the VR enable command 688.

[0123] 15, a timing diagram illustrating a power-down sequence when the VR_EN pin is low with the low power status register at a high value in the program mode of operation is shown. A timing diagram 720 is shown. The timing diagram 720 may include waveforms 422-438. The waveforms 422-438 may be similar to the waveforms 422-438 shown in connection with FIG. 8.

[0124] Vertical lines 722-724 are shown. The vertical lines 722-724 may correspond to particular timings and / or responses by the PMIC 100. The vertical line 722 may correspond to a high-to-low transition of the VR_EN waveform 430. The vertical line 724 may correspond to a low-to-high transition of the VR_EN waveform 430.

[0125] The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may each be at a high value. There may be no VR disable command on bus 90. The register value 104 may be set to 1.

[0126] After time 722, when the VR_EN waveform 430 transitions low, the PWR_GOOD waveform 438 may transition from high to low. Next, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, then the SWC waveform 432 may transition from high to low. After the SWC waveform 432 transitions from high to low, the VOUT_1.8V waveform 424 and the VOUT_1.0V waveform 426 may transition from high to low, and the VIN_BULK waveform 422 may remain high.

[0127] At time 724, the VR_EN waveform 430 may transition from low to high. After time 724, when the VR_EN waveform 430 returns high, the VOUT_1.8V waveform 424 may transition from low to high, and then the VOUT_1.0V waveform 426 may transition from low to high. Next, the SWC waveform 432 may transition from low to high, then the SWB waveform 434 may transition from low to high, then the SWA waveform 436 may transition from low to high, and then the PWR_GOOD waveform 438 may transition from low to high.

[0128] Regardless of how regulators 106a-106n are turned on (e.g., using signal VR_EN or a VR enable command on bus 90), regulators 106a-106n may be powered down based on the operating mode (e.g., programmable operating mode or secure operating mode) of PMIC 100. In the programmable operating mode, when register value 104 is set to 1, PMIC 100 can allow host controller 20 to power down any or all of regulators 106a-106n using three different methods.

[0129] In one method, when the PMIC 100 is in the programmable operating mode and register value 104 is set to 1, the host controller 20 can use a VR disable command (e.g., register R32[7] is set to 0 or signal VR_EN transitions low) to power down the regulators 106a-106n. The PMIC 100 can execute one or more power-off sequences according to a configuration (e.g., defined by register R58 and / or defined by register R5A) to preserve the voltage relationships as configured in registers 102a-102n. The PMIC 100 can enter a quiescent P1 power state 388.

[0130] In one example, the PMIC 100 can control the signal PWR_GOOD by providing a VR disable command using the VR_EN pin (e.g., by setting the signal VR_EN low). The PMIC 100 can then assert the signal PWR_GOOD low. The host controller 20 can re-enable the output regulators 106a-106n by asserting the signal VR_EN high. The PMIC 100 can exit the quiescent P1 power state 388 (e.g., move to the idle P3 power state 386). The PMIC 100 can execute one or more power-on sequences according to the registers 102a-102n and float the signal PWR_GOOD after the timing parameter tPMIC_PWR_GOOD_OUT and additional timing parameters are satisfied as shown in the timing diagram 720. The PMIC 100 may not need to be power-cycled.

[0131] In another example, the signal PWR_GOOD can be controlled by the host controller 20, which provides a VR disable command to the PMIC 100 using the bus 90 (e.g., with register value R32[7] set to 0). The PMIC 100 can leave the signal PWR_GOOD floating because a fault condition may not exist (e.g., the VR disable command may be an intentional command from the host controller 20). The PMIC 100 can exit the quiescent P1 power state 388 simply by the signal VR_EN transitioning high. The host controller 20 can re-enable the regulators 106a-106n by asserting the signal VR_EN high. The PMIC 100 can then continue to float the signal PWR_GOOD until it executes one or more power-on sequences according to the registers 102a-102n and adds additional timing parameters to the time tPMIC_PWR_GOOD_OUT. PMIC 100 may then assume normal control of signal PWR_GOOD (eg, as shown in connection with FIG. 16).

[0132] In general, simultaneous use of the signal VR_EN and the VR enable (or VR disable) command on bus 90 is not permitted. For example, if the signal VR_EN transitions low first, the signal PWR_GOOD will follow low and remain low for any subsequent commands on bus 90.

[0133] In another method for controlling the power-down of the regulators 106a-106n, the PMIC 100 can configure one or more bits of the registers 102a-102n (e.g., with bits [6, 4:3] of register R2F set to 0) in any particular sequence desired by the host controller 20. The PMIC 100 cannot execute a power-off sequence without instructions from the host controller 20. The PMIC 100 can keep the signal PWR_GOOD floating because the power-down may be an intentional command from the host controller 20 (e.g., not a fault condition). The host controller 20 can re-enable any of the disabled regulators 106a-106n by configuring one or more bits of the registers 102a-102n (e.g., with bits [6, 4:3] of register R2F set to 1) in any particular sequence desired by the host controller 20. The behavior of the signal PWR_GOOD can be illustrated in connection with FIG. 16.

[0134] In yet another method for controlling the power-down of the regulators 106a-106n, a register 102a-102n (e.g., register R32[5] set to 1) can drive the signal PWR_GOOD low. The PMIC 100 can execute one or more power-down sequences according to the registers 102a-102n to maintain the voltage relationship configured by the registers 102a-102n and drive the signal PWR_GOOD low. The PMIC 100 can preserve the contents of all registers 102a-102n (e.g., including the MTP error log register). The PMIC 100 may not enter the quiescent P1 power state 388. The host controller 20 can re-enable the regulators 106a-106n by issuing a VR enable command on the bus 90 (e.g., by setting register R32[7] to 1), and the PMIC 100 can execute one or more power-on sequences and float the signal PWR_GOOD after the tPMIC_PWR_GOOD timing parameter is met. The PMIC 100 may not require a power cycle.

[0135] The PMIC 100 can be configured to generate an internal VR disable command at any time in response to one or more events. The PMIC 100 can execute one or more power-off sequences according to the registers 102a-102n (e.g., register R58 and register R5A) to preserve the voltage relationships configured in the registers 102a-102n. The PMIC 100 may not enter the quiescent P1 power state 388. The PMIC 100 can then assert the signal PWR_GOOD low. The host controller 20 can re-enable the regulators 106a-106n with a VR enable command (via signal VR_EN or bus 90), and the PMIC 100 can float the signal PWR_GOOD. The PMIC 100 may not require a power cycle.

[0136] 16, a timing diagram illustrating a power-down sequence when the VR_EN pin is high with the low power state register at a low value in a secure mode of operation is shown. Timing chart 780 is shown. Timing chart 780 may include waveforms 422-438. Waveforms 422-438 may be similar to waveforms 422-438 shown in connection with FIG. 8.

[0137] A vertical line 782 is shown. The vertical line 782 may correspond to a particular timing and / or response by the PMIC 100. The vertical line 782 may correspond to a VR disable command generated by the host controller 20 on the bus 90.

[0138] The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may each be at a high value. The VR_EN waveform 430 may not transition before time 782. The register value 104 may be set to 1.

[0139] Before and after time 782, when a VR disable command 784 is on bus 90, the PWR_GOOD waveform 438 remains high. After time 782, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, then the SWC waveform 432 may transition from high to low. After the SWC waveform 432 transitions from high to low, the VOUT_1.8V waveform 424 and the VOUT_1.0V waveform 426 may transition from high to low, and the VIN_BULK waveform 422 may remain high. After time 782, the state of the VR_EN waveform 430 has no effect.

[0140] After time 782, the PMIC 100 is in the quiescent P1 power state 388. A transition 786 of the VR_EN waveform 430 is shown after time 782. The transition 786 may be the VR_EN waveform 430 changing from low to high. The PMIC 100 may exit the quiescent P1 power state when the VR_EN waveform 430 transitions from low to high. After the transition 786, the VOUT_1.8V waveform 424 may transition from low to high, and then the VOUT_1.0V waveform 426 may transition from low to high. Next, the SWC waveform 432 may transition from low to high, then the SWB waveform 434 may transition from low to high, and then the SWA waveform 436 may transition from low to high. The PWR_GOOD waveform 438 may remain static high.

[0141] 17, a timing diagram illustrating a disable or enable command on the bus during a secure mode of operation is shown. A timing chart 830 is shown. The timing chart 830 may include waveforms 422-438. The waveforms 422-438 may be similar to the waveforms 422-438 shown in connection with FIG. 8.

[0142] Vertical lines 832-834 are shown. The vertical lines 832-834 may correspond to particular timing and / or responses by the PMIC 100. The vertical line 832 may correspond to a high-to-low transition of the VR_EN waveform 430. The vertical line 834 may correspond to a low-to-high transition of the VR_EN waveform 430.

[0143] The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may each be at a high value. There may be no VR disable command on the bus 90. The register value 104 may be set to 0.

[0144] After time 832, when the VR_EN waveform 430 transitions low, the PWR_GOOD waveform 438 may transition from high to low. Next, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, and then the SWC waveform 432 may transition from high to low. When the VR_EN waveform 430 transitions from high to low, host controller 20 providing a VR enable or VR disable command on bus 90 may have no effect on the operation of PMIC 100.

[0145] At time 834, the VR_EN waveform 430 may transition from low to high. After time 834, when the VR_EN waveform 430 returns high, the SWC waveform 432 may transition from low to high, then the SWB waveform 434 may transition from low to high, then the SWA waveform 436 may transition from low to high, then the PWR_GOOD waveform 438 may transition from low to high. The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may each remain at a high value.

[0146] Regardless of how regulators 106a-106n are turned on (e.g., using signal VR_EN or a VR enable command on bus 90), regulators 106a-106n may be powered down based on the operating mode (e.g., programmable operating mode or secure operating mode) of PMIC 100. In secure operating mode, when register value 104 is set to 0, PMIC 100 can allow host controller 20 to power down any or all of regulators 106a-106n using two different methods.

[0147] In one method, when the PMIC 100 is in a secure operating mode and the register value 104 is set to 0, the host controller 20 can provide a VR disable command by transitioning the signal VR_EN low. The PMIC 100 can then assert the signal PWR_GOOD low. The PMIC 100 can execute one or more power-down sequences according to the registers 102a-102n (e.g., register R58 and register R5A) to maintain the voltage relationship configured by the registers 102a-102n. The host controller 20 can re-enable the output regulators 106a-106n by asserting the signal VR_EN high. The PMIC 100 can execute one or more power-on sequences according to the registers 102a-102n and float the signal PWR_GOOD after the timing parameter tPMIC_PWR_GOOD_OUT is satisfied. The PMIC 100 may not need to be power-cycled. A VR disable command or a VR enable command on bus 90 (e.g., register value R32[7] set to 0 or 1) may have no effect on PMIC 100. Setting one or more bits (e.g., register value R2F[6,4:3] to 0) may have no effect on PMIC 100 (as shown in connection with FIG. 18).

[0148] Alternatively, when the PMIC 100 is in secure operating mode and the register value 104 is set to 0, the regulators 106a-106n can be powered down by setting the register value R32[5] to 1 and driving the signal PWR_GOOD low. The PMIC 100 can execute one or more power-down sequences according to the registers 102a-102n (e.g., register R58 and / or register R5A) to maintain the voltage relationships configured in the registers 102a-102n. The PMIC 100 can drive the signal PWR_GOOD low and unlock only the register R32. The PMIC 100 may allow the host controller 20 to issue a VR enable command. The PMIC 100 can preserve the contents of all registers 102a-102n (e.g., including the MTP error log register). In secure operating mode, the PMIC 100 can keep all write-protected registers locked (except R32[7]). The host controller 20 can re-enable the regulators 106a-106n by issuing a VR enable command on the bus 90, and the PMIC 100 can execute one or more power-on sequences and float the PWR_GOOD signal after the tPMIC_PWR_GOOD timing parameter is met. After the host controller 20 issues the VR enable command, the PMIC 100 can re-lock the register R32. The PMIC 100 may not require a power cycle to re-enable the output regulators 106a-106n.

[0149] The PMIC 100 can be configured to generate an internal VR disable command at any time in response to one or more events. The PMIC 100 can execute one or more power-off sequences according to the registers 102a-102n to maintain the voltage relationships configured in the registers 102a-102n. The PMIC 100 can then assert the signal PWR_GOOD low. In a secure operating mode, the PMIC 100 may require a power cycle. A VR enable command (e.g., provided on the bus 90 or by the signal VR_EN) may have no effect on the PMIC 100, and the PMIC 100 can keep the signal PWR_GOOD low.

[0150] 18, a timing diagram is shown illustrating a power-down sequence when the VR_EN pin is high and the low power state register is at a high or low value in a secure mode of operation. A timing chart 880 is shown. The timing chart 880 may include waveforms 422-438. The waveforms 422-438 may be similar to the waveforms 422-438 shown in connection with FIG. 8.

[0151] A vertical line 882 is shown. The vertical line 882 may correspond to a particular timing and / or response by the PMIC 100. The vertical line 882 may correspond to a VR disable command on the bus 90.

[0152] The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may each be at a high value. The VR_EN waveform 430 may be at a static high value. Because the VR_EN waveform 430 is held high, a VR disable command 884 or a VR enable command on the bus 90 can have no effect on the PMIC 100. The register value 104 may be set to 0 or 1. The SWC waveform 432, the SWB waveform 434, and the SWA waveform 436 may be on and may be switching. The signal PWR_GOOD may be held high.

[0153] 19, a timing diagram illustrating a power-down sequence using the VR_EN pin with the low power state register at a high value in a secure mode of operation is shown. A timing chart 930 is shown. The timing chart 930 may include waveforms 422-438. The waveforms 422-438 may be similar to the waveforms 422-438 shown in connection with FIG. 8.

[0154] Vertical lines 932-934 are shown. Vertical lines 932-934 may correspond to particular timing and / or responses by the PMIC 100. Vertical line 932 may correspond to a high-to-low transition of the VR_EN waveform 430. Vertical line 934 may correspond to a low-to-high transition of the VR_EN waveform 430.

[0155] The VIN_BULK waveform 422, the VOUT_1.8V waveform 424, and the VOUT_V1.0V waveform 426 may each be at a high value. Also, the SWC waveform 432, the SWB waveform 434, the SWA waveform 436, and the PWR_GOOD waveform 438 may each be at a high value. A VR disable command or a VR enable command on the bus 90 may have no effect. The register value 104 may be set to 1.

[0156] After time 932, when the VR_EN waveform 430 transitions low, the PWR_GOOD waveform 438 may transition from high to low. Next, the SWA waveform 436 may transition from high to low, then the SWB waveform 434 may transition from high to low, then the SWC waveform 432 may transition from high to low. After the SWC waveform 432 transitions low, the VOUT_1.8V waveform 424 and the VOUT_1.0V waveform 426 may transition from high to low.

[0157] At time 934, the VR_EN waveform 430 may transition from low to high. After time 934, when the VR_EN waveform 430 returns high, the VOUT_1.8V waveform 424 and the VOUT_1.0V waveform 426 may transition from low to high. Next, the SWC waveform 432 may transition from low to high, then the SWB waveform 434 may transition from low to high, then the SWA waveform 436 may transition from low to high, and then the PWR_GOOD waveform 438 may transition from low to high.

[0158] Regardless of how regulators 106a-106n are turned on (e.g., using signal VR_EN or a VR enable command on bus 90), regulators 106a-106n may be powered down based on the operating mode (e.g., programmable operating mode or secure operating mode) of PMIC 100. In secure operating mode, when register value 104 is set to 1, PMIC 100 can allow host controller 20 to power down any or all of regulators 106a-106n using two different methods.

[0159] In one method, when the PMIC 100 is in the secure mode of operation and the register value 104 is set to 1, the host controller 20 can provide a VR disable command by transitioning the signal VR_EN low. The PMIC 100 can then assert the signal PWR_GOOD low. The PMIC 100 can execute one or more power-down sequences according to the registers 102a-102n (e.g., register R58 and register R5A) to maintain the voltage relationships configured by the registers 102a-102n. The PMIC 100 can then enter the quiescent P1 power state 388.

[0160] The host controller 20 can re-enable the output regulators 106a-106n by asserting the signal VR_EN high. The PMIC 100 can exit the quiescent P1 power state 388 and move to the idle P3 power state 386. The PMIC 100 can then execute one or more power-on sequences according to the registers 102a-102n and float the signal PWR_GOOD after additional timing parameters are met in addition to the timing parameter tPMIC_PWR_GOOD_OUT. The PMIC 100 may not need to be power-cycled. A VR disable command or a VR enable command on the bus 90 (e.g., register value R32[7] set to 0 or 1) can have no effect on the PMIC 100. Setting one or more bits (e.g., register value R2F[6,4:3] to 0) can have no effect on the PMIC 100 (as shown in connection with FIG. 18).

[0161] Alternatively, when the PMIC 100 is in the secure operating mode and the register value 104 is set to 1, the regulators 106a-106n can be powered down by setting the register value R32[5] to 1 and driving the signal PWR_GOOD low. The PMIC 100 can execute one or more power-down sequences according to the registers 102a-102n (e.g., register R58 and / or register R5A) to maintain the voltage relationships configured in the registers 102a-102n. The PMIC 100 can drive the signal PWR_GOOD low and unlock only the register R32. The PMIC 100 can preserve the contents of all the registers 102a-102n (e.g., including the MTP error log register). In the secure operating mode, the PMIC 100 can keep all write-protected registers (except R32[7]) locked. The PMIC 100 may not enter the quiescent P1 power state 388.

[0162] The host controller 20 can re-enable the regulators 106a-106n by issuing a VR enable command on the bus 90, and the PMIC 100 can execute one or more power-on sequences and float the PWR_GOOD signal after the tPMIC_PWR_GOOD timing parameter is met. After the host controller 20 issues the VR enable command, the PMIC 100 can re-lock the register R32. The PMIC 100 may not require a power cycle to re-enable the output regulators 106a-106n.

[0163] The PMIC 100 can be configured to generate an internal VR disable command at any time in response to one or more events. The PMIC 100 can execute one or more power-off sequences according to the registers 102a-102n to preserve the voltage relationships configured in the registers 102a-102n. The PMIC 100 may not enter the quiescent P1 power state 388. The PMIC 100 can then assert the signal PWR_GOOD low. In a secure operating mode, the PMIC 100 may require a power cycle. A VR enable command (e.g., provided on the bus 90 or by the signal VR_EN) may have no effect on the PMIC 100, and the PMIC 100 can keep the signal PWR_GOOD low.

[0164] The functions performed by the diagrams of Figures 1-19 can be implemented using one or more conventional general-purpose processors, digital computers, microprocessors, microcontrollers, RISC (reduced command set computer) processors, CISC (complex command set computer) processors, SIMD (single command multiple data) processors, signal processors, central processing units (CPUs), arithmetic logic units (ALUs), video digital signal processors (VDSPs), and / or similar computing devices programmed according to the teachings herein, as will be apparent to those skilled in the art. Appropriate software, firmware, coding, routines, commands, opcodes, microcode, and / or program modules can be readily prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those skilled in the art. The software is typically executed from one or more media by one or more processors in a machine implementation.

[0165] The invention may also be implemented by preparing one or more chips or dies arranged as an ASIC (application specific integrated circuit), platform ASIC, FPGA (field programmable gate array), PLD (programmable logic device), CPLD (complex programmable logic device), sea of ​​gates, RFIC (radio frequency integrated circuit), ASSP (application specific standard product), one or more monolithic integrated circuits, flip-chip module and / or multi-chip module, or by interconnecting an appropriate network of conventional component circuits, as described herein, modifications and variations of which will be readily apparent to those skilled in the art.

[0166] Accordingly, the present invention may also include a computer product, which may be one or more storage media and / or one or more transmission media containing instructions that can be used to program a machine to perform one or more processes or methods according to the present invention. Execution of the instructions contained in the computer product by the machine, together with operation of peripheral circuitry, may convert input data into one or more output signals representing a physical object or substance, such as one or more files on the storage medium, and / or audio and / or visual depictions. Storage media include, but are not limited to, any type of disk, including floppy disks, hard drives, magnetic disks, optical disks, CD-ROMs, DVDs, and magneto-optical disks, as well as circuits such as ROM (read-only memory), RAM (random access memory), EPROM (erasable programmable ROM), EEPROM (electrically erasable programmable ROM), UVPROM (ultraviolet erasable programmable ROM), flash memory, magnetic cards, optical cards, and / or any type of medium suitable for storing electronic commands.

[0167] Elements of the present invention may form part or all of one or more devices, units, components, systems, machines, and / or apparatuses. Devices may include, but are not limited to, servers, workstations, storage array controllers, storage systems, personal computers, laptop computers, notebook computers, palm computers, cloud servers, personal digital assistants, portable electronic devices, battery-powered devices, set-top boxes, encoders, decoders, transcoders, compressors, decompressors, pre-processors, post-processors, transmitters, receivers, transceivers, mobile phones, digital cameras, positioning and / or navigation systems, medical equipment, heads-up displays, wireless devices, audio recording, audio storage and / or audio playback devices, video recording, video storage and / or video playback devices, gaming platforms, peripherals, and / or multi-chip modules. Those skilled in the art will appreciate that elements of the present invention may be implemented in other types of apparatuses to meet the criteria of a particular application.

[0168] The various signals of the present invention are generally "on" (e.g., digital high (HIGH), or 1) or "off" (e.g., digital low (LOW), or 0). However, the particular polarity of the on (e.g., asserted) and off (e.g., deasserted) states of the signals may be adjusted (e.g., inverted) to meet the design criteria of a particular implementation. Additionally, inverters can be added to change the particular polarity of the signals.

[0169] The terms "may," "can," "could," "could," "might," "could," "may," and "generally," when used herein in conjunction with "is(are)" and a verb, are meant to convey the intention that the description is exemplary and is considered broad enough to encompass both the specific examples provided in the disclosure as well as alternative examples that can be derived based on the disclosure. The terms "may," "generally," and the like, as used herein, should not be construed as necessarily implying the desirability or possibility of omitting the corresponding element.

[0170] While the present invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various modifications and changes in form and detail may be made therein without departing from the scope of the invention.

Claims

1. A power enable pin, Bus and an integrated circuit having a power output configured to supply power to components of a device and a power input source supplying current to the power output, the integrated circuit having a plurality of power states including at least a low power state in which the power input source draws a first non-zero level of current and the power output is off, and an idle state in which the power input source draws a second level of current greater than the first level and the power output is on, supplying power to components of the device; An apparatus comprising: the integrated circuit is configured to independently transition from the low power state to the idle state based at least in part on either (a) a change in value of a signal received via the power enable pin, or (b) receipt of a command via the bus to cause the integrated circuit to enter the idle state; the plurality of power states further includes a third power state; the apparatus further comprising a register including a plurality of bits, a predetermined bit of the plurality of bits corresponding to the third power state; the integrated circuit is configured to (c) transition from the idle state to the third power state based at least in part on the value of the predetermined bit; Device.

2. 10. The apparatus of claim 1, the integrated circuit is configured to transition from the idle state to the third power state based at least in part on (c) the value of the predetermined bit and (a) a change in the value of a signal received via the power enable pin; Device.

3. 10. The apparatus of claim 1, the integrated circuit is configured to transition from the idle state to the third power state based at least in part on (c) the value of the predetermined bit and (d) receipt of a command over the bus to cause the integrated circuit to enter the third power state. Device.

4. 10. The apparatus of claim 1, the integrated circuit is configured to transition from the third power state to the idle state based at least in part on (c) the value of the predetermined bit and (a) a change in the value of a signal received via the power enable pin. Device.

5. 10. The apparatus of claim 1, the power output unit includes a plurality of regulators; the plurality of regulators are turned off when the integrated circuit is in the low power state and turned on when the integrated circuit is in the idle state; Device.

6. 10. The apparatus of claim 1, the apparatus comprises a plurality of registers, each register containing a plurality of bits; a specific bit in a specific register among the plurality of registers corresponds to a secure mode of operation of the integrated circuit; the integrated circuit is configured to operate in the secure mode of operation based at least in part on the value of the particular bit; the secure operation mode is a mode in which modification of at least some of the plurality of registers is prohibited; Device.

7. 7. The apparatus of claim 6, When the integrated circuit operates in the secure mode of operation, it allows modification of the plurality of registers during a power-on operation prior to receiving a power enable command, enables the power output unit to supply power to components of the device based at least in part on the power enable command, and prohibits modification of at least some of the plurality of registers after receiving the power enable command. Device.

8. 8. The apparatus of claim 7, the power enable command being provided by either (a) a change in value of a signal received via the power enable pin, or (b) receipt of a command via the bus to cause the integrated circuit to enter the idle state; Device.

9. 10. The apparatus of claim 1, the power enable pin is implemented as an input configured to control the state of the power output; Device.

10. 10. The apparatus of claim 1, In the low power state, the device is configured to operate with the power outlet turned off and access to the bus disabled; In the idle state, the device is configured to turn on the power output with a 0 A load and enable access to the bus. Device.

11. 10. The apparatus of claim 1, the integrated circuit is configured to transition from the idle state to the low power state based at least in part on either (a) a change in value of a signal received via the power enable pin, or (e) receipt of a command via the bus to cause the integrated circuit to enter the low power state. Device.

12. A power enable pin, an integrated circuit having a power output configured to supply power to components of a device and a power input source supplying current to the power output, the integrated circuit having a plurality of power states including at least a low power state in which the power input source draws a first non-zero level of current and the power output is off, and an idle state in which the power input source draws a second level of current greater than the first level and the power output is on, supplying power to components of the device; a plurality of registers each containing a plurality of bits; An apparatus comprising: a predetermined bit of the plurality of bits corresponds to the low power state; a particular register among the plurality of registers includes a particular bit corresponding to a secure mode of operation of the integrated circuit; the integrated circuit is configured to operate in the secure mode of operation based at least in part on a value of the particular bit of the particular register; the secure operation mode is a mode in which changes to at least some of the plurality of registers are prohibited; the integrated circuit is configured to transition from the low power state to the idle state based at least in part on (a) a change in value of a signal received via the power enable pin and (b) the value of the predetermined bit. Device.

13. 13. The apparatus of claim 12, the integrated circuit is configured to transition from the idle state to the low power state based at least in part on (a) a change in value of a signal received via the power enable pin and (c) the value of the predetermined bit. Device.

14. 13. The apparatus of claim 12, the power output unit includes a plurality of regulators; the plurality of regulators are turned off when the integrated circuit is in the low power state and turned on when the integrated circuit is in the idle state; Device.

15. 13. The apparatus of claim 12, the device further comprises a bus; the integrated circuit is configured to transition from the idle state to the low power state based at least in part on (b) the value of the predetermined bit and (c) receipt of a command over the bus to cause the integrated circuit to enter the low power state. Device.

16. 13. The apparatus of claim 12, When the integrated circuit operates in the secure mode of operation, the integrated circuit allows modification of the plurality of registers during a power-on operation before receiving a power enable command, controls power supply to components of the device by the power output unit to be turned on based at least in part on the power enable command, and prohibits modification of at least some of the plurality of registers after receiving the power enable command. Device.

17. 17. The apparatus of claim 16, the device further comprises a bus; the power enable command being provided by either (a) a change in value of a signal received via a power enable pin, or (d) receipt of a command via the bus to cause the integrated circuit to enter the idle state; Device.

18. 13. The apparatus of claim 12, the power enable pin is implemented as an input configured to control the state of the power output; Device.

19. 13. The apparatus of claim 12, the device further comprises a bus; In the low power state, the device is configured to operate with the power outlet turned off and access to the bus disabled; In the idle state, the device is configured to turn on the power output with a 0 A load and enable access to the bus. Device.

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