III-V / Si hybrid MOS optical modulator with traveling-wave electrodes

Abstract

III-V / Si hybrid MOS optical modulator with traveling wave electrodes. A III-V / Si hybrid MOS optical modulator with traveling wave electrodes for high efficiency and high bandwidth optical modulation is disclosed. The III-V / Si hybrid MOS optical modulator with traveling wave electrodes is a traveling wave modulator. The traveling wave modulator includes a III-V compound semiconductor layer, a silicon layer, and an oxide layer between the III-V compound semiconductor layer and the silicon layer. The traveling wave modulator includes at least one first metal layer, at least one second metal layer, and a semiconductor layer. The electrode trace width of each second metal layer and the spacing between adjacent second metal layers are adjusted to achieve impedance and velocity matching. The traveling wave electrodes are designed to be integrated with the III-V / Si hybrid MOS optical modulator under forward and reverse bias.

Description

[Technical Field]

[0001] This disclosure generally relates to a III-V compound semiconductor and silicon (Si) hybrid metal-oxide-semiconductor (MOS) optical modulator with traveling-wave electrodes, which uses a series-push-pull (SPP) driving scheme to mitigate the effect of large capacitance for high-speed modulation. [Background technology]

[0002] III-V compound semiconductors are alloys containing elements from groups III and V of the periodic table. Among III-V semiconductors is a subset of nitride semiconductors. III-V / Si hybrid metal-oxide-semiconductor (MOS) optical modulators are promising for high-efficiency, low-energy, and high-speed optical modulation. However, because MOS optical modulators have large oxide capacitances and impedance and speed matching is difficult, no III-V / Si hybrid MOS optical modulators using traveling-wave electrodes have been demonstrated.

[0003] There is a trade-off between modulation efficiency and modulation bandwidth. Currently, MOS optical modulators are mainly equipped with lumped electrodes. The large oxide capacitance limits the modulation bandwidth, especially under forward bias. When the modulation bandwidth reaches 30 GHz, parasitic effects from the metal pad and substrate become significant, further limiting the achievable modulation bandwidth. The large oxide capacitance also poses a challenge in the design of traveling-wave electrodes, because it is difficult to achieve speed and impedance matching with excessive load capacitance.

[0004] The following modulators are disclosed in the current state of the art and in the published literature: High-speed silicon optical modulator using metal oxide semiconductor capacitor. In this prior art, the modulator has a Poly-Si / Si MOS structure, the electrodes are concentrated, the bandwidth is about 1 GHz, and the phase shifter length is 2.5 mm. A high-speed, high-efficiency MOS junction Si optical modulator using solid-phase crystallization of polycrystalline silicon, a high-performance MOS capacitive Si optical modulator for optical wiring, and a surface-illuminated Ge photodetector. The modulator has a Poly-Si / Si MOS structure, a concentrated electrode, a bandwidth of approximately 4 GHz to 7 GHz, and a phase shifter length of 200 μm. High bandwidth and capacitance efficiency silicon MOS modulator. The modulator has a Poly-Si / Si MOS structure, the electrodes are concentrated, the bandwidth is over 35GHz, and the phase shifter length is 200μm. This is a low-power 300mm silicon photonics platform integrated with a SiGe-enhanced Si capacitive modulator. The modulator has a Poly-Si / SiGe MOS structure with concentrated electrodes, a bandwidth of approximately 4GHz, and a phase shifter length of 700μm. This is a 30GHz heterogeneously integrated capacitance InP-on-Si Mach-Zehnder modulator. In this prior art, the modulator has an InP / Si MOS structure, the electrodes are concentrated, the bandwidth is approximately 11 (30) GHz, and the phase shifter length is 500 (200) μm. Heterogeneously integrated III-V / Si MOS capacitive Mach-Zehnder modulator. In this prior art, the modulator has an InGaAsP MOS structure, lumped electrodes, a bandwidth of approximately 2.2 GHz, and a phase shifter length of 250 μm. Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, the modulation bandwidth of conventional MOS optical modulators with large oxide capacitance is limited. When the modulation frequency exceeds 30 GHz, the parasitic effects of the metal pads and substrate become significant, further limiting the modulation bandwidth.

[0006] Therefore, there is a demand for a III-V / Si hybrid MOS optical modulator using traveling wave electrodes that can simultaneously achieve high modulation efficiency and a wide modulation bandwidth. [Means for solving the problem]

[0007] The following summary is provided to facilitate an understanding of some of the innovative features unique to the disclosed embodiments and is not intended to be a complete description. A complete understanding of the various aspects of the embodiments disclosed herein can be obtained by considering the specification, claims, drawings, and abstract as a whole.

[0008] In a first aspect of the present disclosure, a III-V / Si hybrid MOS optical modulator comprises a traveling wave electrode including first and second metal layers functioning as traveling wave electrodes, a III-V compound semiconductor layer, a silicon layer, and an oxide layer between the III-V compound semiconductor layer and the silicon layer, the thickness of the oxide layer being designed to enable impedance and speed matching of the modulator.

[0009] According to a first aspect of the present disclosure, the device further includes at least one first connector and at least one second connector.

[0010] According to a first aspect of the present disclosure, the traveling wave electrodes are driven by a series-push-pull (SPP) driving scheme.

[0011] According to a first aspect of the present disclosure, the first metal layer includes three metal portions spaced apart from one another.

[0012] According to a first aspect of the present disclosure, the second metal layer includes two metal portions spaced apart from each other.

[0013] According to the first aspect of the present disclosure, the spacing between adjacent second metal portions is approximately 5 μm to approximately 60 μm.

[0014] According to the first embodiment of the present disclosure, the oxide layer has a thickness of about 5 nm to about 50 nm.

[0015] According to the first aspect of the present disclosure, the III-V compound semiconductor layer is made of InGaAsP, InP, or other III-V compound materials with strong photoelectric effect.

[0016] In a second aspect of the present disclosure, a method for obtaining design parameters for fabricating a III-V / Si hybrid MOS optical modulator with traveling-wave electrodes includes the steps of fabricating a III-V compound semiconductor layer and a silicon layer, with an oxide layer between the III-V compound semiconductor layer and the silicon layer, fabricating a first connector connecting to the semiconductor layer, fabricating a first metal layer connecting to the first connector, fabricating a second connector connecting to the first metal layer, and fabricating a second metal layer connecting to the second connector, wherein the thickness of the oxide layer is designed to enable impedance and velocity matching of the modulator. The thickness of the oxide layer affects the resulting modulation efficiency and bandwidth. That is, if the oxide layer is too thin or too thick, impedance and velocity matching cannot be achieved.

[0017] According to a second aspect of the present disclosure, the traveling wave electrodes are driven by a series-push-pull (SPP) driving scheme.

[0018] According to a second aspect of the present disclosure, the first metal layer includes three first metal portions spaced apart from one another.

[0019] According to a second aspect of the present disclosure, the second metal layer includes two second metal portions spaced apart from each other.

[0020] According to a second aspect of the present disclosure, each second metal portion has a spacing between adjacent second metal portions of about 5 μm to about 60 μm.

[0021] According to a second aspect of the present disclosure, the oxide layer has a thickness of about 5 nm to about 50 nm. [Brief explanation of the drawings]

[0022] [Figure 1] Schematic diagram of a III-V / Si hybrid MOS optical modulator with traveling wave electrodes and an SPP driving scheme.

[0023] [Figure 2]FIG. 1 is a block diagram showing the various elements and processes involved in a simulation to obtain design parameters for a traveling wave electrode of a III-V / Si hybrid MOS optical modulator.

[0024] [Figure 3] Schematic diagram of a III-V / Si hybrid MOS optical modulator operating under forward bias.

[0025] [Figure 4] Schematic diagram of a III-V / Si hybrid MOS optical modulator operating under reverse bias.

[0026] [Figure 5A] 1 is a characteristic impedance graph plotted with electrode spacing along the X-axis and electrode trace width along the Y-axis during carrier collection under forward bias.

[0027] [Figure 5B] 1 is a microwave refractive index graph plotted with electrode spacing along the X-axis and electrode trace width along the Y-axis during carrier accommodation under forward bias.

[0028] [Figure 6A] 1 is a characteristic impedance graph plotted with electrode spacing along the X-axis and electrode trace width along the Y-axis during carrier depletion under reverse bias.

[0029] [Figure 6B] 1 is a microwave refractive index graph plotted with electrode spacing along the X-axis and electrode trace width along the Y-axis during carrier depletion under reverse bias.

[0030] [Figure 7A] 1 is a simulated modulation bandwidth graph plotted with frequency along the X-axis and S-21 response along the Y-axis during carrier acquisition under forward bias.

[0031] [Figure 7B] 10 is another simulated modulation bandwidth graph plotted with frequency along the X-axis and S-21 response along the Y-axis during carrier acquisition under forward bias.

[0032] [Figure 7C] 1 shows a simulated modulation bandwidth graph plotted with acoustic level along the X-axis and frequency along the Y-axis during carrier depletion in reverse bias.

[0033] [Figure 7D] 10 shows another simulated modulation bandwidth graph plotted with frequency along the X-axis and S-21 response along the Y-axis during depletion in reverse bias.

[0034] [Figure 8] 1 shows a flowchart of an exemplary process for obtaining design parameters for fabricating traveling wave electrodes used in III-V / Si hybrid MOS optical modulators.

[0035] [Figure 9] 1 shows a flowchart of an exemplary process for achieving electrode width and spacing design to achieve impedance and velocity matching for a traveling wave modulator. DETAILED DESCRIPTION OF THE INVENTION

[0036] The foregoing summary, as well as the following detailed description of exemplary embodiments, will be better understood when read in conjunction with the accompanying drawings. For the purpose of illustrating the disclosure, exemplary configurations of the disclosure are shown in the drawings. However, the disclosure is not limited to the particular methods and instrumentalities disclosed herein. Moreover, those skilled in the art will appreciate that the drawings are not to scale. Wherever possible, similar elements will be designated by the same numerals.

[0037] The specific configurations discussed in the following description are non-limiting examples that may be modified and are cited merely to illustrate at least one embodiment and are not intended to limit its scope.

[0038] 1 shows a schematic diagram of a III-V / Si hybrid MOS optical modulator having traveling-wave electrodes driven by a series-push-pull (SPP) scheme. A cross-sectional view 100 illustrates exemplary design parameters for the various layers and component orientations relative to one another in providing traveling-wave electrodes used in a III-V / Si hybrid MOS optical modulator with desired characteristics and properties. The provided modulator disclosed herein may also be referred to as a traveling-wave modulator.

[0039] In one embodiment, a modulator disclosed herein may include at least one semiconductor layer 112, at least one first metal layer 108, and at least one second metal layer 102 arranged in a predetermined manner as shown in Figure 1. At least one first connector 110 may connect the first metal layer 108 and the semiconductor layer 112. At least one second connector 104 may connect the first metal layer 108 and the second metal layer 102.

[0040] The semiconductor layer 112 may include a silicon layer 103, an oxide layer 126, and a III-V compound semiconductor layer 101 to form an oxide capacitor. The first metal layer 108, the second metal layer 102, and the semiconductor layer 112 may be arranged and configured to simultaneously achieve impedance and velocity matching of the traveling wave modulator.

[0041] In one embodiment, the oxide layer 126 separates the III-V semiconductor layer 101 and the silicon layer 103, whereby the modulators disclosed herein can be provided with oxide filled to fill the space or gap between the III-V semiconductor layer 101 and the silicon layer 103, providing the oxide layer 126.

[0042] In one embodiment, the first metal layer 108 may include three spaced-apart first metal portions 108a, 108b, 108c. The two distal metal portions 108a, 108c may be positioned with overlapping portions at opposite ends of and connected to the semiconductor layer 112. The remaining metal portion 108b may be positioned proximal and central to the semiconductor layer 112. In this embodiment, three connectors 110 may be used to connect the three metal portions of the first metal layer 108 to the semiconductor layer 112.

[0043] In one embodiment, the second metal layer 102 may include two second metal portions 102 a, 102 b spaced apart from one another. Each of the two metal portions 102 a, 102 b may be positioned to overlap and connect to one of the distal metal portions 108 a, 108 c. In this embodiment, two connectors 104 may be used to connect the two metal portions of the second metal layer 102 to the two distal metal portions of the first metal layer 108.

[0044] In one embodiment, the second metal portions 102a, 102b may have trace widths 120, 124 and spacing 122 between adjacent second metal portions.

[0045] To achieve impedance and speed matching in a MOS traveling-wave optical modulator, the widths 120 and 124, spacing 122, and thickness of the oxide layer (i.e., gap) 126 between the III-V semiconductor layer 101 and the silicon layer 103 are important factors to consider. The measurements 120, 122, and 124 can each vary from 20 μm to 130 μm, depending on the oxide capacitance, which is determined by the thickness of the oxide layer 126. In one embodiment, spacing 122 can range from 5 μm to 60 μm. In one embodiment, spacing 122 can be selected from approximately 20 μm, 30 μm, 40 μm, or 50 μm. For a carrier accumulation mode with an oxide layer thickness of 45 nm, the widths 120 and 124 change linearly from 46.7 μm to 126.7 μm as spacing 122 increases from 20 μm to 50 μm. For carrier depletion mode with an oxide layer thickness of 10 nm, the widths 120 and 124 change linearly from 27.1 μm to 119.5 μm as the spacing 122 increases from 20 μm to 50 μm.

[0046] The thickness of the oxide layer can be sufficient to allow impedance and velocity matching. The thickness of the oxide layer 126 (i.e., the gap between 101 and 103) can vary from 5 nm to 100 nm, preferably from 5 nm to 50 nm. In one embodiment for carrier depletion mode using a reverse bias, the oxide layer thickness is about 10 nm. In one embodiment for carrier accumulation mode using a forward bias, the oxide layer thickness is about 45 nm.

[0047] Using the series-push-pull (SPP) drive scheme 100, the trace width 120 and / or 124 of each second metal portion (102a and 102b) and the spacing 122 between adjacent second metal portions can be adjusted by changing the positions of the first connector 110 and the second connector 104. The central first metal portion 108b can be used to provide electrical bias to the III-V / Si hybrid MOS optical phase shifters on the left and right sides of 108b. By applying a microwave modulation signal to the second metal portions 102a and 102b, the modulation signal can be evenly distributed to the two III-V / Si hybrid MOS optical phase shifters. By connecting two III-V / Si hybrid MOS optical phase shifters in series, the total equivalent capacitance can be halved. The specified structure allows for impedance and velocity matching of the traveling-wave modulators. In one embodiment of the present invention, the large oxide capacitance is halved by using SPP drive, which allows for impedance and velocity matching of the traveling-wave modulators. Impedance and velocity matching allows for modulation bandwidths exceeding 60 GHz with small bias voltages, so the spacing and trace width of the traveling wave electrodes are important design parameters.

[0048] The III-V / Si hybrid MOS optical modulator disclosed herein can be designed taking into account the distance between the connector and the metal layer, the width of the doped regions 111a and 111b, and the spacing 122 between adjacent second metal portions within the same second metal layer. In this regard, the doped regions are located within the silicon region 103, whereby the width of the doped regions 111a and 111b can be 3 μm to 6 μm. The distance between the connector and the metal layer and the spacing between adjacent metal portions are limited by the lithography used in fabrication and can range from 1 to 90 μm. The spacing and trace width within the second metal layer, as well as the thickness of the oxide layer, can be designed to achieve impedance and speed matching. The SPP driving scheme reduces capacitance by half, enabling impedance and speed matching.

[0049] FIG. 2 shows a block diagram 200 illustrating the various elements and processes involved in a simulation to obtain design parameters for traveling-wave electrodes of a III-V / Si hybrid MOS optical modulator. The HFSS simulation process begins in step 202, where HFSS is used to simulate various electrode designs with different spacings and widths. Attenuation, refractive index, Z, and S-parameters are obtained in step 206. The data from step 206 is then used to build an RLGC model in step 214. A Silvaco simulation is performed, as in step 208, to obtain an RC model of the III-V / Si hybrid MOS optical phase shifter, as in step 218. This step can also be performed numerically, as in step 212. The unloaded RLGC model is loaded with the RC model of the III-V / Si hybrid MOS phase shifter. The loaded RLGC model generates an electrode design to match Z and n, as in steps 220 and 222. As in steps 224 and 226, a full-stack HFSS simulation of the III-V / Si hybrid MOS optical modulator is performed to obtain the corresponding 3-dB modulation bandwidth. This simulation flow provides different characteristic impedances Z0 and refractive index n by varying the electrode width and spacing. The impedance-velocity matching condition is achieved when Z0 is close to 50 Ω and n is close to 3.7, the optical group index. Under the impedance-velocity matching condition, a large 3-dB modulation bandwidth is expected. Using this simulation flow, the relationship between electrode width and spacing that enables impedance and velocity matching of the modulator is obtained.

[0050] Figure 3 shows a schematic diagram of a III-V / Si hybrid MOS optical modulator 300, consistent with the modulator of Figure 1, operating under forward bias. Shown in Figures 3 and 4 are the n-III-V material 302, the p-Si material 304, and the oxide layer 303. Figure 3 shows the modulator under forward bias (electric field E 308). 306 and 310 are electrons and holes in the n-III-V and p-Si materials, respectively. III-V / Si hybrid MOS optical modulators under forward bias exhibit high modulation efficiency (V depending on oxide thickness) due to efficient free carrier dispersion effects in the III-V material. π L<0.1Vcm).

[0051] As shown in Figure 4, the modulator 300 is driven under reverse bias. Note that the present invention can operate not only under reverse bias (electric field E308) using carrier depletion and the FK effect for optical modulation, but also under forward bias using carrier accumulation. The present invention provides a design for a traveling-wave electrode with an SPP drive method that alleviates the effects of large capacitance for high-speed modulation. Note that Figures 3 and 4 explain the modulation mechanism by free carriers and are not directly related to the design of traveling-wave electrodes.

[0052] 5A shows a characteristic impedance graph 402 of a III-V / Si hybrid MOS optical modulator under forward bias, plotted with electrode spacing along the X-axis and electrode trace width along the Y-axis when accommodating carriers. ox Figure 5B shows the simulation results for a III-V / Si hybrid MOS optical modulator with a rf = 45 nm. Figure 5B shows a microwave index graph 404 for a III-V / Si hybrid MOS optical modulator under forward bias, plotted with the electrode spacing along the X-axis and the electrode trace width along the Y-axis during carrier accommodation under forward bias. The relationship between electrode spacing (S) and width (W) that allows impedance and velocity matching is W = 2.667 × S - 6.67. Regions 401 and 403 indicate the locations where impedance and velocity matching are simultaneously achieved.

[0053] 6A shows a characteristic impedance graph 502 of a III-V / Si hybrid MOS optical modulator under reverse bias, plotted with electrode spacing along the X-axis and electrode trace width along the Y-axis during carrier depletion. ox Figure 6B shows the simulation results for a III-V / Si hybrid MOS optical modulator with a r = 10 nm. Figure 6B shows a microwave index graph 504 of a III-V / Si hybrid MOS optical modulator under reverse bias, plotted with electrode spacing along the X-axis and electrode trace width along the Y-axis during carrier depletion. The relationship between electrode spacing (S) and width (W) that allows impedance and velocity matching is W = 3.08 × S - 34.47. Regions 501 and 503 represent locations where impedance and velocity matching are simultaneously achieved.

[0054] Figure 7A shows the oxide layer thickness of 45 nm and V π 6 shows a simulated graph 602 of modulation bandwidth plotted with frequency along the X-axis and S-21 response along the Y-axis when carrier accommodation is at a forward bias of L=0.6Vcm. The graph shows a phase shifter length of 0.5mm, V π =12V, V pp = 4.8 V, the 3-dB modulation bandwidth is 57 GHz. π is the voltage required for a π phase shift, and V pp is the voltage swing of the modulation signal. Graphs 603, 604, 605, and 606 are plotted at Gap20, Gap30, Gap40, and Gap50, which correspond to electrode spacings of 20 μm, 30 μm, 40 μm, and 50 μm, respectively.

[0055] Figure 7B shows the oxide layer thickness of 45 nm and V π 6 shows another simulated modulation bandwidth graph 612 plotted with frequency along the X-axis and S-21 response along the Y-axis during carrier capture at a forward bias of L=0.6 Vcm. The graph shows that the 3-dB modulation bandwidth is π = 6V, and V ppGraphs 613, 614, 615, and 616 are plotted at Gap 20, Gap 30, Gap 40, and Gap 50.

[0056] Figure 7C shows the results for oxide layers with a thickness of 10 nm and V π 6 shows a simulated modulation bandwidth graph 622 plotted with frequency along the X-axis and S-21 response along the Y-axis during carrier depletion at a reverse bias of L=0.15 Vcm. The graph shows that the 3-dB modulation bandwidth is π = 3V, and V pp = 1.2 V and 63 GHz. Graphs 623, 624, 625 and 626 are plotted at Gap 20, Gap 30, Gap 40 and Gap 50.

[0057] Figure 7D shows the oxide layer thickness of 45 nm and V π 6 shows another simulated modulation bandwidth graph 632 plotted with frequency along the X-axis and S-21 response along the Y-axis during depletion at reverse bias of L=0.6Vcm. The graph shows a phase shifter length of 1mm, V π =1.5V, V pp Graphs 633, 634, 635, and 636 are plotted for Gap20, Gap30, Gap40, and Gap50.

[0058] FIG. 8 shows a flowchart of an exemplary process 800 for achieving a structure for fabricating traveling-wave electrodes used in a III-V / Si hybrid MOS optical modulator. First, a semiconductor layer is fabricated in step 802. In this step, the thickness of the oxide layer between the III-V layer and the Si layer is controlled to obtain a designed capacitance. In step 804, a first connector connected to the semiconductor layer is fabricated. Next, a first metal layer connected to the first connector is fabricated in step 806. Next, a second connector connected to the first metal layer is fabricated in step 808. Next, a second metal layer connected to the second connector is fabricated in step 810. The width of the second metal portion in the second layer and the spacing between adjacent second metal portions in the second layer are determined by simulation. A series-push-pull (SPP) driving scheme halves the large oxide capacitance, enabling impedance and speed matching.

[0059] 9 shows a flowchart of an exemplary process 850 for obtaining an electrode design to achieve impedance and velocity matching of a traveling-wave modulator. As in step 852, at least one electrode design is input into an unloaded resistance, inductance, conductance, and capacitance (RLGC) model. Then, as in step 854, the RLGC model is loaded with a resistance-capacitance (RC) model of a III-V / Si hybrid MOS phase shifter. Next, as in step 856, at least one design parameter for fabricating a traveling-wave electrode is obtained. As in step 858, a full-stack structure is simulated in a high-frequency structure simulator using the design parameters. As in step 860, the 3-dB modulation bandwidth of the modulator is obtained.

[0060] III-V / Si hybrid metal-oxide-semiconductor (MOS) optical modulators are promising for high-efficiency, low-energy, and high-speed optical modulation. However, traveling-wave electrodes have not been demonstrated in this type of modulator due to the large oxide capacitance that makes impedance and velocity matching difficult. This invention discloses a traveling-wave electrode design for III-V / Si hybrid MOS optical modulators. By using a series-push-pull (SPP) configuration and a different biasing scheme, we achieve impedance and velocity matching and realize a modulation bandwidth of over 60 GHz with a small bias voltage.

[0061] The high modulation efficiency of the III-V / Si hybrid MOS optical modulator enables a short optical phase shifter length with low drive voltage. The short phase shifter length results in low RF loss and high modulation bandwidth. The SPP drive method reduces the element capacitance by half and enables impedance and speed matching.

[0062] In particular, the traveling wave electrode was designed to be integrated with a III-V / Si hybrid MOS optical modulator under forward (carrier accumulation) and reverse (carrier depletion) bias conditions. Table 1 below shows various parameters of the traveling wave electrode under forward and reverse bias conditions. In Table 1 below, EOT is the oxide thickness, L is the phase shifter length, and V is the phase shifter length. π is the voltage required for the π phase shifter, V π L is V π and L, V pp is the driving peak-to-peak voltage, f 3dB is the 3-dB modulation bandwidth. By adjusting the electrode wiring width and metal electrode spacing to predetermined values, along with other parameters and biasing methods, we realized a structure that matches the impedance and speed of the traveling-wave modulator. [Table 1] Table 1

[0063] This invention describes the design of traveling-wave electrodes for III-V / Si hybrid MOS optical modulators. The proposed technology is also applicable to other optical modulators based on metal-oxide-semiconductor (MOS) or semiconductor-insulator-semiconductor (SIS) capacitors, such as SiGe / Si or poly-Si / Si. The III-V materials of this invention are not limited to InGaAsP, InP, or other III-V compound materials with strong optical-electrical effects. The traveling-wave electrodes designed for III-V / Si hybrid MOS optical modulators enable larger modulation bandwidths and overcome the RC limitations imposed by lumped electrodes. A bandwidth exceeding 60 GHz is predicted with a phase shifter as short as 500 mm.

[0064] It will be appreciated that variations of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications, and various presently unforeseen or unanticipated alternatives, modifications, variations or improvements thereon may subsequently occur to those skilled in the art, which are also intended to be encompassed by the following claims.

[0065] Although embodiments of the present disclosure have been described in considerable detail and comprehensively to cover possible aspects, those skilled in the art will recognize that other versions of the present disclosure are possible.

Claims

1. A III-V / Si hybrid MOS optical modulator having traveling wave electrodes, first and second metal layers that function as traveling wave electrodes; a III-V compound semiconductor layer and a silicon layer; an oxide layer between the III-V compound semiconductor layer and the silicon layer; the thickness of the oxide layer is designed to allow impedance and speed matching of the modulator; the first metal layer includes three first metal portions separated from one another; The second metal layer includes two second metal portions spaced apart from each other.

2. The modulator of claim 1 further comprising at least one first connector and at least one second connector.

3. 2. The modulator of claim 1, wherein the traveling wave electrodes are driven by a series-push-pull (SPP) driving scheme.

4. 2. The modulator of claim 1, wherein the spacing between adjacent second metal portions is 5 μm to 60 μm.

5. 2. The modulator of claim 1, wherein the oxide layer has a thickness of 5 nm to 50 nm.

6. 2. The modulator of claim 1, wherein the III-V compound semiconductor layer comprises InGaAsP, InP, or other III-V compound material having an optoelectronic effect.

7. 1. A method for manufacturing a III-V / Si hybrid MOS optical modulator having traveling wave electrodes, comprising: fabricating a III-V compound semiconductor layer and a silicon layer with an oxide layer between the III-V compound semiconductor layer and the silicon layer; fabricating at least one first connector connecting to the III-V compound semiconductor layer; fabricating a metal portion of a first metal layer that connects to at least one of the first connectors, the first metal layer including a plurality of metal portions; fabricating at least one second connector for connecting to another metal portion from the plurality of metal portions of the first metal layer; and fabricating a second metal layer connecting to the at least one second connector; the thickness of the oxide layer is designed to allow impedance and speed matching of the modulator; the first metal layer includes three first metal portions spaced apart from one another; The method, wherein the second metal layer includes two second metal portions spaced apart from one another.

8. The method of claim 7, wherein the traveling wave electrodes are driven by a series-push-pull (SPP) driving scheme.

9. The method of claim 7 , wherein each second metal portion has a spacing between adjacent second metal portions of 5 μm to 60 μm.

10. The method of claim 7 , wherein the oxide layer has a thickness of 5 nm to 50 nm.

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