Solar cell and its manufacturing method

Abstract

The present disclosure discloses a solar cell comprising a semiconductor substrate, a first doped layer and a second doped layer on one side of the semiconductor substrate, and a third doped layer on the surface of the first doped layer opposite the semiconductor substrate, the first doped layer comprising a first dopant and a second dopant, the second doped layer comprising a second dopant, the third doped layer comprising a first dopant and a second dopant, at least a portion of the third doped layer having the same conductivity type as the first doped layer, and the first doped layer and the second doped layer having opposite conductivity types. The present disclosure further provides a method for manufacturing a solar cell. The solar cell of the present disclosure can be manufactured with two regions of doped semiconductor by patterning only once.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to the technical field of solar cells, and more particularly to solar cells and methods for manufacturing the same.

[0002] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application bearing application number 202111644240.1 and entitled "Solar Cell and Manufacturing Method Thereof," filed with the China Patent Office on December 29, 2021, the entire contents of which are incorporated herein by reference. [Background technology]

[0003] In conventional solar cell structures, back-contact solar cells have higher photoelectric conversion efficiencies because they lack a front-surface shielding electrode. Back-contact cells have p-type and n-type regions on different areas of the back surface, with positive and negative electrodes mounted on top of these, respectively. In addition, such unshielded front-surface cells not only have higher conversion efficiencies, but also have a more aesthetically pleasing appearance and are easier to assemble with the back electrode components. IBC cells are currently one of the mainstream technologies for achieving high-efficiency crystalline silicon cells.

[0004] However, the IBC cell has a complex structure, which makes its manufacturing process complicated. Typically, at least two patterning steps are required to achieve patterning of the p-type and n-type regions, which makes the manufacturing cost high. Summary of the Invention [Problem to be solved by the invention]

[0005] In view of the above problems, the present disclosure proposes a solar cell and a manufacturing method thereof that can fabricate two doped semiconductor regions by a single patterning. Furthermore, the doped regions fabricated by this method have a passivation contact structure on both electrodes, which enhances the passivation effect and significantly reduces the recombination rate in the metal region, thereby improving the efficiency of the cell. [Means for solving the problem]

[0006] The present disclosure provides a method for manufacturing a solar cell, comprising the following steps. providing a semiconductor substrate; forming a first doped layer on a first surface of the semiconductor substrate; patterning the first doped layer to leave a portion; forming a third doped layer on a surface of the first doped layer opposite the semiconductor substrate by a heat treatment, and forming a second doped layer on a first surface of the semiconductor substrate not covered by the first doped layer; the first doped layer includes a first dopant and a second dopant; the second doped layer includes a second dopant; the third doped layer includes a first dopant and a second dopant; the first doped layer and the second doped layer are of opposite conductivity types; At least a portion of the third doped layer has the same conductivity type as the first doped layer.

[0007] further comprising forming a first semiconductor layer on the first surface of the semiconductor substrate and then diffusing a first dopant into the first semiconductor layer, thereby forming a first doped layer, or forming a first doped layer on the first surface of the semiconductor substrate by in situ doping; A first auxiliary layer is formed on the surface of the first doped layer opposite the semiconductor substrate, and then a portion of the first auxiliary layer and the first doped layer is removed by etching, thereby completing the patterning and leaving a portion of the first doped layer.

[0008] further forming a second doped layer by in situ doping on a surface of the first doped layer opposite the semiconductor substrate and on a first surface of the semiconductor substrate that is not covered with the first doped layer; By heat treating the second doped layer above the first doped layer, the first dopant in the first doped layer diffuses into the second doped layer above it, and the second dopant in the second doped layer also diffuses into the first doped layer, thereby converting the second doped layer above the first doped layer into a third doped layer.

[0009] Furthermore, the heat treatment is a laser treatment or a heat treatment, When the laser treatment is used, the area of ​​the third doped layer that is directly irradiated with the laser has the same conductivity type as the first doped layer.

[0010] Furthermore, in the third doped layer, a region of the same conductivity type as the first doped layer penetrates the third doped layer in the thickness direction.

[0011] further forming a second semiconductor layer on a surface of the first doped layer opposite to the semiconductor substrate and on a first surface of the semiconductor substrate that is not covered with the first doped layer; Under the conditions of the heat treatment, the second dopant is diffused into the second semiconductor layer, and because the temperature is high, the first dopant in the first doped layer also diffuses into the second semiconductor layer above it, so that the second semiconductor layer above the first doped layer becomes a third doped layer, and the second semiconductor layer on the first surface of the semiconductor substrate becomes a second doped layer.

[0012] Furthermore, in the third doped layer, the conductivity of at least a portion of a region close to the first doped layer is the same as the conductivity type of the first doped layer.

[0013] Furthermore, before forming the third doped layer, the peak doping concentration of the first dopant in the first doped layer is 1×10 19 to 5×10 21 atoms / cm 3 .

[0014] Furthermore, after forming the third doped layer, the doping concentration of the first dopant in the first doped layer is greater than the doping concentration of the second dopant; In the third doped layer, the doping concentration of the first dopant in at least a portion of the region is higher than the doping concentration of the second dopant.

[0015] Furthermore, the peak doping concentration of the first dopant in the first doped layer is 1×10 19 to 3×10 21 atoms / cm 3 ; In the second doped layer, the peak doping concentration of the second dopant is 1×10 to 3×10 atoms / cm; The peak doping concentration of the first dopant in at least a portion of the third doped layer is 1×10 20 to 5×10 20 atoms / cm 3 .

[0016] Furthermore, the heating peak temperature of the heat treatment is 850° C. or higher, preferably 900° C. or higher, and more preferably 1000° C., and the heating time at the peak temperature is 10 minutes or longer.

[0017] Furthermore, when forming the third doped layer, the temperature is high enough that the first and second dopants in the first and third doped layers diffuse into the semiconductor substrate, thereby forming a third doped region; and / or a second dopant in the second doped layer diffuses into the semiconductor substrate, thereby forming a fourth doped region; Preferably, in the third doped region, the peak doping concentration of the first dopant is 1×10 18 to 3×10 21 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 17 to 3×10 19 atoms / cm 3; Preferably, in the fourth doped region, the peak doping concentration of the second dopant is 1×10 18 to 3×10 19 atoms / cm 3 .

[0018] Furthermore, the first dopant is a Group VA element or a Group IIIA element, and the second dopant is a Group VA element or a Group IIIA element, and preferably, the first dopant is a Group VA element and the second dopant is a Group IIIA element.

[0019] Furthermore, before forming the third doped layer, The method further includes a step of etching away the first doped layer and the second doped layer at a boundary between the second doped layer and the first doped layer on the first surface of the semiconductor substrate to expose the first surface of the semiconductor substrate, thereby positioning an isolation region between the first doped layer and the second doped layer.

[0020] Furthermore, after forming the third doped layer, The method further includes a step of etching away the first doped layer, the second doped layer, and the third doped layer at the boundary between the second doped layer and the first doped layer on the first surface of the semiconductor substrate to expose the first surface of the semiconductor substrate, thereby positioning an isolation region between the first doped layer and the second doped layer.

[0021] Furthermore, the first doped layer, the second doped layer and the third doped layer are all one of a doped polycrystalline silicon layer, a microcrystalline silicon layer or an amorphous silicon layer.

[0022] The present disclosure provides a solar cell, a semiconductor substrate having a first doped layer and a second doped layer on a first surface of the semiconductor substrate, and a third doped layer on a surface of the first doped layer opposite the semiconductor substrate; the first doped layer includes a first dopant and a second dopant; the second doped layer includes a second dopant; the third doped layer includes a first dopant and a second dopant; At least a portion of the third doped layer has the same conductivity type as the first doped layer; The first doped layer and the second doped layer are of opposite conductivity types.

[0023] Furthermore, the thickness of the first doped layer is 50 to 300 nm, The third doped layer and the second doped layer have the same thickness, both of which are 150 nm or less.

[0024] Furthermore, when the thickness d of the third doped layer is 30 nm or less, the entire region in the third doped layer has the same conductivity type as the first doped layer.

[0025] Furthermore, when the thickness of the third doped layer is 30 nm < d ≤ 150 nm, in the third doped layer, the region close to the first doped layer has the same conductivity type as the first doped layer in at least a part of the region.

[0026] Furthermore, when the thickness of the third doped layer is 30 nm < d ≤ 150 nm, in the third doped layer, the region having the same conductivity type as the first doped layer penetrates the third doped layer in the thickness direction.

[0027] Furthermore, in the first doped layer, the doping concentration of the first dopant increases from the surface on the side opposite to the semiconductor substrate to the surface on the semiconductor substrate side and then decreases, and the doping concentration of the second dopant gradually decreases.

[0028] Furthermore, in the second doped layer, the doping concentration of the second dopant is the same from the surface on the side opposite to the semiconductor substrate to the surface on the semiconductor substrate side.

[0029] Furthermore, in the third doped layer, the doping concentration of the first dopant gradually increases from the surface on the side opposite to the semiconductor substrate to the surface on the semiconductor substrate side, and the doping concentration of the second dopant is the same from the surface on the side opposite to the semiconductor substrate to the surface on the semiconductor substrate side.

[0030] Furthermore, the third doped layer not only covers the surface of the first doped layer on the side opposite to the semiconductor substrate, but also covers the side surface of the first doped layer close to the second doped layer, and the third doped layer covering the side surface of the first doped layer contacts the second doped layer.

[0031] and / or a first interface layer located between the semiconductor substrate and the first doped layer. a second interface layer extending from a surface of the first doped layer opposite the first interface layer to a side thereof and covering a portion of the semiconductor substrate not covered by the first doped layer, and the second doped layer and the third doped layer being respectively provided on one side surface of the second interface layer; and / or The semiconductor device further includes a backside passivation layer, the backside passivation layer covering the third doped layer and the second doped layer.

[0032] Furthermore, the first doped layer and the third doped layer have the same width, and an isolation region is located between the first doped layer and the third doped layer and the second doped layer.

[0033] and / or a first interface layer located between the semiconductor substrate and the first doped layer. The semiconductor device may further include a second interface layer, the second interface layer being located between the first doped layer and the third doped layer and between the second doped layer and the semiconductor substrate; and / or may further include a back surface passivation layer, the back surface passivation layer covering the third doped layer, the isolation region, and the second doped layer.

[0034] The semiconductor device further includes a first electrode and a second electrode, wherein the first electrode penetrates the back surface passivation layer and contacts a region of the third doped layer having the same conductivity type as the first doped layer, and the second electrode penetrates the back surface passivation layer and contacts the second doped layer.

[0035] Furthermore, the solar cell is manufactured by the method described above. [Effects of the Invention]

[0036] The solar cell provided by the present disclosure can fabricate two doped semiconductor regions with a single patterning. Furthermore, the doped regions fabricated by this method have a passivation contact structure on both electrodes, which provides a high passivation effect and significantly reduces the recombination rate in the metal region, thereby improving the cell efficiency. Furthermore, this back contact fabrication method requires only one high-temperature heat treatment, reducing thermal damage caused by the high-temperature heat treatment. [Brief explanation of the drawings]

[0037] The drawings are intended to provide a better understanding of the present disclosure and are not intended to unduly limit the disclosure.

[0038] [Figure 1] 1 is a structural schematic diagram of a solar cell provided in the present disclosure. [Figure 2] 1 is a structural schematic diagram of a solar cell provided in the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0039] The following describes exemplary embodiments of the present disclosure. The description includes various details of the embodiments of the present disclosure for ease of understanding, and these details should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications to the embodiments described herein are possible without departing from the scope and spirit of the present disclosure. Similarly, for clarity and conciseness, the following description will omit descriptions of known functions and structures. In the present disclosure, the up and down positions are determined by the direction of light incidence, and the light incidence portion is considered to be the top.

[0040] The present disclosure provides two solar cells, specifically as follows.

[0041] As shown in FIG. 1 , the first solar cell includes a semiconductor substrate 1, one side surface of which is divided into a first region and a second region. A first interface layer 2, a first doped layer 3, a second interface layer 4, and a third doped layer 5 are sequentially formed on one side surface of the semiconductor substrate 1 in the first region. A second interface layer 4 and a second doped layer 6 are sequentially formed on the same side surface of the semiconductor substrate 1 in the second region. The second interface layer 4 extends from one side surface of the first doped layer 3 to its side surface and covers the semiconductor substrate 1 in the second region. The third doped layer 5 not only covers the second interface layer 4 on the side of the first doped layer 3 opposite the semiconductor substrate 1, but also covers the side surface close to the second doped layer 6, and the third doped layer 5 extending to the side surface is in contact with the second doped layer 6. A back surface passivation layer 7 is further provided on the surface of the third doped layer 5 opposite to the second interface layer 4, covering the third doped layer 5 and the second doped layer 6. A first electrode 8 is further provided on the back surface passivation layer 7 above the third doped layer 5, penetrating the back surface passivation layer 7 and contacting the third doped layer 5. The first doped layer 3 and the second doped layer 6 have opposite conductivity types. The conductivity of at least a portion of the third doped layer 5 is the same as that of the first doped layer 3, and in the third doped layer 5, the region of the same conductivity type as the first doped layer 3 is a first conductivity type region, and the region of the third doped layer 5 of the same conductivity type as the second doped layer is a second conductivity type region. The first electrode 8 is in contact with the first conductivity type region in the third doped layer 5, and the first electrode is electrically connected to the first doped layer 3 via the first conductivity type region, and a second electrode 9 is further provided on the back surface passivation layer 7 above the second doped layer 6, penetrating the back surface passivation layer 7 and contacting the second doped layer 6.

[0042] The first electrode 8 and second electrode 9 may be gold, silver or aluminum.

[0043] The semiconductor substrate 1 is a silicon substrate or a germanium substrate.

[0044] The semiconductor substrate 1 may be p-type or n-type.

[0045] In the present disclosure, the conductivity type may be measured using an ECV or the like, or may be measured using a pn tester.

[0046] The doping concentration may be measured by the ECV method.

[0047] The doping elements in the first doped layer, the second doped layer, the third doped region and the fourth doped region may be revealed by STEM or by SIMS.

[0048] In the present disclosure, the first interface layer 2 may be one or more of an oxide layer, a nitride layer, a carbide layer, and a hydrogenated amorphous silicon layer, where the oxide layer includes a mixture of one or more of silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, HfO2, Ga2O3, Ta2O5, and Nb2O5, the nitride layer includes one or more of silicon nitride, aluminum nitride, TiN, and TiCN, and the carbide includes SiC, SiCN, etc. Specifically, the first interface layer 2 may be a tunnel oxide layer, and its thickness may be 0.5 to 5 nm, for example, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, or 5 nm.

[0049] In the present disclosure, the second interface layer 4 may be one or more of an oxide layer, a nitride layer, a carbide layer, and a hydrogenated amorphous silicon layer, where the oxide layer includes a mixture of one or more of silicon oxide, silicon oxynitride, aluminum oxide, titanium oxide, HfO2, Ga2O3, Ta2O5, and Nb2O5, the nitride layer includes one or more of silicon nitride, aluminum nitride, TiN, and TiCN, and the carbide includes SiC, SiCN, etc. Preferably, the second interface layer 4 is silicon oxide, and its thickness may be 0.5 to 5 nm, for example, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, or 5 nm.

[0050] In the present disclosure, a front passivation layer and an anti-reflection layer are sequentially provided on the surface of the semiconductor substrate 1 opposite to the first interface layer 2, and the front passivation layer may be made of one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.

[0051] In the present disclosure, the first doped layer 3 may be a doped amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, nanosilicon, or a mixture of one or more thereof, and is preferably a doped amorphous silicon layer. Since the manufacturing temperature of amorphous silicon is lower, the amorphous silicon does not need to be annealed separately, but can be annealed during any of the subsequent doping or heating processes, and the process time is relatively shorter. The thickness of the first doped layer 3 is 50 to 300 nm, and may be, for example, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, or 300 nm.

[0052] Specifically, the second doped layer 6 may be a doped amorphous silicon layer, a doped microcrystalline silicon layer, a polycrystalline silicon layer, nanosilicon, or a mixture of one or more thereof, and is preferably a doped amorphous silicon layer. Since the manufacturing temperature of amorphous silicon is lower, the processing time is relatively shorter. The thickness of the second doped layer 6 is 150 nm or less, and may be, for example, 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm.

[0053] Specifically, the third doped layer 5 may be a doped amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, nanosilicon, or a mixture of one or more thereof. Preferably, the third doped layer 5 and the second doped layer 6 are made of the same material, and the thickness of the third doped layer 5 is 150 nm or less, for example, 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, or 150 nm.

[0054] Specifically, the third doped layer 5 and the second doped layer 6 have the same thickness.

[0055] In the present disclosure, the first doped layer 3 includes a first dopant and a second dopant, and the peak doping concentration of the first dopant is greater than the peak doping concentration of the second dopant; the second doped layer 6 includes a second dopant; the third doped layer 5 includes a first dopant and a second dopant; Since the peak doping concentration of the first dopant in at least a portion of the third doped layer 5 is greater than the peak doping concentration of the second dopant, the conductivity of at least a portion of the third doped layer 5 is the same as that of the first doped layer 3.

[0056] If the first doped layer 3 is p-type, the second doped layer 6 is n-type. Conversely, if the first doped layer 3 is n-type, the second doped layer 6 is p-type. Taking silicon as an example, p-type conductive dopants are generally Group IIIA elements, such as gallium (Ga) or boron (B). N-type dopants are generally Group VA elements, such as phosphorus (P).

[0057] Specifically, in the first doped layer 3, the peak doping concentration of the first dopant is 1×10 19 ~3×10 21 atoms / cm 3 For example, 1×10 19 atoms / cm3 , 2 × 10 19 atoms / cm 3 , 3×10 19 atoms / cm 3 , 4×10 19 atoms / cm 3 , 5×10 19 atoms / cm 3 , 6×10 19 atoms / cm 3 , 7×10 19 atoms / cm 3 , 8×10 19 atoms / cm 3 , 9×10 19 atoms / cm 3 , 1×10 20 atoms / cm 3 , 2 × 10 20 atoms / cm 3 , 3×10 20 atoms / cm 3 , 4×10 20 atoms / cm 3 , 5×10 20 atoms / cm 3 , 6×10 20 atoms / cm 3 , 7×10 20 atoms / cm 3 , 8×10 20 atoms / cm 3 , 9×10 20 atoms / cm 3 , 1×10 21 atoms / cm 3 , 2 × 10 21 atoms / cm 3 or 3 x 10 21 atoms / cm 3 may be.

[0058] In the second doped layer 6, the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 For example, 1×10 19 atoms / cm 3 , 2 × 10 19 atoms / cm3 or 3 x 10 19 atoms / cm 3 may be.

[0059] In the third doped layer 5, the peak doping concentration of the first dopant in at least a portion of the layer is 1×10 20 ~5×10 20 atoms / cm 3 For example, 1×10 20 atoms / cm 3 , 2 × 10 20 atoms / cm 3 , 3×10 20 atoms / cm 3 , 4×10 20 atoms / cm 3 or 5 x 10 20 atoms / cm 3 may be.

[0060] In the present disclosure, the first dopant is a Group VA element or a Group IIIA element, preferably a Group VA element, and the second dopant is a Group VA element or a Group IIIA element, preferably a Group IIIA element.

[0061] Specifically, the first dopant is phosphorus, gallium or boron, preferably phosphorus, and the second dopant is phosphorus, gallium or boron, preferably boron.

[0062] A dopant is a material doped with a doping substance, for example, if the doping substance is POCl3, the dopant is phosphorus.

[0063] Phosphorus-containing doping materials typically include POCl3 (commonly used during thermal diffusion), PH3 (phosphane used for ion implantation or in-situ doping, etc.), phosphorus-containing silicon oxide (doped by APCVD), etc. Boron-containing doping materials typically include BBr3, BCl3 (BBr3 and BCl3 are both used during thermal diffusion), and B2H6 (diborane is commonly used during in-situ doping or ion implantation).

[0064] In the present disclosure, within the first doped layer 3, the doping concentration of the first dopant increases and then decreases from the surface opposite to the semiconductor substrate 1 to the surface on the semiconductor substrate 1 side, and the doping concentration of the second dopant gradually decreases.

[0065] In the second doped layer 6, the doping concentration of the second dopant is the same from the surface opposite to the semiconductor substrate 1 to the surface on the semiconductor substrate 1 side; In the third doped layer 5, the doping concentration of the first dopant gradually increases from the surface opposite to the first doped layer 3 to the surface on the first doped layer 3 side, and the doping concentration of the second dopant is the same from the surface opposite to the semiconductor substrate 1 to the surface on the semiconductor substrate 1 side.

[0066] Furthermore, when the thickness of the third doped layer 5 is less than 30 nm, the concentration of the first dopant in the third doped layer 5 is greater than the concentration of the second dopant, and the entire third doped layer 5 has the same conductivity type as the first doped layer 3. When the thickness d of the third doped layer 5 is 30 nm to 150 nm, the concentration of the first dopant in a portion is greater than the concentration of the second dopant, and the conductivity type of that portion in the third doped layer 5 is the same as that of the first doped layer 3, and the concentration of the first dopant in a portion is smaller than the concentration of the second dopant, and the conductivity type of that portion is opposite to that of the first doped layer 3.

[0067] Specifically, when the thickness d of the third doped layer 5 is 30 nm to 150 nm, the conductivity of at least a portion of the region of the third doped layer 5 close to the first doped layer 3 is the same as the conductivity type of the first doped layer 3, and the first electrode penetrates the back surface passivation layer 7 into the third doped layer and comes into contact with the first conductivity type region.

[0068] Specifically, when the thickness of the third doped layer 5 is 30 nm < d ≤ 150 nm, in the third doped layer 5, the region having the same conductivity type as the first doped layer 3 penetrates the third doped layer 5 in the thickness direction, and the first electrode penetrates the back surface passivation layer and directly contacts the first conductivity type region.

[0069] In the present disclosure, within the side of the semiconductor substrate 1 close to the first doped layer 3, the first dopant or the first dopant and the second dopant penetrate the first interface layer 2 and enter the semiconductor substrate 1 to form a third doped region 11, that is, the third doped region 11 contains the first dopant or the first dopant and the second dopant.

[0070] Within the side of the semiconductor substrate 1 close to the second doped layer 6, the second dopant penetrates the second interface layer 4 and enters the semiconductor substrate 1 to form a fourth doped region 12, that is, the fourth doped region 12 contains the second dopant.

[0071] In one specific embodiment, there is only a third doped region 11 in the semiconductor substrate 1.

[0072] In one specific embodiment, there is a fourth doped region 12 in the semiconductor substrate 1.

[0073] In one specific embodiment, there are both a third doped region 11 and a fourth doped region 12 in the semiconductor substrate 1.

[0074] The manufacturing method of the first solar cell is as follows: Step 1 of preparing a semiconductor substrate 1; Step 2 of forming a first doped layer 3 on the first surface of the semiconductor substrate 1; Step 3 of patterning the first doped layer 3 so as to leave a part; and step 4 of forming a third doped layer 5 on a surface of the first doped layer 3 opposite to the semiconductor substrate 1 by heat treatment, and forming a second doped layer 6 on a first surface of the semiconductor substrate 1 that is not covered with the first doped layer 3; the first doped layer 3 includes a first dopant and a second dopant; the second doped layer 6 includes a second dopant; the third doped layer 5 includes a first dopant and a second dopant; the first doped layer 3 and the second doped layer 6 are of opposite conductivity types; At least a portion of the third doped layer 5 has the same conductivity type as the first doped layer 3 .

[0075] In step 2, a first interface layer 2 is formed on one surface of the semiconductor substrate 1 using LPCVD at a temperature of 400 to 700°C, and a first doped layer 3 is formed on the surface of the first interface layer 2 opposite the semiconductor substrate 1 by in-situ doping LPCVD.

[0076] Alternatively, in step 2, a first interface layer 2 is formed on one surface of the semiconductor substrate 1 using LPCVD at a temperature of 400 to 700°C, a first semiconductor layer is formed on the surface of the first interface layer 2 opposite to the semiconductor substrate 1, and the first dopant is doped into the first semiconductor layer by diffusion, thereby forming a first doped layer 3.

[0077] The first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer.

[0078] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~5×10 21 atoms / cm 3 is.

[0079] In step 3, a first auxiliary layer is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are removed by etching, thereby completing the patterning and leaving only the first doped layer 3 in the first region.

[0080] Specifically, the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride. Preferably, the silicon oxide film formed during the phosphorus doping process may be used as the first auxiliary layer. The first auxiliary layer is then patterned, and the first auxiliary layer, the first doped layer 3, and the first interface layer 2 are removed from areas other than the first region by, for example, printing a pattern using an etching paste, or by using a short-pulse laser to remove the first auxiliary layer, the first doped layer 3, and the first interface layer 2 from areas other than the first region.

[0081] In a preferred solution, an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 except for the first region, and the same alkaline solution is used to form a textured structure on the surface of the semiconductor substrate 1 in the second region. By using the alkaline solution, the patterning of the first doped layer 3 in the first region is completed, and the texture fabrication in the second region is also completed at the same time. This greatly simplifies the IBC fabrication procedure and eliminates the currently commonly used process of fabricating a single-sided texture.

[0082] There are two methods for fabricating single-sided texture in the prior art: Method 1 is to first polish the silicon wafer on both sides, then fabricate a first auxiliary layer on one side, then fabricate the texture, and then remove the first auxiliary layer after the texture fabrication is completed.

[0083] In Method 2, the silicon wafer is first double-sided polished, then a first auxiliary layer is fabricated on one side, then single-sided polished, and then the first auxiliary layer is removed.

[0084] Both of the conventional single-sided texture manufacturing methods are complicated and require the single-sided texture manufacturing process to be completed at the beginning of the battery manufacturing process, which requires at least four steps. Furthermore, the texture may be damaged during subsequent normal battery manufacturing processes, reducing the texture anti-reflection effect of the battery.

[0085] In step 4, before forming the second doped layer and the third doped layer, a second interface layer 4 may be formed first, which not only covers the surface and side of the first doped layer opposite to the semiconductor substrate, but also covers the first surface of the semiconductor substrate that is not covered by the first doped layer.

[0086] In one specific embodiment, a second doped layer 6 is formed on the surface of the second interface layer 4 opposite the semiconductor substrate 1 and the first doped layer 3 by in-situ doping LPCVD, where in-situ doping refers to simultaneously completing amorphous silicon deposition and doping. The second doped layer 6 above the first doped layer 3 is then heat-treated, causing the first dopant in the first doped layer 3 to diffuse into the second doped layer 6 above it, and the second dopant in the second doped layer 6 above the first doped layer also diffuses into the first doped layer 3, thereby converting the second doped layer 6 above the first doped layer 3 into a third doped layer 5, while the second doped layer 6 above the first surface not covered by the first doped layer 3 remains as the second doped layer 6.

[0087] Specifically, the heat treatment is a laser treatment or a thermal treatment, and when the laser treatment is used, the region in the third doped layer 5 that is directly irradiated with the laser is a first conductivity type region (the first conductivity type region penetrates the third doped layer 5 in the thickness direction), the conductivity type of which is the same as the conductivity type of the first doped layer 3, and the doping concentration of the first dopant is greater than the doping concentration of the second dopant.

[0088] The power of the laser treatment is greater than 5 W, preferably 5 W to 30 W, to further improve the heating effect. The wavelength is longer than 500 nm, and a green laser device with a wavelength of 532 nm, a yellow laser device with a wavelength of 589 nm, a red laser device with a wavelength of 635 nm, 660 nm, 670 nm, or 671 nm, or an infrared laser device with a wavelength of 808 nm, 914 nm, 946 nm, 980 nm, 1047 nm, 1053 nm, 1064 nm, 1320 nm, or 1342 nm may be used.

[0089] In another specific embodiment, a second semiconductor layer is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3, and under heat treatment conditions, the second dopant is diffused into the second semiconductor layer, and because the temperature is high, the first dopant in the first doped layer 3 also diffuses into the second semiconductor layer above it, so that the second semiconductor layer above the first doped layer 3 becomes a third doped layer 5, and the second semiconductor layer on the first surface of the semiconductor substrate 1 becomes a second doped layer 6.

[0090] Specifically, in the third doped layer 5 , the region close to the first doped layer 3 has the same conductivity type as that of the first doped layer 3 in at least a part of the region.

[0091] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~3×10 21 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0092] The peak doping concentration of the first dopant in a portion of the third doped layer 5 is 1×10 20 ~5×10 20 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm3 is.

[0093] The peak doping concentration of the second dopant in the second doped layer 6 is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0094] Specifically, the heating peak temperature of the heat treatment is 850°C or higher, preferably 900°C or higher, and more preferably 1000°C, and may be, for example, 850°C, 900°C, 1000°C, 1100°C, 1200°C, etc. The heating time at the peak temperature is 10 minutes or longer, preferably 30 minutes or longer, and may be, for example, 10 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes, etc.

[0095] The second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer, and the high peak temperature of the heat treatment converts the amorphous silicon or microcrystalline silicon in the second semiconductor layer into polycrystalline silicon, thereby increasing the conductivity of the second semiconductor layer.

[0096] Optionally, after the heat treatment, an oxide film that may have formed during heating may be removed. The solution used to remove the oxide film layer contains fluorine, and specifically, a solution containing HF or NHF may be used to remove the oxide film layer.

[0097] The method further includes the following steps 5 and 6.

[0098] In step 5, a back passivation layer 7 is formed on the surfaces of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and a front passivation layer is formed on the surface of the semiconductor substrate 1 opposite the first interface layer 2.

[0099] In step 6, a first electrode 8 is formed above the third doped layer 5, penetrating the back surface passivation layer 7, and a second electrode 9 is formed above the second doped layer 6, penetrating the back surface passivation layer 7.

[0100] Specifically, there are various methods for forming the electrodes. For example, a burn-through paste may be directly applied onto the rear surface passivation layer 7, and then the electrode paste may be passed through the rear surface passivation layer 7 after heat treatment to form contact with the third doped layer 5 and the second doped layer 6. Alternatively, holes may be first drilled on the rear surface passivation layer 7, and then electrodes may be formed using methods such as electrode paste, laser transfer, electroplating, chemical plating, light-induced plating, or physical vapor deposition such as evaporation and sputtering. Of course, electrodes may be formed using one or a combination of the above methods.

[0101] The first method for manufacturing a solar cell includes the following steps 1 to 6.

[0102] In step 1, a semiconductor substrate 1 is provided. In step 2, a first doped layer 3 is formed on a first surface of the semiconductor substrate 1. Specifically, a first interface layer 2 is formed on one surface of the semiconductor substrate 1 using LPCVD at a temperature of 400 to 700°C, and a first doped layer 3 is formed on the surface of the first interface layer 2 opposite the semiconductor substrate 1 by in-situ doping LPCVD.

[0103] Alternatively, in step 2, a first interface layer 2 is formed on one surface of the semiconductor substrate 1 using LPCVD at a temperature of 400 to 700°C, a first semiconductor layer is formed on the surface of the first interface layer 2 opposite to the semiconductor substrate 1, and the first dopant is doped into the first semiconductor layer by diffusion, thereby forming a first doped layer 3.

[0104] The first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer.

[0105] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~5×10 21 atoms / cm 3 is.

[0106] In step 3, the first doped layer 3 is patterned so as to leave some portions. Specifically, a first auxiliary layer is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are removed by etching, thereby completing the patterning and leaving only the first doped layer 3 in the first region.

[0107] Specifically, the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride. Preferably, the silicon oxide film formed during the phosphorus doping process may be used as the first auxiliary layer. The first auxiliary layer is then patterned, and the first auxiliary layer, the first doped layer 3, and the first interface layer 2 are removed from areas other than the first region by, for example, printing a pattern using an etching paste, or by using a short-pulse laser to remove the first auxiliary layer, the first doped layer 3, and the first interface layer 2 from areas other than the first region.

[0108] In a preferred solution, an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 except for the first region, and the same alkaline solution is used to form a textured structure on the surface of the semiconductor substrate 1 in the second region. By using the alkaline solution, the patterning of the first doped layer 3 in the first region is completed, and the texture fabrication in the second region is also completed at the same time. This greatly simplifies the IBC fabrication procedure and eliminates the currently commonly used process of fabricating a single-sided texture.

[0109] There are two methods for fabricating single-sided texture in the prior art: Method 1 is to first polish the silicon wafer on both sides, then fabricate a first auxiliary layer on one side, then fabricate the texture, and then remove the first auxiliary layer after the texture fabrication is completed.

[0110] In Method 2, the silicon wafer is first double-sided polished, then a first auxiliary layer is fabricated on one side, then single-sided polished, and then the first auxiliary layer is removed.

[0111] Both of the conventional single-sided texture manufacturing methods are complicated and require the single-sided texture manufacturing process to be completed at the beginning of the battery manufacturing process, which requires at least four steps. Furthermore, the texture may be damaged during subsequent normal battery manufacturing processes, reducing the texture anti-reflection effect of the battery.

[0112] In step 4, a third doped layer 5 is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1 by heat treatment, and a second doped layer 6 is formed on the first surface of the semiconductor substrate 1 that is not covered by the first doped layer 3.

[0113] the first doped layer 3 includes a first dopant and a second dopant; the second doped layer 6 includes a second dopant; the third doped layer 5 includes a first dopant and a second dopant; the first doped layer 3 and the second doped layer 6 are of opposite conductivity types; At least a portion of the third doped layer 5 has the same conductivity type as the first doped layer 3 .

[0114] Specifically, a second interface layer 4 may be formed before the second doped layer and the third doped layer are formed, and the second interface layer 4 not only covers the surface and side of the first doped layer opposite the semiconductor substrate, but also covers the first surface of the semiconductor substrate that is not covered by the first doped layer.

[0115] In one specific embodiment, a second doped layer 6 is formed by in-situ doping LPCVD on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3. Subsequently, the second doped layer 6 above the first doped layer 3 is heat-treated, so that the first dopant in the first doped layer 3 diffuses into the second doped layer 6 thereon, and the second dopant in the second doped layer 6 above the first doped layer also diffuses into the first doped layer 3, thereby converting the second doped layer 6 above the first doped layer 3 into the third doped layer 5, while the second doped layer 6 above the first surface not covered by the first doped layer 3 remains as the second doped layer 6.

[0116] Specifically, the heating treatment is a laser treatment or a heat treatment, and when the laser treatment is used, the region of the third doped layer 5 that is directly irradiated with the laser is a first conductivity type region (the first conductivity type region penetrates the third doped layer 5 in the thickness direction), and the conductivity type thereof is the same as that of the first doped layer 3, and the doping concentration of the first dopant is higher than that of the second dopant. The power of the laser treatment is greater than 5 W, preferably 5 W to 30 W, to further improve the heating effect. The wavelength may be longer than 500 nm, and examples thereof include a green laser device with a wavelength of 532 nm, a yellow laser device with a wavelength of 589 nm, a red laser device with a wavelength of 635 nm, 660 nm, 670 nm, or 671 nm, and infrared lasers with wavelengths of 808 nm, 914 nm, 946 nm, 980 nm, 1047 nm, 1053 nm, 1064 nm, 1320 nm, and 1342 nm may also be used.

[0117] In another specific embodiment, a second semiconductor layer is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3, and under heat treatment conditions, the second dopant is diffused into the second semiconductor layer, and because the temperature is high, the first dopant in the first doped layer 3 also diffuses into the second semiconductor layer above it, so that the second semiconductor layer above the first doped layer 3 becomes a third doped layer 5, and the second semiconductor layer on the first surface of the semiconductor substrate 1 becomes a second doped layer 6.

[0118] Specifically, in the third doped layer 5 , the region close to the first doped layer 3 has the same conductivity type as that of the first doped layer 3 in at least a part of the region.

[0119] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~3×10 21 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0120] The peak doping concentration of the first dopant in a portion of the third doped layer 5 is 1×10 20 ~5×10 20 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0121] The peak doping concentration of the second dopant in the second doped layer 6 is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0122] Specifically, the heating peak temperature under the heat treatment or heating conditions is 850°C or higher, preferably 900°C or higher, and more preferably 1000°C, and may be, for example, 850°C, 900°C, 1000°C, 1100°C, 1200°C, etc. At the peak temperature, the heating time is 10 minutes or longer, preferably 30 minutes or longer, and may be, for example, 10 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes, etc.

[0123] The second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer, and the high peak temperature of the heat treatment converts the amorphous silicon or microcrystalline silicon in the second semiconductor layer into polycrystalline silicon, thereby increasing the electrical conductivity of the second semiconductor layer.

[0124] Optionally, after the heat treatment, an oxide film that may have formed during heating may be removed. The solution used to remove the oxide film layer contains fluorine, and specifically, a solution containing HF or NHF may be used to remove the oxide film layer.

[0125] In step 5, a back passivation layer 7 is formed on the surfaces of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and a front passivation layer is formed on the surface of the semiconductor substrate 1 opposite the first interface layer 2.

[0126] In step 6, a first electrode 8 is formed above the third doped layer 5, penetrating the back surface passivation layer 7, and a second electrode 9 is formed above the second doped layer 6, penetrating the back surface passivation layer 7.

[0127] Specifically, there are various methods for forming the electrodes. For example, a burn-through paste may be directly applied onto the rear surface passivation layer 7, and then the electrode paste may be passed through the rear surface passivation layer 7 after heat treatment to form contact with the third doped layer 5 and the second doped layer 6. Alternatively, holes may be first drilled on the rear surface passivation layer 7, and then electrodes may be formed using methods such as electrode paste, laser transfer, electroplating, chemical plating, light-induced plating, or physical vapor deposition such as evaporation and sputtering. Of course, electrodes may be formed using one or a combination of the above methods.

[0128] 2 , the second solar cell includes a semiconductor substrate 1, one side of which is divided into a first region and a second region, with a gap therebetween. A first interface layer 2, a first doped layer 3, a second interface layer 4, and a third doped layer 5 are sequentially formed on one side of the semiconductor substrate 1 in the first region. A second interface layer 4 and a second doped layer 6 are sequentially formed on the same side of the semiconductor substrate 1 in the second region. The third doped layer 5, the second interface layer 4, the first doped layer 3, and the side surfaces of the first interface layer 2 close to the second doped layer 6, the surface of the semiconductor substrate 1 not covered by the first doped layer 3 and the second doped layer 6, and the side surfaces of the second interface layer 4 and the second doped layer 6 close to the first doped layer 3 form a groove, which is an isolation region 10. A back surface passivation layer 7 is further formed on the surface of the third doped layer 5 opposite the second interface layer 4, covering the third doped layer 5, the isolation region 10, and the second doped layer 6. A first electrode 8 is further provided on the back surface passivation layer 7 above the third doped layer 5, penetrating the back surface passivation layer 7 and contacting the third doped layer 5, and a second electrode 9 is further provided on the back surface passivation layer 7 above the second doped layer 6, penetrating the back surface passivation layer 7 and contacting the second doped layer 6.

[0129] The second solar cell and the first solar cell differ only in that the second solar cell has an isolation region 10 between the first region and the second region, and only the rear surface passivation layer 7 is present within the isolation region 10 (the third doped layer 5 and the second doped layer 6 are not in contact with each other). Therefore, the semiconductor substrate 1, the first interface layer 2, the second interface layer 4, the first doped layer 3, the second doped layer 6, the third doped layer 5, the rear surface passivation layer 7, the first electrode 8, and the second electrode 9 in the second solar cell can all be referred to as those in the first solar cell. The depth h of the isolation region 10 is 300 nm to 1 μm, and may be, for example, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1 μm. The width w of the isolation region 10 is 10 to 200 μm, and preferably 30 to 100 μm. For example, it may be 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, or 200 μm.

[0130] The backside passivation layer 7 in the isolation region 10 is conformal with the isolation region 10 .

[0131] The isolation region 10 is used to isolate the p-type and n-type semiconductor regions, preventing leakage current and preventing phenomena such as heat generation due to breakdown of the lateral pn junction. In the solution of the present disclosure, the presence of the isolation region 10 is even more important because both p-type doping and n-type doping exist in the first doped region.

[0132] The back surface passivation layer 7 has equal thickness on the first doped layer 3 , the isolation region 10 and the second doped layer 6 .

[0133] The second method for manufacturing a solar cell includes the following steps 1 to 6.

[0134] In step 1, a semiconductor substrate 1 is provided. In step 2, a first doped layer 3 is formed on one surface of the semiconductor substrate 1. In step 3, the first doped layer 3 is patterned so as to leave some portions. In step 4, a third doped layer 5 is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1 by heat treatment, and a second doped layer 6 is formed on the first surface of the semiconductor substrate 1 that is not covered by the first doped layer 3. In step 5, a second auxiliary layer is formed on the surfaces of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and the areas near the boundary between the third doped layer 5 and the second doped layer 6 are not covered with the second auxiliary layer.

[0135] In step 6, the third doped layer 5 and the second doped layer 6 that are not covered by the second auxiliary layer are removed by etching, thereby exposing the semiconductor substrate 1 (the exposed semiconductor substrate 1 is called an isolation region 10), and the third doped layer 5, the second interface layer 4, the side surfaces of the first doped layer 3 and the first interface layer 2 that are close to the isolation region 10, the surface of the semiconductor substrate 1 in the isolation region 10, and the side surfaces of the second interface layer 4 and the second doped layer 6 that are close to the isolation region 10 form one isolation region 10.

[0136] the first doped layer 3 includes a first dopant and a second dopant; the second doped layer 6 includes a second dopant; the third doped layer 5 includes a first dopant and a second dopant; the first doped layer 3 and the second doped layer 6 are of opposite conductivity types; The conductivity type of at least a portion of the third doped layer 5 is the same as the conductivity type of the first doped layer.

[0137] In step 2, a first interface layer 2 is formed on one surface of the semiconductor substrate 1 using LPCVD at a temperature of 400 to 700°C.

[0138] In one specific embodiment, a first doped layer 3 is formed on the surface of the first interface layer 2 opposite to the semiconductor substrate 1 by in-situ doping LPCVD.

[0139] In another specific embodiment, a first semiconductor layer is formed on the surface of the first interface layer 2 opposite the semiconductor substrate 1, and the first dopant is doped into the first semiconductor layer, thereby forming a first doped layer 3.

[0140] The first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer.

[0141] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~5×10 21 atoms / cm 3 is.

[0142] In step 3, a first auxiliary layer is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are removed by etching, thereby completing the patterning and leaving only the first doped layer 3 in the first region.

[0143] Specifically, the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride. Preferably, the silicon oxide film formed during the phosphorus doping process may be used as the first auxiliary layer. The first auxiliary layer is then patterned, and the first auxiliary layer, the first doped layer 3, and the first interface layer 2 are removed from areas other than the first region by, for example, printing a pattern using an etching paste, or by using a short-pulse laser to remove the first auxiliary layer, the first doped layer 3, and the first interface layer 2 from areas other than the first region.

[0144] In a preferred solution, an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 except for the first region, and the same alkaline solution is used to form a textured structure on the surface of the semiconductor substrate 1 in the second region. By using the alkaline solution, the patterning of the first doped layer 3 in the first region is completed, and the texture fabrication in the second region is also completed at the same time. This greatly simplifies the IBC fabrication procedure and eliminates the currently commonly used process of fabricating a single-sided texture.

[0145] There are two methods for fabricating single-sided texture in the prior art: Method 1 is to first polish the silicon wafer on both sides, then fabricate a first auxiliary layer on one side, then fabricate the texture, and then remove the first auxiliary layer after the texture fabrication is completed.

[0146] In Method 2, the silicon wafer is first double-sided polished, then a first auxiliary layer is fabricated on one side, then single-sided polished, and then the first auxiliary layer is removed.

[0147] Both of the conventional single-sided texture manufacturing methods are complicated and require the single-sided texture manufacturing process to be completed at the beginning of the battery manufacturing process, which requires at least four steps. Furthermore, the texture may be damaged during subsequent normal battery manufacturing processes, reducing the texture anti-reflection effect of the battery.

[0148] In step 4, before forming the second doped layer and the third doped layer, a second interface layer 4 may be formed first, which not only covers the surface and side of the first doped layer opposite to the semiconductor substrate, but also covers the first surface of the semiconductor substrate that is not covered by the first doped layer.

[0149] In one specific embodiment, a second doped layer 6 is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3 by in-situ doping LPCVD, where in-situ doping refers to simultaneously completing amorphous silicon deposition and doping. Subsequently, the second doped layer 6 above the first doped layer 3 is heat-treated, causing the first dopant in the first doped layer 3 to diffuse into the second doped layer 6 above it, and the second dopant in the second doped layer 6 above the first doped layer also diffuses into the first doped layer 3, thereby converting the second doped layer 6 above the first doped layer 3 into a third doped layer 5, while the second doped layer 6 above the first surface not covered by the first doped layer 3 remains as the second doped layer 6.

[0150] Specifically, the heating treatment is a laser treatment or a heat treatment, and when the laser treatment is used, the region of the third doped layer 5 that is directly irradiated with the laser is a first conductivity type region (the first conductivity type region penetrates the third doped layer 5 in the thickness direction), and the conductivity type thereof is the same as that of the first doped layer 3, and the doping concentration of the first dopant is higher than that of the second dopant. The power of the laser treatment is greater than 5 W, preferably 5 W to 30 W, to further improve the heating effect. The wavelength may be longer than 500 nm, and examples thereof include a green laser device with a wavelength of 532 nm, a yellow laser device with a wavelength of 589 nm, a red laser device with a wavelength of 635 nm, 660 nm, 670 nm, or 671 nm, and infrared lasers with wavelengths of 808 nm, 914 nm, 946 nm, 980 nm, 1047 nm, 1053 nm, 1064 nm, 1320 nm, and 1342 nm may also be used.

[0151] In another specific embodiment, a second semiconductor layer is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3, and under heat treatment conditions, the second dopant is diffused into the second semiconductor layer, and because the temperature is high, the first dopant in the first doped layer 3 also diffuses into the second semiconductor layer above it, so that the second semiconductor layer above the first doped layer 3 becomes a third doped layer 5, and the second semiconductor layer on the first surface of the semiconductor substrate 1 becomes a second doped layer 6.

[0152] Specifically, in the third doped layer 5 , the region close to the first doped layer 3 has the same conductivity type as that of the first doped layer 3 in at least a part of the region.

[0153] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~3×10 21 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0154] The peak doping concentration of the first dopant in a portion of the third doped layer 5 is 1×10 20 ~5×10 20 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0155] The peak doping concentration of the second dopant in the second doped layer 6 is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0156] Specifically, the heating peak temperature under the heat treatment or heating conditions is 850°C or higher, preferably 900°C or higher, and more preferably 1000°C, and may be, for example, 850°C, 900°C, 1000°C, 1100°C, 1200°C, etc. At the peak temperature, the heating time is 10 minutes or longer, preferably 30 minutes or longer, and may be, for example, 10 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes, etc.

[0157] The second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer, and the high peak temperature of the heat treatment converts the amorphous silicon or microcrystalline silicon in the second semiconductor layer into polycrystalline silicon, thereby increasing the electrical conductivity of the second semiconductor layer.

[0158] Optionally, after the heat treatment, an oxide film that may have formed during heating may be removed. The solution used to remove the oxide film layer contains fluorine, and specifically, a solution containing HF or NHF may be used to remove the oxide film layer.

[0159] In step 5, the second auxiliary layer may be a dielectric film such as silicon oxide, silicon nitride, or the like.

[0160] In step 6, the third doped layer 5, the second doped layer 6 and the second interface layer 4 underneath are removed by etching paste or laser.

[0161] Preferably, when removing the third doped layer 5, the second doped layer 6, and the underlying second interface layer 4, a portion of the semiconductor substrate 1 below the second interface layer 4 may also be removed, thereby increasing the depth of the isolation region 10. The deeper the isolation region 10, the higher the isolation effect. Generally, a certain amount of dopant in either the first or second semiconductor layer penetrates the interface layer into the semiconductor substrate, and as mentioned above, doping in the semiconductor substrate 1 also carries the risk of heat generation due to leakage or breakdown. Therefore, extending the isolation region 10 into the semiconductor substrate 1 can reduce the risk of heat generation due to leakage or breakdown.

[0162] Furthermore, after the etching step is completed, the second auxiliary layer is removed.

[0163] The method further includes the following steps 7 and 8.

[0164] In step 7, a back passivation layer 7 is formed on the surfaces of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and a front passivation layer is formed on the surface of the semiconductor substrate 1 opposite the first interface layer 2.

[0165] In step 8, a first electrode 8 is formed above the third doped layer 5, penetrating the back surface passivation layer 7, and a second electrode 9 is formed above the second doped layer 6, penetrating the back surface passivation layer 7.

[0166] Specifically, there are various methods for forming the electrodes. For example, a burn-through paste may be directly applied onto the rear surface passivation layer 7, and then the electrode paste may be passed through the rear surface passivation layer 7 after heat treatment to form contact with the third doped layer 5 and the second doped layer 6. Alternatively, holes may be first drilled on the rear surface passivation layer 7, and then electrodes may be formed using methods such as electrode paste, laser transfer, electroplating, chemical plating, light-induced plating, or physical vapor deposition such as evaporation and sputtering. Of course, electrodes may be formed using one or a combination of the above methods.

[0167] The second method for manufacturing a solar cell includes the following steps 1 to 8.

[0168] In step 1, a semiconductor substrate 1 is provided. In step 2, a first doped layer 3 is formed on one surface of the semiconductor substrate 1. Specifically, the first interface layer 2 is formed on one surface of the semiconductor substrate 1 by LPCVD, and the temperature used is 400 to 700°C.

[0169] In one specific embodiment, a first doped layer 3 is formed on the surface of the first interface layer 2 opposite to the semiconductor substrate 1 by in-situ doping LPCVD.

[0170] In another specific embodiment, a first semiconductor layer is formed on the surface of the first interface layer 2 opposite the semiconductor substrate 1, and the first dopant is doped into the first semiconductor layer, thereby forming a first doped layer 3.

[0171] The first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer.

[0172] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~5×10 21 atoms / cm 3 is.

[0173] In step 3, the first doped layer 3 is patterned so as to leave some portions. Specifically, a first auxiliary layer is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are removed by etching, thereby completing the patterning and leaving only the first doped layer 3 in the first region.

[0174] Specifically, the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride. Preferably, the silicon oxide film formed during the phosphorus doping process may be used as the first auxiliary layer. The first auxiliary layer is then patterned, and the first auxiliary layer, the first doped layer 3, and the first interface layer 2 are removed from areas other than the first region by, for example, printing a pattern using an etching paste, or by using a short-pulse laser to remove the first auxiliary layer, the first doped layer 3, and the first interface layer 2 from areas other than the first region.

[0175] In a preferred solution, an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 except for the first region, and the same alkaline solution is used to form a textured structure on the surface of the semiconductor substrate 1 in the second region. By using the alkaline solution, the patterning of the first doped layer 3 in the first region is completed, and the texture fabrication in the second region is also completed at the same time. This greatly simplifies the IBC fabrication procedure and eliminates the currently commonly used process of fabricating a single-sided texture.

[0176] There are two methods for fabricating single-sided texture in the prior art: Method 1 is to first polish the silicon wafer on both sides, then fabricate a first auxiliary layer on one side, then fabricate the texture, and then remove the first auxiliary layer after the texture fabrication is completed.

[0177] In Method 2, the silicon wafer is first double-sided polished, then a first auxiliary layer is fabricated on one side, then single-sided polished, and then the first auxiliary layer is removed.

[0178] Both of the conventional single-sided texture manufacturing methods are complicated and require the single-sided texture manufacturing process to be completed at the beginning of the battery manufacturing process, which requires at least four steps. Furthermore, the texture may be damaged during subsequent normal battery manufacturing processes, reducing the texture anti-reflection effect of the battery.

[0179] In step 4, a third doped layer 5 is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1 by heat treatment, and a second doped layer 6 is formed on the first surface of the semiconductor substrate 1 that is not covered by the first doped layer 3. Specifically, a second interface layer 4 may be formed before the second doped layer and the third doped layer are formed, and the second interface layer 4 not only covers the surface and side of the first doped layer opposite the semiconductor substrate, but also covers the first surface of the semiconductor substrate that is not covered by the first doped layer.

[0180] In one specific embodiment, a second doped layer 6 is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3 by in-situ doping LPCVD, where in-situ doping refers to simultaneously completing amorphous silicon deposition and doping. Subsequently, the second doped layer 6 above the first doped layer 3 is heat-treated, causing the first dopant in the first doped layer 3 to diffuse into the second doped layer 6 above it, and the second dopant in the second doped layer 6 above the first doped layer also diffuses into the first doped layer 3, thereby converting the second doped layer 6 above the first doped layer 3 into a third doped layer 5, while the second doped layer 6 above the first surface not covered by the first doped layer 3 remains as the second doped layer 6.

[0181] Specifically, the heating treatment is a laser treatment or a heat treatment, and when the laser treatment is used, the region of the third doped layer 5 that is directly irradiated with the laser is a first conductivity type region (the first conductivity type region penetrates the third doped layer 5 in the thickness direction), and the conductivity type thereof is the same as that of the first doped layer 3, and the doping concentration of the first dopant is higher than that of the second dopant. The power of the laser treatment is greater than 5 W, preferably 5 W to 30 W, to further improve the heating effect. The wavelength may be longer than 500 nm, and examples thereof include a green laser device with a wavelength of 532 nm, a yellow laser device with a wavelength of 589 nm, a red laser device with a wavelength of 635 nm, 660 nm, 670 nm, or 671 nm, and infrared lasers with wavelengths of 808 nm, 914 nm, 946 nm, 980 nm, 1047 nm, 1053 nm, 1064 nm, 1320 nm, and 1342 nm may also be used.

[0182] In another specific embodiment, a second semiconductor layer is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3, and the second dopant is diffused into the second semiconductor layer under heating conditions. Because the temperature is high, the first dopant in the first doped layer 3 also diffuses into the second semiconductor layer above it, so that the second semiconductor layer above the first doped layer 3 becomes a third doped layer 5, and the second semiconductor layer on the first surface of the semiconductor substrate 1 becomes a second doped layer 6.

[0183] Specifically, in the third doped layer 5 , the region close to the first doped layer 3 has the same conductivity type as that of the first doped layer 3 in at least a part of the region.

[0184] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~3×10 21 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0185] The peak doping concentration of the first dopant in a portion of the third doped layer 5 is 1×10 20 ~5×10 20 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0186] The peak doping concentration of the second dopant in the second doped layer 6 is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0187] Specifically, the heating peak temperature under the heat treatment or heating conditions is 850°C or higher, preferably 900°C or higher, and more preferably 1000°C, and may be, for example, 850°C, 900°C, 1000°C, 1100°C, 1200°C, etc. At the peak temperature, the heating time is 10 minutes or longer, preferably 30 minutes or longer, and may be, for example, 10 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes, etc.

[0188] The second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer, and the high peak temperature of the heat treatment converts the amorphous silicon or microcrystalline silicon in the second semiconductor layer into polycrystalline silicon, thereby increasing the electrical conductivity of the second semiconductor layer.

[0189] Optionally, after the heat treatment, an oxide film that may have formed during heating may be removed. The solution used to remove the oxide film layer contains fluorine, and specifically, a solution containing HF or NHF may be used to remove the oxide film layer.

[0190] In step 5, a second auxiliary layer is formed on the surfaces of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and the areas near the boundary between the third doped layer 5 and the second doped layer 6 are not covered with the second auxiliary layer.

[0191] The second auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.

[0192] In step 6, the third doped layer 5 and the second doped layer 6 that are not covered by the second auxiliary layer are removed by etching, thereby exposing the semiconductor substrate 1 (the exposed semiconductor substrate 1 is called an isolation region 10), and the third doped layer 5, the second interface layer 4, the side surfaces of the first doped layer 3 and the first interface layer 2 that are close to the isolation region 10, the surface of the semiconductor substrate 1 in the isolation region 10, and the side surfaces of the second interface layer 4 and the second doped layer 6 that are close to the isolation region 10 form one isolation region 10.

[0193] the first doped layer 3 includes a first dopant and a second dopant; the second doped layer 6 includes a second dopant; the third doped layer 5 includes a first dopant and a second dopant; the first doped layer 3 and the second doped layer 6 are of opposite conductivity types; The conductivity type of at least a portion of the third doped layer 5 is the same as the conductivity type of the first doped layer.

[0194] Specifically, the third doped layer 5, the second doped layer 6 and the second interface layer 4 thereunder are removed using an etching paste or a laser.

[0195] Preferably, when removing the third doped layer 5, the second doped layer 6, and the underlying second interface layer 4, a portion of the semiconductor substrate 1 below the second interface layer 4 may also be removed, thereby increasing the depth of the isolation region 10. The deeper the isolation region 10, the higher the isolation effect. Generally, a certain amount of dopant in either the first or second semiconductor layer penetrates the interface layer into the semiconductor substrate, and as mentioned above, doping in the semiconductor substrate 1 also carries the risk of heat generation due to leakage or breakdown. Therefore, extending the isolation region 10 into the semiconductor substrate 1 can reduce the risk of heat generation due to leakage or breakdown.

[0196] Furthermore, after the etching step is completed, the second auxiliary layer is removed.

[0197] In step 7, a back passivation layer 7 is formed on the surfaces of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and a front passivation layer is formed on the surface of the semiconductor substrate 1 opposite the first interface layer 2.

[0198] In step 8, a first electrode 8 is formed above the third doped layer 5, penetrating the back surface passivation layer 7, and a second electrode 9 is formed above the second doped layer 6, penetrating the back surface passivation layer 7.

[0199] Specifically, there are various methods for forming the electrodes. For example, a burn-through paste may be directly applied onto the rear surface passivation layer 7, and then the electrode paste may be passed through the rear surface passivation layer 7 after heat treatment to form contact with the third doped layer 5 and the second doped layer 6. Alternatively, holes may be first drilled on the rear surface passivation layer 7, and then electrodes may be formed using methods such as electrode paste, laser transfer, electroplating, chemical plating, light-induced plating, or physical vapor deposition such as evaporation and sputtering. Of course, electrodes may be formed using one or a combination of the above methods.

[0200] The second method for manufacturing a solar cell includes the following steps 1 to 7.

[0201] In step 1, a semiconductor substrate 1 is provided. In step 2, a first doped layer 3 is formed on one surface of the semiconductor substrate 1. Specifically, the first interface layer 2 is formed on one surface of the semiconductor substrate 1 by LPCVD, and the temperature used is 400 to 700°C.

[0202] In one specific embodiment, a first doped layer 3 is formed on the surface of the first interface layer 2 opposite to the semiconductor substrate 1 by in-situ doping LPCVD.

[0203] In another specific embodiment, a first semiconductor layer is formed on the surface of the first interface layer 2 opposite the semiconductor substrate 1, and the first dopant is doped into the first semiconductor layer by diffusion, thereby forming a first doped layer 3.

[0204] The first semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer.

[0205] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~5×10 21 atoms / cm 3 is.

[0206] In step 3, the first doped layer 3 is patterned so as to leave some portions. Specifically, a first auxiliary layer is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1, and then the first auxiliary layer and the first doped layer 3 above the second region are removed by etching, thereby completing the patterning and leaving only the first doped layer 3 in the first region.

[0207] Specifically, the first auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride. Preferably, the silicon oxide film formed during the phosphorus doping process may be used as the first auxiliary layer. The first auxiliary layer is then patterned, and the first auxiliary layer, the first doped layer 3, and the first interface layer 2 are removed from areas other than the first region by, for example, printing a pattern using an etching paste, or by using a short-pulse laser to remove the first auxiliary layer, the first doped layer 3, and the first interface layer 2 from areas other than the first region.

[0208] In a preferred solution, an alkaline solution is used to remove the first doped layer 3 and the first interface layer 2 except for the first region, and the same alkaline solution is used to form a textured structure on the surface of the semiconductor substrate 1 in the second region. By using the alkaline solution, the patterning of the first doped layer 3 in the first region is completed, and the texture fabrication in the second region is also completed at the same time. This greatly simplifies the IBC fabrication procedure and eliminates the currently commonly used process of fabricating a single-sided texture.

[0209] There are two methods for fabricating single-sided texture in the prior art: Method 1 is to first polish the silicon wafer on both sides, then fabricate a first auxiliary layer on one side, then fabricate the texture, and then remove the first auxiliary layer after the texture fabrication is completed.

[0210] In Method 2, the silicon wafer is first double-sided polished, then a first auxiliary layer is fabricated on one side, then single-sided polished, and then the first auxiliary layer is removed.

[0211] Both of the conventional single-sided texture manufacturing methods are complicated and require the single-sided texture manufacturing process to be completed at the beginning of the battery manufacturing process, which requires at least four steps. Furthermore, the texture may be damaged during subsequent normal battery manufacturing processes, reducing the texture anti-reflection effect of the battery.

[0212] In step 4, a second interface layer 4 is first formed, which not only covers the surface and side of the first doped layer opposite the semiconductor substrate, but also covers the first surface of the semiconductor substrate that is not covered by the first doped layer.

[0213] A second doped layer 6 is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3 by in-situ doping LPCVD, where in-situ doping refers to completing amorphous silicon deposition and doping simultaneously.

[0214] A second auxiliary layer is formed on each surface of the second doped layer 6 opposite the second interface layer 4, and the boundary portion between the second doped layer 6 and the first doped layer on the first surface of the semiconductor substrate 1 is not covered with the second auxiliary layer.

[0215] The first doped layer 3, the second doped layer 6, the first interface layer and the second interface layer that are not covered by the second auxiliary layer are all removed by etching to expose the first surface of the semiconductor substrate, thereby positioning an isolation region 10 between the first doped layer 3 and the second doped layer 6. Then, the second auxiliary layer is removed.

[0216] The second auxiliary layer may be a dielectric film such as silicon oxide or silicon nitride.

[0217] Preferably, when the first doped layer 3, the second doped layer 6, and the underlying first interface layer and second interface layer 4 are removed to expose the first surface of the semiconductor substrate 1, the corresponding portion of the semiconductor substrate 1 may be further removed, thereby increasing the depth of the isolation region 10. The deeper the isolation region 10, the higher the isolation effect. Generally, a certain amount of dopant in either the first or second semiconductor layer penetrates the interface layer into the semiconductor substrate, and as mentioned above, doping in the semiconductor substrate 1 also poses the risk of heat generation due to leakage or breakdown. Therefore, extending the isolation region 10 into the semiconductor substrate 1 reduces the risk of heat generation due to leakage or breakdown.

[0218] Furthermore, after the etching step is completed, the second auxiliary layer is removed.

[0219] In step 5, the second doped layer 6 above the first doped layer 3 is heat-treated, causing the first dopant in the first doped layer 3 to diffuse into the second doped layer 6 above it, and the second dopant in the second doped layer 6 above the first doped layer also diffuses into the first doped layer 3, thereby converting the second doped layer 6 above the first doped layer 3 into a third doped layer 5, and the second doped layer 6 above the first surface that is not covered by the first doped layer 3 remains as the second doped layer 6.

[0220] Specifically, in the third doped layer 5 , the region close to the first doped layer 3 has the same conductivity type as that of the first doped layer 3 in at least a part of the region.

[0221] The peak doping concentration of the first dopant in the first doped layer 3 is 1×10 19 ~3×10 21 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0222] The peak doping concentration of the first dopant in a portion of the third doped layer 5 is 1×10 20 ~5×10 20 atoms / cm 3 and the peak doping concentration of the second dopant is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0223] The peak doping concentration of the second dopant in the second doped layer 6 is 1×10 19 ~3×10 19 atoms / cm 3 is.

[0224] Specifically, the heating peak temperature under the heat treatment or heating conditions is 850°C or higher, preferably 900°C or higher, and more preferably 1000°C, and may be, for example, 850°C, 900°C, 1000°C, 1100°C, 1200°C, etc. At the peak temperature, the heating time is 10 minutes or longer, preferably 30 minutes or longer, and may be, for example, 10 minutes, 20 minutes, 30 minutes, 40 minutes, 50 minutes, 60 minutes, etc.

[0225] The second semiconductor layer may be a polycrystalline silicon layer, a microcrystalline silicon layer, or an amorphous silicon layer, and the high peak temperature of the heat treatment converts the amorphous silicon or microcrystalline silicon in the second semiconductor layer into polycrystalline silicon, thereby increasing the electrical conductivity of the second semiconductor layer.

[0226] Optionally, after the heat treatment, an oxide film that may have formed during heating may be removed. The solution used to remove the oxide film layer contains fluorine, and specifically, a solution containing HF or NHF may be used to remove the oxide film layer.

[0227] the first doped layer 3 includes a first dopant and a second dopant; the second doped layer 6 includes a second dopant; the third doped layer 5 includes a first dopant and a second dopant; the first doped layer 3 and the second doped layer 6 are of opposite conductivity types; The conductivity type of at least a portion of the third doped layer 5 is the same as the conductivity type of the first doped layer.

[0228] In step 6, a back passivation layer 7 is formed on the surfaces of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and a front passivation layer is formed on the surface of the semiconductor substrate 1 opposite the first interface layer 2.

[0229] In step 7, a first electrode 8 is formed above the third doped layer 5, penetrating the back surface passivation layer 7, and a second electrode 9 is formed above the second doped layer 6, penetrating the back surface passivation layer 7.

[0230] Specifically, there are various methods for forming the electrodes. For example, a burn-through paste may be directly applied onto the rear passivation layer 7, and then heat-treated to allow the electrode paste to pass through the rear passivation layer 7 and make contact with the third doped layer 5 and the second doped layer 6. Alternatively, holes may be first drilled on the rear passivation layer 7, and then electrodes may be formed using methods such as electrode paste, laser transfer, electroplating, chemical plating, light-induced plating, or physical vapor deposition such as evaporation and sputtering. Of course, electrodes may be formed using one or a combination of the above methods. Example

[0231] All experimental methods used in the following examples are conventional methods unless otherwise required.

[0232] Unless otherwise specified, all materials, reagents, etc. used in the following examples are commercially available. Example 1

[0233] The solar cell in this example is a first solar cell, and includes the following steps 1 to 7.

[0234] In step 1, a semiconductor substrate 1 is provided. A p-type silicon wafer was prepared as the semiconductor substrate 1, and its thickness was 200 μm.

[0235] In step 2, a first doped layer 3 is formed on one surface of the semiconductor substrate 1. Specifically, a first interface layer 2 is formed on one surface of the semiconductor substrate 1 using LPCVD at a temperature of 700°C, and a phosphorus-doped amorphous silicon layer 3 is formed on the surface of the first interface layer 2 opposite the semiconductor substrate 1. The phosphorus-doped amorphous silicon 3 is formed by in-situ doping LPCVD, with a deposition source of SiH4 and a phosphorus-containing doping source of PH3.

[0236] The first interface layer 2 is a silicon oxide layer with a thickness of 1 nm, and the intrinsic amorphous silicon layer is 100 nm thick.

[0237] The peak doping concentration of the first dopant in the first doped layer 3 is 3×10 21 atoms / cm 3 is.

[0238] In step 3, the first doped layer 3 is patterned so as to leave some portions. Specifically, a 20 nm thick silicon oxide layer (i.e., a first auxiliary layer) is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1, and then a short-pulse laser is used to etch away the silicon oxide, the first doped layer 3, and the first interface layer 2 above the second region, thereby completing the patterning and leaving only the first doped layer 3 in the first region.

[0239] In step 4, a silicon oxide layer (i.e., a second auxiliary layer) is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1, covering the first doped layer 3 and the surface of the semiconductor substrate 1 that is not covered by the first doped layer 3, and has a thickness of 20 nm. In step 5, a second doped layer 6 is formed on the surface of the second interface layer 4 opposite the semiconductor substrate 1 and the first doped layer 3 by in-situ doping LPCVD. In-situ doping refers to simultaneously completing amorphous silicon deposition and doping. The second doped layer 6 is 25 nm thick, and the boron-containing dopant used in in-situ doping is BH, thereby forming the second doped layer 6. Subsequently, the second doped layer 6 above the first doped layer 3 is heat-treated (peak temperature 900°C, heating time 30 minutes), causing the phosphorus in the first doped layer 3 to diffuse into the second doped layer 6 above it. The boron in the second doped layer 6 in the first region also diffuses into the first doped layer 3, thereby converting the corresponding second doped layer 6 in the first region into a third doped layer 5, while the corresponding second doped layer 6 in the second region remains as a second doped layer 6. Due to the high heat treatment temperature, the amorphous silicon layer is converted into a polycrystalline silicon layer. Any region in the third doped layer 5 has the same conductivity as the first doped layer 3 .

[0240] The peak doping concentration of phosphorus in the first doped layer 3 is 2×1021 atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0241] The peak doping concentration of phosphorus in the third doped layer 5 is 2×10 21 atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0242] The second doped layer 6 has a thickness of 25 nm and a doping concentration of boron of 2×10 19 atoms / cm 3 is.

[0243] In step 6, a back surface passivation layer 7 (a 15 nm thick aluminum oxide layer) is formed on the surface of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and a front surface passivation layer (a 15 nm thick aluminum oxide layer) is formed on the surface of the semiconductor substrate 1 opposite the first interface layer 2.

[0244] In step 7, a first electrode 8 is formed above the third doped layer 5 and penetrates the back surface passivation layer 7, and a second electrode 9 is formed above the second doped layer 6 and penetrates the back surface passivation layer 7. Both the first electrode 8 and the second electrode 9 are silver electrodes.

[0245] The performance of the solar cell is shown in Table 1. Example 2

[0246] The solar cell in this example is a second solar cell, and includes the following steps 1 to 9.

[0247] In step 1, a semiconductor substrate 1 is provided. A p-type silicon wafer was prepared as the semiconductor substrate 1, and its thickness was 200 μm.

[0248] In step 2, a first doped layer 3 is formed on one surface of the semiconductor substrate 1. Specifically, a first interface layer 2 is formed on one surface of the semiconductor substrate 1 using LPCVD at a temperature of 700°C, and a phosphorus-doped amorphous silicon layer 3 is formed on the surface of the first interface layer 2 opposite the semiconductor substrate 1. This phosphorus-doped amorphous silicon is formed by in-situ doping LPCVD, with a deposition source of SiH4 and a phosphorus-containing doping source of PH3.

[0249] The first interface layer 2 is a silicon oxide layer with a thickness of 1 nm, and the intrinsic amorphous silicon layer is 100 nm thick.

[0250] The peak doping concentration of the first dopant in the first doped layer 3 is 3×10 21 atoms / cm 3 is.

[0251] In step 3, the first doped layer 3 is patterned so as to leave some portions. Specifically, a 20 nm thick silicon oxide layer (i.e., a first auxiliary layer) is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1, and then a short-pulse laser is used to etch away the silicon oxide, the first doped layer 3, and the first interface layer 2 above the second region, thereby completing the patterning and leaving only the first doped layer 3 in the first region.

[0252] In step 4, a silicon oxide layer (i.e., a second auxiliary layer) is formed on the surface of the first doped layer 3 opposite the semiconductor substrate 1, covering the first doped layer 3 and the surface of the semiconductor substrate 1 that is not covered by the first doped layer 3, and has a thickness of 20 nm. In step 5, a second doped layer 6 is formed on the surface of the second interface layer 4 opposite the semiconductor substrate 1 and the first doped layer 3 by in-situ doping LPCVD. In-situ doping refers to simultaneously completing amorphous silicon deposition and doping. The second doped layer 6 is 25 nm thick, and the boron-containing dopant used in in-situ doping is BH, thereby forming the second doped layer 6. Subsequently, the second doped layer 6 above the first doped layer 3 is heat-treated (peak temperature 900°C, heating time 30 minutes), causing the phosphorus in the first doped layer 3 to diffuse into the second doped layer 6 above it. The boron in the second doped layer 6 in the first region also diffuses into the first doped layer 3, thereby converting the corresponding second doped layer 6 in the first region into a third doped layer 5, while the corresponding second doped layer 6 in the second region remains as a second doped layer 6. Due to the high heat treatment temperature, the amorphous silicon layer is converted into a polycrystalline silicon layer. Any region in the third doped layer 5 has the same conductivity as the first doped layer 3 .

[0253] The peak doping concentration of phosphorus in the first doped layer 3 is 2×10 21 atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0254] The peak doping concentration of phosphorus in the third doped layer 5 is 2×10 21 atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0255] The second doped layer 6 has a thickness of 25 nm and a doping concentration of boron of 2×10 19 atoms / cm 3 is.

[0256] In step 6, a second auxiliary layer is formed on the surfaces of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and the areas near the boundary between the third doped layer 5 and the second doped layer 6 are not covered with the second auxiliary layer.

[0257] The second auxiliary layer may be silicon oxide and has a thickness of 20 nm.

[0258] In step 7, a short-pulse laser is used to etch away the third doped layer 5, the second doped layer 6 and the second interface layer 4 underneath that are not covered by the second auxiliary layer, thereby exposing the semiconductor substrate 1 (the exposed semiconductor substrate 1 is called an isolation region 10), and the sides of the third doped layer 5, the second interface layer 4, the first doped layer 3 and the first interface layer 2 close to the isolation region 10, the surface of the semiconductor substrate 1 in the isolation region 10, and the sides of the isolation region 10 close to the second interface layer 4 and the second doped layer 6 form one isolation region 10, and the width w of the isolation region 10 is 100 μm.

[0259] After the etching step is completed, the second auxiliary layer is removed and then the second auxiliary layer is removed using an acid solution of dilute hydrofluoric acid.

[0260] In step 8, a back surface passivation layer 7 (a 15 nm thick aluminum oxide layer) is formed on the surface of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and a front surface passivation layer (a 15 nm thick aluminum oxide layer) is formed on the surface of the semiconductor substrate 1 opposite the first interface layer 2.

[0261] In step 9, a first electrode 8 is formed above the third doped layer 5 and penetrates the back surface passivation layer 7, and a second electrode 9 is formed above the second doped layer 6 and penetrates the back surface passivation layer 7. Both the first electrode 8 and the second electrode 9 are silver electrodes.

[0262] The performance of the solar cell is shown in Table 1. Example 3

[0263] The differences between Example 3 and Example 2 are as follows: the thickness of the second doped layer 6 is different; in this example, the thickness of the second doped layer 6 is 50 nm, and a portion of the third doped layer 5 has the same conductivity as the first doped layer 3. The performance of the solar cell is shown in Table 1. Example 4

[0264] The differences between Example 4 and Example 2 are as follows: the thickness of the second doped layer 6 is different; in this example, the thickness of the second doped layer 6 is 100 nm, and a portion of the third doped layer 5 has the same conductivity as the first doped layer 3. The performance of the solar cell is shown in Table 1. Example 5

[0265] The difference between Example 5 and Example 2 is in step 5. In step 5 of Example 5, an amorphous silicon layer having a thickness of 25 nm is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3. The boron is doped into the amorphous silicon layer by boron diffusion. The boron-containing dopant is BBr3. The peak temperature of the boron diffusion is 900°C. The heating time is 30 minutes. This results in the formation of a second doped layer 6. The phosphorus in the first doped layer 3 is diffused into the second doped layer 6 thereon. The boron in the second doped layer 6 on the first region also diffuses into the first doped layer 3. This converts the corresponding second doped layer 6 on the first region into a third doped layer 5, while the corresponding second doped layer 6 on the second region remains as the second doped layer 6. Due to the high temperature of the boron diffusion process, the amorphous silicon layer is converted into a polycrystalline silicon layer. Any region in the third doped layer 5 has the same conductivity as the first doped layer 3 .

[0266] The peak doping concentration of phosphorus in the first doped layer 3 is 2×10 21 atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0267] The peak doping concentration of phosphorus in the third doped layer 5 is 2×10 21atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0268] The second doped layer 6 has a thickness of 25 nm and a doping concentration of boron of 2×10 19 atoms / cm 3 is.

[0269] The performance of the solar cell is shown in Table 1. Example 6

[0270] The differences between the sixth embodiment and the second embodiment are as follows. In step 5, a second doped layer 6 is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3 by in-situ doping LPCVD, where in-situ doping refers to simultaneously completing amorphous silicon deposition and doping. The second doped layer 6 is 25 nm thick, and the boron-containing doping material used in in-situ doping is B2H6, thereby forming the second doped layer 6.

[0271] In step 6, a second auxiliary layer is formed on the surfaces of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and the areas near the boundary between the third doped layer 5 and the second doped layer 6 are not covered with the second auxiliary layer.

[0272] The second auxiliary layer may be silicon oxide and has a thickness of 20 nm.

[0273] In step 7, a short-pulse laser is used to etch away the third doped layer 5, the second doped layer 6 and the second interface layer 4 underneath that are not covered by the second auxiliary layer, thereby exposing the semiconductor substrate 1 (the exposed semiconductor substrate 1 is called an isolation region 10), and the sides of the third doped layer 5, the second interface layer 4, the first doped layer 3 and the first interface layer 2 close to the isolation region 10, the surface of the semiconductor substrate 1 of the isolation region 10, and the sides of the second interface layer 4 and the second doped layer 6 close to the isolation region 10 form one isolation region 10, and the width w of the isolation region 10 is 100 μm.

[0274] After the etching step is completed, the second auxiliary layer is removed and then the second auxiliary layer is removed using an acid solution of dilute hydrofluoric acid.

[0275] In step 8, the second doped layer 6 above the first doped layer 3 is heat-treated (peak temperature 900°C, heating time 30 minutes) to diffuse the phosphorus in the first doped layer 3 into the second doped layer 6 above it, and the boron in the second doped layer 6 on the first region also diffuses into the first doped layer 3, thereby converting the corresponding second doped layer 6 on the first region into the third doped layer 5, while the corresponding second doped layer 6 on the second region remains as the second doped layer 6. Also, due to the high temperature of the heat treatment, the amorphous silicon layer is converted into a polycrystalline silicon layer. Any region in the third doped layer 5 has the same conductivity as the first doped layer 3.

[0276] The peak doping concentration of phosphorus in the first doped layer 3 is 2×10 21 atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0277] The peak doping concentration of phosphorus in the third doped layer 5 is 2×10 21 atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0278] The second doped layer 6 has a thickness of 25 nm and a doping concentration of boron of 2×10 19 atoms / cm 3 is.

[0279] In step 9, a back surface passivation layer 7 (a 15 nm thick aluminum oxide layer) is formed on the surface of the third doped layer 5 and the second doped layer 6 opposite the second interface layer 4, and a front surface passivation layer (a 15 nm thick aluminum oxide layer) is formed on the surface of the semiconductor substrate 1 opposite the first interface layer 2.

[0280] In step 10, a first electrode 8 is formed above the third doped layer 5 and penetrates the back surface passivation layer 7, and a second electrode 9 is formed above the second doped layer 6 and penetrates the back surface passivation layer 7. Both the first electrode 8 and the second electrode 9 are silver electrodes.

[0281] The performance of the solar cell is shown in Table 1. Example 7

[0282] The differences between Example 7 and Example 2 are as follows: The thickness of the second doped layer 6 is different. In this example, the thickness of the second doped layer 6 is 200 nm, and a part of the third doped layer 5 has the same conductivity as the first doped layer 3.

[0283] The performance of the solar cell is shown in Table 1. Example 8

[0284] The difference between Example 8 and Example 2 is in step 5. In step 5 of Example 8, a boron-containing polycrystalline silicon layer is formed on the surface of the second interface layer 4 opposite to the semiconductor substrate 1 and the first doped layer 3 by an in-situ doping method, using B2H6 as a doping source during the in-situ doping, and the formed polycrystalline silicon has a thickness of 100 nm, thereby forming a second doped layer 6. Next, a laser is locally irradiated onto a first region of the second doped layer 6 above the first doped layer 3 (the laser power for the laser treatment is 25 W, and the laser is a green laser device with a wavelength of 532 nm), causing the phosphorus in the first doped layer 3 to diffuse into the first region of the second doped layer 6 thereon, and the boron in the second doped layer 6 on the first region also diffuses into the first doped layer 3, thereby converting the corresponding second doped layer 6 on the first region into a third doped layer 5, and the doping concentration of the first dopant in the laser-irradiated region of the third doped layer 5 is greater than the doping concentration of the second dopant, and its conductivity type is the same as that of the first doped layer 3, while the corresponding second doped layer 6 on the second region not irradiated with the laser remains the second doped layer 6, the first region is a first electrode region, and the region in contact with the first electrode in the third doped layer 5 has the same conductivity as the first doped layer 3.

[0285] The peak doping concentration of phosphorus in the first doped layer 3 is 2×10 21 atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0286] The peak doping concentration of phosphorus in the third doped layer 5 is 2×10 21 atoms / cm 3 and the peak doping concentration of boron is 2×10 19 atoms / cm 3 is.

[0287] The second doped layer 6 has a thickness of 100 nm and a doping concentration of boron of 2×10 19 atoms / cm 3is.

[0288] The performance of the solar cell is shown in Table 1.

[0289] [Table 1]

[0290] Conclusion: As can be seen from Table 1, comparing Example 1 and Example 2, forming a spacing region between the p-type and n-type regions on the battery and using it to isolate the p-type and n-type semiconductor regions reduces the recombination at the pn junction site, reduces lateral leakage, and improves both the open circuit voltage and fill factor to a certain extent.

[0291] Comparing Example 2 and Example 5, Example 5 uses boron diffusion instead of in-situ doped boron diffusion, and the surface concentration of the boron diffusion is slightly higher than that of the in-situ doped boron, which reduces the contact resistance, improves the FF to a certain extent, and slightly reduces the open circuit voltage, while maintaining the same efficiency.

[0292] A comparison of Examples 2, 3, 4, and 7 reveals that Example 3 has the highest efficiency. The main reasons for this are as follows: In Example 2, the second doped layer is 25 nm thick, and the entire third doped layer is inverted to n-type. However, because the second doped layer is thin (also 25 nm), the second doped layer cannot completely block metallic recombination at the second electrode, resulting in a slightly lower open-circuit voltage than Example 3. In Example 4, the second doped layer is 100 nm thick, and only the bottom layer of the third doped layer is inverted to n-type, with some of the top layer still remaining p-type. This means that the first electrode penetrates the surface third doped layer to contact the bottom n-type third doped layer, resulting in a slightly lower FF than Example 3. In Example 7, the second doped layer is 200 nm thick, and the third doped layer is thick, resulting in poor contact between the first electrode and the n-type bottom layer of the third doped layer, which affects the fill factor.

[0293] As can be seen from a comparison between Example 2 and Example 6, there is no significant difference between forming the spacing region and then heating, and heating and then forming the spacing region, and the electrical performance is also similar.

[0294] Compared with Example 4, in Example 8, the laser continues to heat the electrode region, so that the top p-type polycrystalline silicon layer below the electrode continues to convert to n-type, forming better contact between the first electrode and the n-type doped semiconductor, and improving the fill factor.

[0295] Therefore, the solar cell described in the present disclosure requires only one patterning and one high-temperature heat treatment, and the doped regions produced by this method have a passivation contact structure on both electrodes, which has a high passivation effect and significantly reduces the recombination rate in the metal region, thereby improving the cell efficiency and reducing the thermal damage caused by the high-temperature heat treatment.

[0296] Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above specific embodiments and application fields, and the above specific embodiments are merely illustrative and instructive, and are not limiting. A person skilled in the art can realize various configurations under the teachings of this specification without departing from the scope of the claims of the present disclosure, and all of them are included in the protection scope of the present disclosure. [Explanation of symbols]

[0297] 1. Semiconductor substrate 2 First interface layer 3 First doped layer 4 Second interface layer 5 Third doped layer 6 Second doped layer 7 Backside passivation layer 8 1st electrode 9 Second electrode 10 Quarantine area 11 Third doped region 12 Fourth doped region

Claims

1. providing a semiconductor substrate; forming a first doped layer on a first surface of the semiconductor substrate; patterning the first doped layer to leave a portion; forming a third doped layer on a surface of the first doped layer opposite the semiconductor substrate by a heat treatment, and forming a second doped layer on a first surface of the semiconductor substrate not covered by the first doped layer; the first doped layer includes a first dopant and a second dopant; the second doped layer includes a second dopant; the third doped layer includes a first dopant and a second dopant; the first doped layer and the second doped layer are of opposite conductivity types; At least a portion of the third doped layer has the same conductivity type as the first doped layer; The step of forming a third doped layer on a surface of the first doped layer opposite the semiconductor substrate by a heat treatment, and forming a second doped layer on a first surface of the semiconductor substrate not covered by the first doped layer, includes: forming a second doped layer on a surface of the first doped layer opposite the semiconductor substrate and on a first surface of the semiconductor substrate not covered by the first doped layer; a second doped layer above the first doped layer is heat-treated to diffuse a first dopant in the first doped layer into the second doped layer thereon, and a second dopant in the second doped layer also diffuses into the first doped layer, thereby converting the second doped layer above the first doped layer into a third doped layer.

2. Prior to forming the third doped layer, the peak doping concentration of the first dopant in the first doped layer is 1×10 １９ ~5 x 10 ２１ atoms / cm ３ The method according to claim 1, wherein

3. After forming the third doped layer, the doping concentration of the first dopant in the first doped layer is greater than the doping concentration of the second dopant; 2. The method of claim 1, wherein the doping concentration of the first dopant in at least a portion of the third doped layer is greater than the doping concentration of the second dopant in at least a portion of the third doped layer.

4. The peak doping concentration of the first dopant in the first doped layer is 1×10 １９ ~3 x 10 ２１ atoms / cm ３ and In the second doped layer, the peak doping concentration of the second dopant is 1×10 １９ ~3 x 10 １９ atoms / cm ３ and a peak doping concentration of the first dopant in at least a portion of the third doped layer is greater than or equal to 1×10 ２０ ~5 x 10 ２０ atoms / cm ３ The method according to claim 3, wherein

5. After forming the third doped layer, 2. The method of claim 1, further comprising the step of: removing the first doped layer, the second doped layer, and the third doped layer at a boundary between the second doped layer and the first doped layer on the first surface of the semiconductor substrate by etching to expose the first surface of the semiconductor substrate, thereby positioning an isolation region between the first doped layer and the second doped layer.

6. a semiconductor substrate having a first doped layer and a second doped layer on a first surface of the semiconductor substrate, and a third doped layer on a surface of the first doped layer opposite the semiconductor substrate; the first doped layer includes a first dopant and a second dopant; the second doped layer includes a second dopant; the third doped layer includes a first dopant and a second dopant; At least a portion of the third doped layer has the same conductivity type as the first doped layer; the first doped layer and the second doped layer are of opposite conductivity types; a peak doping concentration of the first dopant in at least a portion of the third doped layer is greater than a peak doping concentration of the second dopant; The solar cell, wherein the first doped layer, the second doped layer and the third doped layer are all doped polycrystalline silicon layers.

7. the thickness of the first doped layer is 50 to 300 nm; 7. The solar cell according to claim 6, wherein the third doped layer and the second doped layer have the same thickness, each of which is 150 nm or less.

8. 8. The solar cell according to claim 7, wherein when the thickness d of the third doped layer is 30 nm or less, the entire area of ​​the third doped layer has the same conductivity type as the first doped layer.

9. 8. The solar cell according to claim 7, wherein when the thickness of the third doped layer is 30 nm<d≦150 nm, the conductivity of at least a portion of the region of the third doped layer close to the first doped layer is the same as the conductivity type of the first doped layer.

10. 8. The solar cell of claim 7, wherein when the thickness of the third doped layer is 30 nm<d≦150 nm, a region of the third doped layer having the same conductivity type as the first doped layer penetrates the third doped layer in the thickness direction.

11. 7. The solar cell of claim 6, wherein in the first doped layer, the doping concentration of the first dopant increases and then decreases from the surface opposite the semiconductor substrate to the surface on the semiconductor substrate side, and the doping concentration of the second dopant gradually decreases.

12. 7. The solar cell according to claim 6, wherein the doping concentration of the second dopant in the second doped layer is the same from the surface opposite to the semiconductor substrate to the surface on the semiconductor substrate side.

13. In the third doped layer, the doping concentration of the first dopant gradually increases from a surface opposite to the semiconductor substrate to a surface facing the semiconductor substrate; 7. The solar cell according to claim 6, wherein the doping concentration of the second dopant is the same from the surface opposite to the semiconductor substrate to the surface on the semiconductor substrate side.

14. 7. The solar cell of claim 6, wherein the third doped layer not only covers the surface of the first doped layer opposite the semiconductor substrate, but also covers a side surface of the first doped layer close to the second doped layer, and the third doped layer covering the side surface of the first doped layer is in contact with the second doped layer.

15. a first interface layer located between the semiconductor substrate and the first doped layer; and / or a second interface layer extending from a surface of the first doped layer opposite the first interface layer to a side thereof and covering a portion of the semiconductor substrate not covered by the first doped layer, and the second doped layer and the third doped layer being respectively provided on one side surface of the second interface layer; and / or 15. The solar cell of claim 14, further comprising a back surface passivation layer, the back surface passivation layer covering the third doped layer and the second doped layer.

16. 7. The solar cell of claim 6, wherein the first doped layer and the third doped layer have the same width, and an isolation region is located between the first doped layer and the third doped layer and the second doped layer.

17. a first interface layer located between the semiconductor substrate and the first doped layer; and / or 17. The solar cell of claim 16, further comprising a second interface layer, the second interface layer being located between the first doped layer and the third doped layer and between the second doped layer and the semiconductor substrate; and / or a back surface passivation layer, the back surface passivation layer covering the third doped layer, the isolation region, and the second doped layer.

18. 18. The solar cell of claim 15, further comprising a first electrode and a second electrode, wherein the first electrode penetrates the rear surface passivation layer and contacts a region of the third doped layer that has the same conductivity type as the first doped layer, and the second electrode penetrates the rear surface passivation layer and contacts the second doped layer.

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