Filters and Multiplexers

Abstract

To provide a filter with which it is possible to suppress the leakage of a high frequency signal between terminals.SOLUTION: A filter 100 comprises: a laminate in which a plurality of dielectric layers are laminated; an input terminal Tin that is provided to the surface of the laminate; an output terminal Tout that is provided to the surface of the laminate; a path 40 that is provided inside of the laminate, and along which a high frequency signal is transferred from the input terminal Tin to the output terminal Tout; a first terminal that is provided to the surface of the laminate, and where a high frequency signal is neither inputted nor outputted; a second terminal which is one of the input terminal Tin and the output terminal Tout; and a line M1 that is provided in the laminate, and is connected at one end to a node N1 which is provided in the path 40 so that a DC current is conducted to and from the second terminal and connected at other end to the first terminal, and the impedance of which, at the center frequency of a passband, is almost open when the first terminal is seen from the node N1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to filters and multiplexers. [Background technology]

[0002] Wireless communication terminals for LTE (Long Term Evolution) and 5G (5th Generation) mobile communication systems, etc., use filters that remove unwanted interference waves. A known filter has a laminate in which dielectric layers are stacked. An electrolytic plating process or the like can cause the thickness of terminals provided on the surface of the laminate to become non-uniform. To prevent this, it is known to provide plating electrodes that conduct direct current (DC) to some of the terminals (see, for example, Patent Document 1). It is also known to form a plating film on the terminals and then cut off the short-circuit pattern connecting the terminals (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2016-39334 [Patent Document 2] Japanese Utility Model Application Publication No. 6-52127 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Documents 1 and 2, the thickness of the terminals can be made uniform. However, the provision of plating electrodes increases the size of the laminate. In addition, the number of processes increases due to the cutting of the short pattern. These factors increase the cost of the filter. It is conceivable to connect the terminals using a line that conducts direct current to prevent the thickness from varying. However, high-frequency signals leak between the terminals via the line. As such, there are cases where it is necessary to connect the terminals so that direct current flows between them, but to provide a line that prevents high-frequency signals from leaking.

[0005] The present invention has been made in view of the above-mentioned problems, and has as its object to suppress leakage of high frequency signals between terminals. [Means for solving the problem]

[0006] The present invention relates to a laminate in which a plurality of dielectric layers are stacked, an input terminal provided on the surface of the laminate, an output terminal provided on the surface of the laminate, a path provided within the laminate for transmitting a high frequency signal from the input terminal to the output terminal, and a signal path provided on the surface of the laminate for inputting and outputting a high frequency signal. Not The filter includes a first terminal, a second terminal that is either the input terminal or the output terminal, and a line that is provided within the laminate, one end of which is connected to a node provided in the path so that a direct current flows between the first terminal and the second terminal, and the other end of which is connected to the first terminal, and the impedance when viewed from the node to the first terminal at the center frequency of the pass band is approximately open.

[0007] In the above configuration, the configuration may include a third terminal that is the other of the input terminal and the output terminal other than the second terminal, and another line that is provided within the laminate, has one end connected to another node provided in the path so that a direct current flows between the third terminal and the other end connected to the first terminal, and has an impedance that is substantially open when the first terminal is viewed from the other node at the center frequency.

[0008] In the above configuration, the impedance at the center frequency when viewed from the node via the line to the first terminal can be configured such that, when a Smith chart is expressed in polar coordinates with an angle of 0° at an open position and a radius of the outer periphery being 1, the angle is equal to or less than +45° and equal to or greater than −45°, and the radius is equal to or greater than 0.8 and equal to or less than 1.0.

[0009] In the above configuration, the line is formed from one conductor layer provided between adjacent dielectric layers among the plurality of dielectric layers, and when assuming a microstrip line formed with the nearest ground pattern, the effective relative dielectric constant is εreff and the center frequency is f0, the length is 6.18×10 7 ×√(εreff) / f0 or greater and 1.031×10 7 ×√(εreff) / f0 or less.

[0010] In the above configuration, the line can be formed from one conductor layer provided between adjacent dielectric layers among the plurality of dielectric layers, and can have a line pattern whose shape, when viewed from the stacking direction of the plurality of dielectric layers, includes a spiral portion.

[0011] In the above configuration, when viewed from the stacking direction of the plurality of dielectric layers, the area of ​​a region in the spiral region of the line pattern that overlaps with the nearest ground pattern can be 0.3 times or less the area of ​​the spiral region of the line pattern.

[0012] In the above configuration, the line is formed from one conductor layer provided between adjacent dielectric layers among the plurality of dielectric layers, and has a width that is equal to the width at which a high-frequency signal is transmitted within the laminate. will be The line pattern may have the smallest width among the line patterns.

[0013] The present invention relates to a laminate in which a plurality of dielectric layers are stacked, an input terminal provided on the surface of the laminate, an output terminal provided on the surface of the laminate, a path provided within the laminate for transmitting a high frequency signal from the input terminal to the output terminal, and a signal path provided on the surface of the laminate for inputting and outputting a high frequency signal. Nota second terminal which is either the input terminal or the output terminal; and a line which is provided within the laminate, the line having one end connected to a node provided in the path so that a direct current flows between the first terminal and the second terminal and the other end connected to the first terminal, the impedance of the first terminal as viewed from the node at the center frequency of the pass band being within a range of +45° or less and -45° or more, and a radius of 0.8 or more and 1.0 or less, when a Smith chart is represented in polar coordinates with an angle of 0° at an open position and a radius of 1.

[0014] The above configuration can include a third terminal which is the other of the input terminal and the output terminal that is not the second terminal, and another line which is provided within the laminate, one end of which is connected to another node provided in the path so that a direct current flows between the third terminal and the other end of which is connected to the first terminal, and the impedance when the first terminal is viewed from the other node at the center frequency is an angle of not more than +45° and not more than −45° when a Smith chart is represented by polar coordinates, and is located with a radius of not less than 0.8 and not more than 1.0.

[0015] In the above configuration, the first terminal and the second terminal may be connected to each other via no path other than the line through which a direct current flows.

[0016] In the above configuration, the area of ​​the second terminal may be half or less or twice or more the area of ​​the first terminal.

[0017] In the above configuration, the first terminal may be a ground terminal.

[0018] The present invention is a multiplexer including the above filter. [Effects of the Invention]

[0019] According to the present invention, leakage of high frequency signals between terminals can be suppressed. [Brief explanation of the drawings]

[0020] [Figure 1] 1A and 1B are circuit diagrams of a filter according to a first embodiment. [Figure 2] 2(a) and 2(b) are a perspective view and a cross-sectional view of the filter according to the first embodiment. [Figure 3] FIG. 3 is an exploded perspective view of the dielectric layer in the first embodiment. [Figure 4] FIG. 4 is an exploded perspective view of the dielectric layer in the first embodiment. [Figure 5] 5(a) to 5(c) are plan views of the dielectric layers in Example 1. FIG. [Figure 6] 6(a) to 6(c) are plan views of the dielectric layers in Example 1. FIG. [Figure 7] 7(a) to 7(c) are plan views of the dielectric layers in Example 1. FIG. [Figure 8] 8(a) to 8(c) are diagrams showing the transmission characteristics and reflection characteristics of each filter in Simulation 1. FIG. [Figure 9] 9(a) to 9(c) are perspective views showing line patterns M1a and M2a in filter A. FIG. [Figure 10] FIG. 10 is a perspective view showing line patterns M1a and M2a in filter B. As shown in FIG. [Figure 11] FIG. 11 is a diagram showing the pass characteristics S21 of filters A to C in simulation 2. In FIG. [Figure 12] 12(a) and 12(b) are diagrams showing the pass characteristics S21 and the reflection characteristics S11 in the vicinity of the pass bands of filters A to C, respectively, in simulation 2. FIG. [Figure 13] FIG. 13(a) is a perspective view of a microstrip line, and FIG. 13(b) is a Smith chart of the impedance when looking from one end of the microstrip line to the other end. [Figure 14] FIG. 14 is a diagram showing the insertion loss of a filter relative to the phase of a microstrip line. [Figure 15] FIG. 15 is a diagram showing the insertion loss of the filter B for the line patterns M1a and M2a. [Figure 16] 16(a) and 16(b) are plan views of the line pattern M1a and the terminals. [Figure 17] FIG. 17 is a diagram showing the insertion loss versus the area ratio. [Figure 18] FIG. 18 is a circuit diagram of a diplexer in accordance with the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. [Example]

[0022] A bandpass filter (BPF) used in 5G will be described as an example in Example 1. 5G uses millimeter waves such as the 28 GHz band, and even a filter with a passband of 6 GHz or less is required to have an attenuation band up to around 30 GHz.

[0023] 1(a) and 1(b) are circuit diagrams of a filter according to a first embodiment. FIG. 1(b) is a circuit diagram showing an example of a filter circuit F1. As shown in FIG. 1(a), a high-frequency signal input to an input terminal Tin is transmitted through a path 40 and output from an output terminal Tout. A filter circuit F1 is provided on the path 40. The filter circuit F1 is a BPF. A transmission line R0 and a capacitor C1 are provided between the input terminal Tin and the filter circuit F1. A transmission line R0 and a capacitor C1 are provided between the filter circuit F1 and the output terminal Tout. The transmission line R0 is a line connecting the input terminal Tin or the output terminal Tout to the filter circuit F1. The capacitor C1 passes the high-frequency signal and blocks DC current.

[0024] Nodes N1 and N2 are provided within the path 40. The node N1 is DC-connected to the input terminal Tin and is not DC-connected to the output terminal Tout. The node N2 is DC-connected to the output terminal Tout and is not DC-connected to the input terminal Tin. One end of the line M1 is connected to the node N1 and the other end is connected to the ground terminal Tg. One end of the line M2 is connected to the node N2 and the other end is connected to the ground terminal Tg. The line M1 DC-connects between the node N1 and the ground terminal Tg, and leaves the node N1 and the ground terminal Tg substantially open in the pass band. The line M2 DC-connects between the node N2 and the ground terminal Tg, and leaves the node N2 and the ground terminal Tg substantially open in the pass band.

[0025] As shown in FIG. 1(b), the filter circuit F1 includes transmission lines R1 to R3 and capacitors C2 to C5. The filter 100 has an input terminal Tin and an output terminal Tout that are symmetrical with respect to the capacitors C5 and C4. The symmetrical capacitors C1 to C3, transmission lines R0 to R3, and nodes N3 and N4 are denoted by the same reference numerals. The transmission line R1, capacitor C5, and transmission line R1 are connected in series to a path 40. The capacitor C2, transmission line R2, and capacitor C3 are connected in series between a node N3 between the transmission line R1 and capacitor C5 and a node N4. The transmission line R3 is connected to the node N4 as an open stub. The capacitor C4 is connected between the node N4 and the transmission line R3. The filter 100 may have an asymmetrical input terminal Tin and an output terminal Tout.

[0026] 2(a) and 2(b) are a perspective view and a cross-sectional view of the filter according to Example 1. The stacking direction of the dielectric layers 11a to 11i is defined as the Z direction, the arrangement direction of the input terminals Tin and the output terminals Tout in the planar direction of the dielectric layers 11a to 11i is defined as the X direction, and the direction perpendicular to the X direction is defined as the Y direction.

[0027] As shown in FIGS. 2(a) and 2(b), the filter 100 includes a laminate 10. The laminate 10 includes a plurality of laminated dielectric layers 11a-11i. The laminate 10 includes a plurality of laminated dielectric layers 11a-11i. Terminals 14 are provided on a surface (e.g., the bottom surface) of the laminate 10. The terminals 14 include, for example, an input terminal Tin, an output terminal Tout, and a ground terminal Tg. The ground terminal Tg functions as a reference potential surface of the transmission line, as will be described later. For this reason, the area of ​​the ground terminal Tg is, for example, 70 times the area of ​​each of the input terminal Tin and the output terminal Tout. An orientation identification mark is provided on the top surface of the laminate 10 using a conductor layer 12a. The terminal 14 includes a metal layer 14a provided on the bottom surface of the laminate 10 and a metal layer 14b provided on the bottom surface of the metal layer 14a.

[0028] 3 and 4 are exploded perspective views of the dielectric layers in Example 1. FIGS. 5(a) to 7(c) are plan views of the dielectric layers in Example 1. FIGS. 5(a) to 7(b) show the conductor layers and via wiring on the upper surfaces of the dielectric layers 11b to 11i. FIG. 7(c) shows the terminal 14 on the lower surface of the dielectric layer 11i, seen from above through the dielectric layer 11i, and the via wiring 13i penetrating the dielectric layer 11i. In FIGS. 3 to 7(b), the via wirings 13b to 13h penetrating the next-higher dielectric layers 11b to 11h are shown on the upper surfaces of the dielectric layers 11c to 11i.

[0029] As shown in Fig. 3, a conductor layer 12a that forms a direction identification mark is provided on the upper surface of the dielectric layer 11a. As shown in Fig. 3 and Fig. 5(a), a conductor layer 12b that forms a ground pattern Ga is provided on the upper surface of the dielectric layer 11b. As shown in Fig. 3 and Fig. 5(b), a conductor layer 12c that forms an electrode C4a is provided on the upper surface of the dielectric layer 11c. Via wiring 13b that penetrates the dielectric layer 11b forms via wiring groups 16b to 16g.

[0030] As shown in FIGS. 3 and 5(c), a conductor layer 12d forming line patterns R1a, R2a, and R3a is provided on the upper surface of the dielectric layer 11d. One end of the line pattern R1a corresponds to the electrode C1a, and the other end corresponds to the electrode C2a. One end of the line pattern R2a corresponds to the electrode C2a, and the other end corresponds to the electrode C3a. One end of the line pattern R3a corresponds to the electrodes C3a and C4b. Via wiring 13c penetrating the dielectric layer 11c forms via wiring groups 16b to 16g.

[0031] As shown in Figures 3 and 6(a), a conductor layer 12e that forms electrodes C1b and C2b is provided on the upper surface of the dielectric layer 11e. Via wiring 13d that penetrates the dielectric layer 11d forms a via wiring group 16b to 16g. As shown in Figures 4 and 6(b), a conductor layer 12f that forms electrode C3b is provided on the upper surface of the dielectric layer 11f. Some of the via wiring 13e that penetrates the dielectric layer 11e form the via wiring group 16b to 16g. Some of the via wiring 13e is via wiring 15a.

[0032] 4 and 6(c), a conductor layer 12g forming a line pattern R0a is provided on the upper surface of the dielectric layer 11g. Part of the via wirings 13f penetrating the dielectric layer 11f forms a via wiring group 16b to 16g. Part of the via wirings 13f is the via wiring 15a.

[0033] 4 and 7(a), a conductor layer 12h that forms line patterns M1a and M2a is provided on the upper surface of a dielectric layer 11h. Part of via wiring 13g that penetrates through a dielectric layer 11g forms via wiring groups 16b to 16g. Part of the via wiring 13g is via wirings 15b and 15c.

[0034] 4 and 7(b), a conductor layer 12i that forms line patterns M1b, M2b and ground patterns Gb-Gg is provided on the upper surface of the dielectric layer 11i. Some of the via wirings 13h that penetrate the dielectric layer 11h form via wiring groups 16b-16g. Some of the via wirings 13h are via wirings 15b-15g.

[0035] 4 and 7(c), terminals 14 including an input terminal Tin, an output terminal Tout, and a ground terminal Tg are provided on the lower surface of the dielectric layer 11i. Some of the via wirings 13i penetrating the dielectric layer 11i form a via wiring group 16b to 16g. Some of the via wirings 13i are via wirings 15b, 15c, 15f, and 15g.

[0036] The via wiring groups 16b to 16f penetrate the dielectric layers 11b to 11i and electrically connect the ground terminal Tg to the ground pattern Ga. The via wiring groups 16b to 16f are also provided between the conductor layers 12d, as in the dielectric layer 11d in Fig. 5(c), and suppress electromagnetic field coupling between the conductor layers 12d.

[0037] The electrodes C1a and C1b sandwiching the dielectric layer 11d form a capacitor C1. The electrodes C2a and C2b sandwiching the dielectric layer 11d form a capacitor C2. The electrodes C3a and C3b sandwiching the dielectric layers 11d and 11e form a capacitor C3. The electrodes C4a and C4b sandwiching the dielectric layer 11c form a capacitor C4. The space between the line patterns R1a on the dielectric layer 11d forms a capacitor C5.

[0038] The via wiring 15a electrically connects one end of the line pattern R0a to the electrode C1b. The via wiring 15b electrically connects the other end of the line pattern R0a and one end of the line pattern M1b to the input terminal Tin. The via wiring 15c electrically connects the other end of the line pattern R0a and one end of the line pattern M2b to the output terminal Tout. The via wiring 15d electrically connects the other end of the line pattern M1b to one end of the line pattern M1a. The via wiring 15e electrically connects the other end of the line pattern M2b to one end of the line pattern M2a. The via wiring 15f electrically connects the other end of the line pattern M1a to the ground terminal Tg. The via wiring 15g electrically connects the other end of the line pattern M2a to the ground terminal Tg.

[0039] The line patterns R1a to R3a and mainly the ground pattern Ga form the transmission lines R1 to R3, respectively. The line patterns M1a, M1b, and via wirings 15d and 15f mainly form the line M1. The line patterns M2a, M2b, and via wirings 15e and 15g mainly form the line M2.

[0040] The dielectric layers 11a-11i are made of a ceramic material and contain, as a main component, an oxide of, for example, Si, Ca, and Mg (e.g., diopside crystal, CaMgSiO). The main component of the dielectric layers 11a-11i may be an oxide other than Si, Ca, and / or Mg. Furthermore, the dielectric layers 11a-11i may contain, as an insulating material, an oxide of at least one of Ti, Zr, and Al.

[0041] The metal layer 14a of the conductive layers 12a-12i, the via wirings 13b-13i, and the terminals 14 is a metal layer whose main component is, for example, Ag, Pd, Pt, Cu, Ni, Au, an Au-Pd alloy, or an Ag-Pt alloy. In addition to the above metal materials, the metal layer 14a may also contain an electrically non-conductive material such as TiO2, ZrO2, or Al2O3. The metal layer 14b of the terminals 14 is a Ni film and a Sn film.

[0042] The conductive layers 12a-12i and the metal layer 14a are formed on the surfaces of the dielectric layers 11a-11i using a screen printing method or a transfer method. The dielectric layers 11a-11i are stacked and pressure-bonded to form a plate-shaped laminate. The plate-shaped laminate is then cut into individual pieces to form the laminate 10. At this stage, the metal layer 14b is not formed on the laminate 10.

[0043] The metal layer 14b on the laminate 10 is formed, for example, by barrel plating. In barrel plating, the laminate 10 and conductive metal particles (media) are immersed in a plating solution. A current is passed through the plating solution while the plating solution is stirred. This causes the plating metal to deposit on the surface of the metal layer 14a. The current flows when the media contacts the metal layer 14a of the laminate 10, causing the plating metal to deposit. The larger the area of ​​the metal layer 14a, the higher the probability that the metal layer 14a will come into contact with the media. This increases the amount of plating metal that deposits. Thus, the amount of plating metal that deposits depends on the area of ​​the metal layer 14a. The metal layer 14b is, for example, a Ni film and a Sn film from the metal layer 14a side. The Sn film is a solder layer for mounting electronic components on a motherboard or the like, and the Ni film is a barrier layer for suppressing interdiffusion between the solder layer and the metal layer 14a.

[0044] As shown in FIG. 2A, the area of ​​the ground terminal Tg is larger than the area of ​​the input terminal Tin and the area of ​​the output terminal Tout. Therefore, if the path 40 is not connected to the input terminal Tin and the output terminal Tout in a DC manner, the input terminal Tin and the output terminal Tout will be thinner than the ground terminal Tg. This will result in poor coplanarity. Therefore, when the filter 100 is mounted on a mounting substrate, the bonding between the input terminal Tin and the output terminal Tout and the mounting substrate will be weak.

[0045] In the first embodiment, the lines M1 and M2 are provided to connect the ground terminal Tg to the input terminal Tin and the output terminal Tout in a DC manner. This allows the ground terminal Tg, the input terminal Tin, and the output terminal Tout to have approximately the same potential when the metal layer 14b is formed using a plating method. This allows the thickness of the metal layer 14b at the ground terminal Tg, the input terminal Tin, and the output terminal Tout to be approximately the same. Meanwhile, for high-frequency signals, the lines M1 and M2 are left substantially open. This prevents high-frequency signals from leaking from the path 40 to the ground terminal Tg, thereby preventing degradation of the filter characteristics. The lines M1 and M2 are described below.

[0046] [Simulation 1] First, the pass characteristic S21 and reflection characteristic S11 were simulated for filter C, a comparative example that does not have lines M1 and M2. The relative dielectric constants εr of dielectric layers 11a to 11i were set to 5, 10, and 15. Table 1 shows approximate values ​​of the capacitances of capacitors C1 to C5 when the relative dielectric constants were 5, 10, and 15. [Table 1]

[0047] Table 2 shows the widths W and lengths L of the line patterns R1a to R3a that form the transmission lines R1 to R3 having relative dielectric constants of 5, 10, and 15. [Table 2]

[0048] In Simulation 1, a circuit simulation was performed using the values ​​in Tables 1 and 2. Figures 8(a) to 8(c) are diagrams showing the pass characteristics S21 and reflection characteristics S11 of each filter in Simulation 1. Figures 8(a) to 8(c) show the pass characteristics and reflection characteristics when the relative dielectric constant εr is 5, 10, and 15, respectively.

[0049] As shown in Figures 8(a) to 8(c), the capacitances of capacitors C1 to C5 and the widths W and lengths L of line patterns R1a to R3a were set so that the pass band (Pass) was 27 GHz to 30 GHz. Even when the relative dielectric constant εr was changed to 5, 10, and 15, the pass characteristics S21 and reflection characteristics S11 in the pass band (Pass), the attenuation range below the pass band (Pass), and the attenuation range above the pass band (Pass) remained almost unchanged. Note that Simulation 1 was a circuit simulation using the approximate values ​​in Tables 1 and 2, and is less accurate than the three-dimensional electromagnetic field simulation in Simulation 2, which will be described later.

[0050] [Simulation 2] Simulation 1 showed that the pass characteristic S21 and reflection characteristic S11 of the filter remained almost unchanged even when the relative dielectric constant εr of the dielectric layers 11a to 11i was changed to 5, 10, and 15. Therefore, three-dimensional electromagnetic field simulation 2 was performed using the finite element method, which is more accurate than simulation 1, with the relative dielectric constant εr set to 10. Simulation 2 was performed on filters A to C.

[0051] Filter A is a filter that includes spiral inductors as lines M1 and M2. Filter B is a filter that includes transmission lines as lines M1 and M2. Filter C is a filter that does not include lines M1 and M2, has no DC connection between the input terminal Tin and the ground terminal Tg, and has no DC connection between the output terminal Tout and the ground terminal Tg. Filters A and B are filters of Example 1, and Filter C is a filter of a comparative example.

[0052] 9(a) to 9(c) are perspective views showing the line patterns M1a and M2a in filter A. FIG. 9(a) is a perspective view showing the line patterns M1a and M2a on the top surface of the dielectric layer 11h, FIG. 9(b) is an enlarged perspective view of the line pattern M1a, and FIG. 9(c) is an enlarged perspective view of the line pattern M2a. As shown in FIGS. 9(a) to 9(c), the planar shapes of the line patterns M1a and M2a are spiral (whirl-shaped). In a spiral shape, the current flows in the same direction in adjacent lines. This increases the inductance. Let L be the length of the shortest distance between the line patterns M1a and M2a, W be the width, and t be the thickness.

[0053] Fig. 10 is a perspective view showing the line patterns M1a and M2a in filter B. As shown in Fig. 10, the planar shapes of the line patterns M1a and M2a are linear. The line patterns M1a and M2a and the ground terminal Tg form a microstrip line. The length of the shortest distance between the line patterns M1a and M2a is L, the width is W, and the thickness is t.

[0054] The approximate capacitance values ​​of capacitors C1 to C5 were set to the values ​​in Table 1 when the relative dielectric constant εr was 10. The width W and length L of line patterns R1a to R3a were set to the values ​​in Table 2 when the relative dielectric constant εr was 10.

[0055] The line patterns R1a to R3a have a thickness of 8 μm, and the total thickness of the dielectric layers 11b and 11c between the line patterns R1a to R3a and the ground pattern Ga is 300 μm.

[0056] In filter A, the width W of the line patterns M1a and M2a is 25 μm, the length L is 1200 μm, the thickness t is 8 μm, and the total thickness of the dielectric layers 11h and 11i between the line patterns M1a and M2a and the ground terminal Tg is 35 μm.

[0057] In filter B, the width W of the line patterns M1a and M2a is 25 μm, the length L is 1071 μm, the thickness t is 8 μm, and the total thickness of the dielectric layers 11h and 11i between the line patterns M1a and M2a and the ground terminal Tg is 35 μm.

[0058] Fig. 11 is a diagram showing the pass characteristics S21 of filters A to C in simulation 2. Fig. 12(a) and Fig. 12(b) are diagrams showing the pass characteristics S21 and reflection characteristics S11 near the pass bands of filters A to C, respectively, in simulation 2.

[0059] As shown in Figures 11 to 12(b), if the passband (Pass) in filters A to C is in the range where S21 is -3 dB or more (i.e., the insertion loss is 3 dB or less), the passband (Pass) is 26.4 GHz to 30.6 GHz, and the center frequency f0 of the passband (Pass) is 25.5 GHz. The pass characteristic S21 and reflection characteristic S11 in the passband (Pass) are almost unchanged. In the range of 27.45 GHz to 29.55 GHz where S21 is almost flat, the largest insertion loss is as follows: Filter A: 1.523dB Filter B: 1.600dB Filter C: 1.517dB The maximum insertion loss of both filters A and B is almost the same as that of the comparative example filter C. More specifically, the insertion loss of filter A is similar to that of filter C, but the insertion loss of filter B is 0.08 dB greater than that of filter C.

[0060] As shown in FIG. 11, filter C has the best attenuation characteristics below 20 GHz and between 35 GHz and 50 GHz, followed by filter A, and filter B has the worst.

[0061] We will now explain the optimization of the width and length of the line patterns M1a and M2a in filter B. Figure 13(a) is a perspective view of a microstrip line, and Figure 13(b) is a Smith chart of the impedance viewed from one end of the microstrip line to the other. Figure 13(b) corresponds to S11 viewed from one end of the microstrip line to the other.

[0062] 13(a), in a microstrip line 41, a ground pattern 43 is provided over the entire lower surface of a dielectric layer 42, and a line pattern 44 is provided on the upper surface of the dielectric layer 42. The thickness of the dielectric layer 42 is H, and the width, length, and thickness of the line pattern 44 are W, L, and t, respectively. If the length L of the microstrip line 41 is set to 1 / 4 of the wavelength λ at the center frequency f0 of the pass band Pass, the impedance of the microstrip line 41 becomes infinite and is open.

[0063] As shown in Figure 13(b), the impedance of a microstrip line 41 with a length L of λ / 4 is the open position 45 on the Smith chart. The Smith chart is expressed in polar coordinates, with the radius of the center 46 (the point where the standard impedance is achieved) set to 0 and the radius of the outer periphery set to 1. The angle is measured counterclockwise from the open position 45. The polar coordinates of the center 46 are (0, 0°), and the polar coordinates of the open position 45 are (1, 0°). The polar coordinates of an arbitrary point Q are (r, θ).

[0064] The insertion loss of the filter was simulated using microstrip line 41 as lines M1 and M2. In the simulated microstrip line 41, the width W of the line pattern 44 was 88 μm, the thickness t was 8 μm, the thickness H of the dielectric layer 42 was 100 μm, and the relative dielectric constant was 10.

[0065] FIG. 14 is a diagram showing the insertion loss of the filter versus the phase of the microstrip line 41. The horizontal axis of FIG. 14 represents the length L of the microstrip line 41 in terms of the phase of the center frequency f0. A phase of 0° indicates that the length L is 1 / 4 of the wavelength λ at the center frequency f0. A phase of -45° indicates that the length L is λ / 4 - λ / 16. A phase of +45° indicates that the length L is λ / 4 + λ / 16. The vertical axis of FIG. 14 represents the insertion loss [%]. The insertion loss [%] represents the largest insertion loss in the range of 27.45 GHz to 29.55 GHz in terms of power rather than dB, and represents the insertion loss when the length L is at each phase as a percentage, assuming that the insertion loss when the length L is λ / 4 (phase is 0°) is 100%. For example, when the insertion loss when the length L is λ / 4 is -1.6 dB, the insertion loss expressed in power is 100%. (-1.6 / 10) = 0.692. When the insertion loss [%] is 90%, the insertion loss expressed in power is 0.692 x 0.9 = 0.623. The insertion loss expressed in dB is 10 x log(0.623) = -2.06 dB. The black circles indicate the simulated points, and the curve is the line connecting the black circles.

[0066] As shown in Figure 14, the insertion loss [%] deteriorates when the phase deviates from 0°. This is because when the length L deviates from λ / 4, the impedance position on the Smith chart in Figure 13(b) deviates in angle from (1, 0°), which is the open position 45. This is thought to be because high-frequency signals leak from path 40 to the ground terminal Tg. As shown in Figure 14, if the insertion loss [%] is to be approximately 85% or more, the phase falls within the range 47 of 0° ±22.5°. A phase of 22.5° in microstrip line 41 corresponds to an angle of 45° on the Smith chart in Figure 13(b).

[0067] The line patterns M1a and M2a in filter B correspond to microstrip lines 41, and the width W of the line patterns M1a and M2a was varied to simulate the insertion loss of filter B. FIG. 15 is a diagram showing the insertion loss of filter B relative to the line patterns M1a and M2a. The horizontal axis of FIG. 15 represents the width W of the line patterns M1a and M2a. The vertical axis represents the insertion loss in %, assuming that the insertion loss of filter C in power notation is 100%. The length L of the line patterns M1a and M2a was set to 1150 μm. Length L = 1150 μm is the length L at which filter B's insertion loss is smallest when the length L is varied. Black circles represent the simulation points for filter B. White circles represent the insertion loss of filter A, which will be described later.

[0068] As shown in FIG. 15, as the width W of the line patterns M1a and M2a decreases, the insertion loss [%] decreases (i.e., the insertion loss deteriorates). This is thought to be because as the width W decreases, the characteristic impedance of the microstrip line 41 increases. When the lines M1 and M2 deviate from the ideal λ / 4 line, if the characteristic impedance is large, high-frequency signals are less likely to leak from the path 40 to the ground terminal Tg via the lines M1 and M2. For this reason, it is thought that a smaller width W can suppress the insertion loss. Reducing the width W of the line patterns M1a and M2a increases manufacturing variability. From this perspective, in filter B of FIGS. 10 to 12(b), the width W of the line patterns M1a and M2a is set to 25 μm.

[0069] In filter A, the insertion loss is nearly 100%. The reason for this is that by making the line patterns M1a and M2a spiral, the self-inductance of the line patterns M1a and M1b increases. This increases the impedance of the lines M1 and M2. This is thought to make it less likely that high-frequency signals will leak from path 40 to the ground terminal Tg via the lines M1 and M2. In this way, filter A has a smaller insertion loss than filter B.

[0070] Next, in filter A, the area of ​​the spiral regions of the line patterns M1a and M2a that overlap with the ground terminal Tg was changed in a plan view, and the insertion loss of filter A was simulated. FIGS. 16(a) and 16(b) are plan views of the line pattern M1a and terminals. As shown in FIGS. 16(a) and 16(b), the ground terminal Tg and the input terminal Tin are provided. The line pattern M1a partially overlaps with the ground terminal Tg. The spiral region of the line pattern M1a is defined as a spiral region 48. The spiral region 48 is the region in which the line pattern M1a spirals. In FIG. 16(a), a portion of the line pattern M1a in the spiral region 48 overlaps with the ground terminal Tg. The ratio of the area of ​​the line pattern M1a in the spiral region 48 that overlaps with the ground terminal Tg to the area of ​​the line pattern M1a in the spiral region 48 is defined as the area ratio [%]. In FIG. 16(b), the line pattern M1a in the spiral region 48 does not overlap the ground terminal Tg, and the area ratio is 0%.

[0071] Figure 17 is a graph showing insertion loss [%] versus area ratio. The horizontal axis of Figure 17 represents the area ratio of the line patterns M1a and M2a in the spiral region 48 that overlap with the ground terminal Tg relative to the area of ​​the line patterns M1a and M2a in the spiral region 48. The vertical axis represents the insertion loss in %, assuming that the insertion loss of filter A when the area ratio is 0% is 100%. The length L of the line patterns M1a and M2a was set to 1200 μm. The black circles represent simulation points.

[0072] As shown in Figure 17, when the area ratio is 20% or less, the insertion loss is nearly 100%. When the area ratio exceeds 30%, the insertion loss rapidly deteriorates. This is because, in the spiral shape, when the line patterns M1a and M2a overlap with the ground terminal Tg, the capacitance component between the line patterns M1a and M2a and the ground terminal Tg increases. This is thought to be because high-frequency signals leak from the path 40 to the ground terminal Tg.

[0073] According to the first embodiment, the node N1 is provided in the path 40 so as to conduct a direct current between the node N1 and the input terminal Tin (second terminal). One end of the line M1 is connected to the node N1, and the other end is connected to the ground terminal Tg (first terminal). The line M1 has an impedance when viewed from the node N1 to the ground terminal Tg at the center frequency f0 of the pass band Pass. This connects the input terminal Tin and the ground terminal Tg so as to conduct a direct current. Therefore, when the metal layer 14b is formed using electroplating, it is possible to prevent the thickness of the metal layer 14b from being different between the input terminal Tin and the ground terminal Tg, which would cause deterioration of coplanarity. Furthermore, because the line M1 is substantially open at the center frequency f0, it is possible to suppress high-frequency signals from leaking from the path 40 to the ground terminal Tg, thereby suppressing insertion loss in the pass band. The first terminal does not have to be the ground terminal Tg, and may be any terminal that does not input or output high-frequency signals. Even in this case, it is possible to prevent high frequency signals from leaking from the path 40 to the first terminal.

[0074] One end of the line M2 (another line) is connected to a node N2 (another node) provided in the path 40 so as to conduct a direct current between the line M2 and the output terminal Tout (third terminal), and the other end is connected to the ground terminal Tg. The line M2 has a substantially open impedance when viewed from the node N2 toward the ground terminal Tg at the center frequency f0. This prevents the thickness of the metal layer 14b from differing between the output terminal Tout and the ground terminal Tg, thereby preventing deterioration of coplanarity. It also reduces insertion loss in the passband. It is sufficient that at least one of the lines M1 and M2 is provided. That is, it is sufficient that either the input terminal Tin or the output terminal Tout is the second terminal, and the other is the third terminal.

[0075] In the above description, in order to prevent the thickness of the metal layer 14b from varying depending on the area of ​​the terminal 14, the nodes N1 and N2 are connected to the ground terminal Tg so that a direct current flows therebetween. However, even when a direct current flows between the nodes N1 and N2 and the ground terminal Tg for other reasons, the leakage of high-frequency signals between the terminals can be suppressed by providing the lines M1 and M2 that are substantially open.

[0076] The impedance of the lines M1 and M2 is considered to be substantially open if it is open enough so that a signal at the center frequency f0 does not leak to the ground terminal Tg via the lines M1 and M2 and the insertion loss does not increase. The impedance condition is as shown in FIG. 13(b). When the Smith chart is expressed in polar coordinates, with the angle at the open position being 0° and the radius of the periphery being 1, the impedance seen from the node N1 (and N2) toward the ground terminal Tg is within the range 49 of +45° or less and -45° or more, and the radius is within the range 49 of 0.8 or more and 1.0 or less. To achieve substantially open impedance for the lines M1 and M2, the angle is preferably +22.5° or less and -22.5° or more. The radius is preferably 0.9 or more, more preferably 0.95 or more, and even more preferably 0.98 or more.

[0077] The input terminal Tin (and the output terminal Tout) and the ground terminal Tg are not connected via a path through which a direct current flows other than the line M1 (and M2). In this case, when electrolytic plating is used, the input terminal Tin (and the output terminal Tout) and the ground terminal Tg are not electrically connected, and therefore the thickness of the metal layer 14b differs. Therefore, it is preferable to provide the lines M1 and M2.

[0078] When the area of ​​the input terminal Tin (and the output terminal Tout) is less than half or more than twice the area of ​​the ground terminal Tg, the difference in thickness of the metal layer 14b becomes large. Therefore, it is preferable to provide the line M1 (and M2). When the area of ​​the input terminal Tin (and the output terminal Tout) is less than one-fifth or more than five times the area of ​​the ground terminal Tg, the difference in thickness of the metal layer 14b becomes even larger. When the area of ​​the input terminal Tin (and the output terminal Tout) is less than one-tenth or more than ten times the area of ​​the ground terminal Tg, the difference in thickness of the metal layer 14b becomes even larger. Therefore, it is preferable to provide the line M1 (and M2).

[0079] If the electrical length of the lines M1 and M2 is 1 / 4 of the wavelength λ of the center frequency f0, the lines M1 and M2 are approximately open. In a vacuum, the wavelength λ = c / f0, where c is the speed of light. If εr is the relative permittivity of the dielectric layer, the wavelength λ in the dielectric layer is λ = c / (f0 × √εr). When the lines M1 and M2 are microstrip lines 41, the effective relative permittivity is smaller than the relative permittivity εr of the dielectric layer, and is λ = c / (f0 × √εr). Furthermore, the laminate 10 is not an ideal microstrip line 41; instead, a ground pattern Ga exists above, and a ground terminal Tg and via wiring groups 16b to 16g connected to the ground pattern Ga exist to the side. Furthermore, when viewed from the stacking direction, there are regions where the line patterns M1a and M2b do not overlap with the ground terminal Tg.

[0080] Furthermore, the line M1 is formed from a line pattern M1a formed from the conductor layer 12h and a line pattern M1b formed from the conductor layer 12i. The line M2 is formed from a line pattern M2a formed from the conductor layer 12h and a line pattern M2b formed from the conductor layer 12i. Based on this, we will consider the preferable lengths of the line patterns M1a and M2a in order to make the lines M1 and M2 substantially open.

[0081] First, if the length of the line pattern M1a is 2 / 3 or more (preferably 3 / 4 or more) of the combined length of the line patterns M1a and M1b, most of the lines M1 and M2 are considered to be line patterns M1a and M2a. Furthermore, according to Equation 1, if the width W of the line pattern M1a is the smallest among the widths of the line patterns M1a and M1b that form the line M1, and the line pattern M1a is the farthest from the ground terminal Tg among the line patterns M1a and M1b (i.e., the thickness H of the dielectric layer 42 is the largest), the effective relative dielectric constant of the line pattern M1a will be greater than the effective relative dielectric constant of the line pattern M1b. If the physical lengths of the line patterns M1a and M1b are the same, the electrical length of the line pattern M1a will be greater. Therefore, the electrical length of the line pattern M1a will be closer to the electrical length of the line M1. The same is true for the line pattern M2a.

[0082] For the line pattern M1a, a microstrip line is assumed between the ground pattern Ga and the ground terminal Tg that is closest to the line pattern M1a among the ground terminals Ga and Tg. In this case, the effective relative dielectric constant εreff is expressed by Equation 1.

number

[0083] For filter A, if W = 25 μm, t = 8 μm, H = 35 μm, and εr = 10, the effective relative dielectric constant εreff is approximately 6.0375. When the center frequency f0 is 28.5 GHz, λ / 4 = 1 / 4 × c / (f0 × √εreff) = 1071 μm. In filter A, the length L of the line patterns M1a and M2a that provides the smallest insertion loss is 1200 μm, and in filter B, the length L of the line patterns M1a and M2a that provides the smallest insertion loss is 1150 μm. Thus, compared to λ / 4 calculated by assuming that the line patterns M1a and M2a are ideal microstrip lines 41, the length L of the line patterns M1a and M2a of filter A is 1200 / 1071 = 1.120 times, and the length L of the line patterns M1a and M2a of filter B is 1150 / 1071 = 1.074 times.

[0084] The difference between the length of the line patterns M1a and M2a and the length calculated assuming an ideal microstrip line 41 is thought to be due to the influence of the above-mentioned ground pattern Ga, via wiring groups 16b to 16g, and line patterns M1b and M2b, but it is thought that a similar influence occurs in a typical filter laminate 10. Therefore, the length L of the line patterns M1a and M2a is set to 1.1 times the length calculated assuming an ideal microstrip line 41, and the range in which the length L of the line patterns M1a and M2a is λ / 4±λ / 16 is set to the range in which the lines M1 and M2 are approximately open.

[0085] In this way, assuming that the microstrip line 41 is formed by the line pattern M1a and the ground terminal Tg (the nearest ground pattern), the effective relative dielectric constant is εreff1 and the center frequency of the passband Pass is f0 [Hz]. Then, the length L [m] of the line pattern M1a is 1.1×3 / 16×c / (f0×√εreff1)=6.18×10 7 / (f0×√εreff1) or more and 1.1×5 / 16×c / (f0×√εreff1)=1.031×10 8The length L [m] of the line pattern M1a is 1.1 × 7 / 32 × c / (f0 × √εreff1) = 7.22 × 10 7 / (f0×√εreff1) or more and 1.1×9 / 32×c / (f0×√εreff1)=9.28×10 7 / (f0×√εreff1) or less is more preferable.

[0086] Similarly, assuming that the microstrip line 41 is formed by the line pattern M2a and the ground terminal Tg, the effective relative dielectric constant is εreff2 and the center frequency of the passband Pass is f0 [Hz]. Then, the length L [m] of the line pattern M2a is 6.18×10 7 / (f0×√εreff2) or greater and 1.031×10 8 The length L [m] of the line pattern M2a is preferably 7.22 × 10 7 / (f0×√εreff2) or greater and 9.28×10 7 / (f0×√εreff2) or less is more preferable.

[0087] 9(a) to 9(c), at least a part of the planar shape of the line patterns M1a and M2a is spiral, which makes it possible to further suppress the insertion loss, as in filter A.

[0088] 17, when viewed from the stacking direction, the area of ​​the spiral region 48 of the line pattern M1a that overlaps with the ground terminal Tg is preferably 0.3 times or less, and more preferably 0.2 times or less, the area of ​​the spiral region 48 of the line pattern M1a. The area of ​​the spiral region 48 of the line pattern M2a that overlaps with the ground terminal Tg is preferably 0.3 times or less, and more preferably 0.2 times or less, the area of ​​the spiral region 48 of the line pattern M2a. This allows the insertion loss of the filter A to be further suppressed.

[0089] As shown in FIG. 15, reducing the width W of the line patterns M1a and M2a can suppress the insertion loss of filter B. The width W of the line patterns M1a and M2a is set to be the smallest among the widths of the line patterns R0a-R3a, M1a, M1b, M2a, and M2b, which are formed by multiple conductor layers 12a-12i and transmit high-frequency signals. This further suppresses the insertion loss of filters A and B. The width W of the line patterns M1a and M2a is preferably ½ or less, and more preferably ⅕ or less, of the smallest width of the line patterns R0a-R3a (the width of D0a is 150 μm). The width W of the line patterns M1a and M2a is preferably 50 μm or less, and more preferably 25 μm or less. From the viewpoint of suppressing manufacturing variations in the width W, the width W is preferably 5 μm or more.

[0090] Although a band-pass filter has been described as an example of the filter, a low-pass filter or a high-pass filter may be used as long as the center frequency f0 of the passband Pass can be defined. [Example]

[0091] FIG. 18 is a circuit diagram of a diplexer according to a second embodiment. As shown in FIG. 18, a diplexer 20 includes filters 22 and 24. The filters 22 and 24 are connected between a common terminal Ant and terminals T1 and T2, respectively. An antenna 28 is connected to the common terminal Ant. The filter 22 is, for example, a band-pass filter BPF, which passes high-frequency signals in a high band and suppresses signals of other frequencies. The filter 24 is, for example, a low-pass filter LPF, which passes high-frequency signals in a low band, which has a frequency lower than the high band, and suppresses signals of other frequencies.

[0092] The filter 22 can be the filter of Example 1. Although a diplexer has been described as an example of a multiplexer, the multiplexer may be a triplexer or a quadplexer.

[0093] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0094] 10 Laminate 11a to 11i Dielectric layers 12a~12i Conductor layer 13b~13i, 15a~15g Via wiring 14 terminals 14a, 14b metal layer 20 Diplexer 22, 24 Filter 40 routes 41 Microstrip Line 42 Dielectric Layer 44 Track Pattern 45 Open position 46 center 48 Spiral Region

Claims

1. a laminate in which a plurality of dielectric layers are stacked; an input terminal provided on a surface of the laminate; an output terminal provided on a surface of the laminate; a path provided within the laminate for transmitting a high-frequency signal from the input terminal to the output terminal; a first terminal provided on a surface of the laminate, to which a high-frequency signal is not input or output; a second terminal of either the input terminal or the output terminal; a line provided within the laminate, one end of which is connected to a node provided within the path so that a direct current flows between the line and the second terminal, and the other end of which is connected to the first terminal, and the impedance of the line viewed from the node to the first terminal at a center frequency of a pass band is substantially open; A filter comprising:

2. a third terminal that is the other of the input terminal and the output terminal other than the second terminal; another line that is provided within the laminate, the other end of which is connected to another node provided within the path so as to conduct a direct current between the other node and the third terminal, and the other end of which is connected to the first terminal, and the impedance of which, when viewed from the other node to the first terminal at the center frequency, is substantially open; The filter of claim 1 , comprising:

3. 3. The filter according to claim 1, wherein, when a Smith chart is expressed in polar coordinates with an angle of 0° at an open position and a radius of 1, the impedance seen from the node to the first terminal via the line at the center frequency has an angle of +45° or less and -45° or more, and a radius of 0.8 or more and 1.0 or less.

4. The line is formed from one conductor layer provided between adjacent dielectric layers among the plurality of dielectric layers, and when assuming a microstrip line formed with the nearest ground pattern, the effective relative dielectric constant is εref and the center frequency is f0, the length is 6.18×10 ７ ×√(εreff) / f0 or more and 1.031×10 ７ 4. The filter according to claim 1, further comprising a line pattern having a value of .times. ...

5. 4. The filter according to claim 1, wherein the line is formed from one conductor layer provided between adjacent dielectric layers among the plurality of dielectric layers, and the line pattern has a shape that includes a spiral portion when viewed from a stacking direction of the plurality of dielectric layers.

6. 6. The filter according to claim 5, wherein an area of ​​a region of the spiral region of the line pattern that overlaps with the nearest ground pattern when viewed from a stacking direction of the plurality of dielectric layers is 0.3 times or less the area of ​​the spiral region of the line pattern.

7. 4. The filter according to claim 1, wherein the line is formed from one conductor layer provided between adjacent dielectric layers among the plurality of dielectric layers, and comprises a line pattern having a width that is the smallest among the widths of line patterns through which high-frequency signals are transmitted within the laminate.

8. a laminate in which a plurality of dielectric layers are stacked; an input terminal provided on a surface of the laminate; an output terminal provided on a surface of the laminate; a path provided within the laminate for transmitting a high-frequency signal from the input terminal to the output terminal; a first terminal provided on a surface of the laminate, to which a high-frequency signal is not input or output; a second terminal of either the input terminal or the output terminal; a line that is provided within the laminate, one end of which is connected to a node provided within the path so that a direct current flows between the line and the second terminal, and the other end of which is connected to the first terminal, and when a Smith chart is expressed in polar coordinates with an angle of 0° at an open position and a radius of 1, the impedance of the line as viewed from the node to the first terminal at a center frequency of a pass band is such that an angle is +45° or less and −45° or more, and a radius is 0.8 or more and 1.0 or less; A filter comprising:

9. a third terminal that is the other of the input terminal and the output terminal other than the second terminal; another line that is provided within the laminate, one end of which is connected to another node provided within the path so that a direct current flows between the another line and the third terminal, and the other end of which is connected to the first terminal, and the impedance of the first terminal viewed from the another node at the center frequency is such that, when a Smith chart is expressed in polar coordinates, an angle is equal to or smaller than +45° and equal to or larger than -45°, and a radius is equal to or larger than 0.8 and equal to or smaller than 1.0; The filter of claim 8 comprising:

10. The filter according to claim 1 , wherein the first terminal and the second terminal are not connected via a path other than the line through which a direct current flows.

11. 11. The filter according to claim 1, wherein the area of ​​the second terminal is equal to or less than half or equal to or more than twice the area of ​​the first terminal.

12. 12. The filter according to claim 1, wherein the first terminal is a ground terminal.

13. A multiplexer including a filter according to any one of claims 1 to 12.

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