Solid-state imaging device, imaging device, and distance measuring imaging device

Abstract

A solid-state imaging device that comprises: a pixel circuit (3a) that outputs pixel signals; and a negative feedback circuit (4a). The negative feedback circuit (4a) comprises: a sample-and-hold circuit ("SH circuit") (10a) that samples and holds the pixel signals; and a feedback amp (FA) that negatively feeds back, to the SH circuit (10a), a feedback signal corresponding to the difference between a pixel signal from the pixel circuit (3a) and an output signal from the SH circuit (10a).

Description

[Technical Field]

[0001] The present invention relates to a solid-state imaging device, an imaging device, and a distance measuring imaging device. [Background technology]

[0002] Patent Document 1 discloses a sample-and-hold circuit connected to a pixel circuit.

[0003] Patent Document 2 discloses a method for reducing kTC noise (reset noise) generated in a pixel circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] U.S. Patent No. 10,834,351 [Patent Document 2] Patent No. 6785433 Summary of the Invention [Problem to be solved by the invention]

[0005] However, according to the conventional technology of Patent Document 1, no measures are taken to reduce the kTC noise that occurs when sampling pixel signals, so there is a problem that the noise is large and it is difficult to improve the SN ratio in low illumination.

[0006] Furthermore, according to prior art Patent Document 2, a negative feedback circuit is provided as a method for reducing kTC noise that occurs when a pixel is reset. The negative feedback circuit negatively feeds back the reset component of the pixel signal, but has the problem of being unable to negatively feed back the signal component of the pixel signal.

[0007] Therefore, the present disclosure provides a solid-state imaging device, an imaging device, and a ranging imaging device that improve the SN ratio in low illumination and expand the dynamic range by reducing the kTC noise that occurs during sampling when pixel signals (both reset components and signal components) are read into a sample-and-hold circuit. [Means for solving the problem]

[0008] In order to solve the above problem, the solid-state imaging device of the present disclosure includes a pixel circuit that outputs a pixel signal, and a negative feedback circuit, and the negative feedback circuit includes a sample-and-hold circuit that samples and holds the pixel signal, and a feedback amplifier that negatively feeds back to the SH circuit a feedback signal that corresponds to the difference between the pixel signal from the pixel circuit and the output signal from the SH circuit.

[0009] Also, an imaging device according to one aspect of the present disclosure includes the solid-state imaging device that images a subject, an imaging optical system that guides incident light from the subject to the solid-state imaging device, and a signal processing unit that processes an output signal from the solid-state imaging device.

[0010] In addition, a distance measuring imaging device in one aspect of the present disclosure includes a solid-state imaging device that captures reflected light from an object irradiated with pulsed light, an imaging optical system that guides the reflected light from the object to the solid-state imaging device, and a signal processing unit that processes an output signal from the solid-state imaging device. [Effects of the Invention]

[0011] The solid-state imaging device, imaging device, and distance measuring imaging device of the present disclosure can improve the SN in low illumination and expand the dynamic range. [Brief explanation of the drawings]

[0012] [Figure 1A] FIG. 1A is a diagram showing an example of a circuit of a main part including a pixel circuit and a negative feedback circuit according to Embodiment 1A. [Figure 1B]FIG. 1B is a diagram showing another example of a circuit of a main part including a pixel circuit and a negative feedback circuit according to Embodiment 1A. [Figure 2] FIG. 2 is a diagram showing an example of a circuit of a main part including a pixel circuit and a negative feedback circuit according to embodiment 1B. [Figure 3] FIG. 3 is a block diagram showing an example of the configuration of a solid-state imaging device. [Figure 4] FIG. 4 is a diagram showing an example of a connection between pixel circuits and negative feedback circuits according to the embodiments 1A, 1B, 2A, 2B, and 4. In FIG. [Figure 5] FIG. 5 is a diagram showing a readout period from the pixel circuit to the sample and hold circuit and a readout timing from the sample and hold circuit according to Embodiment 1A. [Figure 6] FIG. 6 is a diagram showing a readout period from the pixel circuit to the sample-and-hold circuit and a readout timing from the sample-and-hold circuit according to embodiment 1B. [Figure 7] FIG. 7 is a diagram showing waveforms of the slope signals of the sample and hold switch control signal (φSH) and the read selection switch element control signal (φSE). [Figure 8] FIG. 8 is a diagram showing the relationship between the slope period and the kTC noise level. [Figure 9] FIG. 9 is a diagram showing the variation (standard deviation) of kTC noise in a predetermined region. [Figure 10] FIG. 10 is a flowchart illustrating an example of a process for generating a slope signal. [Figure 11] FIG. 11 is a diagram showing an example in which the solid-state imaging device according to any of the embodiments 1A, 1B, 2A, 2B, and 4 is configured as a stacked back-illuminated image sensor. [Figure 12] FIG. 12 is a diagram showing an example in which the solid-state imaging device according to any of the embodiments 1A, 1B, 2A, 2B, and 4 is configured as a stacked back-illuminated image sensor. [Figure 13] FIG. 13 is a diagram showing an example in which the solid-state imaging device according to any of the embodiments 1A, 1B, 2A, 2B, and 4 is configured as a stacked back-illuminated image sensor. [Figure 14]FIG. 14 is a diagram showing an example of a circuit of a main part including a pixel circuit and a negative feedback circuit according to embodiment 2A. [Figure 15] FIG. 15 is a diagram showing an example of a circuit of a main part including a pixel circuit and a negative feedback circuit according to embodiment 2B. [Figure 16] FIG. 16 is a diagram showing an outline of how WDR is implemented within a pixel. [Figure 17] FIG. 17 is a diagram showing a readout period from the pixel circuit to the sample and hold circuit and a readout timing from the sample and hold circuit according to Embodiment 2A. [Figure 18] FIG. 18 is a diagram showing a readout period from a pixel circuit to a sample-and-hold circuit and a readout timing from the sample-and-hold circuit according to embodiment 2B. [Figure 19] FIG. 19 is a diagram illustrating an example of the configuration of a signal processing unit that performs WDR synthesis using three frames. [Figure 20] FIG. 20 is a diagram showing an example of a circuit of a main part including a pixel circuit and a negative feedback circuit according to the third embodiment. [Figure 21] FIG. 21 is a diagram showing an example of a connection between a pixel circuit and a negative feedback circuit according to the third embodiment. [Figure 22] FIG. 22 is a schematic layout of a pixel circuit, a feedback amplifier FA, and a sample-and-hold circuit according to the third embodiment. [Figure 23] FIG. 23 is a diagram showing an example in which the solid-state imaging device according to the third embodiment is configured as a stacked back-illuminated image sensor. [Figure 24] FIG. 24 is a diagram showing an example of a circuit of a main part including a pixel circuit and a negative feedback circuit according to the fourth embodiment. [Figure 25] FIG. 25 is a diagram showing timings relating to the accumulation of charges in the photodiode and the storage capacitor element in the global shutter system according to the fourth embodiment. [Figure 26] FIG. 26 is a diagram showing timings relating to the accumulation of charges in the photodiode and the storage capacitor element in the rolling shutter system according to the fourth embodiment. [Figure 27]FIG. 27 is a diagram showing a readout period from the pixel circuit to the sample and hold circuit and a readout timing from the sample and hold circuit according to the fourth embodiment. [Figure 28] FIG. 28 is a diagram illustrating an example of a camera system equipped with the imaging device according to the fifth embodiment. [Figure 29] FIG. 29 is a diagram illustrating an example of a distance measuring system equipped with a distance measuring imaging device according to the fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0013] (Findings that formed the basis of this disclosure) The present inventors have found that the solid-state imaging device described in the Background Art section has the following problems.

[0014] In the solid-state imaging device disclosed in Patent Document 1, the signal charge generated in the photodiode PD is transferred to and accumulated in the charge storage section (FD), output from the amplification transistor, and the voltage-converted pixel signal is sampled and held in the sample-and-hold capacitance element C. Here, since no measures are taken to reduce kTC noise, the level is high, which poses the problem of degrading low-illumination noise.

[0015] To reduce kTC noise, the sample and hold capacitance element C must have high density and low leakage characteristics.

[0016] The reason why high density characteristics are required is that kTC noise is expressed in voltage as √(kT / C)(V), and the noise level decreases as the capacitance value C increases. In particular, high density is essential to fit into a layout area that corresponds to the cell size as pixels become increasingly miniaturized.

[0017] Low leakage characteristics are also required because, with the global shutter method of simultaneously exposing all pixels, there is a long accumulation period (signal retention period) from when the pixel circuit 3 is read out to the sample and hold capacitance element C until the signal is actually read out. In particular, because the vertical scanning circuit scans and reads out each row in a rolling manner, it is necessary that the first readout row and the last readout row are not affected by the leakage characteristics of the sample and hold capacitance element C.

[0018] The reality is that using process technology to create a sample-and-hold capacitor element C that combines these two characteristics is technically difficult and presents cost challenges. In particular, this difficulty is set to increase as pixel miniaturization continues.

[0019] Therefore, the present disclosure provides a solid-state imaging device and an imaging apparatus that improves the SN in low illumination and expands the dynamic range.

[0020] (Outline of a solid-state imaging device according to one embodiment of the present disclosure) 1A, a solid-state imaging device according to one embodiment of the present disclosure includes a pixel circuit 3a that outputs a pixel signal, and a negative feedback circuit 4a, and the negative feedback circuit 4a includes a sample-and-hold circuit 10a that samples and holds the pixel signal, and a feedback amplifier that negatively feeds back to the SH circuit 10a a feedback signal corresponding to the difference between the pixel signal from the pixel circuit 3a and the output signal from the sample-and-hold circuit 10a. Hereinafter, the sample-and-hold circuit may be abbreviated as the SH circuit.

[0021] The pixel circuit 3a in FIG. 1A is an example of a pixel circuit, and may be the pixel circuit 3b in FIG. 14 or the pixel circuit 3c in FIG.

[0022] The pixel circuit 3a in FIG. 1A is configured to hold signal charges from the photodiode PD in a charge storage section (FD0).

[0023] In the pixel circuit 3b of FIG. 14 and the pixel circuit 3c of FIG. 15, a storage circuit having switch elements (OF, GC1, GC2) as overflow gates and storage capacitance elements (C1, C2) is provided to hold the signal charge that overflows from the photodiode PD.

[0024] Here, pixel circuit 3b in Fig. 14 has a configuration in which the above-mentioned storage circuit is provided in the horizontal direction relative to photodiode PD, while pixel circuit 3c in Fig. 15 has a configuration in which a group of storage circuits for overflow signal charge, each of which is configured as multiple stages (the number of stages is m, where m ≥ 1) of the above-mentioned storage circuits, are arranged in series in the vertical direction.

[0025] Furthermore, during the exposure period, pixel circuit 3c receives the charge that overflows from the photodiode PD in the storage capacitor element of the storage circuit when m=1. When m≧2, the pixel circuit 3c is configured so that the charge that overflows from this storage capacitor element is further received in the storage capacitor element in the subsequent storage circuit.

[0026] 1A is an example of a negative feedback circuit, and may be the negative feedback circuit 4b in FIG. 2 or the negative feedback circuit 4c in FIGS.

[0027] Next, three configuration examples (first, second, and third configuration examples) of a solid-state imaging device according to one embodiment of the present disclosure will be described. The first configuration example includes the pixel circuit 3a and negative feedback circuit 4a of FIG. 1A. The second configuration example includes the pixel circuit 3b and negative feedback circuit 4c of FIG. 14. The third configuration example includes the pixel circuit 3c and negative feedback circuit 4c of FIG. 15.

[0028] [First Configuration Example of Solid-State Imaging Device] First, the first configuration example will be described.

[0029] The solid-state imaging device 100 of FIG. 3 includes a plurality of pixel circuits 3 arranged in a matrix, and a plurality of negative feedback circuits 4 also arranged in a matrix. The pixel circuit 3 is any one of pixel circuits 3a, 3b, and 3c. When there is no need to distinguish between the pixel circuits 3a, 3b, and 3c, they will be referred to as pixel circuit 3. The negative feedback circuit 4 is any one of negative feedback circuits 4a, 4b, and 4c. When there is no need to distinguish between the negative feedback circuits 4a, 4b, and 4c, they will be referred to as negative feedback circuit 4.

[0030] The first configuration example of the solid-state imaging device 100 includes the pixel circuit 3a of FIG. 1A and a negative feedback circuit 4a connected to the pixel circuit 3a.

[0031] The pixel circuit 3a includes a photodiode PD, a transfer transistor TG, a charge storage unit FD0, a transfer transistor TG, an amplifying transistor SF1, a reset transistor RS, and a selection transistor SEL_RS.

[0032] The photodiode PD is a photoelectric conversion element that converts incident light into a signal charge.

[0033] The charge storage unit FD0 is formed as, for example, a floating diffusion layer, and holds the signal charge generated in the photodiode PD. In the drawing, the storage capacitance element of the charge storage unit FD0 is denoted as C0.

[0034] The amplification transistor SF1 outputs a pixel signal corresponding to the signal charge of the charge storage unit FD0 to the vertical signal line 19B via the selection transistor SEL_RS.

[0035] The reset transistor RS resets the charge storage unit FD0.

[0036] The selection transistor SEL_RS is a switch element that selects whether or not to output a pixel signal from the amplification transistor SF1 to the vertical signal line 19B.

[0037] Furthermore, the pixel signal includes at least two types of components: a reset component and a signal component.

[0038] The negative feedback circuit 4a will be explained later.

[0039] [Second Configuration Example of Solid-State Imaging Device] Next, a second configuration example will be described. The second configuration example shows a configuration in which the above-mentioned storage circuits are provided in the horizontal direction.

[0040] The second configuration example of the solid-state imaging device 100 includes the pixel circuit 3b of FIG. 14 and a negative feedback circuit 4c connected to the pixel circuit 3b.

[0041] The second configuration example in Fig. 14 differs from the first configuration example in Fig. 1A in the circuit configurations of the pixel circuit 3b and the negative feedback circuit 4c. The following description will focus on the differences.

[0042] The pixel circuit 3b differs from the pixel circuit 3a in that the positions of the first storage capacitance element C1, the first gain control transistor GC1, the second storage capacitance element C2, and the second gain control transistor GC2 are added laterally from the viewpoint of charge movement.

[0043] The reset transistor RS can be reset in three ways by controlling the first gain control transistor GC1 and the second gain control transistor GC2: That is, the reset transistor RS can reset the charge storage unit FD0, the first charge storage unit FD1, and the second charge storage unit FD2.

[0044] When the transfer transistor TG is in the ON state, the charge that overflows from the charge storage unit FD0 is transferred to and held in the first storage capacitor element C1 as indicated by the dotted arrow A in the figure.

[0045] The first gain control transistor GC1 is a transistor that controls the connection between the charge storage unit FD0 and the first storage capacitor element C1. The first gain control transistor GC1 acts as a switching element and is in an ON state and an OFF state.

[0046] The signal charge that overflows the photodiode PD during exposure is transferred to and held in the second storage capacitor element C2, as indicated by the dotted arrow B in the figure. Here, an overflow element OF is provided between the photodiode PD and the second storage capacitor element C2, and the signal charge that overflows from the photodiode PD is transferred to the second storage capacitor element C2 via the overflow element OF rather than being transferred to the first storage capacitor element C1 via the transfer transistor TG.

[0047] Furthermore, the signal charge that has overflowed the second storage capacitor element C2 is discharged to the power supply via the second gain control transistor GC2 and RS.

[0048] In the second configuration example of the pixel circuit 3b, as shown by the dotted arrow B, the signal charge overflowing from the photodiode PD does not pass through the charge storage unit FD0 but is stored in the storage capacitor element Since the charge is accumulated in C2, the influence of the dark current component in the charge accumulation unit FD0 can be reduced. In addition, the presence of the overflow element OF makes it possible to control the overflow level and the depth of the charge channel, thereby reducing the influence of the dark current component generated in the surface layer.

[0049] The second gain control transistor GC2 is a transistor for gain control that controls the connection between the first storage capacitor element C1 and the second storage capacitor element C2. The second gain control transistor GC2 serves as a switching element and is in an ON state and an OFF state.

[0050] 14, a second configuration example of the solid-state imaging device 100 includes a pair of a switch element and a storage capacitor element, and an overflow storage circuit is provided to hold signal charges overflowing from the photodiode PD. The first-stage storage circuit is a pair of a first gain control transistor GC1 and a first storage capacitor element C1. The second-stage storage circuit is a pair of a second gain control transistor GC2 and a second storage capacitor element C2.

[0051] The negative feedback circuit 4c will be explained later.

[0052] This second configuration example makes it possible to achieve both an expansion of the dynamic range and an improvement in the signal-to-noise ratio.

[0053] [Third Configuration Example of Solid-State Imaging Device] Next, a third configuration example will be described. The third configuration example shows a configuration in which the above-described storage circuits are connected in two stages (m=2) in the vertical direction.

[0054] The solid-state imaging device 100 in FIG. 3 illustrates one of the pixel circuits 3c arranged in a matrix in FIG. 15 according to the third configuration example, and includes a negative feedback circuit 4c connected to the pixel circuit 3c.

[0055] The third configuration example of FIG. 15 is the first configuration example of FIG. 2 In comparison with the configuration example 1, the pixel circuit 3b is different, while the negative feedback circuit 4c is the same. The following description will focus on the differences.

[0056] The figure shows one of a plurality of pixel circuits 3c arranged in a matrix, which includes a photodiode PD, a transfer transistor TG, a charge storage unit FD0, a transfer transistor TG, an amplifier transistor SF1, a reset transistor RS, a first storage capacitor element C1, a first gain control transistor GC1, a second storage capacitor element C2, a second gain control transistor GC2, and a selection transistor SEL_RS.

[0057] The photodiode PD is a photoelectric conversion element that converts incident light into signal charge. The signal charge that overflows the photodiode PD during exposure is transferred to and held in the first storage capacitor element C1, as indicated by the dotted arrow D in the figure. Furthermore, the signal charge that overflows from the first storage capacitor element C1 is transferred to and held in the second storage capacitor element C2.

[0058] The charge storage unit FD0 is formed as, for example, a floating diffusion layer, and holds the signal charge generated in the photodiode PD. In the drawing, the storage capacitance element of the charge storage unit FD0 is denoted as C0.

[0059] The amplification transistor SF1 outputs a pixel signal corresponding to the signal charge of the charge storage unit FD0 to the vertical signal line 19B via the selection transistor SEL_RS.

[0060] The reset transistor RS resets the charge storage unit FD0. Specifically, the reset transistor RS can perform three types of resetting under the control of the first gain control transistor GC1 and the second gain control transistor GC2. That is, the reset transistor RS can reset the charge storage unit FD0, the first charge storage unit FD1, and the second charge storage unit FD2.

[0061] The first storage capacitor element C1 holds signal charges that overflow from the photodiode PD. For example, the first storage capacitor element C1 stores the signal charges that overflow from the photodiode PD during exposure via the transfer transistor TG and the first gain control transistor GC1.

[0062] The first gain control transistor GC1 is a transistor that controls the connection between the charge storage unit FD0 and the first storage capacitor element C1. The first gain control transistor GC1 acts as a switching element, taking an ON state and an OFF state. Note that the gate voltages of the transfer transistor TG and the first gain control transistor GC1 do not have to be completely OFF during exposure, and may be set so that signal charges overflowing from the photodiode PD can be transmitted from the transfer transistor TG to the first storage capacitor element C1 via the charge storage unit FD0 and the first gain control transistor GC1.

[0063] The second storage capacitor C2 holds the signal charge that has overflowed from the first storage capacitor C1. For example, the second storage capacitor C2 stores the signal charge that has overflowed from the first storage capacitor C1 via the second gain control transistor GC2.

[0064] The second gain control transistor GC2 is a gain control transistor that controls the connection between the first storage capacitor element C1 and the second storage capacitor element C2. The second gain control transistor GC2 acts as a switching element and is in an ON state and an OFF state. The gate voltage of the second gain control transistor GC2 does not have to be in a completely OFF state during exposure, and may be set so that signal charges overflowing from the first storage capacitor element C1 can be transmitted to the second storage capacitor element C2 via the second gain control transistor GC2.

[0065] The negative feedback circuit 4c will be explained later.

[0066] In this second configuration example as well, it is possible to achieve both an expansion of the dynamic range and an improvement in the signal-to-noise ratio.

[0067] [Configuration example of a negative feedback circuit for a solid-state imaging device] The negative feedback circuits 4a and 4c relating to the first to third configuration examples will be described below, along with the negative feedback circuits 4b and 4d.

[0068] The feedback amplifiers FA of the negative feedback circuits 4a and 4c are provided for the sample and hold circuits 10a, 10b, and 10c, which correspond one-to-one to the pixel circuits 3a, 3b, and 3c, respectively. The same is true for the feedback amplifier FA of the negative feedback circuit 4b. Alternatively, the feedback amplifier FA of the negative feedback circuit 4d is provided for the plurality of sample and hold circuits 10 (SH circuits 10a, 10b, and 10c) which correspond one-to-one to the plurality of pixel circuits 3a, 3b, or 3c.

[0069] Hereinafter, as needed, the sample-and-hold circuits 10a, 10b, and 10c will be collectively referred to as the sample-and-hold circuit 10. Similarly, as needed, the negative feedback circuits 4a, 4b, 4c, and 4d will be collectively referred to as the negative feedback circuit 4.

[0070] In the negative feedback circuit 4, the output of the amplifying transistor SF1 of the pixel circuit is input to the positive input terminal of the feedback amplifier FA. The output signal of the sample and hold circuit 10 is negatively fed back to the sample and hold circuit 10 via feedback line 17A. The output signal of the sample and hold circuit 10 is input to the negative input terminal of the feedback amplifier FA via feedback line 17B and the amplifying transistor SF2. The feedback amplifier FA operates so that the differential voltage between the output of the amplifying transistor SF1 and the output of the amplifying transistor SF2 (amplifying transistor SF3) converges to zero.

[0071] When the negative feedback circuit 4 applies negative feedback, the selection transistor SEL_GS is always kept in the ON state by the selection control signal φSEL_GS, and electrically connects the source of the amplification transistor SF2 (amplification transistor SF3) to the vertical signal line 19 A. Similarly, the selection transistor SEL_RS is always kept in the ON state by the selection control signal φSEL_RS, and electrically connects the source of the amplification transistor SF1 to the vertical signal line 19 B.

[0072] Furthermore, when the signal of the sample and hold capacitance element C of the negative feedback circuit 4 is read out via the vertical signal line 19A and subjected to AD processing by the column AD circuit 25, SEL_GS is turned on by the selection control signal φSEL_GS.

[0073] In the above first to third configuration examples, an operation of capturing a low-illuminance frame, an operation of capturing a high-illuminance frame, an operation of combining a low-illuminance frame and a high-illuminance frame, an operation of combining a low-illuminance frame, a medium-illuminance frame and a high-illuminance frame, etc. are performed.

[0074] Here, a low-illuminance frame refers to, for example, a frame captured with all storage circuits turned off, and is suitable for low-illuminance environments. A high-illuminance frame refers to, for example, a frame captured with all storage circuits turned on, and is suitable for high-illuminance environments. A medium-illuminance frame refers to, for example, a frame captured with some of the storage circuits turned on, and is suitable for medium-illuminance environments. Note that high, medium, and low illuminance do not refer to absolute illuminance, but rather to relative relationships.

[0075] When capturing an image of a low-illuminance frame, the signal component signals are captured with the multiple storage circuits in the OFF state, and the signal charge that has been completely transferred from the photodiode PD to the charge storage unit FD0 is read out by the negative feedback circuit 4. The reset component and signal component signals are transitioned from the ON state to the OFF state by applying a gentle slope signal to the control signal φSH of each sample and hold switch element (SH) of the sample and hold circuit 10 of the negative feedback circuit 4, while the kTC noise of the sample and hold capacitance element is reduced by negative feedback via the feedback amplifier FA, making it possible to hold the signal.

[0076] Similarly, when capturing an image of a medium-illuminance frame, the signal component signal is captured with the first-stage storage circuit (GC1) in the ON state, and the signal charge completely transferred from the photodiode PD to the charge storage unit FD0 is mixed with the charge in the first-stage storage capacitor (GC1) and read out by the negative feedback circuit 4. The reset component and signal component signals are transitioned from the ON state to the OFF state by applying a gentle slope signal to the control signal φSH of each sample and hold switch element (SH) of the sample and hold circuit 10 of the negative feedback circuit 4, while the kTC noise of the sample and hold capacitor element is reduced by negative feedback via the feedback amplifier FA, making it possible to hold the signal.

[0077] Similarly, when capturing an image of a high-illuminance frame, the signal component signal is captured with the first-stage storage circuit (GC1) and second-stage storage circuit (GC2) in the ON state, and the signal charge completely transferred from the photodiode PD to the charge storage unit FD0 is mixed with the charge in the first-stage storage capacitor (GC1) and second-stage storage capacitor (GC2), and then read out by the negative feedback circuit 4. The reset component and signal component signals are transitioned from the ON state to the OFF state by applying a gentle slope signal to the control signal φSH of each sample-and-hold switch element (SH) of the sample-and-hold circuit 10 of the negative feedback circuit 4, while the kTC noise of the sample-and-hold capacitor element is reduced by negative feedback via the feedback amplifier FA, making it possible to hold the signal.

[0078] The signal of each sample and hold capacitance element is read out row by row in a rolling manner by a read selection switch element control signal φSE, and is subjected to CDS (=signal component-reset component) processing by an ADC circuit to extract only the signal level.

[0079] This makes it possible to further expand the dynamic range by matching and synthesizing the signal components read out in low-illuminance areas with the signal components read out in high-illuminance areas, or by selectively reading out appropriate frames depending on the illuminance.

[0080] According to this method, when capturing low-illumination frames, using only the signal charge transferred from the photodiode PD to the charge storage unit FD0 increases the in-pixel gain, i.e., the gain at which the signal charge is converted into voltage by the amplifier transistor SF. This increases the voltage (pixel signal) corresponding to the amount of received light relative to noise generated by the amplifier transistor SF and analog circuitry. Furthermore, the kTC noise generated when the pixel signal is sampled and held can be reduced by the negative feedback circuit 4. In other words, when capturing a dark subject, it is possible to output a high-quality image with a high signal-to-noise ratio (SN).

[0081] On the other hand, when capturing medium- and high-illuminance frames, multiple or all of the storage circuits are used to lower the in-pixel gain, expanding the dynamic range and enabling high-illuminance light reception. Furthermore, the negative feedback circuit 4 can improve the signal-to-noise ratio. In other words, for bright subjects, the gradation according to the subject is accurately reproduced, making it possible to output an image without blown-out highlights.

[0082] Furthermore, the three frames for WDR (Wide Dynamic Range) - low-light, medium-light, and high-light - can be generated at exactly the same time using exactly the same pixels, which means that false colors, discoloration, and blurring can be eliminated.

[0083] The technology to reduce kTC noise generated when pixel signals are sampled and held using the negative feedback circuit 4 can be applied not only to imaging devices using the global shutter method, but also to distance measuring devices using the TOF (Time of Flight) method. Of course, it can also be extended to the rolling shutter method in addition to the global shutter method.

[0084] For example, by providing multiple photodiodes PD with different sensitivities in the pixel circuit 3 and increasing the number of storage capacitor elements, the number of pixel signals can be further increased by combining these signal charges. This increases the number of frames for WDR and further expands the dynamic range.

[0085] In addition, although it is generally very difficult to use a highly saturated pixel, this embodiment makes it possible to increase the saturation level with a small capacitance of the photodiode PD. To increase the storage capacitance in the storage circuit, the voltage amplitude between the capacitance terminals may be increased, and in order to increase the capacitance area within a limited pixel cell, the semiconductor chip that constitutes the solid-state imaging device may be made three-dimensional or multi-layered.

[0086] For example, the storage capacitor element in the storage circuit may be disposed on a semiconductor chip having pixels or on a semiconductor chip having a logic circuit. Even if disposed on a semiconductor chip having pixels, the storage capacitor element may be formed on the top layer or the bottom layer of the metal layer.

[0087] As outlined above, a solid-state imaging device according to an aspect of the present disclosure includes a pixel circuit 3 and a negative feedback circuit 4. The pixel circuit 3 includes a photodiode PD, a charge storage unit FD0, a transfer transistor TG that transfers signal charges generated in the photodiode PD to the charge storage unit FD0, an amplification transistor SF1 that outputs a pixel signal corresponding to the signal charges of the charge storage unit FD0, a reset transistor RS that resets the charge storage unit FD0, a first storage capacitor element C1, a first gain control transistor GC1 that controls a connection between the charge storage unit FD0 and the first storage capacitor element C1, and a second gain control transistor GC2 that controls a connection between the charge storage unit FD0 and the first storage capacitor element C1. and a second gain control transistor GC2 that controls the connection with the second storage capacitance element C2. The negative feedback circuit 4 has a sample-and-hold circuit 10 and a feedback amplifier FA, and the output signal of the pixel circuit 3 is input to the positive input terminal of the feedback amplifier FA via the amplification transistor SF1, and the output of the feedback amplifier FA is negatively fed back to the sample-and-hold circuit 10 and input to the negative input terminal of the feedback amplifier FA via the amplification transistor SF2 (amplification transistor SF3), thereby reducing kTC noise that occurs when single or multiple pixel signals are sampled and held.

[0088] As outlined above, a solid-state imaging device according to one embodiment of the present disclosure includes a pixel circuit 3 that outputs a pixel signal, and a negative feedback circuit 4, and the negative feedback circuit 4 includes a sample-and-hold circuit 10 that samples and holds the pixel signal, and a feedback amplifier FA that negatively feeds back to the SH circuit 10 a feedback signal that corresponds to the difference between the pixel signal from the pixel circuit 3 and the output signal from the SH circuit.

[0089] According to this, the kTC noise generated in the SH circuit 10 can be suppressed by applying negative feedback, the image quality in low illumination can be improved, and the dynamic range can be expanded.

[0090] Here, the SH circuit 10 includes an SH unit circuit 10u that samples and holds a pixel signal, and an amplifier transistor SF2 that amplifies the output signal of the SH unit circuit 10u and outputs the amplified signal to the feedback amplifier FA, the SH unit circuit 10u includes a first sample and hold switch element SH for sampling the feedback signal, and a first sample and hold capacitance element C connected to the first sample and hold switch element SH, the pixel signal from the pixel circuit 3 is input to the positive input terminal of the feedback amplifier FA, the feedback signal of the feedback amplifier FA is input to the first sample and hold switch element SH, the output signal of the amplifier transistor SF2 is input to the negative input terminal of the feedback amplifier FA, and the feedback amplifier FA, the SH unit circuit, and the amplifier transistor SF2 may form a feedback loop.

[0091] This allows the voltage levels of a single pixel signal or multiple pixel signals to be matched with those of the sample and hold capacitor element C, and furthermore, kTC noise generated in the SH circuit 10 can be suppressed by applying negative feedback, thereby improving image quality in low illumination and expanding the dynamic range.

[0092] Here, the SH unit circuit may include a first read selection switch element that connects the first sample and hold capacitive element and the amplifying transistor.

[0093] This makes it possible to suppress the influence of the parasitic capacitance of the wiring in the SH unit circuit compared to a configuration that does not include the first read selection switch element, and for example, to shorten the time it takes for the feedback loop to stabilize in the sample operation.

[0094] Here, the negative feedback circuit 4 may include a feedback capacitance element CS connected to one of the two terminals of the first sample and hold switch element SH to which the feedback signal is input, and an attenuator capacitance element CC connected in parallel to the first sample and hold switch element SH.

[0095] This makes it possible to further suppress the kTC noise generated in the SH circuit 10. This makes it possible to improve image quality in low illumination and expand the dynamic range.

[0096] Here, the pixel circuit 3 may output a plurality of pixel signals, and the sample-and-hold circuit 10 may have a plurality of the SH unit circuits 10u corresponding to the plurality of pixel signals.

[0097] This allows the kTC noise generated in the SH circuit 10 to be suppressed by applying negative feedback in a plurality of pixel signals at gains for a plurality of illuminances, thereby improving image quality with pixel signals at low illuminances and enabling pixel signals to be generated at gains for a plurality of illuminances, thereby easily expanding the dynamic range.

[0098] Here, the plurality of pixel signals may include a first pixel signal, a second pixel signal, and a third pixel signal having different exposure sensitivities from each other, and the plurality of SH unit circuits may include a first SH unit circuit, a second SH unit circuit, and a third SH unit circuit.

[0099] This allows for suppressing kTC noise generated in the SH circuit 10 by applying negative feedback to, for example, a first pixel signal with HCG (High Conversion Gain) for low illumination, a second pixel signal with MCG (Middle Conversion Gain) for medium illumination, and a third pixel signal with LCG (Low Conversion Gain) for high illumination. This improves image quality using the first pixel signal at low illumination, and easily expands the dynamic range by combining these three signals.

[0100] Here, the first sample and hold capacitance elements in two or more of the plurality of SH unit circuits may be connected in parallel to mix corresponding pixel signals. Here, a plurality of the pixel circuits 3 and a plurality of the SH circuits 10 may be provided, and the feedback amplifier (FA) may be shared by two or more SH circuits (10).

[0101] This allows a single feedback amplifier FA to be shared by multiple sample-and-hold circuits for negative feedback, resulting in efficient layout area and being particularly effective for miniaturizing pixel circuits.

[0102] Here, the pixel signal may include a reset component and a signal component, and the SH unit circuit 10u may include the first sample and hold switch element SH, the first sample and hold capacitive element C, a second sample and hold switch element for sampling the feedback signal, and a second sample and hold capacitive element connected to the second sample and hold switch element, wherein the first sample and hold capacitive element C holds the reset component, and the second sample and hold capacitive element C holds the signal component.

[0103] According to this, the characteristics of the solid-state imaging device (for example, the threshold voltage V of the amplification transistor SF2) t、Even if the process, temperature, and voltage conditions change, CDS can cancel out the variations by subtracting the reset component from the signal component, allowing a correct pixel signal to be obtained.

[0104] Here, the SH unit circuit may include a first read selection switch element that connects the first sample and hold capacitance element and the amplification transistor, and a second read selection switch element that connects the second sample and hold capacitance element and the amplification transistor.

[0105] This makes it possible to suppress the influence of the parasitic capacitance of the wiring in the SH unit circuit compared to a configuration that does not include the first read selection switch element, and for example, to shorten the time it takes for the feedback loop to stabilize in the sample operation.

[0106] Here, the plurality of pixel circuits 3 may be arranged in a matrix, the plurality of SH circuits 10 may be arranged in a matrix, the pixel circuits 3 and the SH circuits 10 may be stacked one-to-one, and the feedback amplifier FA may be arranged between the SH circuits 10 in a planar view.

[0107] This shortens the readout distance from the pixel circuits 3 to the SH circuits 10 that correspond one-to-one. Also, the negative feedback load from the feedback amplifiers FA to the SH circuits 10 becomes approximately equal on the left and right, making it possible to achieve approximately equal reduction effects in kTC noise and eliminating regular fixed components of noise.

[0108] Here, the first sample-and-hold switch element SH may transition from an ON state to an OFF state in accordance with a control signal having a slope-shaped voltage waveform.

[0109] According to this, the generation of kTC noise can be further suppressed by the turn-off operation of the control signal having a slope-shaped voltage waveform of each sample-hold switch element SH of the negative feedback circuit 4.

[0110] Here, the negative feedback circuit 4 may include a third sample and hold switch element SH10 inserted in the feedback loop between the output terminal of the feedback amplifier FA and the input terminal of the first sample and hold switch element SH, and the third sample and hold switch element SH10 may transition from an ON state to an OFF state in accordance with a control signal having a sloping voltage waveform.

[0111] According to this, the generation of kTC noise can be further suppressed by the turn-off operation of the control signal having a slope-shaped voltage waveform of the sample-and-hold switch element SH10 of the negative feedback circuit 4.

[0112] Here, the negative feedback circuit 4 may include a measurement unit 6 that measures the noise level of the first sample and hold capacitive element C in the SH circuit 10, and a determination unit that determines the gradient of the sloping voltage waveform so as to reduce the measured noise level.

[0113] This makes it possible to appropriately suppress the kTC noise level even if the characteristics of the sample-and-hold circuit 10 or the control signal of the sample-and-hold switch element SH change.

[0114] Here, the negative feedback circuit has a switch circuit (SW11, SH10) for switching whether or not to perform negative feedback in the sample-and-hold operation, and at least one of the plurality of pixel signals One Negative feedback may be implemented for some pixel signals, and negative feedback may not be implemented for other pixel signals.

[0115] According to this, when pixel signals are read from pixel circuit 3 to negative feedback circuit 4, for example, negative feedback is applied to at least pixel signal 1 (HCG), which reduces kTC noise and improves low-illumination noise. Furthermore, if negative feedback is not applied to pixel signal 2 (MCG) or pixel signal 3 (LCG), speed can be increased, and both characteristics can be achieved.

[0116] Here, the feedback amplifier FA has a gain switching function, and in the negative feedback circuit 4, Each of The gain of the feedback amplifier FA may be set for each time.

[0117] According to this, when pixel signals are read from pixel circuit 3 to negative feedback circuit 4, for example, negative feedback is applied to at least pixel signal 1 (HCG) with the gain of the feedback amplifier FA being large, so kTC noise can be significantly reduced and low-illumination noise can be improved. Furthermore, negative feedback is applied to pixel signal 2 (MCG) or pixel signal 3 (LCG) with the gain of the feedback amplifier FA being small, so kTC noise cannot be significantly reduced, but the convergence time can be speeded up, making it possible to achieve both characteristics.

[0118] Here, the capacitance values ​​of the first sample and hold capacitive elements C in the plurality of SH unit circuits 10u may differ depending on the corresponding pixel signals.

[0119] According to this, when pixel signals are read out to pixel circuit 3c, for example, if the capacitance value of pixel signal 1 (HCG) is made the largest, kTC noise can be reduced the most compared to pixel signal 2 (MCG) and pixel signal 3 (LCG), and low-illumination noise can be improved.

[0120] Here, the pixel circuit 3 has an output transistor SF1 that outputs the pixel signal, and the size of the amplification transistor SF2 may be larger than the size of the output transistor SF1.

[0121] This makes it possible to reduce device noise that occurs when a signal is read out from the negative feedback circuit 4 via the amplifying transistor SF2.

[0122] Here, the plurality of pixel circuits 3 may be exposed using a global shutter method or a rolling shutter method, and the plurality of pixel circuits 3 may output pixel signals to the plurality of SH circuits 10 simultaneously for all pixels, and the plurality of SH circuits 10 may be read out using a rolling method.

[0123] This allows the device to be mounted in an imaging device and a distance measuring imaging device that captures an object with a wide dynamic range and without distortion or blurring between pixel signals (HCG, MCG, LCG).

[0124] Here, the solid-state imaging device may include a plurality of semiconductor chips bonded together, one of the plurality of semiconductor chips having a plurality of the pixel circuits 3, and another of the plurality of semiconductor chips having a plurality of the SH circuits 10.

[0125] This allows, for example, the feedback amplifier FA and multiple shared sample switch elements (SH) and sample hold capacitor elements (C) to be mounted on separate chips, reducing the number of shared elements. This speeds up the readout time from the pixel circuit 3 to the negative feedback circuit 4, which is advantageous for pixel characteristics and optical characteristics. This is particularly effective for fine cells.

[0126] Moreover, an imaging device according to one aspect of the present disclosure includes the solid-state imaging device that images a subject, an imaging optical system that guides incident light from the subject to the solid-state imaging device, and a signal processing unit that processes an output signal from the solid-state imaging device.

[0127] In addition, a distance measuring imaging device according to one aspect of the present disclosure includes a solid-state imaging device that captures reflected light from an object irradiated with pulsed light, an imaging optical system that guides the reflected light from the object to the solid-state imaging device, and a signal processing unit that processes an output signal from the solid-state imaging device.

[0128] Hereinafter, a solid-state imaging device according to an embodiment of the present disclosure will be described with reference to the drawings.

[0129] (Embodiment 1A) First, a configuration example of a solid-state imaging device according to the present embodiment will be described. In embodiment 1A, a configuration example in which the in-pixel gain in pixel circuit 3a in the first configuration example of FIG. 1A is a single gain will be described in detail.

[0130] [Configuration example of solid-state imaging device 100] FIG. 3 is a block diagram showing an example of the configuration of the solid-state imaging device 100 according to the embodiment 1A.

[0131] The solid-state imaging device 100 shown in the figure includes a pixel array section 1, a horizontal scanning circuit 12, a vertical scanning circuit 14, a plurality of vertical signal lines 19A, a plurality of vertical signal lines 19B, a timing control section 20, a column processing section 26, a reference signal generating section 27, an output circuit 28, and signal processing sections 70 and 80. The solid-state imaging device 100 also includes an MCLK terminal for receiving an external master clock signal, a DATA terminal for transmitting and receiving commands or data to and from the outside, a D1 terminal for transmitting video data to the outside, and other terminals to which a power supply voltage and a ground voltage are supplied.

[0132] The pixel array section 1 has a plurality of pixel circuits 3a arranged in a matrix. The plurality of pixel circuits 3 are arranged in n rows and m columns in FIG.

[0133] The horizontal scanning circuit 12 sequentially scans the memories 256 in the plurality of column AD circuits 25, thereby outputting the AD-converted pixel signals to the signal processing units 70 and 80 via horizontal signal lines. This scanning may be performed in the same order as the arrangement of the column AD circuits 25.

[0134] The vertical scanning circuit 14 scans, row by row, horizontal scanning line groups (also referred to as row control line groups) 15 provided for each row of pixel circuits 3 in the pixel array unit 1. In this way, the vertical scanning circuit 14 selects pixel circuits 3a row by row and causes the pixel circuits 3a belonging to the selected row to simultaneously output pixel signals to m vertical signal lines 19. The number of horizontal scanning line groups 15 provided is the same as the number of pixel circuit 3 rows.

[0135] In FIG. 3, n horizontal scanning line groups 15 (V1, V2, . . . , Vn) are provided for the pixel circuit 3a, and each includes a reset control signal φRS, a read control signal φTG, and a selection control line φSEL_RS.

[0136] In addition, n horizontal scanning line groups 16 (VSH1, VSH2, ..., VSHn) are provided for the negative feedback circuit 4a, and each includes a sample and hold switch control signal φSH, a read selection switch element control signal φSE, and a selection control line φSEL_GS that constitute each sample and hold circuit 10.

[0137] The vertical signal line 19A is provided in the negative feedback circuit 4 and transmits pixel signals from the pixel circuits 3 belonging to a selected row to the column AD circuit 25. In addition, the multiple vertical signal lines 19A and 19B consist of m vertical signal lines (H1, . . . , Hm) in FIG. 3. The multiple ADC input lines consist of m ADC input lines (ADIN1, . . . , ADINm).

[0138] The slope signal generating unit 30 determines the slope of each sample hold switch control signal φSH of the negative feedback circuit 4a and, if necessary, the slope of the read selection switch element control signal φSE to generate an optimal slope signal and reduce kTC noise.

[0139] Vertical scanning circuit 1 4 is The output signal supplied from the slope signal generating unit 30 is converted into the horizontal scanning line group 16 (VSHn) based on the control signal group CN1. twist , the sample and hold switch control signal φSH (SH1, SH2, . . . , SHn) of the negative feedback circuit 4, and, if necessary, the read selection switch element control signal φSE (SE1, SE2, . . . , SEn) as Supply.

[0140] The timing control unit 20 generates various control signals to control the entire solid-state imaging device 100. The various control signals include control signals CN1, CN2, CN4, CN5, and CN8, and counter clock signals CK0 and CK1. For example, the timing control unit 20 receives a master clock MCLK via a terminal, generates various internal clocks, and controls the horizontal scanning circuit 12, vertical scanning circuit 14, etc.

[0141] The column processing unit 26 includes a column AD circuit 25 provided for each column. Each column AD circuit 25 performs AD conversion on the pixel signal from the vertical signal line 19A.

[0142] Each of the column AD circuits 25 includes a voltage comparator 252 , a counter unit 254 , and a memory 256 .

[0143] The voltage comparator 252 compares the analog pixel signal from the vertical signal line 19A with a reference signal RAMP, which includes a ramp waveform (i.e., a triangular wave), generated by the reference signal generation unit 27, and inverts an output signal indicating the comparison result when, for example, the former becomes larger than the latter.

[0144] Counter unit 254 counts the time from when the triangular wave in reference signal RAMP starts to change until the output signal of voltage comparator 252 inverts. The time until inversion is determined according to the value of the analog pixel signal, so the count value is the value of the digitized pixel signal.

[0145] The memory 256 stores the count value of the counter unit 254, that is, the digital pixel signal.

[0146] The reference signal generating unit 27 generates a reference signal RAMP including a triangular wave, and outputs the reference signal RAMP to the positive input terminal of the voltage comparator 252 in each column AD circuit 25 .

[0147] The output circuit 28 outputs the digital pixel signal to the video data terminal D1.

[0148] The signal processing unit 70 has a WDR synthesis circuit 76 and is composed of a memory 77, a low illuminance signal circuit 71, a medium illuminance signal circuit 72, a high illuminance signal circuit 73, and the WDR synthesis circuit 76.

[0149] The signal processing unit 80 detects kTC noise in the kTC noise detection region using a noise calculation circuit 86 and stores the optimum value of the noise in an optimum value holding circuit 87. The kTC noise detection region is, for example, the OB region, which is a region that includes optical black pixels. As soon as the signal processing unit 80 completes the search in the kTC noise detection region, it sends the optimum value to the timing control circuit, and the slope signal generation unit 30 reads out a signal at the optimum slope voltage.

[0150] As a result, the signal processing units 70 and 80 aim to achieve both an expansion of the dynamic range and an improvement of the S / N ratio.

[0151] The vertical scanning circuit 14, the reference signal generating unit 27, and the slope signal generating unit 30 may be collectively referred to as a driving unit. The column processing unit 26 and the horizontal scanning circuit 12 may be collectively referred to as a control unit. The noise calculation circuit 86 may be referred to as a measurement unit. The optimal value holding circuit 87 may be referred to as a determination unit.

[0152] [Pixel circuit configuration example] Next, a configuration example of the pixel circuit 3a will be described.

[0153] 1A is a diagram showing an example of a main circuit including a pixel circuit 3a according to embodiment 1A. The pixel circuit 3a in the diagram includes a photodiode PD, a transfer transistor TG, a storage capacitor element C0, a charge storage unit FD0, a reset transistor RS, a first gain control transistor GC1, an amplification transistor SF1, and a selection transistor SEL_RS.

[0154] The horizontal scanning line group 15(Vn) also includes a reset control signal φRS, a read control signal φTG, a first gain control signal φGC1, a second gain control signal φGC2, and a selection control line φSEL_RS.

[0155] The horizontal scanning line group 16 (VSHn) includes a sample and hold switch control signal φSH, a read selection switch element control signal φSE, and a selection control line φSEL_GS.

[0156] The photodiode PD is a photoelectric conversion element such as a photodiode, and performs photoelectric conversion with a predetermined sensitivity, that is, generates an electric charge according to the amount of received light.

[0157] Furthermore, the storage capacitance element C0 connected to the charge storage unit FD0 holds signal charges (e.g., electrons) transferred from the photodiode PD, converts the held signal charges into a voltage, and supplies the converted voltage to the gate of the amplifier transistor SF1. The substantial capacitance of the charge storage unit FD0 includes not only the capacitance of the charge storage unit FD0 itself, but also the gate capacitance of the amplifier transistor SF, the gate-drain capacitance of the amplifier transistor SF, and the stray capacitance of the gate-drain capacitance.

[0158] The transfer transistor (TG) is a switch transistor that is turned on and off in response to a read control signal φTG. When the read control signal φTG is at a high level, the transfer transistor TG transfers the signal charge photoelectrically converted by the photodiode PD to the charge accumulation unit FD0.

[0159] The reset transistor RS is a switch transistor that is turned on and off in response to a reset control signal φRS. When the reset control signal φRS is at a high level, the reset transistor RS sets the power supply voltage applied to the drain to the charge storage unit FD0.

[0160] The amplifying transistor SF1 forms a source follower in conjunction with a load current source P1 connected to the vertical signal line 19B, and outputs the gate voltage, ie, the voltage of the charge storage unit FD0, to the vertical signal line 19B as an analog pixel signal.

[0161] The selection transistor SEL_RS is a switch transistor that is turned on and off in response to a selection control signal φSEL_RS When the selection control signal φSEL_RS is at a high level, the selection transistor SEL_RS electrically connects the source of the amplification transistor SF1 to the vertical signal line 19B.

[0162] 4 shows the connection between the pixel chip and logic chip in FIGS. 1A, 1B, and 2. The pixel circuit 3 is connected to a negative feedback circuit 4 for each single pixel, and a signal is input thereto. The signal from the negative feedback circuit 4 is read out through a vertical signal line 19A, and the number of vertical signal lines may be increased to increase the number of pixel signal readout signals and speed up the operation.

[0163] [HCG readout operation example] Next, we will explain the HCG (High Conversion Gain) readout operation in the solid-state imaging device 100 equipped with the pixel circuit 3a and negative feedback circuit 4a shown in FIG. 1A. The HCG readout operation uses only the charge storage unit FD0 to store signal charges, increasing the conversion gain of the amplification transistor SF1. Therefore, the HCG operation is a highly sensitive imaging operation that is suitable for imaging in low-illumination environments.

[0164] In the CDS (correlated double sampling) in the HCG readout operation from the negative feedback circuit 4a, the signal level is read out after the kTC noise of the analog pixel signal is read out. In CDS, the difference between the kTC noise and the signal level is calculated.

[0165] [Configuration and operation example of a negative feedback circuit] At high illuminance, signal charge is stored in the photodiode PD of the pixel circuit, while at low illuminance, kTC noise can be reduced by the negative feedback circuit 4a, achieving low noise. As a result, the dynamic range can be expanded. Generally, when sample-and-hold is performed using the control signal φSH of the sample-and-hold switch elements (SH20, SH21), kTC noise occurs in the sample-and-hold capacitance elements (C20, C21).

[0166] As a countermeasure, the output of the amplifying transistor SF1 of the pixel circuit is connected to the positive input terminal of the feedback amplifier FA. The sample and hold circuit 10a is provided with sample and hold capacitance elements (C20, C21), sample and hold switch elements (SH20, SH21), and read selection switch elements (SE26, SE27), which are connected to a feedback line 17B and input to the gate of the amplifying transistor SF2. The output of the amplifying transistor SF2 is connected to the negative input terminal of the feedback amplifier, and the feedback line 17A, which is the feedback output signal, is connected to the input terminal of the sample and hold switch elements (SH20, SH21) to perform negative feedback.

[0167] As a result, a signal with reduced noise that is equal to the pixel signal level is held in the sample and hold capacitor elements (C20, C21).

[0168] Furthermore, the control signal φSH input to the sample-and-hold switch elements (SH20, SH21) has a sloping voltage waveform that gradually transitions from the ON state to the OFF state. Hereinafter, a signal having a sloping voltage waveform will be referred to as a slope signal.

[0169] FIG. 7 is a diagram showing the waveform of a slope signal. As shown in FIG. 7, the control voltage of the sample and hold capacitor element changes gradually as a slope signal. FIG. 8 is a diagram showing the relationship between the slope period and the noise level of the sample and hold capacitor element. As shown in FIGS. 8 and 9, while negative feedback is applied, the kTC noise gradually approaches such that the input voltage at one end of the feedback amplifier becomes the output voltage of the amplifying transistor SF1 of the pixel circuit 3. As the two potentials become closer, the rate of change of the voltage of the sample and hold capacitor elements (C20, C21) becomes smaller. When the two potentials become equal, the potential of the sample and hold capacitor elements (C20, C21) is fixed.

[0170] Finally, the operation of this feedback amplifier FA is turned off, thereby completing the operation.

[0171] The sample and hold capacitance element (C20) holds a signal of the reset component (RST component) of HCG, while the sample and hold capacitance element (C21) holds a signal of the signal component (SIG component) of HCG.

[0172] In addition, by subtracting the reset component from the signal component using CDS, the variations can be canceled, kTC noise can be reduced, and the signal can be extracted with good S / N ratio.

[0173] Here, the product of the bandwidth B and gain G of the feedback amplifier FA is constant. Setting the gain G high can efficiently reduce kTC noise, but the bandwidth B becomes narrower and convergence takes a relatively long time. On the other hand, converging in a short time (wide bandwidth B) reduces the gain G and kTC noise cannot be efficiently reduced.

[0174] Furthermore, it is preferable that the bandwidth of the feedback amplifier FA is wider than the bandwidth of the pixel section, in which case the high frequency components of the kTC noise can be efficiently cancelled.

[0175] As described above, in this embodiment, the dynamic range can be expanded by improving low illumination by reducing kTC noise.

[0176] The selection transistor SEL_GS is a switch transistor that is turned on and off in response to a selection control signal φSEL_GS When the selection control signal φSEL_GS is at a high level, the selection transistor SEL_GS electrically connects the source of the amplification transistor SF2 to the vertical signal line 19A.

[0177] The photodiode PD is exposed to light for an exposure period using a global shutter or a rolling shutter. The amount of charge generated by exposure is assumed to be Q0.

[0178] In the global shutter method, a global reset is performed simultaneously on all pixels, starting exposure, and the exposure time is represented by T_Q0. Next, the charge from the photodiodes is simultaneously read out to the sample and hold capacitor elements (C20, C21). After that, the signal charge in the sample and hold capacitor elements (C20, C21) is read out from the vertical signal line A in a rolling manner for each row.

[0179] In the rolling shutter method, all pixels are scanned row by row for each selected row, shuttering, and exposure begins; the exposure time is represented by T_Q0. Next, charge is read from the photodiode to the sample and hold capacitor elements (C20, C21) by scanning row by row for the selected row. After that, the signal charge in the sample and hold capacitor elements (C20, C21) is read out from the vertical signal line 19A in a rolling manner for each row.

[0180] FIG. 5 shows an example of the timing of a signal read operation.

[0181] First, at time t500, the photodiode PD and the charge storage unit FD0 are reset and exposure is awaited. Then, at time t501, the shutter is operated and exposure begins. At time t502, the exposure time ends.

[0182] Next, at time t502, RS is turned ON to reset FD0, entering the readout period of the reset component. At time t506, TG is turned ON to transfer the signal charge accumulated in the photodiode to FD0 by the transfer signal (TG), entering the readout period of the signal component.

[0183] First, at times t503 and t507, the control signal φSH of the sample and hold switch elements (SH20 and SH21) and the control signal φSE of the readout selection switch elements (SE26 and SE27) are turned ON, thereby connecting the sample and hold capacitance elements (C20 and C21) to the feedback lines 17A and 17B. As a result, the output signal of the pixel circuit 3a is negatively fed back to the sample and hold capacitance elements (C20 and C21).

[0184] In the negative feedback circuit 4a, the sample-and-hold switch element SH10 is always in the ON state, the switch element SW1 is always in the ON state, and the switch element SW11 is always in the OFF state.

[0185] In the negative feedback circuit 4a, address selection is performed by the control signal φSH of the sample and hold switch elements (SH20, SH21) and the control signal φSE of the read selection switch elements (SE26, SE27), and the signal is sampled and held in one of the multiple sample and hold capacitance elements (C20, C21) shared by the feedback amplifier FA to reduce noise, and this operation is repeated.

[0186] First, at times t503 and t507, the sample and hold switch elements (SH20 and SH21) and the readout selection switch elements (SE26 and SE27) are turned ON, and the signals of the sample and hold capacitance elements (C20 and C21) are supplied to the negative input terminal of the feedback amplifier FA via the amplification transistor SF2. At this time, the output voltage of the sample and hold capacitance elements (C20 and C21) via the amplification transistor SF2 operates to converge to the output signal via the amplification transistor SF1 of the pixel circuit 3, which is applied to the positive input terminal of the feedback amplifier FA.

[0187] Next, at times t504 and t508, the control signal φSH of the sample-and-hold switch elements (SH20 and SH21) is turned OFF, generating kTC noise. Therefore, kTC noise is added to the voltage of the sample-and-hold capacitor elements (C20 and C21) after reset. While the feedback amplifier FA is operating and its output is connected to the feedback line 17A (until times t505 and t509), the negative feedback circuit remains formed. Therefore, the kTC noise generated by turning OFF the control signal φSH of the sample-and-hold switch elements (SH20 and SH21) at times t504 and t508 is reduced to 1 / (1+A), where A is the gain of the feedback amplifier FA.

[0188] Furthermore, by turning off the control signal φSE of the read selection switch elements (SE26 and SE27), kTC noise occurs at the node of the gate of the amplifier transistor SF2, but this parasitic capacitance is negligible because it is sufficiently small compared to the sample and hold capacitance elements (C20 and C21). This can be seen from the fact that kTC noise can be expressed in terms of charge as √(kTC)(C).

[0189] For the reasons stated above, the read selection switch element control signal φSE may be turned off by a slope signal or a rectangular signal in conjunction with the corresponding sample and hold switch control signal φSH, or may be turned off after the sample and hold switch control signal φSH.

[0190] The feedback amplifier FA may be in a constantly operating state during the period when the pixel circuit 3a is read out to the sample and hold circuit 10a (from time t502 to t510).

[0191] As a result of the above operation, the voltage across the amplifying transistor SF2 just before the control signal φSH of the sample and hold switch elements (SH20, SH21) is turned OFF (just before noise reduction begins) converges to a level approximately equal to the voltage across the amplifying transistor SF2 of the pixel signal applied to the positive input terminal of the feedback amplifier FA.

[0192] Generally, the product G×B of the gain G and band B of the amplifier that makes up the feedback amplifier FA is constant, so increasing the gain G narrows the band B (lower the cutoff frequency). In other words, it takes time for the feedback amplifier FA to converge. Conversely, lowering the gain G widens the band B (higher the cutoff frequency). In other words, it shortens the time for the feedback amplifier FA to converge.

[0193] For this reason, it is necessary to determine the gain of the feedback amplifier FA taking into consideration the noise level and convergence time.

[0194] Thus, according to the embodiment of the present disclosure, it is possible to reduce the kTC noise generated by turning off the control signal φSH of the sample and hold switch elements (SH20, SH21), and to cancel the generated kTC noise in a relatively short time.

[0195] In this example, the sample and hold capacitive elements (C20, C21) hold the reset component of HCG (signal for RST), and the sample and hold capacitive element C21 holds the signal component of HCG (signal for SIG).

[0196] Next, by turning on the control signal φSE of the read selection switch element SE26 at t511, the reset component (sample and hold capacitance element C20) is read out and transferred via the amplification transistor SF2, and by turning on the control signal φSE of the read selection switch element SE27 at t512, the signal component (sample and hold capacitance element C21) is read out and transferred via the amplification transistor SF2.

[0197] Here, if there is a variation ΔV1 in the amplifying transistor SF1, ΔV1 is added to the signal level of the sample and hold capacitance element C20 for the signal component and the signal level of the sample and hold capacitance element C21 for the reset component, but the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling the variation.

[0198] Here, if there is a variation ΔV2 in the amplifying transistor SF2, the signal level of the sample and hold capacitance element C20 for the signal component and the signal level of the sample and hold capacitance element C21 for the reset component will be reduced by ΔV2, but as described above, the CDS of the AD conversion circuit subtracts the reset component from the signal component, so the variation is canceled.

[0199] Here, when the sample and hold switch elements SH20 and SH21 are turned OFF, a coupling ΔV3 is superimposed on the sample and hold capacitive element C20 for the signal component and the sample and hold capacitive element C21 for the reset component due to the parasitic capacitance value Cgs and sample and hold capacitance value of each sample and hold switch element, but as described above, the CDS of the AD conversion circuit subtracts the reset component from the signal component, so ΔV3 is canceled.

[0200] The negative feedback operation reduces the noise to 1 / (1+A), but a small amount remains. Because the CDS in the AD conversion circuit subtracts the reset component from the signal component, the total noise is given by the root mean square of the noise generated in the sample and hold capacitance element C20 for the signal component and the sample and hold capacitance element C21 for the reset component, but this is small.

[0201] In the prior art (Patent Document 1), there was no negative feedback circuit, so kTC noise was generated when the sample-hold switch was turned off, which worsened low-illumination noise and narrowed the dynamic range.

[0202] In this embodiment, the sample-and-hold switch is turned off while a negative feedback circuit is applied to the reset component and signal component of the pixel, thereby significantly reducing kTC noise. Furthermore, the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling out circuit variations in the amplifier transistors SF1 and SF2. As a result, low-light noise is reduced and the dynamic range is expanded.

[0203] Furthermore, in the negative feedback circuit 4a in this embodiment, there are only two sample and hold capacitance elements (C20, C21), so the readout time from the pixel circuit 3a to the negative feedback circuit 4a (from time t502 to t510) is short. In other words, the signal retention time in the FD0 section is short, so the circuit is less susceptible to the effects of dark current and parasitic sensitivity in the FD0 section, and both characteristics are good.

[0204] In the sample and hold circuit 10a of the negative feedback circuit 4a in this embodiment, the output terminals of the sample and hold switch elements (SH20, SH21) are connected to the sample and hold capacitive elements (C20, C21) and the readout select switch elements (SE26, SE27). The output terminals of the sample and hold switch elements (SH20, SH21) are connected to the gate nodes of the amplifier transistors SF2 via the readout select switch elements (SE26, SE27). The sample and hold circuit 10a is not limited to this configuration, and may have the following configuration. That is, the sample and hold circuit 10a may have a configuration including an SH unit circuit 10w, similar to the configuration of the sample and hold circuit 10a in FIG. 1B. The SH unit circuit 10w differs from the SH unit circuit 10u in FIG. 1A in that the readout select switch elements (SE26, SE27) are omitted and new connection wiring is added to the input terminals of the sample and hold switch elements (SH20, SH21). The new connection wiring connects the input terminal (this input terminal also serves as the output terminal) of the sample and hold switch element (each of SH20 and SH21) to the node of the gate of the amplifier transistor SF2.

[0205] In other words, the input terminal (and output terminal) of the sample and hold switch element (SH20, SH21) is directly connected to the node connecting the sample and hold switch element SH10 and the switch element SW11 and to the node of the gate of the amplification transistor SF2. Also, the other terminal of the sample and hold switch element (SH20) is connected to the sample and hold capacitive element (C20, C21) as in FIG. 1A. As a result, the sample and hold switch elements (SH20, SH21) in FIG. 1B function as both the sample and hold switch elements (SH20, SH21) in FIG. 1A and the read select switch elements (SE26, SE27).

[0206] In this case, in the operation and timing diagram of the negative feedback circuit 4, the timing of the read selection switch element control signal φSE (SE26, SE27 in this example) can be read as the timing of the sample and hold switch control signal φSH (SH20, SH21 in this example). When reading out the signals of the sample and hold capacitive elements (C20, C21), the sample and hold switch element SH10 and switch element SW11 must be turned OFF. At this time, the parasitic capacitance of the floating wiring is negligible compared to the capacitance of the sample and hold capacitive elements (C20, C21), and does not affect the holding voltage of the sample and hold capacitive elements (C20, C21).

[0207] This configuration has the advantages of reducing the area by reducing the number of elements, and simplifying the control signals by reducing the number of control signals.

[0208] In the sample and hold circuit 10a of the negative feedback circuit 4a in this embodiment, the output terminals of the sample and hold switch elements (SH20, SH21) are connected to the sample and hold capacitor elements (C20, C21) and the read selection switch elements (SE26, SE27), and are connected to the node of the gate of the single amplifying transistor SF2, but the following configuration may also be used: That is, the read selection switch elements (SE26, SE27) may be eliminated, and the output terminal of the sample and hold switch element (SH20) may be connected to the node of the sample and hold capacitor element (C20) and the gate of the amplifying transistor SF2, and the output terminal of the sample and hold switch element (SH21) may be connected to the node of the sample and hold capacitor element (C21) and the gate of the third amplifying transistor SF3.

[0209] Note that, while the vertical signal line 19A was conventionally mounted on the pixel chip and was less susceptible to noise, according to this embodiment, it passes through the analog circuit of the logic chip and may therefore be more susceptible to noise. For this reason, in the logic chip, a power supply or GND wiring layer may be disposed above or below the wiring layer of the vertical signal line 19A to serve as an electromagnetic shield.

[0210] The amplifier transistor SF2 of the negative feedback circuit 4 has device noise (thermal noise, 1 / f noise, RTS noise), etc., and in order to suppress these, it is effective to make the transistor area as large as possible in order to reduce device noise, and it is preferable to make it larger than the amplifier transistor SF2 of the pixel circuit 3.

[0211] The sample and hold capacitor is composed of an MIM capacitor, a MOS capacitor, etc., and is required to have low leakage characteristics and high density capacitance characteristics, and a light-shielding layer is required at the substrate contact portion to suppress parasitic sensitivity.

[0212] [Example of a circuit for a slope signal that serves as a control signal for a switch element] This embodiment is composed of a photodiode PD, a transfer transistor (TG), and a negative feedback circuit 4a, which is composed of sample-and-hold switch elements (SH20, SH21), sample-and-hold capacitance elements (C20, C21), an amplifying transistor SF2, and a feedback amplifier FA, and is further composed of read selection switch elements (SE26, SE27).

[0213] The sample-and-hold switch control signal φSH and, if necessary, the readout selection switch element control signal φSE are supplied from the horizontal scanning line group 16 (VSHn).

[0214] As mentioned above, the control signal φSH of these sample-and-hold switch elements (SH20, SH21) applies a gently sloping signal when the sample-and-hold switches are turned off, which allows the negative feedback circuit 4a to function properly and reduces kTC noise. For example, Figure 7 shows how this slope signal is gradually turned off during the slope period. Figure 8 shows the relationship between this slope period and the kTC noise level. It can be seen that the noise level drops sharply at the beginning of the slope period, but then gradually decreases after a while.

[0215] The issue here is variations in the switching elements due to process, power supply voltage, and temperature. Process variations can be fixed to optimal values ​​during shipping inspection. On the other hand, variations in power supply voltage and temperature fluctuate during actual operation, so they must be corrected during operation.

[0216] A circuit as a countermeasure is shown in Figure 3. The slope signal generator 30 has a built-in DAC circuit, and first generates a slope signal using the clock CK1 and control signal CN5 sent from the timing controller 20. The slope signal is configured so that when reading out noise components in the kTC noise detection region (the OB region in Figure 3), the signal in a predetermined region is read out by the control signal CN5, and the inclination of the slope is determined by the clock CK1.

[0217] 9 is a diagram showing the variation (standard deviation) of kTC noise in a predetermined region. The readout signal in the kTC noise detection region (OB region) is subjected to the normal distribution shown in FIG. 9 for each predetermined region by the noise calculation circuit 86 in the signal processing unit 80, and the σ (standard deviation) of the noise signal is calculated. The most optimal slope setting is then held by the optimal value holding circuit 87.

[0218] Here, the optimum value is the value when the signal readout in the kTC noise detection region is at a minimum value.

[0219] Furthermore, the determination of the slope of the sample and hold switch elements (SH20, SH21) may be performed for a predetermined region or for different regions, and may be performed multiple times.

[0220] The signal processing unit 80 measures the kTC noise while changing the slope of the voltage waveform for each row of pixel circuits belonging to a kTC noise detection area as a predetermined region, calculates the variation σ (standard deviation), and determines the optimal slope of the voltage waveform based on the variation for each row of pixel circuits belonging to the predetermined region.

[0221] [Example of operation of the slope signal that serves as the control signal for the switch element] In this embodiment, the OB region is used to generate the slope signal.

[0222] FIG. 10 is a flowchart showing an example of a process for generating a slope signal of the sample-and-hold switch control signal φSH. <s1>Start scanning the first line of a frame with <s2>The signal in the OB area is read out. <s3>The slope signal is initialized to generate a control signal φSH for each sample-and-hold switch element and a readout selection switch element control signal φSE for each of the predetermined regions. <s4>Then, the standard deviation σ of the kTC noise of each sample-and-hold switch in a predetermined region is calculated. Here, this calculation may be performed for a predetermined region or for different regions. Furthermore, this calculation may be performed multiple times. <s5>In this case, the slope of the slope signal is changed. <s4> <s5>Repeat the above steps. <s6>The gradient of the slope signal at which the noise level σ is at its minimum is selected as the optimum value. <s7>In this case, the signal in the effective region 7 is controlled by the control signals φSH and φSE. Here, the gradient of the slope signal represents the gradient of the amplitude level and the time width.

[0223] Furthermore, by increasing the analog gain during detection, the accuracy of detecting kTC noise increases, enabling stable detection.

[0224] As described above, according to this embodiment, the kTC noise of the sample and hold capacitance element can be reduced, so that low-illumination noise can be improved and the dynamic range can be expanded.

[0225] [Example of a pixel circuit and negative feedback circuit configured using stacked BSI] In particular, as pixel cells become increasingly miniaturized, this can be achieved by providing a sample and hold capacitance element (for example, an MIM capacitance or an MOM capacitance) of the SH circuit 10 of the negative feedback circuit 4 on the wiring layer side of the logic chip, thereby increasing the underlying area of ​​the negative feedback circuit 4.

[0226] 11, 12, and 13 are diagrams showing an example in which the solid-state imaging device according to embodiment 1A is configured as a stacked back-illuminated image sensor. The solid-state imaging device in these figures includes a first semiconductor chip and a second semiconductor chip or multiple semiconductor chips bonded together. The first semiconductor chip and the second semiconductor chip are bonded together on their respective wiring layer sides. In the figures, PD denotes a photodiode PD, C denotes a first sample-and-hold capacitance element, FA denotes a feedback amplifier, and SW denotes a sample-and-hold switch element and a readout selection switch element.

[0227] The first semiconductor chip is referred to as a pixel chip in the figure, and includes a main part of the solid-state imaging device 100 as a back-illuminated CMOS image sensor. The first semiconductor chip includes the photodiodes PD of the pixel circuits 3.

[0228] The second and third semiconductor chips are designated as logic chip A and logic chip B in the figure, and include main logic circuits such as signal processing units 70 and 80. The second semiconductor chip includes a feedback amplifier FA of a negative feedback circuit 4, a sample-and-hold switch element SH, a readout selection switch element SE, and a sample-and-hold capacitor C.

[0229] In such a solid-state imaging device 100, each pixel is mounted on a pixel chip as a stacked BSI type CIS, and a negative feedback circuit 4 corresponding to each pixel is mounted on a logic chip. In other words, a PD can be mounted on each pixel circuit 3 on the pixel chip, and a negative feedback circuit 4 can be configured on each pixel on the logic chip, and negative feedback can be applied, which relatively reduces parasitic resistance and parasitic capacitance, and by increasing speed, high-frequency noise can be reduced, thereby reducing kTC noise. Specifically, the pixel chip and logic chip may be connected at connection point A shown in Figures 1A, 1B, and 4.

[0230] 11 is a diagram showing an example in which the solid-state imaging device according to embodiment 1A is configured as a stacked back-illuminated image sensor. A stacked BSI type CIS is used, and each pixel on a pixel chip is mounted thereon, and a negative feedback circuit 4 corresponding to each pixel circuit 3 is mounted on a logic chip. A photodiode PD is mounted on each pixel on the pixel chip, and a feedback amplifier FA, sample and hold switch element SH, readout selection switch element SE, and sample and hold capacitor element C can be configured on the logic chip for each negative feedback circuit 4, and negative feedback is applied to each pixel, allowing for higher speeds, which in turn reduces high-frequency noise and significantly reduces kTC noise.

[0231] FIG. 12 is a diagram showing an example in which the solid-state imaging device according to embodiment 1A is configured as a stacked back-illuminated image sensor. A stacked BSI CIS is used, with each pixel mounted on a pixel chip, and a negative feedback circuit 4 mounted on a logic chip corresponding to each pixel circuit 3. A photodiode PD and a sample-and-hold capacitor C are mounted on each pixel on the pixel chip, while a feedback amplifier FA, a sample-and-hold switch element SH, and a readout selection switch element SE can be configured on each negative feedback circuit 4 on the logic chip. Negative feedback is applied to each pixel, increasing speed, thereby reducing high-frequency noise and significantly reducing kTC noise. If there are limitations on the mounting area, the sample-and-hold capacitor C may be mounted separately on the pixel chip and the logic chip.

[0232] FIG. 13 shows an example of a solid-state imaging device according to embodiment 1A configured as a stacked back-illuminated image sensor. A stacked BSI CIS is used, with each pixel mounted on a pixel chip, and a negative feedback circuit 4 corresponding to each pixel circuit 3 mounted on a logic chip. A photodiode PD is mounted on each pixel on the pixel chip, and a feedback amplifier FA, sample-and-hold switch element SH, readout selection switch element SE, and sample-and-hold capacitor element C are configured on logic chip A for each negative feedback circuit 4, while a feedback amplifier FA can be configured on logic chip B for each negative feedback circuit 4. Negative feedback is applied to each pixel, increasing speed, thereby reducing high-frequency noise and significantly reducing kTC noise. This configuration is effective for fine pixel cells, where mounting area is limited.

[0233] (Embodiment 1B) In embodiment 1B, a configuration example in which capacitances (CC20, CC21) are provided between the feedback capacitance element CS and the source and drain of the sample and hold switch elements (SH20, SH21) in the first configuration example of Fig. 2 to control the sample and hold switch element SH10 will be described in detail. The following will mainly describe the differences from embodiment 1A.

[0234] In comparison with embodiment 1A, embodiment 1B can reduce kTC noise and achieve high-speed convergence, as will be described later.

[0235] [Configuration and operation example of a negative feedback circuit] At high illuminance, signal charge is stored in the photodiode PD of the pixel circuit, while at low illuminance, kTC noise can be reduced by the negative feedback circuit 4b, achieving low noise. As a result, the dynamic range can be expanded. Generally, when sample-and-hold is performed using the control signal φSH of the sample-and-hold switch elements (SH20, SH21), kTC noise occurs in the sample-and-hold capacitance elements (C20, C21).

[0236] As a countermeasure, the output of the amplification transistor SF1 of the pixel circuit is connected to the positive input terminal of the feedback amplifier FA. The SH circuit 10b is provided with sample and hold capacitance elements (C20, C21), sample and hold switch elements (SH20, SH21), source-drain capacitances (CC20, CC21) of the sample and hold switch elements, and readout selection switch elements (SE26, SE27), which are connected to a feedback line 17B, input to the gate of the amplification transistor SF2, and connected to the negative input terminal of the feedback amplifier FA. The feedback line 17A, which is the output signal of the feedback amplifier FA, is connected to one end of the sample and hold switch element SH10, the other end of which is connected to a feedback capacitance element CS and to the input terminals of the sample and hold switch elements (SH20, SH21), forming negative feedback.

[0237] As a result, a signal with reduced noise that is equal to the pixel signal level is held in the sample and hold capacitor elements (C20, C21).

[0238] The control signal φSH input to the sample and hold switch element SH10 has a sloping voltage waveform that gradually transitions from the ON state to the OFF state. Hereinafter, a signal having a sloping voltage waveform will be referred to as a slope signal.

[0239] Here, the control signal φSH of the sample and hold capacitance element (SH10) in FIG. 7 is a slope signal, the relationship between the slope period and noise level in FIG. 8, and the kTC noise as shown in FIG. 9 are the same as in embodiment 1A.

[0240] Furthermore, the timing of charge accumulation in the photodiode PD in the global shutter system and the rolling shutter system is the same as in embodiment 1A.

[0241] FIG. 6 shows an example of the timing of a signal read operation.

[0242] First, at time t600, the photodiode PD and the charge storage unit FD0 are reset to wait for the start of exposure. Then, at time t601, the shutter is operated and exposure begins. At time t602, the exposure time ends.

[0243] Next, at time t602, RS is turned ON to reset FD0, entering the readout period of the reset component. At time t607, TG is turned ON to transfer the signal charge accumulated in the photodiode to FD0 by the transfer signal (TG), entering the readout period of the signal component.

[0244] Here, the configuration of the negative feedback circuit 4b will be explained with reference to Patent Document 2, pointing out the differences.

[0245] The difference with Patent Document 2 is that while Patent Document 2 has a configuration in which negative feedback is applied only to the reset component (reset transistor) of the pixel signal as the configuration of negative feedback circuit 4b, this embodiment has a configuration in which negative feedback is applied to both the reset component and the signal component, making it possible to reduce kTC noise for both signals. In other words, if the configuration of Patent Document 2 were applied directly to a sample-and-hold circuit, two negative feedback circuits would be required, one for the reset component and one for the signal component, but the advantage of this embodiment is that this can be achieved with a single negative feedback circuit.

[0246] Another difference is that each of the sample and hold switch element SH10, feedback capacitor element CS, and amplifier transistor SF2 is shared by multiple pairs of sample and hold switch elements (SH20, SH21), read selection switch elements (SE26, SE27), and sample and hold capacitor elements (C20, C21), thereby improving layout efficiency. In the negative feedback circuit 4b of this embodiment, only two pairs are shared, but more pairs may be used. The more pairs there are, the greater the layout effect becomes.

[0247] First, at times t603 and t608, the control signal φSH of the sample and hold switch elements (SH20, SH21) and the control signal φSE of the readout selection switch elements (SE26, SE27), and the control signal φSH of the sample and hold switch element (SH10) are turned ON, thereby connecting the sample and hold capacitance elements (C20, C21) to the feedback lines 17A and 17B. As a result, the output signal of the pixel circuit 3 is negatively fed back to the sample and hold capacitance elements (C20, C21).

[0248] Here, the switch element SW1 is always ON, and the switch element SW11 is always OFF.

[0249] In the negative feedback circuit 4b, address selection is performed by the control signal φSH of the sample and hold switch elements (SH20, SH21) and the control signal φSE of the read selection switch elements (SE26, SE27), and the signal is sampled and held in one of the multiple sample and hold capacitance elements (C20, C21) shared by the feedback amplifier FA to reduce noise, and this operation is repeated.

[0250] First, at times t603 and t608, the sample and hold switch element SH10, the sample and hold switch elements (SH20 and SH21), and the read selection switch elements (SE26 and SE27) are turned ON, and the signals of the sample and hold capacitive elements (C20 and C21) are supplied to the negative input terminal of the feedback amplifier FA via the amplification transistor SF2. At this time, the output voltage of the sample and hold capacitive elements (C20 and C21) via the amplification transistor SF2 operates to converge to the output signal via the amplification transistor SF1 of the pixel circuit 3, which is applied to the positive input terminal of the feedback amplifier FA.

[0251] Next, at times t604 and t609, the control signal φSH of the sample and hold switch elements (SH20 and SH21) is turned OFF, generating kTC noise. As a result, kTC noise is added to the voltage of the sample and hold capacitance elements (C20 and C21) after they are turned OFF.

[0252] The negative feedback circuit remains formed while the feedback amplifier FA is operating and its output is connected to the feedback line 17A (until times t605 and t610). As a result, the kTC noise generated by turning off the control signal φSH of the sample-and-hold switch elements (SH20 and SH21) at times t604 and t609 is reduced to 1 / (1+A), where A is the gain of the feedback amplifier FA.

[0253] Furthermore, by turning off the control signal φSE of the read selection switch elements (SE26 and SE27), kTC noise occurs at the node of the gate of the amplifier transistor SF2, but this parasitic capacitance is negligible because it is sufficiently small compared to the sample and hold capacitance elements (C20 and C21). This can be seen from the fact that kTC noise can be expressed in terms of charge as √(kTC)(C).

[0254] For the above reasons, the read selection switch element control signal φSE may be turned off by a rectangular signal, or may be turned off after the sample and hold switch control signal φSH.

[0255] As a result of the above operation, the voltage across the amplifying transistor SF2 just before the control signal φSH of the sample and hold switch elements (SH20, SH21) is turned OFF (just before noise reduction begins) converges to a level approximately equal to the voltage across the amplifying transistor SF2 of the pixel signal applied to the positive input terminal of the feedback amplifier FA.

[0256] Next, a description will be given of the noise reduction operation during the period from when the control signal φSH of the sample and hold switch element SH20 is turned OFF until when the control signal φSH of the sample and hold switch element SH10 is turned OFF (times t604 to t606 and t609 to t611 in FIG. 6).

[0257] Generally, the product G×B of the gain G and bandwidth B of the amplifier that makes up the feedback amplifier FA is constant, so increasing the gain G narrows the bandwidth B (lowering the cutoff frequency). In other words, it takes time for the feedback amplifier FA to converge.

[0258] Conversely, by lowering the gain G, the band B becomes wider (the cut-off frequency becomes higher), which means that the convergence time in the feedback amplifier FA is shortened.

[0259] At times t604 and t609, the gain of the feedback amplifier FA is set low to prioritize high-speed convergence. In other words, since the band B is set wide, noise can be reduced by prioritizing high-speed convergence at the beginning of the noise reduction period.

[0260] Next, at times t605 and t610, noise reduction is prioritized, and the gain of the feedback amplifier FA is set high. This allows the noise level to be reduced even more significantly by the above-mentioned 1 / (1+A). At this time, because band B is set narrow, it takes time for the feedback amplifier FA to converge. However, between t604 and t605 and between t609 and t610, the voltage level of the sample and hold capacitive elements (C20, C21) is already controlled to near the convergence level, so the range of voltage to converge is narrow. Overall, it is possible to suppress an increase in convergence time due to the narrowing of the band.

[0261] Next, the control signal φSH of the sample-and-hold switch element SH10 is turned OFF (times t606 and t611), and kTC noise is generated. The magnitude of the kTC noise applied to the sample-and-hold capacitance elements (C20 and C21) at this time is approximately (C20 / CS) compared to when the sample-and-hold switch element SH10, feedback capacitance element CS, and source-drain capacitance CC20 of the sample-and-hold switch are not present. 1 / 2 × (CC20 / (CC20+C20)) times (where CC20=CC21). In this way, the larger the feedback capacitance element CS, the smaller the generated noise, and the smaller the source-drain capacitance (CC20, CC21) of the sample-hold switch elements (SH20, SH21), the greater the attenuation rate.

[0262] Thus, according to the embodiment of the present disclosure, it is possible to reduce the kTC noise generated by turning off the control signal φSH of the sample and hold switch elements (SH20, SH21), and to cancel the generated kTC noise in a relatively short time.

[0263] By sharing the feedback capacitance element CS and appropriately setting the source-drain capacitance (CC20, CC21) of the sample-and-hold switch, it is possible to sufficiently reduce the kTC noise that occurs when the control signal φSH of the sample-and-hold switch element SH10 is turned off.

[0264] In this example, the sample and hold capacitive elements (C20, C21) hold the reset component of HCG (signal for RST), and the sample and hold capacitive element C21 holds the signal component of HCG (signal for SIG).

[0265] Next, by turning on the control signal φSE of the read selection switch element SE26 at t613, the reset component (sample and hold capacitance element C20) is read out and transferred via the amplification transistor SF2, and by turning on the control signal φSE of the read selection switch element SE27 at t614, the signal component (sample and hold capacitance element C21) is read out and transferred via the amplification transistor SF2.

[0266] As described in embodiment 1A, the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling out the variations.

[0267] (Embodiment 2A) 14 shows embodiment 2A, which will be described in detail below, with a second configuration example in which one stage of storage circuits is provided in the horizontal direction in the first configuration example of FIG. 1A. The following will focus on the differences from embodiment 1A.

[0268] The solid-state imaging device 100 in embodiment 2A will be described from the viewpoint of the difference from embodiment 1A. The configuration example of the solid-state imaging device 100 is the same except for the number of Vn controls in the horizontal scanning line group 15.

[0269] In this embodiment, the charge overflowing from the photodiode PD is stored directly in the second storage capacitor element C2 without passing through the FD portion or near the surface, so that the dark current component can be reduced.

[0270] [Pixel circuit configuration example] Next, a configuration example of the pixel circuit 3b will be described.

[0271] 14 is a diagram showing an example of a main circuit including a pixel circuit 3b and a negative feedback circuit 4c according to embodiment 2A. The pixel circuit 3b in the diagram includes a photodiode (PD), a transfer transistor TG, an overflow element OF, a first storage capacitor C1, a second storage capacitor C2, a first gain control transistor GC1, a second gain control transistor GC2, a charge storage unit FD0, a storage capacitor C0, a charge storage unit FD1, a charge storage unit FD2, a reset transistor RS, an amplification transistor SF1, and a selection transistor SEL_RS.

[0272] Furthermore, the horizontal scanning line group 15 Vn includes a reset control signal φRS, a read control signal φTG, an overflow control line φOF, and a selection control line φSEL_RS.

[0273] The photodiode PD is a photoelectric conversion element such as a photodiode, and performs photoelectric conversion with a predetermined sensitivity, that is, generates an electric charge according to the amount of received light.

[0274] Furthermore, the storage capacitance element C0 connected to the charge storage unit FD0 holds signal charges (e.g., electrons) transferred from the photodiode PD, converts the held signal charges into a voltage, and supplies the converted voltage to the gate of the amplifier transistor SF1. The substantial capacitance of the charge storage unit FD0 includes not only the capacitance of the charge storage unit FD0 itself, but also the gate capacitance of the amplifier transistor SF1, the gate-drain capacitance and gate-source capacitance of the amplifier transistor SF1, and the stray capacitance of the source wiring of the first gain control transistor GC1 when the first gain control transistor GC1 is OFF.

[0275] The transfer transistor TG is a switch transistor that is turned on and off in response to a read control signal φTG. When the read control signal φTG is at a high level, the transfer transistor TG transfers the signal charge photoelectrically converted by the photodiode PD to the charge accumulation unit FD0.

[0276] The first gain control transistor GC1 is a switch transistor that is turned on and off in response to a read control signal φGC1. The second gain control transistor GC2 transfers the signal charge stored in the second storage capacitance element C2 to the charge storage unit FD0 when the read control signal φGC2 is at a high level.

[0277] Even if the overflow gate OF is always OFF in response to the read control signal φOF, the signal charge photoelectrically converted by the photodiode PD is transferred to the second storage capacitor element C2 via the overflow gate OF. Alternatively, the overflow gate OF can serve as an overflow gate and switch transistor that turns ON and OFF in response to the read control signal φOF, and can transfer the signal charge photoelectrically converted by the photodiode PD to the second storage capacitor element C2 via the overflow gate OF when the read control signal φOF is at a high level.

[0278] The second storage capacitor element C2 changes the conversion gain for converting the signal charge in the charge storage unit FD0 into a voltage. That is, when the signal charge is transferred from the photodiode PD to the charge storage unit FD0, turning the second gain control transistor GC2 OFF increases the conversion gain of the charge storage unit FD0, resulting in C0. Conversely, turning the second gain control transistor GC2 ON connects the charge storage units FD0 and FD1, lowering the conversion gain so that more signal charge can be stored, resulting in C0 + C1 + C2.

[0279] The reset transistor RS is a switch transistor that is turned on and off in response to a reset control signal φRS. When the reset control signal φRS is set to a high level, the reset transistor RS can reset the charge storage units FD0, FD1, and FD2.

[0280] The amplifying transistor SF1 forms a source follower in conjunction with a load current source P1 connected to the vertical signal line 19B, and outputs the gate voltage, ie, the voltage of the charge storage unit FD0, to the vertical signal line 19B as an analog pixel signal.

[0281] The selection transistor SEL_RS is a switch transistor that is turned on and off in response to a selection control signal φSEL_RS When the selection control signal φSEL_RS is at a high level, the selection transistor SEL_RS electrically connects the source of the amplification transistor SF1 to the vertical signal line 19B.

[0282] Here, low-illuminance exposure is exposure for low illuminance and the in-pixel gain is set high (HCG), medium-illuminance exposure is exposure for medium illuminance and the in-pixel gain is set medium (MCG), and high-illuminance exposure is exposure for high illuminance and the in-pixel gain is set low (LCG).

[0283] [Example of HCG, MCG, and LCG readout operation] First, the readout operations of HCG (High Conversion Gain), MCG (Middle Conversion Gain), and LCG (Low Conversion Gain) in the solid-state imaging device 100 of FIG. 3 will be described.

[0284] In embodiment 2A, as shown in FIG. 17, first, the reset component of the MCG (C22 of S1) is read from time t102 to t106, the reset component of the HCG (C20 of S0) is read from time t106 to t110, the signal component of the HCG (C21 of S0) is read from time t110 to t114, the signal component of the MCG (C23 of S1) is read from time t114 to t118, the signal component of the LCG (C25 of S2) is read from time t118 to t122, and the reset component of the LCG (C24 of S2) is read from time t122 ​​to t126.

[0285] [HCG readout operation example] Next, the HCG (High Conversion Gain) readout operation will be described for the solid-state imaging device 100 of Fig. 3. The HCG readout operation is an imaging operation in which the first gain control transistor GC1 is turned off and the first storage capacitor element C1 is not used, and the conversion gain of the amplifying transistor SF1 is increased by using only the charge storage unit FD0 to store signal charges. Therefore, the HCG operation is a high-sensitivity imaging operation that is suitable for imaging in low-illumination environments.

[0286] The HCG read operation is the same as that in the embodiment 1A of FIG.

[0287] [MCG read operation example] Next, we will explain the MCG (Middle Conversion Gain) readout operation in the solid-state imaging device 100 of Figure 3. The MCG readout operation is an imaging operation in which the first gain control transistor GC1 is turned on and the first storage capacitor element C1 is used, and both the charge storage unit FD0 and the first storage capacitor element C1 are used to store signal charges, thereby lowering the conversion gain of the amplification transistor SF1. Therefore, the MCG operation is a medium-sensitivity imaging operation that is suitable for imaging in high-illumination environments. The gain for converting signal charges in the charge storage unit FD1 into voltage can be selectively switched between high and low gain depending on whether the first gain control transistor GC1 is turned on or off.

[0288] [LCG read operation example] Next, the LCG (Low Conversion Gain) readout operation of the solid-state imaging device 100 of FIG. 3 will be described. The LCG readout operation is an imaging operation in which the first gain control transistor GC1 and the second gain control transistor GC2 are turned ON and the first storage capacitor element C1 and the second storage capacitor element C2 are used. The charge storage unit FD0, the first storage capacitor element C1, and the second storage capacitor element C2 are all used to store signal charges, and the conversion gain of the amplification transistor SF1 is reduced. Therefore, the LCG operation is a low-sensitivity imaging operation suitable for imaging in high-illumination environments. The gain for converting signal charges in the charge storage unit FD2 into voltage can be selectively switched between high and low gain depending on whether the second gain control transistor GC2 is turned ON or OFF.

[0289] [Configuration and operation example of a negative feedback circuit] At high illuminance, signal charge is stored in the first storage capacitor element C1 and the second storage capacitor element C2 of the pixel circuit, while at low illuminance, kTC noise is reduced by the negative feedback circuit 4b, achieving low noise. As a result, the dynamic range can be expanded. Generally, when sample-and-hold is performed using the control signal φSH of the sample-and-hold switch elements (SH20, SH21, SH22, SH23, SH24, SH25), kTC noise occurs in the sample-and-hold capacitor elements (C20, C21, C22, C23, C24, C25).

[0290] As a countermeasure, the output of the amplification transistor SF1 of the pixel circuit is connected to the positive input terminal of the feedback amplifier FA. The SH circuit 10c is provided with sample and hold capacitance elements (C20, C21, C22, C23, C24, C25), sample and hold switch elements (SH20, SH21, SH22, SH23, SH24, SH25), and readout selection switch elements (SE26, SE27, SE28, SE29, SE30, SE31), which are connected to a feedback line 17B and input to the gate of the amplification transistor SF2. The output of the amplification transistor SF2 is connected to the negative input terminal of the feedback amplifier. The feedback line 17A, which is the feedback output signal, is connected to the input terminal of the sample and hold switch elements (SH20, SH21, SH22, SH23, SH24, SH25) and performs negative feedback.

[0291] As a result, the sample and hold capacitor elements (C20, C21, C22, C23, C24, C25) hold signals that are equal to the pixel signal level and have reduced noise.

[0292] Furthermore, the control signal φSH input to the sample and hold switch elements (SH20, SH21, SH22, SH23, SH24, SH25) has a sloping voltage waveform that gradually transitions from the ON state to the OFF state. Hereinafter, a signal having a sloping voltage waveform will be referred to as a slope signal.

[0293] FIG. 7 is a diagram showing the waveform of a slope signal. As shown in FIG. 7, the sample and hold switch control signal φSH changes gradually as a slope signal. FIG. 8 is a diagram showing the relationship between the slope period and the noise level of the sample and hold capacitive elements. As shown in FIGS. 8 and 9, while negative feedback is applied, the kTC noise gradually approaches such that the input voltage at one end of the feedback amplifier becomes the output voltage of the amplifying transistor SF1 of the pixel circuit 3. As the two potentials become closer, the rate of change of the voltages of the sample and hold capacitive elements (C20, C21, C22, C23, C24, C25) becomes smaller. When the two potentials become equal, the potentials of the sample and hold capacitive elements (C20, C21, C22, C23, C24, C25) are fixed.

[0294] Finally, the operation of the feedback amplifier FA is stopped or the negative feedback loop is interrupted, thereby stopping the negative feedback and completing the operation.

[0295] The sample and hold capacitance element (C20) holds the signal of the RST component of HCG, while the sample and hold capacitance element (C21) holds the signal of the signal component of HCG.

[0296] The sample and hold capacitor (C22) holds the signal of the RST component of MCG, while the sample and hold capacitor (C23) holds the signal of the signal component of MCG.

[0297] The sample and hold capacitor (C24) holds the signal of the RST component of the LCG, while the sample and hold capacitor (C25) holds the signal of the signal component of the LCG.

[0298] The photodiode PD, the first storage capacitor element C1, and the second storage capacitor element C2 are exposed during the exposure period using a global shutter or a rolling shutter. The amounts of charge generated in the photodiode PD, the first storage capacitor element C1, and the second storage capacitor element C2 are assumed to be Q0, Q1, and Q2.

[0299] In the global shutter method, a global reset is performed on all pixels simultaneously, and exposure begins. Since each exposure period is the same, the exposure time is T_Q0 = T_Q1 = T_Q2. Next, the charge from the photodiodes is simultaneously read out to the sample and hold capacitor elements (C20, C21, C22, C23, C24, C25). After that, the signal charge in the sample and hold capacitor elements (C20, C21, C22, C23, C24, C25) is read out in a rolling manner.

[0300] In the rolling shutter method, all pixels are scanned row by row for a selected row, shuttering and then exposure begins. Since each exposure period is the same, the exposure time is T_Q0 = T_Q1 = T_Q2. Next, the charge from the photodiode is read out to the sample and hold capacitor elements (C20, C21, C22, C23, C24, C25) by scanning row by row for the selected row. After that, the signal charge in the sample and hold capacitor elements (C20, C21, C22, C23, C24, C25) is read out in a rolling manner.

[0301] FIG. 17 shows an example of the timing of a signal read operation.

[0302] First, at time t100, the photodiodes PD, FD0, GC1, and GC2 are reset and exposure is started. Then, at time t101, the shutter is operated and exposure begins. At time t102, the exposure time ends.

[0303] Next, at time t102, RS and GC1 are turned ON to reset FD0 and enter the readout period for the reset component of MCG. Next, at time t106, GC1 is turned OFF to enter the readout period for the reset component of HCG. Next, at time t110, TG is turned ON to transfer the signal charge accumulated in the photodiode to FD0 by the transfer signal (TG) and enter the readout period for the signal component (Q0) of HCG. Next, at time t114, TG and GC1 are turned ON to transfer the signal charge overflowing from FD0 to the storage capacitor by GC1. element (C1) and enters the readout period of the signal component (Q0+Q1) of MCG. Next, at time t118, TG, GC1, and GC2 are turned ON to element The charge of C2 is transferred to FD0 by GC2, and the readout period of the signal component (Q0+Q1+Q2) of LCG begins. Next, at time t122, RS, GC1, and GC2 are turned ON, and the readout period of the reset component of LCG begins.

[0304] Then, at times t103, t107, t111, t115, t119, and t123, the control signals of the sample and hold switch elements (SH22, SH20, SH21, SH23, SH25, and SH24) and the readout selection switch elements (SE28, SE26, SE27, SE29, SE31, and SE30) are turned ON, thereby connecting the sample and hold capacitance elements (C22, C20, C21, C23, C25, and C24) to feedback lines 17A and 17B, respectively. As a result, the output signal of pixel circuit 3 is negatively fed back to the sample and hold capacitance elements (C22, C20, C21, C23, C25, and C24).

[0305] Here, the control signal φSH of the sample-and-hold switch element SH10 is always ON, the switch element SW1 is always ON, and the switch element SW11 is always OFF.

[0306] In the negative feedback circuit 4c, address selection is performed by a control signal φSH of the sample and hold switch elements (SH22, SH20, SH21, SH23, SH25, SH24) and a control signal φSE of the read selection switch elements (SE28, SE26, SE27, SE29, SE31, SE30), and the signal is sampled and held in one of the multiple sample and hold capacitance elements (C22, C20, C21, C23, C25, C24) shared by the feedback amplifier FA to reduce noise, and this operation is repeated.

[0307] First, at times t103, t107, t111, t115, t119, and t123, the sample and hold switch elements (SH22, SH20, SH21, SH23, SH25, and SH24) and the readout selection switch elements (SE28, SE26, SE27, SE29, SE31, and SE30) are turned ON, and signals from the sample and hold capacitance elements (C22, C20, C21, C23, C25, and C24) are supplied to the negative input terminal of the feedback amplifier FA via the amplification transistor SF2. At this time, the output voltages from the sample and hold capacitance elements (C22, C20, C21, C23, C25, and C24) via the amplification transistor SF2 operate to converge to the output signal from the amplification transistor SF1 of the pixel circuit 3, which is applied to the positive input terminal of the feedback amplifier FA.

[0308] Next, at times t104, t108, t112, t116, t120, and t124, the control signal φSH of the sample-and-hold switch elements (SH22, SH20, SH21, SH23, SH25, and SH24) and the control signal φSE of the read select switch elements (SE28, SE26, SE27, SE29, SE31, and SE30) are turned OFF, generating kTC noise. As a result, kTC noise is added to the voltages of the sample-and-hold capacitance elements (C22, C20, C21, C23, C25, and C24) after reset.

[0309] While the feedback amplifier FA is operating and its output is connected to the feedback line 17A, the negative feedback circuit remains formed (until times t105, t109, t113, t117, t121, and t125). Therefore, when the control signal φSH for the sample-and-hold switch elements (SH22, SH20, SH21, SH23, SH25, and SH24) is turned OFF at times t104, t108, t112, t116, t120, and t124, the kTC noise generated is reduced to 1 / (1+A), where A is the gain of the feedback amplifier FA.

[0310] By turning off the gate voltage of the read selection switch elements (SE28, SE26, SE27, SE29, SE31, and SE30), kTC noise occurs at the gate node of the amplifier transistor SF2, but this parasitic capacitance is sufficiently small compared to the sample and hold capacitance elements (C22, C20, C21, C23, C25, and C24), so it is at a negligible level. This can be seen from the fact that kTC noise can be expressed in terms of charge as √(kTC)(C).

[0311] For the reasons stated above, the read selection switch element control signal φSE may be turned off by a slope signal or a rectangular signal in conjunction with the corresponding sample and hold switch control signal φSH, or may be turned off after the sample and hold switch control signal φSH.

[0312] The feedback amplifier FA may be in a constantly operating state during the period when the pixel circuit 3b is read out to the sample and hold circuit 10c (from time t102 to t126).

[0313] As a result of the above operation, the voltage across the amplifying transistor SF2 just before the control signal φSH of the sample and hold switch elements (SH22, SH20, SH21, SH23, SH25, SH24) is turned OFF (just before noise reduction begins) converges to a level approximately equal to the voltage across the amplifying transistor SF2 of the pixel signal applied to the positive input terminal of the feedback amplifier FA.

[0314] Generally, the product G×B of the gain G and bandwidth B of the amplifier that makes up the feedback amplifier FA is constant, so increasing the gain G narrows the bandwidth B (lowering the cutoff frequency). In other words, it takes time for the feedback amplifier FA to converge.

[0315] Conversely, by lowering the gain G, the band B becomes wider (the cut-off frequency becomes higher), which means that the convergence time in the feedback amplifier FA is shortened.

[0316] For this reason, it is necessary to determine the gain of the feedback amplifier FA taking into consideration the noise level and convergence time.

[0317] Thus, according to the embodiment of the present disclosure, it is possible to reduce the kTC noise generated by turning off the control signal φSH of the sample and hold switch elements (SH22, SH20, SH21, SH23, SH25, SH24), and also to cancel the generated kTC noise in a relatively short time.

[0318] Next, by turning on the control signal φSE of the read selection switch element SE26 at t127, the reset component of the HCG (sample and hold capacitance element C20) is read out and transferred via the amplification transistor SF2, and by turning on the control signal φSE of the read selection switch element SE27 at t128, the signal component of the HCG (sample and hold capacitance element C21) is read out and transferred via the amplification transistor SF2.

[0319] Next, by turning on the control signal φSE of the read selection switch element SE28 at t129, the reset component of the MCG (sample and hold capacitance element C22) is read and transferred via the amplification transistor SF2, and by turning on the control signal φSE of the read selection switch element SE29 at t130, the signal component of the MCG (sample and hold capacitance element C23) is read and transferred via the amplification transistor SF2.

[0320] Next, by turning on the control signal φSE of the read selection switch element SE30 at t131, the reset component of the LCG (sample and hold capacitance element C24) is read out and transferred via the amplification transistor SF2, and by turning on the control signal φSE of the read selection switch element SE31 at t132, the signal component of the LCG (sample and hold capacitance element C25) is read out and transferred via the amplification transistor SF2.

[0321] Here, regarding the readout order of signals from the sample and hold capacitive elements, there is no particular rule for the readout order of each gain, and any readout order is acceptable. Preferably, since CDS is performed, the order is reset component and signal component for each gain.

[0322] As described in embodiment 1A, the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling out the variations.

[0323] [Expanded dynamic range] A feature of this embodiment is that the exposure control of the three frames of high-illuminance exposure, medium-illuminance exposure, and high-illuminance exposure that combine WDR is performed using the global shutter method and the rolling shutter method, with exposure occurring at exactly the same timing and using exactly the same pixels, eliminating false colors, coloring, and blurring.

[0324] For pixel signals in frames in low-light areas (low-light exposure), the in-pixel gain is set to high (HCG), for pixel signals in frames in medium-light areas (medium-light exposure), the in-pixel gain is set to medium (MCG), and for pixel signals in frames in high-light areas (high-light exposure), the in-pixel gain is set to low (LCG), thereby improving noise in low light and expanding the dynamic range in high light.

[0325] Figure 19 shows an overview of the WDR in-pixel synthesis method. Figure 16 is a diagram showing an example of the configuration of a signal processing unit that performs WDR synthesis using three frames. For WDR, low-illuminance exposure is set by HCG to produce a signal charge of Q0, medium-illuminance exposure is set by MCG to produce a signal charge of (Q0+Q1), and high-illuminance exposure is set by LCG to produce a signal charge of (Q0+Q1+Q2).

[0326] The horizontal axes of (1), (2), (3), and (4) in Figure 16 represent the product of illuminance and exposure time, illuminance for a fixed period of time, or exposure time at a fixed illuminance. On the vertical axes, (1) represents the charge accumulation level, (2) represents the signal potential of the pixel section, (3) represents the value after AD conversion, and (4) represents the SN level.

[0327] The details of the WDR synthesis circuit 76 constituting the signal processing unit 70 are shown in Figures 16(3) and 16(4). The "illuminance vs. exposure time" at the boundary between low-illuminance exposure and medium-illuminance exposure corresponds to the charge Q0' just before the charge Q0 saturates in (1) and corresponds to the signal potential FDH of the pixel unit in (2). The "illuminance vs. exposure time" at the boundary between medium-illuminance exposure and high-illuminance exposure corresponds to the charge Q0+Q1' just before the charge Q0+Q1 saturates in (1) and corresponds to the signal potential FDM of the pixel unit in (2). Furthermore, the "illuminance vs. exposure time" at the maximum high-illuminance exposure corresponds to the charge Q0+Q1+Q2' just before the charge Q0+Q1+Q2 saturates in (1) and corresponds to the signal potential FDL of the pixel unit in (2).

[0328] In this way, the pixel signal of the first low-illuminance frame (low-illuminance exposure), the pixel signal of the second medium-illuminance frame (medium-illuminance exposure), and the pixel signal of the third high-illuminance frame (high-illuminance exposure) are combined to realize a wide dynamic range function (WDR function), i.e., the dynamic range is expanded.

[0329] In this way, according to this embodiment, it is possible to improve both the dynamic range and the SN ratio while reducing the reset noise of the storage capacitor element.

[0330] Conventionally, there was no negative feedback circuit, so kTC noise was generated when the sample-hold switch was turned off, which worsened low-light noise and narrowed the dynamic range.

[0331] In this embodiment, the sample-and-hold switch is turned off while a negative feedback circuit is applied to the reset component and signal component of the pixel, thereby significantly reducing kTC noise. Furthermore, the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling out variations in the amplifier transistors SF1 and SF2. As a result, low-light noise is reduced and the dynamic range can be expanded.

[0332] (Embodiment 2B) Fig. 15 shows embodiment 2B, which will be described in detail below, in which the third configuration example has two vertical rows of storage circuits, as opposed to the second configuration example of Fig. 14 where the storage circuits are arranged horizontally. The following will focus on the differences from embodiment 2A.

[0333] The solid-state imaging device 100 in embodiment 2A will be described from the viewpoint of the differences from embodiment 2A. The configuration example of the solid-state imaging device 100 is the same except for the number of horizontal scanning line groups 15 to be controlled.

[0334] [Pixel circuit configuration example] Next, a configuration example of the pixel circuit 3c will be described.

[0335] 15 is a diagram showing an example of a main circuit including a pixel circuit 3c and a negative feedback circuit 4c according to embodiment 2B. The pixel circuit 3c in the diagram includes a photodiode (PD), a transfer transistor TG, a first storage capacitor C1, a second storage capacitor C2, a first gain control transistor GC1, a second gain control transistor GC2, a charge storage unit FD0, a storage capacitor C0, a charge storage unit FD1, a charge storage unit FD2, a reset transistor RS, an amplification transistor SF1, and a selection transistor SEL_RS.

[0336] Furthermore, the horizontal scanning line group 15 Vn includes a reset control signal φRS, a read control signal φTG, an overflow control line φOF, and a selection control line φSEL_RS.

[0337] The photodiode PD is a photoelectric conversion element that converts incident light into signal charge. The signal charge that overflows the photodiode PD during exposure is transferred to and held in the first storage capacitor element C1, as indicated by the dotted arrow D in the figure. Furthermore, the signal charge that overflows from the first storage capacitor element C1 is transferred to and held in the second storage capacitor element C2.

[0338] Furthermore, the storage capacitance element C0 connected to the charge storage unit FD0 holds signal charges (e.g., electrons) transferred from the photodiode PD, converts the held signal charges into a voltage, and supplies the converted voltage to the gate of the amplifier transistor SF1. The substantial capacitance of the charge storage unit FD0 includes not only the capacitance of the charge storage unit FD0 itself, but also the gate capacitance of the amplifier transistor SF1, the gate-drain capacitance and gate-source capacitance of the amplifier transistor SF1, and the stray capacitance of the source wiring of the first gain control transistor GC1 when the first gain control transistor GC1 is OFF.

[0339] The transfer transistor TG is a switch transistor that is turned on and off in response to a read control signal φTG. When the read control signal φTG is at a high level, the transfer transistor TG transfers the signal charge photoelectrically converted by the photodiode PD to the charge accumulation unit FD0.

[0340] The first gain control transistor GC1 transfers the signal charge stored in the first storage capacitor element C1 to the charge storage unit FD0 when the read control signal φGC1 is at a high level, and the second gain control transistor GC2 transfers the signal charge stored in the second storage capacitor element C2 to the charge storage unit FD0 when the read control signal φGC2 is at a high level.

[0341] When the signal charge photoelectrically converted by the photodiode PD overflows, the signal charge is transferred to the first storage capacitor element C1 by adjusting the control voltage φGC1 of the first gain control transistor GC1, or when the signal charge exceeds a preset potential.

[0342] When the signal charge photoelectrically converted by the photodiode PD overflows, the signal charge is transferred to the second storage capacitor element C2 by adjusting the control voltage φGC2 of the second gain control transistor GC2, or when the signal charge exceeds a preset potential.

[0343] Furthermore, the first storage capacitor element C1 and the second storage capacitor element C2 change the conversion gain for converting the signal charge in the charge storage unit FD0 into a voltage. That is, when transferring signal charge from the photodiode PD to the charge storage unit FD0, turning the second gain control transistor GC2 OFF increases the conversion gain of the charge storage unit FD0, resulting in C0. Turning the first gain control transistor GC1 ON connects the charge storage units FD0 and FD1, lowering the conversion gain to C0+C1 so that more signal charge can be stored. Furthermore, turning the second gain control transistor GC2 ON connects the charge storage units FD0, FD1, and FD2, lowering the conversion gain to C0+C1+C2 so that more signal charge can be stored.

[0344] The reset transistor RS is a switch transistor that is turned on and off in response to a reset control signal φRS. When the reset control signal φRS is at a high level, the reset transistor RS resets the charge storage units FD0, FD1, and FD2.

[0345] The amplifying transistor SF1 forms a source follower in conjunction with a load current source P1 connected to the vertical signal line 19B, and outputs the gate voltage, ie, the voltage of the charge storage unit FD0, to the vertical signal line 19B as an analog pixel signal.

[0346] The selection transistor SEL_RS is a switch transistor that is turned on and off in response to a selection control signal φSEL_RS When the selection control signal φSEL_RS is at a high level, the selection transistor SEL_RS electrically connects the source of the amplification transistor SF1 to the vertical signal line 19B.

[0347] [Example of HCG, MCG, and LCG readout operation] First, the readout operations of HCG (High Conversion Gain), MCG (Middle Conversion Gain), and LCG (Low Conversion Gain) in the solid-state imaging device 100 of FIG. 3 will be described.

[0348] In embodiment 2B, as shown in FIG. 18, first, the HCG reset component (C20) is read from time t902 to t906, the HCG signal component (C21) is read from time t906 to t910, the MCG signal component (C23) is read from time t910 to t914, the LCG signal component (C25) is read from time t914 to t918, the LCG reset component (C24) is read from time t918 to t922, and the MCG reset component (C22) is read from time t922 to t926.

[0349] [HCG readout operation example] Next, the HCG (High Conversion Gain) readout operation will be described for the solid-state imaging device 100 of Fig. 3. The HCG readout operation is an imaging operation in which the first gain control transistor GC1 is turned off and the first storage capacitor element C1 is not used, and the conversion gain of the amplifying transistor SF1 is increased by using only the charge storage unit FD0 to store signal charges. Therefore, the HCG operation is a high-sensitivity imaging operation that is suitable for imaging in low-illumination environments.

[0350] The HCG read operation is the same as that in the embodiments 1A and 2A of FIG.

[0351] [MCG read operation example] Next, we will explain the MCG (Middle Conversion Gain) readout operation in the solid-state imaging device 100 of Figure 3. The MCG readout operation is an imaging operation in which the first gain control transistor GC1 is turned on and the first storage capacitor element C1 is used, and both the charge storage unit FD0 and the first storage capacitor element C1 are used to store signal charges, thereby lowering the conversion gain of the amplification transistor SF1. Therefore, the MCG operation is a medium-sensitivity imaging operation that is suitable for imaging in high-illumination environments. The gain for converting signal charges in the charge storage unit FD1 into voltage can be selectively switched between high and low gain depending on whether the first gain control transistor GC1 is turned on or off.

[0352] [LCG read operation example] Next, the LCG (Low Conversion Gain) readout operation in the solid-state imaging device 100 of FIG. 3 will be described. The LCG readout operation is an imaging operation in which the second gain control transistor GC2 is turned ON and the second storage capacitor element C2 is used. The charge storage unit FD0, the first storage capacitor element C1, and the second storage capacitor element C2 are all used to store signal charges, and the conversion gain of the amplification transistor SF1 is reduced. Therefore, the LCG operation is a low-sensitivity imaging operation that is suitable for imaging in high-illumination environments. The gain for converting signal charges into voltage in the charge storage unit FD2 can be selectively switched between high and low gain depending on whether the second gain control transistor GC2 is ON or OFF.

[0353] [Configuration and operation example of a negative feedback circuit] First, the configuration of the negative feedback circuit 4 is the same in the embodiments 2A and 2B, and therefore a description thereof will be omitted.

[0354] First, as in the embodiment 2A, the sample and hold capacitive element (C20) holds a signal of the RST component of HCG, while the sample and hold capacitive element (C21) holds a signal of the signal component of HCG.

[0355] The sample and hold capacitor (C22) holds the signal of the RST component of MCG, while the sample and hold capacitor (C23) holds the signal of the signal component of MCG.

[0356] The sample and hold capacitor (C24) holds the signal of the RST component of the LCG, while the sample and hold capacitor (C25) holds the signal of the signal component of the LCG.

[0357] The global shutter exposure method and the rolling shutter exposure method are also omitted since they are the same as those in embodiment 2A.

[0358] FIG. 18 shows an example of the timing of a read operation.

[0359] First, at time t900, the photodiodes PD, FD0, GC1, and GC2 are reset and exposure is started. Then, at time t901, the shutter is operated and exposure begins. At time t902, the exposure time ends.

[0360] Next, at time t902, the readout period for the HCG reset component begins. Next, at time t906, TG is turned on, and the signal charge accumulated in the photodiode is transferred to FD0 by the transfer signal (TG), entering the readout period for the HCG signal component (Q0). Next, at time t910, TG and GC1 are turned on, and the signal charge overflowing from FD0 is transferred to the first storage capacitor element C1 by GC1, entering the readout period for the MCG signal component (Q0+Q1). Next, at time t914, TG, GC1, and GC2 are turned on, and the charge in the second storage capacitor element C2 is transferred to FD0 by GC2, entering the readout period for the LCG signal component (Q0+Q1+Q2). Next, at time t918, RS, GC1, and GC2 are turned on, entering the readout period for the LCG reset component. Next, at time t922, RS and GC1 are turned on, entering the readout period for the MCG reset component.

[0361] Then, at times t903, t907, t911, t915, t919, and t923, the control signal φSH of the sample and hold switch elements (SH20, SH21, SH23, SH25, SH24, and SH22) and the control signal φSE of the readout selection switch elements (SE26, SE27, SE29, SE31, SE30, and SE28) are turned ON, thereby connecting the sample and hold capacitance elements (C20, C21, C23, C25, C24, and C22) to the feedback line 17A and the feedback line 17B. As a result, the output signal of the pixel circuit 3 is negatively fed back to the sample and hold capacitance elements (C20, C21, C23, C25, C24, and C22).

[0362] Here, the control signal φSH of the sample-and-hold switch element SH10 is always ON, the switch element SW1 is always ON, and the switch element SW11 is always OFF.

[0363] In the negative feedback circuit 4c, address selection is performed by a control signal φSH of the sample and hold switch elements (SH20, SH21, SH23, SH25, SH24, SH22) and a control signal φSE of the read selection switch elements (SE26, SE27, SE29, SE31, SE30, SE28), and noise is reduced by sampling and holding the signal in one of the multiple sample and hold capacitance elements (C20, C21, C23, C25, C24, C22) shared by the feedback amplifier FA.

[0364] First, at times t903, t907, t911, t915, t919, and t923, the sample and hold switch elements (SH20, SH21, SH23, SH25, SH24, and SH22) and the read selection switch elements (SE26, SE27, SE29, SE31, SE30, and SE28) are turned ON, and signals from the sample and hold capacitive elements (C20, C21, C23, C25, C24, and C22) are supplied to the negative input terminal of the feedback amplifier FA via the amplification transistor SF2. At this time, the output voltages from the sample and hold capacitive elements (C20, C21, C23, C25, C24, and C22) via the amplification transistor SF2 converge to the output signal from the pixel circuit 3 via the amplification transistor SF1, which is applied to the positive input terminal of the feedback amplifier FA.

[0365] Next, at times t904, t908, t912, t916, t920, and t924, the control signal φSH of the sample-and-hold switch elements (SH20, SH21, SH23, SH25, SH24, and SH22) and the control signal φSE of the read select switch elements (SE26, SE27, SE29, SE31, SE30, and SE28) are turned OFF, generating kTC noise. As a result, kTC noise is added to the voltages of the sample-and-hold capacitance elements (C20, C21, C23, C25, C24, and C22).

[0366] While the feedback amplifier FA is operating and its output is connected to the feedback line 17A, the state in which the negative feedback circuit is formed continues (until times t905, t909, t913, t917, t921, and t925). Therefore, when the gain of the feedback amplifier FA is A, the kTC noise generated by turning off the control signal φSH of the sample-and-hold switch elements (SH20, SH21, SH23, SH25, SH24, and SH22) at times t904, t908, t912, t916, t920, and t924 is reduced to a magnitude of 1 / (1+A).

[0367] Furthermore, by turning off the control signal φSE of the read selection switch elements (SE26, SE27, SE29, SE31, SE30, and SE28), kTC noise occurs at the node of the gate of the amplifying transistor SF2, but this parasitic capacitance is sufficiently small compared to the sample and hold capacitance elements (C20, C21, C23, C25, C24, and C22), so it is at a negligible level. This can be seen from the fact that kTC noise can be expressed in terms of charge as √(kTC)(C).

[0368] For the reasons stated above, the read selection switch element control signal φSE may be turned off by a slope signal or a rectangular signal in association with the corresponding sample and hold switch control signal φSH, or may be turned off after the sample and hold switch control signal φSH.

[0369] The feedback amplifier FA may be in a constantly operating state during the period when the pixel circuit 3c is read out to the sample and hold circuit 10c (from time t902 to t926).

[0370] As a result of the above operation, the voltage across the amplifying transistor SF2 just before the control signal φSH of the sample and hold switch elements (SH20, SH21, SH23, SH25, SH24, SH22) is turned OFF (just before noise reduction begins) converges to a level approximately equal to the voltage across the amplifying transistor SF2 of the pixel signal applied to the positive input terminal of the feedback amplifier FA.

[0371] Generally, the product G×B of the gain G and bandwidth B of the amplifier that makes up the feedback amplifier FA is constant, so increasing the gain G narrows the bandwidth B (lowering the cutoff frequency). In other words, it takes time for the feedback amplifier FA to converge.

[0372] Conversely, by lowering the gain G, the band B becomes wider (the cut-off frequency becomes higher), which means that the convergence time in the feedback amplifier FA is shortened.

[0373] For this reason, it is necessary to determine the gain of the feedback amplifier FA taking into consideration the noise level and convergence time.

[0374] Thus, according to the embodiment of the present disclosure, it is possible to reduce the kTC noise generated by turning off the control signal φSH of the sample and hold switch elements (SH20, SH21, SH23, SH25, SH24, SH22), and also to cancel the generated kTC noise in a relatively short time.

[0375] Next, by turning on the control signal φSE of the read selection switch element SE26 at t927, the reset component of the HCG (sample and hold capacitance element C20) is read out and transferred via the amplification transistor SF2, and by turning on the control signal φSE of the read selection switch element SE27 at t928, the signal component of the HCG (sample and hold capacitance element C21) is read out and transferred via the amplification transistor SF2.

[0376] Next, by turning on the control signal φSE of the read selection switch element SE28 at t929, the reset component of the MCG (sample and hold capacitance element C22) is read and transferred via the amplification transistor SF2, and by turning on the control signal φSE of the read selection switch element SE29 at t930, the signal component of the MCG (sample and hold capacitance element C23) is read and transferred via the amplification transistor SF2.

[0377] Next, by turning on the control signal φSE of the read selection switch element SE30 at t931, the reset component of the LCG (sample and hold capacitance element C24) is read out and transferred via the amplification transistor SF2, and by turning on the control signal φSE of the read selection switch element SE31 at t932, the signal component of the LCG (sample and hold capacitance element C25) is read out and transferred via the amplification transistor SF2.

[0378] As described in embodiment 1A, the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling out the variations.

[0379] [Expanded dynamic range] A feature of this embodiment is that the three frames of high-illuminance exposure, medium-illuminance exposure, and high-illuminance exposure that combine WDR are exposed at exactly the same timing and use exactly the same pixels, so false colors, coloring, and blurring do not occur.

[0380] The details of the dynamic range expansion are the same as those in embodiment 2A, and therefore will be omitted.

[0381] Conventionally, there was no negative feedback circuit, so kTC noise was generated when the sample-hold switch was turned off, which worsened low-light noise and narrowed the dynamic range.

[0382] In this embodiment, the sample-and-hold switch is turned off while a negative feedback circuit is applied to the reset component and signal component of the pixel, thereby significantly reducing kTC noise. Furthermore, the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling out variations in the amplifier transistors SF1 and SF2. As a result, low-light noise is reduced and the dynamic range can be expanded.

[0383] In the present embodiment, the pixel circuits 3b and 3c are described as comprising one photodiode PD element, three storage capacitance elements, and three charge storage elements, and as generating three signals, HCG, MCG, and LCG; however, if more elements are provided for each element, it is also possible to generate multiple signals of three or more signals and expand the dynamic range.

[0384] (Embodiment 3) [Configuration example of solid-state imaging device 100] Fig. 3 is a block diagram showing a configuration example of a solid-state imaging device 100 according to embodiment 3. Fig. 20 shows a configuration example of a solid-state imaging device 100 including a plurality of pixel circuits 3 constituting a pixel array section 1, SH circuits 10 each corresponding to each pixel circuit 3, an amplifier transistor SF2, an amplifier transistor SF3, and a negative feedback circuit 4d shared by multiple pixels and configured with a feedback amplifier FA.

[0385] Any of 3a, 3b, and 3c may be applied as the pixel circuit 3. Here, the case where the pixel circuit 3b is applied will be described.

[0386] Any of the SH circuit 10a, SH circuit 10b, and SH circuit 10c may be applied as the sample-and-hold circuit 10. Here, the case where the sample-and-hold circuit 10c is applied will be described.

[0387] That is, a case where embodiment 2A is applied to embodiment 3 will be described.

[0388] In the third embodiment, pixel circuits 3(b) are arranged in an array of s rows and t columns, and SH circuits 10(c) are also arranged in an array of s rows and t columns in a one-to-one correspondence. For example, in FIG. 20, they are arranged in 4 rows and 2 columns. In a negative feedback circuit 4d, a plurality of sample-and-hold circuits 10(c) arranged in a matrix are also arranged in an array of 4 rows and 2 columns. Here, the magnitude relationship between s and t in the s rows and t columns is not particularly specified, and any magnitude relationship is possible.

[0389] For example, the output signal of pixel A in the Fth column is connected to the positive input terminal of feedback amplifier FA via switch element SW1. Feedback line 17A of feedback amplifier FA is connected to feedback line 17B via sample and hold switch element SH10(c) and sample and hold circuit 10(c) corresponding to pixel A in the Fth column, and is connected to the negative input terminal of feedback amplifier FA via amplifier transistor SF2 and switch element SW5. This negative feedback circuit 4d allows the signal of pixel A to be held in the sample and hold capacitive element corresponding to pixel A with noise reduced. The same applies to the pixel signals in the other Fth columns.

[0390] Here, the switch element SW1 is always ON, and the switch element SW11 is always OFF.

[0391] For the Fth column, in the negative feedback circuit 4d, address selection is performed by the control signal φSH of the sample and hold switch elements (SH22, SH20, SH21, SH23, SH25, SH24 in time order in Figure 17) and the control signal φSE of the read selection switch elements (SE28, SE26, SE27, SE29, SE31, SE30 in time order in the same figure), and the signal is sampled and held in one of the multiple sample and hold capacitance elements (C22, C20, C21, C23, C25, C24 in time order in the same figure) shared by the feedback amplifier FA to reduce noise, and this operation is repeated.

[0392] For example, the output signal of pixel E of column F+1 is connected to the positive input terminal of feedback amplifier FA via switch element SW2. Feedback line 17A of feedback amplifier FA is connected to feedback line 17B via sample and hold switch element SH10(c) and SH circuit 10(c) corresponding to pixel E of column F+1, and is connected to the negative input terminal of feedback amplifier FA via amplifier transistor SF3 and switch element SW6. This negative feedback circuit allows the signal of pixel E to be held in the sample and hold capacitor element corresponding to pixel E with reduced noise. The same applies to the pixel signals of the other columns F+1.

[0393] Here, the switch element SW2 is always ON, and the switch element SW12 is always OFF.

[0394] For the F+1th column, in the negative feedback circuit 4d, address selection is performed by the control signal φSH of the sample and hold switch elements (SH22, SH20, SH21, SH23, SH25, SH24 in time order in FIG. 17) and the control signal φSE of the read selection switch elements (SE28, SE26, SE27, SE29, SE31, SE30 in time order in the same figure), and the signal is sampled and held in one of the multiple sample and hold capacitance elements (C22, C20, C21, C23, C25, C24 in time order in the same figure) shared by the feedback amplifier FA to reduce noise, and this operation is repeated.

[0395] If negative feedback is not required and higher speed is prioritized over noise reduction, the switch elements SW1 and SW2 can be turned OFF and the switch elements SW11 and SW12 can be turned ON to directly sample and hold pixel signals in the sample and hold capacitor elements (C22, C20, C21, C23, C25, C24). However, since no negative feedback is applied, kTC noise is superimposed without being reduced. For example, this is an effective way to reduce low-illumination noise by applying negative feedback only to the HCG and achieve higher speed without applying negative feedback to the MCG and LCG.

[0396] There is no particular rule as to the order in which signals are read out from the multiple pixel circuits 3(b) constituting the pixel array unit 1 to the corresponding sample and hold circuits SH10(c), and the signals may be read out regularly or randomly. This read out order is given by the sample and hold switch control signal φSH and the read selection switch element control signal φSE, and although in the figure the signals are supplied from the vertical scanning circuit 14 in the horizontal direction to the pixel array unit 1, they may also be supplied from the vertical direction.

[0397] The number of vertical signal lines 19A in the negative feedback circuit 4d shared by multiple pixels, which includes a plurality of pixel circuits 3(b) constituting the pixel array section 1 and sample-and-hold circuits 10(c) corresponding one-to-one to each pixel circuit 3(b), is the same as the number of vertical signal lines 19B in the pixel circuits. Here, the amplifying transistors connected to the plurality of SH circuits 10(c) are provided for each column, respectively, with amplifying transistors SF2 and SF3. However, if more amplifying transistors and vertical signal lines 19A could be provided, more pixels could be read out simultaneously from the negative feedback circuit 4d, thereby enabling faster readout.

[0398] The slope signal generation unit 30 determines the slope of each sample and hold switch control signal φSH (SH20, SH21, SH22, SH23, SH24, SH25) that constitutes the sample and hold circuit 10(c) for the multiple SH circuits 10(c) that constitute the multi-pixel shared negative feedback circuit 4d, and generates an optimal slope signal to reduce the kTC noise of the sample and hold capacitance elements (C20, C21, C22, C23, C24, C25).

[0399] Furthermore, the vertical scanning circuit 14 scans, row by row, read selection switch control signals φSE (SE26, SE27, SE28, SE29, SE30, SE31) constituting the sample and hold circuit 10, using horizontal scanning line groups (also referred to as row control line groups) 15 provided for each row of the multi-pixel shared negative feedback circuit 4d. This allows pixel signals belonging to the selected row held in the sample and hold circuit 10 to be output sequentially to vertical signal lines 19.

[0400] Here, in the rolling shutter method and the global shutter method, output from OUT(GS) is possible.

[0401] It should be noted that the current sources P1 and P2 can be turned on only when the pixel signal of the pixel circuit 3 is read out to the negative feedback circuit 4d shared by multiple pixels, thereby reducing power consumption.

[0402] The column processing unit 26 includes a column AD circuit 25 provided for each column. Each column AD circuit 25 performs AD conversion on the pixel signals from the vertical signal line 19.

[0403] 21 shows the connection of the pixel chip and logic chip in the multi-pixel shared negative feedback circuit 4d (4 rows and 2 columns) in FIG. 20 as an example of an s-row, t-column multi-pixel shared negative feedback circuit 4d. Pixel circuits 3(b) are also connected to the multi-pixel shared negative feedback circuit 4d in units of 4 rows and 2 columns, and signals are input thereto. Output signals from the Fth and F+1th columns of the multi-pixel shared negative feedback circuit 4d (4 rows and 2 columns) correspond to the Fth and F+1th columns of the pixel circuit 3(b), and are output to the respective vertical signal lines 19A and input to the column AD circuit 25. The number of vertical signal lines 19A may be greater than the number of vertical signal lines in the pixel array to increase the number of pixel signal readout signals and speed up the operation.

[0404] In FIG. 21, the vertical signal line 19B is disconnected and connected to the pixel circuit 3(b) for each negative feedback circuit 4d.

[0405] [Configuration and operation example of negative feedback circuit (low noise)] At high illuminance, signal charge is stored in the first storage capacitor element C1 and the second storage capacitor element C2 of the pixel circuit, while at low illuminance, kTC noise can be reduced by the negative feedback circuit 4d shared by multiple pixels, achieving low noise. As a result, the dynamic range can be expanded. Generally, when sample and hold is performed using the control signal φSH of the sample and hold switch elements (SH20, SH21, SH22, SH23, SH24, SH25), kTC noise occurs in the sample and hold capacitor elements (C20, C21, C22, C23, C24, C25).

[0406] The countermeasures are the same as those in embodiment 2A, and the differences will be explained here.

[0407] The global shutter exposure method and the rolling shutter exposure method are also omitted since they are the same as those in embodiment 2A.

[0408] The differences from embodiment 2A will be explained.

[0409] In the embodiment 2A, there is one pixel circuit 3b (or one pixel circuit 3c in the embodiment 2B) and one sample-and-hold circuit 10c in a one-to-one correspondence with one feedback amplifier FA.

[0410] On the other hand, in the third embodiment, there are multiple pixel circuits 3b or pixel circuits 3b and sample-and-hold circuits 10c in the negative feedback circuit 4d, each of which corresponds one-to-one to one feedback amplifier FA, and these are shared by the feedback amplifier FA.

[0411] For this reason, a signal corresponding to each gain of the pixel circuit 3 (for example, the pixel circuit 3b) must be sent multiple times to each sample-and-hold circuit 10c shared by the feedback amplifier FA.

[0412] If the pixel circuit 3 (for example, pixel circuit 3b) and sample-and-hold circuit 10 are arranged in s rows and t columns as a unit block, sxt negative feedback operations are required, and they must be repeated for three gains (HCG, MCG, LCG), as well as for the reset component and signal component. In this example, there are four rows and two columns, so the number is 8 times x 3 gains x 2 components = 48 times.

[0413] Next, the timing chart of FIG. 17 will be described.

[0414] First, the reset components of the MCG are read out from time t102 to t106 for eight pixels while repeatedly performing negative feedback to the sample-and-hold capacitive element C22 of each sample-and-hold circuit 10c.

[0415] Next, the reset components of HCG are read out from time t106 to t110 for eight pixels while repeatedly performing negative feedback to the sample-and-hold capacitance element C20 of each sample-and-hold circuit 10c.

[0416] Next, from time t110 to t114, the reading of the HCG signal components is performed for eight pixels while repeatedly performing negative feedback to the sample-and-hold capacitance element C21 of each sample-and-hold circuit 10c.

[0417] Next, the reading of the MCG signal components from time t114 to t118 is performed for eight pixels while repeatedly performing negative feedback to the sample-and-hold capacitive element C23 of each sample-and-hold circuit 10c.

[0418] Next, the reading of the LCG signal components from time t118 to t122 ​​is performed for eight pixels while repeatedly performing negative feedback to the sample-and-hold capacitive element C25 of each sample-and-hold circuit 10c.

[0419] Next, the readout of the reset components of the LCG from time t122 ​​to t126 is performed for eight pixels while repeatedly performing negative feedback to the sample-and-hold capacitive element C24 of each sample-and-hold circuit 10c.

[0420] Here, in order to always apply negative feedback, switch element SW1 is always ON and switch element SW11 is always OFF for reading the Fth column. Switch element SW2 is always ON and switch element SW12 is always OFF for reading the F+1th column.

[0421] Alternatively, the selection transistor SEL_RS of the pixel circuit 3 and the sample and hold switch control signal φSH of the SH circuit 10 may be controlled by turning on the switch elements SW1 and SW2 and turning off the switch elements SW11 and SW12.

[0422] Next, for reading out from the sample and hold capacitance elements (C20, C21, C22, C23, C24, C25), the vertical scanning circuit 14 selects the multi-pixel shared negative feedback circuit 4d on a row-by-row basis, and outputs pixel signals from the multi-pixel shared negative feedback circuit 4d belonging to the selected row to two vertical signal lines 19A simultaneously: the signal for the Fth column is output from the amplification transistor SF2, and the signal for the F+1th column is output from the amplification transistor SF3.

[0423] First, the signal from pixel A in row E and column F is output via amplifier transistor SF2, and the signal from pixel E in column F+1 is output via amplifier transistor SF3.

[0424] First, the control signal φSE of the read selection switch element SE26 of pixel A and pixel E is turned ON at t127, so that the reset components of the HCG are simultaneously read out and transferred via the amplification transistors SF2 and SF3, and then the control signal φSE of each read selection switch element SE27 is turned ON at t128, so that the signal components of the HCG are simultaneously read out and transferred via the amplification transistors SF2 and SF3.

[0425] Next, by turning on the control signal φSE of the read selection switch element SE28 of pixel A and pixel E at t129, the reset components of MCG are simultaneously read out and transferred via the amplification transistors SF2 and SF3, and then by turning on the control signal φSE of each read selection switch element SE29 at t130, the signal components of MCG are simultaneously read out and transferred via the amplification transistors SF2 and SF3.

[0426] Next, the control signal φSE of the read selection switch element SE30 of pixel A and pixel E is turned ON at t131, thereby simultaneously reading out and transferring the reset components of the LCG via the amplification transistors SF2 and SF3, and then the control signal φSE of each read selection switch element SE31 is turned ON at t132, thereby simultaneously reading out and transferring the signal components of the LCG via the amplification transistors SF2 and SF3.

[0427] Next, the signal from pixel B in row E+1 and column F and the signal from pixel F in column F+1 are output via amplifier transistors SF2 and SF3, respectively, after undergoing the same operation as that from time t127 to t133.

[0428] Next, the signal from the C pixel in the Fth column of the E+2th row and the signal from the G pixel in the F+1th column are output via the amplification transistors SF2 and SF3, respectively, after undergoing the same operation as that from time t127 to t133.

[0429] Next, the signal from pixel D in row E+3 and column F and the signal from pixel H in column F+1 are output via amplifier transistors SF2 and SF3, respectively, after undergoing the same operation as that from time t127 to t133.

[0430] The readout order from pixel circuit 3 to negative feedback circuit 4d may be regular or random for each frame. If there is fixed variation due to the sample and hold capacitance elements, the sample and hold switch control signal φSH, or the readout selection switch element control signal φSE, regular readout results in fixed noise that is easily visible, but random readout makes this fixed noise less visible, and the perceived noise at low illumination levels is improved.

[0431] As described in embodiment 1A, the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling out the variations.

[0432] [Configuration and operation example of negative feedback circuit (speed up)] The configuration of the negative feedback circuit and the differences from Operation Example 1 will be described.

[0433] The feature of embodiment 3A is that there are a plurality of pixel circuits 3 and sample-hold circuits 10 in one-to-one correspondence with one feedback amplifier FA.

[0434] For this reason, a signal corresponding to each gain of the pixel circuit 3 (for example, the pixel circuit 3b) must be sent multiple times to each sample-and-hold circuit 10 shared by the feedback amplifier FA.

[0435] If the pixel circuit 3 (for example, pixel circuit 3b) and sample-and-hold circuit 10 are arranged in s rows and t columns as a unit block, there will be sxt negative feedback operations, and they will need to be repeated for three gains (HCG, MCG, LCG), as well as for the reset component and signal component. In this example, there are 4 rows and 2 columns, so the number of operations is 8 times x 3 gains x 2 components = 48 times.

[0436] This reduces noise, but there are 48 negative feedback operations, which poses a problem of taking a long time to read data from pixel circuit 3b to negative feedback circuit 4d shared by multiple pixels.

[0437] This leads to a long signal retention time (from time 102 to time 126) in the FD0 section of pixel circuit 3, which is affected by the dark current and parasitic sensitivity of the FD0 section. For this reason, the readout time from pixel circuit 3b to negative feedback circuit 4d needs to be increased, and as explained above, kTC noise, particularly at low illumination levels, needs to be reduced. Below, we will explain measures to achieve both increased speed and reduced noise.

[0438] As shown in Figure 16(4), the kTC noise in the HCG in WDR determines the low-light characteristics, so negative feedback operation is essential. On the other hand, if we focus on the boundary between the MCG and HCG on the SN curve, there is no problem as long as the kTC noise of the MCG is smaller than the shot noise of the HCG. Also, if we focus on the boundary between the LCG and MCG on the SN curve, there is no problem as long as the kTC noise of the LCG is smaller than the shot noise of the MCG.

[0439] 17, the reset components of the MCG are read from time t102 to t106 without negative feedback to the sample and hold capacitor element C22 of the sample and hold circuit 10 for eight pixels, thereby shortening the read time. Here, the switch elements SW1 and SW2 are turned OFF, and the switch elements SW11 and SW12 are turned ON.

[0440] Next, from time t106 to t110, the reset components of the HCG are read out while repeatedly performing negative feedback to the sample-and-hold capacitance elements C20 of the eight sample-and-hold circuits 10. Here, the switch elements SW1 and SW2 are turned on, and the switch elements SW11 and SW12 are turned off.

[0441] Next, from time t110 to t114, the HCG signal components are read out while repeatedly performing negative feedback to the sample-and-hold capacitance elements C21 of the eight sample-and-hold circuits 10. Here, the switch elements SW1 and SW2 are turned on, and the switch elements SW11 and SW12 are turned off.

[0442] Next, the readout of the MCG signal components from time t114 to t118 can be shortened by reading without negative feedback from the sample and hold capacitance elements C23 of the eight sample and hold circuits 10. Here, switch elements SW1 and SW2 are turned OFF, and switch elements SW11 and SW12 are turned ON.

[0443] Next, the readout of the LCG signal components from time t118 to t122 ​​can be shortened by reading without negative feedback from the sample and hold capacitance elements C25 of the eight sample and hold circuits 10. Here, switch elements SW1 and SW2 are turned OFF, and switch elements SW11 and SW12 are turned ON.

[0444] Next, the readout of the reset components of the LCG from time t122 ​​to t126 can be shortened by reading without negative feedback from the sample and hold capacitance elements C24 of the eight sample and hold circuits 10. Here, switch elements SW1 and SW2 are turned OFF, and switch elements SW11 and SW12 are turned ON.

[0445] In the negative feedback circuit 4, the feedback amplifier FA has a gain switching function, and the gain of the feedback amplifier FA for HCG can be made the largest compared to the gains of MCG and LCG. In this case, the convergence time of HCG takes a little longer but the kTC noise can be reduced, and the kTC noise of MCG and LCG cannot be reduced much but the convergence time can be made faster, thereby realizing a reduction in the kTC noise of HCG and a combined speed-up of HCG, MCG, and LCG.

[0446] In the negative feedback circuit 4, the capacitance values ​​of the sample and hold capacitance elements C20 and C21 of the HCG can also be made the largest compared to the capacitance values ​​of the sample and hold capacitance elements C22, C23, C24, and C25 of the MCG and LCG. In this case, the convergence time of the HCG takes a little longer but the kTC noise can be reduced, and the kTC noise of the MCG and LCG cannot be reduced much but the convergence time can be made faster, thereby realizing a reduction in the kTC noise of the HCG and a combined speed-up of the HCG, MCG, and LCG.

[0447] In the negative feedback circuit 4, the gains of the feedback amplifiers FA of the HCG, MCG, and LCG can be made the same to shorten the negative feedback times of the MCG and LCG (times t103 to t105, t115 to t117, t119 to t121, and t123 to t125). In this case, the convergence time of the HCG takes a little longer, but the kTC noise can be reduced, and the kTC noise of the MCG and LCG cannot be reduced much, but the convergence time can be speeded up, thereby reducing the kTC noise in the HCG and speeding up the combined HCG, MCG, and LCG.

[0448] The timing of subsequent signal readout from the sample and hold capacitor is the same as in the [Configuration and Operation Example of Negative Feedback Circuit (Noise Reduction)] of the third embodiment.

[0449] [Expanded dynamic range] A feature of this embodiment is that the three frames of high-illuminance exposure, medium-illuminance exposure, and high-illuminance exposure that combine WDR are exposed at exactly the same timing and use exactly the same pixels, so false colors, coloring, and blurring do not occur.

[0450] The details of the expansion of the dynamic range are omitted since they are the same as those of the embodiments 2A and 2B.

[0451] Conventionally, there was no negative feedback circuit, so kTC noise was generated when the sample-hold switch was turned off, which worsened low-light noise and narrowed the dynamic range.

[0452] In this embodiment, the sample-and-hold switch is turned off while applying a negative feedback circuit to the reset component and signal component of the pixel, thereby significantly reducing kTC noise and achieving low noise. Furthermore, the CDS of the AD conversion circuit subtracts the reset component from the signal component, thereby canceling out variations in the amplifier transistors SF1 and SF2. As a result, low-light noise is reduced and the dynamic range is expanded.

[0453] [Layout example of a multi-pixel shared negative feedback circuit] FIG. 22 shows an example of a layout configuration of a negative feedback circuit 4d shared by multiple pixels with s rows and t columns, in which a plurality of pixel circuits (3a, b, c) and a plurality of sample-and-hold circuits (10a, b, c) are stacked one-to-one in a matrix (s rows x t columns), and in the layout, a feedback amplifier (FA) is placed between the sample-and-hold circuits.

[0454] As a specific example, a 4-row, 2-column layout corresponding to FIG. 20 is shown. In FIG. 20, the feedback amplifier FA is placed between the Fth column of the SH circuit 10 and the F+1th column of the SH circuit 10. It is preferable to place it in the center. The feedback lines A and B are placed so that they are approximately evenly spaced above, below, left, and right, and the loads are also approximately equal above, below, left, and right.

[0455] This shortens the readout distance from pixel circuit 3a, pixel circuit 3b, or pixel circuit 3c to its one-to-one corresponding SH circuit 10a, SH circuit 10b, or SH circuit 10c. Also, the negative feedback load from feedback amplifier FA to each sample-and-hold circuit 10a, SH circuit 10b, or SH circuit 10c is approximately equal in all directions, making it possible to achieve approximately equal kTC noise reduction effects and eliminate regular fixed noise components.

[0456] [Example of a pixel circuit and negative feedback circuit configured using stacked BSI] As pixel cells become increasingly miniaturized, it becomes difficult to mount all of the sample and hold capacitance elements (for example, MIM capacitance and MOM capacitance) of the SH circuit 10 of the negative feedback circuit 4d on the logic chip side.

[0457] An example of a solid-state imaging device configured as a stacked back-illuminated image sensor is shown in FIG. 23. While FIG. 23 shows a negative feedback circuit configuration shared by multiple pixels, it is similar to the single negative feedback circuit configuration of embodiment 1A shown in FIG. 5, and the solid-state imaging device can include a first semiconductor chip, a second semiconductor chip, or multiple semiconductor chips bonded together. Furthermore, the photodiode PD, sample-and-hold capacitor element C, feedback amplifier FA, and sample-and-hold switch element SH can also be arranged in a negative feedback circuit 4d shared by multiple pixels, similar to embodiment 1A.

[0458] (Fourth embodiment) The configuration of embodiment 4 is shown in FIG. 24. The pixel circuit 3a is the same as in embodiment 1A. The negative feedback circuit 4c has the same configuration as in embodiment 2A. The solid-state imaging device 100 is also the same as in the above embodiments. The following description will focus on the differences from the above embodiments.

[0459] [Pixel circuit configuration example] In the fourth embodiment, the pixel circuit 3a is the same as that in the first embodiment.

[0460] [HCG readout operation example] In the fourth embodiment, the pixel circuit 3a is the same as in the first embodiment, and the timing is shown in FIG.

[0461] [Configuration and operation example of a negative feedback circuit] The global shutter method and the rolling shutter method, which are the exposure methods of the embodiment 1A, are continuous exposures (exposure periods are not divided).

[0462] 25 and 26, which show the exposure method of the fourth embodiment, are diagrams showing the timing of charge accumulation in the photodiode PD. The exposure period is divided into multiple periods (N), and in each exposure period, the photodiode PD continues to be exposed for the desired exposure period, with the charge amount being Q0. Therefore, the pixel saturation of the photodiode PD is expanded by N times. In this example, N=3.

[0463] In the global shutter method shown in Figure 25, a global reset is performed on all pixels simultaneously, exposure is started, and the exposure period is divided into multiple periods (N). In each exposure period, the photodiode PD continues to be exposed for the desired exposure period, with the charge amount being Q0. Therefore, the pixel saturation of the photodiode PD is expanded by N times. In this example, N=3.

[0464] The charge readout from the photodiodes is performed for all pixels simultaneously to the sample and hold capacitor elements (C20, C21) after the exposure time T_Q0_1. Next, after the exposure time T_Q0_2, it is performed for all pixels simultaneously to the sample and hold capacitor elements (C22, C23). Next, after the exposure time T_Q0_3, it is performed for all pixels simultaneously to the sample and hold capacitor elements (C24, C25). After that, the analog mixed signals of the sample and hold capacitor elements (C20, C22, C24) and the analog mixed signals of the sample and hold capacitor elements (C21, C23, C25) are read out row by row in a rolling manner.

[0465] In the rolling shutter method shown in Figure 26, all pixels are scanned and shuttered for each selected row, and exposure begins. The exposure period is divided into multiple periods (N), and in each exposure period, the photodiode PD continues to be exposed for the desired exposure period, with the charge amount being Q0. Therefore, the pixel saturation of the photodiode PD is expanded by N times. In this example, N=3.

[0466] The charge readout from the photodiodes is performed row by row to the sample and hold capacitor elements (C20, C21) after the exposure time T_Q0_1. Then, after the exposure time T_Q0_2, it is performed row by row to the sample and hold capacitor elements (C22, C23). Then, after the exposure time T_Q0_3, it is performed row by row to the sample and hold capacitor elements (C24, C25). After that, the analog mixed signals of the sample and hold capacitor elements (C20, C22, C24) and the analog mixed signals of the sample and hold capacitor elements (C21, C23, C25) are read out row by row in a rolling manner.

[0467] FIG. 27 shows an example of the timing of a signal read operation.

[0468] In the fourth embodiment, the exposure timing from time 401 to 402 and the readout timing of the reset component and signal component of the pixel signal to the sample and hold circuit 10 from time 402 to 410 are the same as those in the first embodiment.

[0469] The same applies to the timing from time 411 to time 420, and the timing from time 402 to time 410 is repeated.

[0470] The same applies to the timing from time 421 to time 430, and the timing from time 402 to time 410 is repeated.

[0471] Next, by turning on the control signal φSE of the read selection switch elements (SE26, SE28, SE30) at t431, the analog-mixed reset components of the sample and hold capacitance elements (C20, C22, C24) are read out and transferred via the amplification transistor SF2, and by turning on the control signal φSE of the read selection switch elements (SE27, SE29, SE31) at t614, the analog-mixed signal components of the sample and hold capacitance elements (C21, C23, C25) are read out and transferred via the amplification transistor SF2.

[0472] The CDS in the AD conversion circuit subtracts the reset component from the signal component, canceling out variations in the amplifier transistors SF1 and SF2. As a result, low-light noise is reduced and the dynamic range is expanded.

[0473] [Expanded dynamic range] The feature of this embodiment is that, for example, one frame of high-intensity exposure for synthesizing WDR is divided into multiple times (N times) and constantly exposed, and the same pixels are used, so false colors, coloring, and blurring do not occur.

[0474] First, by dividing the exposure into multiple times (N times) while maintaining constant exposure, pixel saturation can be expanded N times. Then, the charge in the sample-and-hold capacitor element is read out in an analog manner and mixed by turning on the control signal φSE of the selection switch element. As a result, the dynamic range can be expanded without increasing the readout speed or power consumption.

[0475] In this example, in the case of multiple (N) exposures, N = 3, so the dynamic range can be expanded by approximately 10 dB. If the number of multiple (N) exposures is increased, the dynamic range can be easily expanded.

[0476] Here, the idea behind analog mixing is that if the value of the capacitance element is C and the signal level, which is the amount of charge generated in the capacitance element and depends on the illuminance, is ΔV, then the charge ΔQ = C x ΔV, and if this is repeated three times and integrated three times, the amount of charge becomes 3 x ΔQ, and the dynamic range is expanded three times.

[0477] (Embodiment 5A) 28 is a diagram showing a configuration example of an imaging device 200 to which the solid-state imaging device 100 according to any one of Embodiments 1 to 4 is applied. The imaging device in the figure is a camera system, and includes the solid-state imaging device 100, an imaging optical system 202 including a lens, a signal processing unit 203, a drive circuit 204, and a system control unit 205.

[0478] In the imaging device 200, the solid-state imaging device 100 according to the first to fourth embodiments is used.

[0479] Furthermore, the drive circuit 204 receives a control signal corresponding to the drive mode from the system control unit 205 and supplies a drive mode signal to the solid-state imaging device 100. Upon receiving the drive mode signal, the solid-state imaging device 100 generates drive pulses corresponding to the drive mode signal and supplies them to each block within the solid-state imaging device 100.

[0480] Furthermore, the signal processing unit 203 receives the image signal output from the solid-state imaging device 100 and performs various signal processing on the image signal.

[0481] As such, the imaging device in this embodiment comprises the above-mentioned solid-state imaging device 100, an imaging optical system 202 that guides incident light from a subject to the solid-state imaging device 100, and a signal processing unit 203 that processes output signals from the solid-state imaging device 100.

[0482] (Embodiment 5B) 29 is a block diagram showing an example of the configuration of a distance measuring imaging device 300 according to Embodiments 1 to 4. The object to be measured is designated by 190.

[0483] The distance measuring imaging device 300 includes a light source driver 150, a light source unit 160, an optical lens 170, a signal processing circuit 180, and the solid-state imaging device 100.

[0484] In the distance measuring imaging device 300, the solid-state imaging device 100 according to the first to fourth embodiments is used.

[0485] The light source driver 150 supplies a drive signal to the light source unit 160 in accordance with a signal from the solid-state imaging device 100 instructing it to emit light.

[0486] The light source unit 160 generates pulsed light for distance measurement in accordance with a drive signal from the light source driver 150 .

[0487] The optical lens 170 is a lens for collecting pulsed light reflected by the object 190 corresponding to the pulsed light from the light source unit 160 .

[0488] The signal processing circuit 180 calculates the distance to the object 190 based on the signal received from the solid-state imaging device 100 .

[0489] In the solid-state imaging device 100, near-infrared light is irradiated from the light source unit 160 onto an object 190 in the presence of background light. The light reflected from the object 190 is incident on the pixel array unit 1 via the optical lens 170. The reflected light incident on the pixel array unit 1 forms an image, and the formed optical image is converted into a pixel signal. The output of the solid-state imaging device 100 is converted into distance data by the signal processing circuit 180, and may also be converted into a visible distance image or brightness image depending on the application. [Industrial Applicability]

[0490] The present disclosure relates to a solid-state imaging device, and a photographing device or a distance measuring imaging device that uses the solid-state imaging device as an imaging device, and is suitable for, for example, a video camera, a digital camera, a distance measuring system, and the like. [Explanation of symbols]

[0491] 3a, 3b, 3c pixel circuit 4a~4d Negative feedback circuit 10a, 10b, 10c First sample and hold circuit C0 storage capacitance element C1 First storage capacitor element C2 Second storage capacitor element GC1 First gain control transistor GC2 Second gain control transistor FA Feedback Amplifier FD0, FD1, FD2 charge storage units OF Overflow element PD photodiode RS Reset transistor SF1 First amplifying transistor SF2 Second amplifier transistor TG transfer transistor < / s4>

Claims

1. a pixel circuit that outputs a pixel signal; a negative feedback circuit, The negative feedback circuit includes: a sample-and-hold circuit (hereinafter abbreviated as SH circuit) that samples and holds the pixel signal; a feedback amplifier that negatively feeds back to the SH circuit a feedback signal corresponding to a difference between the pixel signal from the pixel circuit and an output signal from the SH circuit. Solid-state imaging device.

2. The SH circuit is an SH unit circuit that samples and holds pixel signals; an amplifying transistor that amplifies an output signal of the SH unit circuit and outputs the amplified signal to the feedback amplifier; The SH unit circuit is a first sample and hold switch element for sampling the feedback signal; a first sample-and-hold capacitance element connected to the first sample-and-hold switch element; a pixel signal from the pixel circuit is input to a positive input terminal of the feedback amplifier; a feedback signal of the feedback amplifier is input to the first sample-and-hold switch element; The output signal of the amplifying transistor is input to the negative input terminal of the feedback amplifier, The feedback amplifier, the SH unit circuit, and the amplifying transistor form a feedback loop. The solid-state imaging device according to claim 1 .

3. The SH unit circuit is a first read selection switch element that connects the first sample-and-hold capacitance element and the amplification transistor; The solid-state imaging device according to claim 2 .

4. The negative feedback circuit includes: a feedback capacitance element connected to one of the two terminals of the first sample-and-hold switch element to which the feedback signal is input; an attenuator capacitance element connected in parallel to the first sample-and-hold switch element; The solid-state imaging device according to claim 2 .

5. the pixel circuit outputs a plurality of pixel signals; The sample and hold circuit a plurality of the SH unit circuits corresponding to the plurality of pixel signals; The solid-state imaging device according to claim 2 .

6. the plurality of pixel signals include a first pixel signal, a second pixel signal, and a third pixel signal having different exposure sensitivities from one another; the plurality of SH unit circuits include a first SH unit circuit, a second SH unit circuit, and a third SH unit circuit; The solid-state imaging device according to claim 5 .

7. The first sample-and-hold capacitance elements in two or more of the plurality of SH unit circuits are connected in parallel to mix corresponding pixel signals. The solid-state imaging device according to claim 5 .

8. a plurality of the pixel circuits and a plurality of the SH circuits; The feedback amplifier is shared by two or more SH circuits. The solid-state imaging device according to claim 1 .

9. the pixel signal includes a reset component and a signal component; The SH unit circuit is the first sample-and-hold switch element; the first sample and hold capacitive element; a second sample and hold switch element for sampling the feedback signal; a second sample-and-hold capacitive element connected to the second sample-and-hold switch element; the first sample-and-hold capacitive element holds the reset component; The second sample-and-hold capacitive element holds the signal component.

5. The solid-state imaging device according to claim 2, 3 or 4.

10. The SH unit circuit is a first read selection switch element connecting the first sample and hold capacitance element and the amplification transistor; a second read selection switch element that connects the second sample-and-hold capacitance element and the amplification transistor; The solid-state imaging device according to claim 9 .

11. the plurality of pixel circuits are arranged in a matrix, the plurality of SH circuits are arranged in a matrix, the pixel circuits and the SH circuits are stacked in a one-to-one relationship; The feedback amplifier is disposed between the SH circuits in a plan view. The solid-state imaging device according to claim 8 .

12. The first sample-and-hold switch element transitions from an ON state to an OFF state in response to a control signal having a slope-shaped voltage waveform. The solid-state imaging device according to claim 2 .

13. the negative feedback circuit includes a third sample-and-hold switch element inserted in the feedback loop between the output terminal of the feedback amplifier and the input terminal of the first sample-and-hold switch element; The third sample-and-hold switch element transitions from an ON state to an OFF state in response to a control signal having a slope-shaped voltage waveform.

13. The solid-state imaging device according to claim 2, 3, 4 or 12.

14. the negative feedback circuit includes a measurement unit for measuring a noise level of the first sample and hold capacitive element in the SH circuit; a determining unit that determines the gradient of the sloping voltage waveform so as to reduce the measured noise level. The solid-state imaging device according to claim 12.

15. the negative feedback circuit has a switch circuit for switching whether or not to perform negative feedback in a sample-and-hold operation; Negative feedback is performed on at least one of the plurality of pixel signals, and negative feedback is not performed on the other pixel signals.

7. The solid-state imaging device according to claim 5.

16. the feedback amplifier has a gain switching function, In the negative feedback circuit, a gain of a feedback amplifier is set for each of the plurality of pixel signals.

7. The solid-state imaging device according to claim 5.

17. The capacitance values ​​of the first sample-and-hold capacitance elements in the plurality of SH unit circuits vary depending on the corresponding pixel signals.

7. The solid-state imaging device according to claim 5.

18. the pixel circuit has an output transistor that outputs the pixel signal; The size of the amplifier transistor is larger than the size of the output transistor The solid-state imaging device according to claim 1 .

19. The solid-state imaging device according to claim 1 for imaging a subject; an imaging optical system that guides incident light from the subject to the solid-state imaging device; a signal processing unit that processes an output signal from the solid-state imaging device; Imaging device.

20. The solid-state imaging device according to claim 1 , which captures an image of light reflected from an object irradiated with pulsed light; an imaging optical system that guides the reflected light from the object to the solid-state imaging device; a signal processing unit that processes an output signal from the solid-state imaging device; Ranging imaging device.

Images