Measuring equipment

Abstract

The present disclosure relates to a measuring device that enables more accurate measurements to be made. Provided is a measuring device comprising: a PLL circuit commonly used to generate a transmission RF signal and a reception LO signal, which are high frequency signals with different frequencies; an IQ correction unit that corrects an IQ error of an LO signal used in generating at least one of the transmission RF signal or the reception LO signal; and a switching unit that switches between an ON state in which correction is performed by the IQ correction unit and an OFF state in which the correction is not performed. The present disclosure can be applied, for example, to a vector network analyzer.

Description

[Technical Field]

[0001] The present disclosure relates to a measurement device, and more particularly to a measurement device that enables more accurate measurements. [Background technology]

[0002] Vector network analyzers (VNA) are devices that measure radio frequency signals in the frequency domain. In a vector network analyzer, a transmission RF (Radio Frequency) signal and a reception LO (Local Oscillator) signal, which are high-frequency signals with different frequencies, are generated by using a single common PLL (Phase Locked Loop) circuit to generate one of the signals through frequency conversion by a mixer (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 3-35174 Summary of the Invention [Problem to be solved by the invention]

[0004] In vector network analyzers, when a common PLL circuit is used, there is a risk that IQ errors may cause the influence of image signals, and it is necessary to suppress measurement errors caused by image signals. However, conventional technology does not provide sufficient countermeasures, and there is a demand for more accurate measurements.

[0005] The present disclosure has been made in light of these circumstances, and makes it possible to perform measurements more accurately. [Means for solving the problem]

[0006] A measurement device according to one aspect of the present disclosure is a measurement device including a PLL circuit commonly used to generate a transmission RF signal and a reception LO signal, which are high-frequency signals having different frequencies; an IQ correction unit that corrects an IQ error in the LO signal used in generating at least one of the transmission RF signal and the reception LO signal; and a switching unit that switches between an on state in which the IQ correction unit performs correction and an off state in which correction is not performed.

[0007] In a measurement device according to one aspect of the present disclosure, a PLL circuit is provided that is used in common for generating a transmission RF signal and a reception LO signal, which are high-frequency signals with different frequencies, and the IQ error of the LO signal used for generating at least one of the transmission RF signal and the reception LO signal is corrected, and the measurement device is switched between an ON state in which the IQ error is corrected and an OFF state in which the IQ error is not corrected.

[0008] The measurement device according to one aspect of the present disclosure may be an independent device or an internal block constituting a single device. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a diagram illustrating an example of the configuration of an embodiment of a measurement device to which the present disclosure is applied. [Figure 2] FIG. 10 is a diagram illustrating the influence of an image signal. [Figure 3] FIG. 10 is a diagram illustrating an example of on / off switching of an IQ correction unit. [Figure 4] 1 shows an example of the configuration of a DLL circuit that constitutes an IQ correction unit. [Figure 5] FIG. 2 is a diagram illustrating a first example of the configuration of a VCDL circuit. [Figure 6] FIG. 10 is a diagram illustrating a second example of the configuration of a VCDL circuit. [Figure 7] FIG. 10 is a diagram illustrating a third example of the configuration of a VCDL circuit. [Figure 8] FIG. 2 is a diagram illustrating an example of the configuration of a drive voltage generating circuit that constitutes a VCDL circuit. [Figure 9]It is a diagram showing a detailed configuration example of a drive voltage generation circuit that constitutes a VCDL circuit. [Figure 10] It is a diagram showing another configuration example of a DLL circuit that constitutes an IQ correction unit. [Figure 11] It is a diagram showing another configuration example of a drive voltage generation circuit that constitutes a VCDL circuit. [Figure 12] It is a diagram showing another detailed configuration example of a drive voltage generation circuit that constitutes a VCDL circuit. [Figure 13] It is a diagram showing another configuration example of an IQ correction unit. [Figure 14] It is a diagram showing a configuration example of a switching unit that performs on / off switching of an IQ correction unit. [Figure 15] It is a diagram showing a configuration example of a drive voltage generation circuit that constitutes a DCDL circuit. [Figure 16] It is a diagram showing a configuration example of a delay circuit replica. [Figure 17] It is a diagram showing another configuration example of an embodiment of a measuring device to which the present disclosure is applied. [Figure 18] It is a diagram showing yet another configuration example of an embodiment of a measuring device to which the present disclosure is applied. [Figure 19] It is a diagram showing an application example of a DLL circuit. [Figure 20] It is a diagram showing another application example of a DLL circuit.

Embodiments for Carrying Out the Invention

[0010] <Configuration of VNA> FIG. 1 is a diagram showing a configuration example of an embodiment of a measuring device to which the present disclosure is applied.

[0011] In FIG. 1, the measuring device 10 is a vector network analyzer (VNA) capable of measuring S parameters (Scattering Parameter) such as S11 and S21 of a device under test (DUT) connected to terminals P1 and P2.

[0012] As shown in FIG. 1, the measurement device 10 is composed of an IF (Intermediate Frequency) signal generator 111, a transmitting mixer 112, a transmitting amplifier 113, a directional coupler 114, a receiver 115R, a receiver 115A, a receiver 115B, a PLL circuit 116, a buffer 117, and an IQ correction unit 118.

[0013] In the measurement device 10, a transmission IF signal from an IF signal generator 111 is frequency-converted by a transmission mixer 112, and a transmission RF signal is output from a transmission amplifier 113 via a directional coupler 114 to a terminal P1.

[0014] The transmitted RF signal is measured by being received by receiver 115R. Meanwhile, a portion of the transmitted RF signal is reflected by the DUT under test, and the reflected signal is input from terminal P1 and received by receiver 115A via directional coupler 114, and is measured. Furthermore, a portion of the transmitted RF signal passes through the DUT under test, and the transmitted signal is input from terminal P2 and received by receiver 115B, and is measured.

[0015] The receiver 115R is composed of an LNA (Low Noise Amplifier) ​​131R, a receiving mixer 132R, a filter 133R, and an ADC (Analog to Digital Converter) 134R. In the receiver 115R, a transmission RF signal input to the LNA 131R is frequency converted by the receiving mixer 132R and passed through the filter 133R to obtain a reception IF signal, and the transmission signal is measured by performing signal processing by the ADC 134R.

[0016] Like receiver 115R, receivers 115A and 115B are each composed of an LNA 131, a receiving mixer 132, a filter 133, and an ADC 134. Receiver 115A measures a reflected signal from the input transmission RF signal, while receiver 115B measures a transmitted signal from the input transmission RF signal.

[0017] Since S11 and S21 are expressed by the relationship of the following equations (1) and (2), it is possible to obtain S11 and S21 from the measurement results of receiver 115R, receiver 115A, and receiver 115B.

[0018] S11 = Reflected signal / Transmitted signal (1) S21 = transmitted signal / transmitted signal (2)

[0019] Furthermore, the measurement apparatus 10 is configured to generate the transmission RF signal and the reception LO signal, which are high-frequency signals with different frequencies, based on a high-frequency reference clock generated by a single PLL circuit 116.

[0020] PLL circuit 116 generates a high-frequency reference clock and changes the frequency of the LO signal (LO signal frequency). The LO signal generated based on the high-frequency reference clock is output to each receiver 115 via transmission mixer 112, buffer 117, and IQ correction unit 118. Hereinafter, the LO signal used on the transmitting side will be referred to as a transmission LO signal, and the LO signal used on the receiving side will be referred to as a reception LO signal.

[0021] In transmission mixer 112, the IF signal from IF signal generator 111 is mixed with a transmission LO signal to perform frequency conversion, and a transmission RF signal is generated. In receiver 115R, reception mixer 132R performs frequency conversion by mixing the input transmission RF signal with a reception LO signal input via buffer 135R, and a reception IF signal is generated. In receivers 115A and 115B, the input transmission RF signal is mixed with a reception LO signal to generate a reception IF signal, similar to receiver 115R.

[0022] The IQ correction unit 118 is an IQ correction mechanism that corrects the IQ error of the LO signal (received LO signal). The IQ correction unit 118 is composed of a DLL (Delay Locked Loop) circuit 141. A selector 142 is provided for the DLL circuit 141. The received LO signal and the output of the DLL circuit 141 (received LO signal after IQ error correction) are input to the selector 142, and either one of the signals is output.

[0023] That is, the selector 142 functions as a switching unit (changeover switch) that switches the IQ correction unit 118 between an ON state and an OFF state. The ON state is a state in which the DLL circuit 141 performs IQ error correction, and the received LO signal after IQ error correction is output. The OFF state is a state in which the DLL circuit 141 does not perform IQ error correction, and the received LO signal is output as is.

[0024] In the measurement device 10, measurement errors caused by image signals are suppressed by providing an IQ correction unit 118. Fig. 2 is a diagram illustrating the influence of image signals. In order to explain the influence of image signals, Fig. 2 shows the configuration of a conventional measurement device, i.e., a configuration that does not include the IQ correction unit 118 compared to the configuration of the measurement device 10 in Fig. 1.

[0025] 2, in conventional measuring devices, an image signal occurs in the RF signal due to IQ errors of the high-frequency reference clock generated by PLL circuit 116 and the transmitting mixer 112, etc. Furthermore, in each receiver 115, frequency conversion is performed by receiving mixer 132 using the receiving LO signal, so image removal is not sufficient due to IQ errors of the receiving LO signal and receiving mixer 132, etc., and the influence of the image signal occurs.

[0026] From these, the image rejection ratio IM of the transmitting mixer 112 is calculated. TX and the image rejection ratio IM of the receiving mixer 132. RX By multiplying with , IM TX *IM RXThe image signal causes an interference signal to appear at the same frequency as the desired signal. Because the interference signal caused by the image signal is difficult to distinguish from the desired signal, the measurement results at each receiver 115 contain errors, resulting in measurement errors for S11 and S21.

[0027] In response to this, by providing an IQ correction unit 118 and correcting the IQ error of the LO signal (received LO signal), it becomes possible to suppress measurement errors caused by image signals. Furthermore, a vector network analyzer requires a relatively wide operating frequency range, and in addition, when using the vector network analyzer for measuring the propagation delay of a DUT, time error precision is required. The IQ correction unit 118 is an IQ correction mechanism configured with a DLL circuit 141, but because it corrects errors based on one period, it tends to be difficult to ensure time error precision at low frequencies.

[0028] Therefore, in the measuring device 10, in addition to the IQ correction unit 118 having the DLL circuit 141, a selector 142 is provided as a mechanism for switching the IQ correction unit 118 between an on state and an off state depending on the LO signal frequency, thereby making it possible to ensure good time error accuracy across a range from low frequencies to high frequencies.

[0029] For example, the selector 142 can switch the IQ correction unit 118 between an on state and an off state in accordance with the LO signal frequency set in the PLL circuit 116 as shown in Fig. 3. Specifically, when the LO signal frequency is in the range of 3 GHz to 9 GHz, the IQ correction unit 118 is set to an on state, and when the LO signal frequency is in the range of 1 GHz to 3 GHz, the IQ correction unit 118 is set to an off state.

[0030] In FIG. 3, the on and off states are switched according to whether the LO signal frequency is higher than 3 GHz or lower than 3 GHz with 3 GHz as the reference frequency. However, the reference frequency is not limited to 3 GHz. That is, in the region where the LO signal frequency is lower than the reference frequency, it is set to the off state, and in the region where the LO signal frequency is higher than the reference frequency, it may be set to the on state.

[0031] <Configuration of DLL Circuit> FIG. 4 is a diagram showing a configuration example of a DLL circuit 141 that constitutes the IQ correction unit 118 in FIG. 1.

[0032] As shown in FIG. 4, the DLL circuit 141 includes a VCDL (Voltage Controlled Delay Line) circuit 211, a phase comparison circuit 212, and an integration circuit 213. The VCDL circuit 211 includes a drive voltage generation circuit 221A and a delay circuit 222A provided for the I signal, and a drive voltage generation circuit 221B and a delay circuit 222B provided for the Q signal.

[0033] The phase comparison circuit 212 compares the phases of the OUT_I signal and the OUT_Q signal, and outputs the comparison result to the integration circuit 213. The integration circuit 213 generates a VCDL control signal based on the comparison result from the phase comparison circuit 212 and outputs it to the VCDL circuit 211. As shown in FIG. 4, the VCDL circuit 211 is configured to control the I, Q phase difference by controlling one of the I signal and the Q signal based on the VCDL control signal from the integration circuit 213.

[0034] FIGS. 5 to 7 are diagrams showing configuration examples of the VCDL circuit 211 that constitutes the DLL circuit 141.

[0035] As shown in FIG. 5, the VCDL circuit 211A includes a drive voltage generation circuit 221 and a delay circuit 222 configured as an inverter. The drive voltage generation circuit 221 generates a drive voltage V based on the input control voltage V C based on, the drive voltage V DRVand outputs it to the inverter, which is the delay circuit 222. Here, to solve the problems of the circuits that perform the controls (a) to (d) described later, the inverter drive voltage is controlled, but to improve the control linearity, the drive voltage V DRV The configuration is to generate the following.

[0036] 5, delay circuit 222 is configured as a single-stage inverter, but it may also be configured as multiple stages of inverters. Furthermore, when handling the I signal and Q signal as differential signals, this can be achieved by using the configuration of VCDL circuit 211B or VCDL circuit 211C shown in FIGS. 6 and 7. Only one stage of delay circuit 222 is shown in FIGS. 6 and 7.

[0037] Fig. 8 is a diagram showing an example of the configuration of the drive voltage generating circuit 221 that constitutes the VCDL circuit 211. Fig. 9 shows a detailed example of the configuration of the drive voltage generating circuit 221 in Fig. 8.

[0038] As shown in FIG. 8, the drive voltage generating circuit 221 includes an OTA (Operational Transconductance Amplifier) ​​261, a delay circuit replica 262, a minimum drive voltage generating circuit 263, and a drive amplifier 264.

[0039] The OTA261 has a control voltage V C and the reference voltage V REF is input. The OTA 261 operates by controlling the control voltage V C - Reference voltage V REF ) proportional to the current I OTA and generates a voltage V using a delay circuit replica 262 that is a replica of the delay circuit 222. replica This voltage V replica and the voltage V generated by the minimum drive voltage generating circuit 263. min The higher voltage of the two is buffered by the drive amplifier 264 to generate the drive voltage V DRV Generate.

[0040] As a result, the drive voltage generation circuit 221 can control the on-current of the delay circuit 222. Here, when replica > V min holds, the delay time of the delay circuit 222 is approximately t D ∝ 1 / I OTA . At this time, by using the delay circuit replica 262, it becomes possible to suppress PVT variations. However, due to the relationship of t D ∝ 1 / I OTA , it is inversely proportional to (control voltage V C - reference voltage V REF ), and it cannot always be said that the control linearity is good. Therefore, by using the minimum drive voltage generation circuit 263 to limit the minimum drive voltage, it becomes possible to improve the control linearity.

[0041] <Other configurations of the DLL circuit> The DLL circuit 141 may control the I signal and the Q signal complementarily (complementary control) to control the delay difference between those signals. FIG. 10 is a diagram showing another configuration example of the DLL circuit 141 that constitutes the IQ correction unit 118 in FIG. 1.

[0042] As shown in FIG. 10, in the DLL circuit 141A, the VCDL circuit 211 has a drive voltage generation circuit 221C, a delay circuit 222A, and a delay circuit 222B, and complementarily controls the I signal and the Q signal based on the VCDL control signal from the integration circuit 213.

[0043] FIG. 11 is a diagram showing a configuration example of the drive voltage generation circuit 221C that constitutes the VCDL circuit 211 in FIG. 10. Further, FIG. 12 shows a detailed configuration example of the drive voltage generation circuit 221C in FIG. 11.

[0044] As shown in FIG. 11, the drive voltage generation circuit 221C is composed of an OTA 271, a delay circuit replica 272A, a delay circuit replica 272B, a minimum drive voltage generation circuit 273, a drive amplifier 274A, and a drive amplifier 274B.

[0045] The OTA 271 receives the control voltage V Cand the reference voltage V REF Based on the current I OTA+ ,I OTA- Generates a current I OTA+ is generated by using a delay circuit replica 272A, which is a replica of the delay circuit 222A, to generate a voltage V replica+ This voltage V replica+ and the voltage V generated by the minimum drive voltage generating circuit 273. min The higher voltage of these two is buffered by the drive amplifier 274A to generate the drive voltage V DRV+ On the other hand, the current I OTA- is generated by using a delay circuit replica 272B, which is a replica of the delay circuit 222B, to generate a voltage V replica- This voltage V replica- and voltage V min The higher voltage of these two is buffered by the drive amplifier 274B to generate the drive voltage V DRV- is generated. The driving voltage V DRV+ is output to the delay circuit 222A, and the driving voltage V DRV- is output to delay circuit 222B.

[0046] The driving voltage V in the VCDL circuit 211 DRV By using complementary control, even-order nonlinearity can be canceled, making it possible to achieve higher control linearity. For example, the delay time t for (control voltage - reference voltage) = V1 D If 1 is the following equation (3), the complementary delay time t D 2, by having the following equation (4), the delay time difference between these two becomes the following equation (5), so the even-order terms of V1 can be canceled. D 1 - t D 2 is proportional to V1 and can achieve high control linearity.

[0047] t D 1 = a0 + a1 * V1 + a2 * V1 2 ···(3) t D 2 = a0 +a1 * (-V1) + a2 * (-V1) 2···(4) t D 1 - t D 2 = 2 * a1 * V1 ···(5)

[0048] <Other configurations of the IQ correction unit> The IQ correction unit 118 may be configured not only by a DLL circuit but also by other circuits such as a PPF (Poly Phase Filter) circuit. FIG. 13 is a diagram showing another configuration example of the IQ correction unit 118 in FIG. 1.

[0049] As shown in FIG. 13, the IQ correction unit 118A is composed of a PPF circuit 311 with four stages of filters consisting of resistors and capacitors, a phase comparison circuit 312, an integration circuit 313, and a control voltage generation circuit 314. In the IQ correction unit 118A, the PPF circuit 311 operates based on the control voltage from the control voltage generation circuit 314, so that the I signal and the Q signal can be controlled, and the IQ error of the LO signal can be corrected.

[0050] <Other configurations of the switching unit> The configuration of the switching unit that switches between the on state and the off state of the IQ correction unit 118 having the DLL circuit 141 is not limited to a selector, and other configurations may be used. FIG. 14 is a diagram showing a configuration example of the switching unit.

[0051] The configuration shown in A of FIG. 14 corresponds to the configuration of FIG. 1, and a selector 142 is provided as the switching unit. The selector 142 switches between the on state and the off state of the IQ correction unit 118 according to the input signal (ON / OFF signal) according to the LO signal frequency set in the PLL circuit 116.

[0052] Also, as shown in B of FIG. 14, the DLL circuit 141 is composed of a VCDL circuit 411, a DLL-FB circuit 412, and a selector 413. By setting the control voltage of the VCDL circuit 411 to a fixed voltage, the DLL circuit 141 can be effectively turned off. With this configuration, the on state and the off state of the IQ correction unit 118 can be switched.

[0053] <Configuration of DCDL> In the above description, the DLL circuit 141 shows a configuration example using the VCDL circuit 211 on the premise of analog control, but a configuration capable of realizing digital control may also be used. Specifically, in the DLL circuit 141, the VCDL circuit 211 can be configured by replacing it with a DCDL (Digital Controlled Delay Line) circuit.

[0054] In this DCDL circuit, for example, digital control can be realized by using the drive voltage generation circuit 221D shown in FIG. 15. As shown in FIG. 15, the drive voltage generation circuit 221D is composed of a current DAC (Digital to Analog Converter) 511, a delay circuit replica 512, a minimum drive voltage generation circuit 513, and a drive amplifier 514.

[0055] The current DAC 511 converts the digital control signal D C input thereto into a current I DAC and converts it into a voltage V replica using the delay circuit replica 512 which is a replica of the delay circuit 222. This voltage V replica is compared with the voltage V min generated by the minimum drive voltage generation circuit 513, and the higher voltage of the two is buffered by the drive amplifier 514 to generate a drive voltage V DRV .

[0056] When the DLL circuit 141 is configured by digital control, the optimal value of the control input of the DCDL circuit can be stored in the memory and used as appropriate. Thereby, it is not necessary for the feedback circuit to always operate, and the power consumption can be reduced.

[0057] <Another Configuration of Delay Circuit Replica> The configuration of the delay circuit replica 262 of the drive voltage generation circuit 221 constituting the VCDL circuit 211 can be variously configured according to the delay circuit 222. FIG. 16 is a diagram showing a configuration example of the delay circuit replica 262.

[0058] The configuration of the delay circuit replica 262 shown in A of FIG. 16 corresponds to the configuration shown in FIG. 9. In B and C of FIG. 16, as other configurations of the delay circuit replica 262, a delay circuit replica 262B which is a configuration corresponding to the delay circuit 222 and a delay circuit replica 262C are illustrated.

[0059] The minimum drive voltage generation circuit 263 of the drive voltage generation circuit 221 that constitutes the VCDL circuit 211 is optimally constituted by a replica circuit, but it is also possible to be constituted by a DAC or the like. At this time, by storing the optimum value in the memory at the time of shipment, the influence of element variations for each individual can be reduced and it is possible to operate with the optimum value.

[0060] Note that although it will be repeated and the explanation is omitted, regarding the configurations of the delay circuit replicas 272A and 272B of the drive voltage generation circuit 221C shown in FIGS. 11 and 12, similarly, it is not limited to the configuration shown in A of FIG. 16, and for example, the configurations shown in B and C of FIG. 16 can be used.

[0061] <Other configurations of the VNA> In the measuring device 10 shown in FIG. 1, a configuration for correcting the IQ error of the received LO signal by the IQ correction unit 118 is shown, but it may also be a configuration for correcting the IQ error of the transmitted LO signal, or a configuration for correcting the IQ errors of the transmitted LO signal and the received LO signal.

[0062] FIG. 17 is a diagram showing another configuration example of an embodiment of a measuring device to which the present disclosure is applied. In FIG. 17, compared with the measuring device 10 shown in FIG. 1, a buffer 151 and an IQ correction unit 152 are provided instead of the buffer 117 and the IQ correction unit 118.

[0063] The IQ correction unit 152 is an IQ correction mechanism that corrects the IQ error of the LO signal (transmission LO signal), and is composed of a DLL circuit 161. A selector 162 is provided for the DLL circuit 161. The transmission LO signal and the output of the DLL circuit 161 (transmission LO signal after IQ error correction) are input to the selector 162, and one of the signals is output.

[0064] That is, the selector 162 functions as a switching unit (changeover switch) that is a mechanism for switching the ON state and OFF state of the IQ correction unit 152. The ON state is a state in which the DLL circuit 161 performs IQ error correction, and the transmission LO signal after IQ error correction is output. The OFF state is a state in which the DLL circuit 161 does not perform IQ error correction, and the transmission LO signal is output as is.

[0065] Fig. 18 is a diagram showing yet another example configuration of an embodiment of a measurement device to which the present disclosure is applied. In Fig. 18, measurement device 10B is provided with buffer 117 and IQ correction unit 118, as well as buffer 151 and IQ correction unit 152, as compared to measurement device 10 shown in Fig. 1 and measurement device 10A shown in Fig. 17.

[0066] In measurement device 10B, since both IQ correction section 118 and IQ correction section 152 are provided, IQ error correction can be performed on both the received LO signal and the transmitted LO signal. Also, since selector 142 is provided for DLL circuit 141 and selector 162 is provided for DLL circuit 161, it is possible to switch IQ correction section 118 between on and off states and IQ correction section 152 between on and off states.

[0067] As described above, the measurement device 10 (including the measurement device 10A and the measurement device 10B) to which the present disclosure is applied includes a PLL circuit 116 that is commonly used to generate the transmission RF signal and the reception LO signal, which are high-frequency signals with different frequencies; an IQ correction unit (at least one of the IQ correction units 118 and 152) that corrects the IQ error of the LO signal used in generating at least one of the transmission RF signal and the reception LO signal; and a switching unit (at least one of the selector 142 and the selector 162) that switches between an on state in which correction is performed by the IQ correction unit and an off state in which correction is not performed.

[0068] With this configuration, the measurement apparatus 10 to which the present disclosure is applied can, for example, switch between the on and off states of the IQ correction unit 118 and the IQ correction unit 152 according to the LO signal frequency, thereby ensuring good time error precision across a range from low frequencies to high frequencies. As a result, the measurement apparatus 10 can perform more accurate measurements of the S parameters of the DUT under test.

[0069] Here, there are two configurations for generating a transmission RF signal and a reception LO signal, which are high-frequency signals with different frequencies, in a vector network analyzer: a 2-PLL configuration in which separate PLL circuits are used to generate the transmission RF signal and the reception LO signal, and a 1-PLL configuration in which a common PLL circuit is used to generate one of the signals by frequency conversion using a mixer. The 1-PLL configuration is disclosed in the above-mentioned Patent Document 1. These two configurations have the following problems.

[0070] In a 2-PLL configuration, an LC-VCO (Voltage Controlled Oscillator) with relatively good phase noise characteristics is essential at high frequencies above 1 GHz, but because each of the multiple PLL circuits requires an oscillator using an inductor, problems with magnetic field coupling arise. To avoid this, it is necessary to increase the VCO frequency, which results in increased power consumption.

[0071] In a 1-PLL configuration, image signals caused by IQ errors in the LO signal degrade VNA measurement accuracy. This effect is particularly pronounced at high frequencies, and to prevent this degradation in VNA measurement accuracy, measures to reduce relative variations are required to reduce IQ errors, which results in increased power consumption.

[0072] On the other hand, IQ correction functions are used in general transceiver configurations. For example, the following document A discloses technology related to IQ correction functions in transceivers. By applying these technologies to a 1-PLL configuration in a vector network analyzer, it becomes possible to achieve a configuration that combines a 1-PLL configuration with an IQ correction mechanism.

[0073] Document A: Japanese Patent Application Laid-Open No. 2016-201619

[0074] In the 1-PLL configuration + IQ correction mechanism configuration, an IQ correction mechanism can be provided for either the transmit RF signal or the receive LO signal. However, even in the 1-PLL configuration + IQ correction mechanism configuration, because vector network analyzers generally have a wide operating frequency range, the effect of errors in the IQ correction mechanism becomes large, especially when the LO signal frequency is low, resulting in degradation of characteristics.

[0075] As a VCDL circuit used in a DLL circuit, for example, a circuit that performs the following controls (a) to (d) is assumed.

[0076] (a) Bias current control using CML (b) Bias current control using an inverter (c) Load capacity control using an inverter (d) Drive voltage control using an inverter

[0077] These control methods each have the following problems: (a) control is difficult to operate at low voltage, (b) control is good at low voltage operation but difficult at high speed, and (c) and (d) control are good at low voltage and high speed operation but have low control linearity, making them difficult to use in DLL circuits where performance is important.

[0078] For example, the control of (b) is described in the following document B, and the control of (d) is described in the following document C.

[0079] Document B: Japanese Patent Application Laid-Open No. 2009-5214 Document C: Japanese Patent Application Laid-Open No. 2009-281888

[0080] As described above, the 1-PLL configuration plus IQ correction mechanism configuration can suppress measurement errors caused by image signals by incorporating the IQ correction mechanism. However, a vector network analyzer requires a relatively wide operating frequency range. Furthermore, when using the vector network analyzer to measure the propagation delay of a DUT, time error precision is required. The IQ correction mechanism can be configured using a DLL circuit or similar, but because it generally uses a period as a reference for error correction, it tends to be difficult to ensure time error precision at low frequencies. Furthermore, when a circuit performing the controls (a) through (d) is used as the VCDL circuit used in the DLL circuit, the problems described above arise.

[0081] Therefore, in the measurement device 10 to which the present disclosure is applied, when using a configuration of 1-PLL configuration + IQ correction mechanism (IQ correction unit), an IQ correction unit (at least one of IQ correction units 118 and 152) that corrects the IQ error of the LO signal used in generating at least one of the transmitted RF signal and the received LO signal is provided, as well as a switching unit (at least one of selector 142 and selector 162) that switches between an ON state in which correction is performed by the IQ correction unit and an OFF state in which correction is not performed. This allows, for example, the ON state and OFF state of the IQ correction unit 118 and the IQ correction unit 152 to be switched depending on the LO signal frequency, making it possible to ensure good time error precision across a range from low frequencies to high frequencies. As a result, more accurate measurements can be performed.

[0082] Furthermore, in the measurement device 10 to which the present disclosure is applied, the VCDL circuit 211 constituting the DLL circuit 141 of the IQ correction unit 118 (the DLL circuit 161 of the IQ correction unit 152) controls the inverter drive voltage, but in order to improve the control linearity, the drive voltage V DRV By adopting a configuration for generating the above, the problems of the circuits that perform the above-mentioned controls (a) to (d) are solved.

[0083] <Modification> In the above description, the DLL circuit 141 is used for IQ error correction in a vector network analyzer, but it can also be applied to, for example, IQ error correction in a wireless communication transmitter / receiver circuit. Alternatively, it can be used as a DLL circuit for clock skew adjustment, as shown in Fig. 19. Fig. 19 shows a configuration in which clock skew is adjusted by a DLL circuit 141B that is configured from a VCDL circuit 611 having a drive voltage generation circuit 621 and a delay circuit 622, a phase comparison circuit 612, and an integration circuit 613.

[0084] 20, it can be used for timing adjustment in a multi-phase clock generation circuit used in wired communications, etc. In FIG. 20, the multi-phase clock generation circuit is configured by a VCDL circuit 711 having a drive voltage generation circuit 721 and a delay circuit 722, a phase comparison circuit 712, and a DLL circuit 141C configured by an integration circuit 713.

[0085] It should be noted that the embodiments of the present disclosure are not limited to the above-described embodiments, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0086] The present disclosure can also be configured as follows.

[0087] (1) a PLL (Phase Locked Loop) circuit commonly used to generate a transmission RF (Radio Frequency) signal and a reception LO (Local Oscillator) signal, which are high-frequency signals with different frequencies; an IQ correction unit that corrects an IQ error of an LO signal used in generating at least one of the transmission RF signal and the reception LO signal; a switching unit that switches between an ON state in which the IQ correction unit performs correction and an OFF state in which the correction unit does not perform correction; A measuring device comprising: (2) The switching unit switches between the on state and the off state in accordance with an LO signal frequency. The measuring device according to (1) above. (3) The switching unit is in the OFF state in a region where the LO signal frequency is lower than a reference frequency, and is in the ON state in a region where the LO signal frequency is higher than the reference frequency. The measuring device according to (2) above. (4) The IQ correction unit has a DLL (Delay Locked Loop) circuit that corrects an IQ error of the LO signal. The measuring device according to (1) above. (5) The DLL circuit has a VCDL (Voltage Controlled Delay Line) circuit, The VCDL includes a drive voltage generating circuit that generates a drive voltage for the delay circuit based on an input control voltage, and the delay circuit. The measuring device according to (4) above. (6) the drive voltage generating circuit includes an OTA (Operational Transconductance Amplifier) ​​that generates a current proportional to the control voltage, and a replica circuit of the delay circuit; The drive voltage is generated using the OTA and the replica circuit. The measuring device according to (5) above. (7) The drive voltage generating circuit further includes a minimum drive voltage generating circuit that limits the minimum value of the drive voltage. The measuring device according to (6) above. (8) The DLL circuit has a VCDL circuit that controls the delay difference between the I signal and the Q signal by controlling them complementarily. The measuring device according to (4) above. (9) The IQ correction unit has a PPF (Poly Phase Filter) circuit that corrects an IQ error of the LO signal. The measuring device according to (1) above. (10) The switching unit is a selector that switches between an LO signal that has been corrected by the IQ correction unit and an LO signal that has not been corrected by the IQ correction unit, and outputs the selected signal in accordance with an input signal corresponding to the LO signal frequency. The measuring device according to (3) above. (11) the transmission RF signal is generated by frequency-converting a transmission IF (Intermediate Frequency) signal using a transmission LO signal by a transmission mixer; a first receiver that receives the transmit RF signal and performs frequency conversion to a receive IF signal using the receive LO signal by a first receive mixer, thereby measuring the transmit signal; a second receiver that receives a portion of the transmission RF signal reflected by the device under test and measures the reflected signal by frequency-converting the portion into a reception IF signal using the reception LO signal by a second reception mixer; a third receiver that receives a portion of the transmission RF signal that has passed through the device under test, and measures the passed signal by frequency-converting the portion into a reception IF signal using the reception LO signal by a third reception mixer; Equipped with A vector network analyzer capable of measuring S parameters of the device under test based on the transmission signal, the reflection signal, and the transmission signal. The measuring device according to any one of (1) to (10) above. [Explanation of symbols]

[0088] 10,10A,10B Measuring equipment, 111 IF signal generator, 112 Transmitting mixer, 113 Transmitting amplifier, 114 Directional coupler, 115R,115A,115B Receiver, 116 PLL circuit, 117 Buffer, 118 IQ correction unit, 131 LNA, 132 Receiving mixer, 133 Filter, 134 ADC, 135 Buffer, 141 DLL circuit, 142 Selector, 151 Buffer, 152 IQ correction unit, 161 DLL circuit, 162 Selector, 211 VCDL circuit, 212 Phase comparator, 213 Integration circuit, 221 Drive voltage generation circuit, 222 Delay circuit, 261,271 OTA, 262,272 Delay circuit replica 263,273 Minimum drive voltage generation circuit, 264,274 Drive amplifier, 311 PPF circuit, 312 Phase comparator circuit, 313 Integration circuit, 314 Control voltage generation circuit, 411 VCDL circuit, 412 DLL-FB circuit, 413 Selector, 511 Current DAC, 512 Delay circuit replica, 513 Minimum drive voltage generation circuit, 514 Drive amplifier

Claims

1. a PLL (Phase Locked Loop) circuit commonly used to generate a transmission RF (Radio Frequency) signal and a reception LO (Local Oscillator) signal, which are high-frequency signals with different frequencies; an IQ correction unit that corrects an IQ error of an LO signal used in generating at least one of the transmission RF signal and the reception LO signal; a switching unit that switches between an ON state in which the IQ correction unit performs correction and an OFF state in which the correction unit does not perform correction; A measuring device comprising:

2. The switching unit switches between the on state and the off state in accordance with an LO signal frequency. The measuring device according to claim 1 .

3. The switching unit is in the OFF state in a region where the LO signal frequency is lower than a reference frequency, and is in the ON state in a region where the LO signal frequency is higher than the reference frequency. The measuring device according to claim 2 .

4. The IQ correction unit has a DLL (Delay Locked Loop) circuit that corrects an IQ error of the LO signal. The measuring device according to claim 1 .

5. The DLL circuit has a VCDL (Voltage Controlled Delay Line) circuit, The VCDL includes a drive voltage generating circuit that generates a drive voltage for the delay circuit based on an input control voltage, and the delay circuit.

5. The measuring device according to claim 4.

6. the drive voltage generating circuit includes an OTA (Operational Transconductance Amplifier) ​​that generates a current proportional to the control voltage, and a replica circuit of the delay circuit; The drive voltage is generated using the OTA and the replica circuit. The measuring device according to claim 5 .

7. The drive voltage generating circuit further includes a minimum drive voltage generating circuit that limits the minimum value of the drive voltage. The measuring device according to claim 6.

8. The DLL circuit has a VCDL circuit that controls the delay difference between the I signal and the Q signal by controlling them complementarily.

5. The measuring device according to claim 4.

9. The IQ correction unit has a PPF (Poly Phase Filter) circuit that corrects an IQ error of the LO signal. The measuring device according to claim 1 .

10. The switching unit is a selector that switches between an LO signal that has been corrected by the IQ correction unit and an LO signal that has not been corrected by the IQ correction unit, and outputs the switched LO signal in accordance with an input signal corresponding to the LO signal frequency. The measuring device according to claim 3 .

11. the transmission RF signal is generated by frequency-converting a transmission IF (Intermediate Frequency) signal using a transmission LO signal by a transmission mixer; a first receiver that receives the transmit RF signal and performs frequency conversion to a receive IF signal using the receive LO signal by a first receive mixer, thereby measuring the transmit signal; a second receiver that receives a portion of the transmission RF signal reflected by the device under test and measures the reflected signal by frequency-converting the portion into a reception IF signal using the reception LO signal by a second reception mixer; a third receiver that receives a portion of the transmission RF signal that has passed through the device under test, and measures the passed signal by frequency-converting the portion into a reception IF signal using the reception LO signal by a third reception mixer; Equipped with A vector network analyzer capable of measuring S parameters of the device under test based on the transmission signal, the reflection signal, and the transmission signal. The measuring device according to claim 1 .

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