Electro-optical devices and electronic equipment

Abstract

To secure light emission period satisfactorily without accelerating line sequential writing.SOLUTION: In an odd-numbered frame V_odd, a plurality of scan lines 12 is sequentially selected, a first selector 122 of a pixel circuit 110 electrically connects one end of a capacitive element C1a to a data line 14 when a scan line 12 corresponding to the one pixel circuit 110 is selected, and a second selector 123 electrically connects one end of a capacitive element C1b to a gate node g of a transistor 121. In an even-numbered frame V_eve, the plurality of scan lines 12 is sequentially selected, when the scan line 12 is selected, the first selector 122 electrically connects the one end of the capacitive element C1b to the data line 14, and the second selector 123 electrically connects the one end of the capacitive element C1a to the gate node g.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to an electro-optical device and an electronic device. [Background technology]

[0002] Electro-optical devices using, for example, OLEDs as light-emitting elements are known. OLED stands for Organic Light Emitting Diode. In such electro-optical devices, pixel circuits including transistors for passing current through the light-emitting elements are provided corresponding to the pixels of the displayed image. The transistors supply current to the light-emitting elements according to the gradation level. This causes the light-emitting elements to emit light at a brightness according to the current. As an example of a technique for driving such light-emitting elements, a technique is known in which data signals are written sequentially during one frame period and then the light-emitting elements are made to emit light all at once, as described in Patent Documents 1 and 2, for example. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2018-28590 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-34038 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in Patent Documents 1 and 2, the process from line-sequential writing of data signals to simultaneous light emission of light-emitting elements must be performed within a limited time of one frame period, which poses the problem that the line-sequential writing must be performed at high speed, or the light emission period cannot be sufficiently secured, resulting in a dark displayed image. [Means for solving the problem]

[0005] an electro-optical device according to one aspect of the present disclosure, including a plurality of pixel circuits arranged corresponding to intersections of data lines and a plurality of scanning lines, each of the pixel circuits including a first selector, a second selector, a first capacitive element, a second capacitive element, a drive transistor, and a light-emitting element, the drive transistor being capable of supplying a current to the light-emitting element according to a voltage of a gate node; in a first frame, the plurality of scanning lines are selected in sequence, and when a scanning line corresponding to the one pixel circuit is selected, the first selector in one pixel circuit of the plurality of pixel circuits electrically connects one end of the first capacitive element to the data line, and the second selector in the one pixel circuit electrically connects one end of the second capacitive element to the gate node; in a second frame different from the first frame, the plurality of scanning lines are selected in sequence, and when the scanning line is selected, the first selector in the one pixel circuit electrically connects one end of the second capacitive element to the data line, and the second selector in the one pixel circuit electrically connects one end of the first capacitive element to the gate node; [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram of a head-mounted display to which an electro-optical device according to a first embodiment is applied. [Figure 2] FIG. 1 is a perspective view showing a configuration of a head-mounted display. [Figure 3] FIG. 2 is a diagram illustrating an optical configuration of a head-mounted display. [Figure 4] FIG. 1 is a perspective view of an electro-optical device. [Figure 5] FIG. 2 is a block diagram showing the electrical configuration of the electro-optical device. [Figure 6] FIG. 2 is a diagram illustrating a pixel circuit in an electro-optical device. [Figure 7] 4 is a timing chart showing the operation of the electro-optical device. [Figure 8] 10 is a timing chart showing the operation of a first modified example of the electro-optical device. [Figure 9]10 is a timing chart showing the operation of a second modified example of the electro-optical device. [Figure 10] 10 is a timing chart showing the operation of a third modified example of the electro-optical device. [Figure 11] FIG. 2 is a diagram showing a pixel circuit of the electro-optical device according to the first embodiment. [Figure 12] FIG. 10 is a diagram showing a pixel circuit of an electro-optical device according to a second embodiment. [Figure 13] 4 is a timing chart showing the operation of the electro-optical device. [Figure 14] 10 is a flowchart illustrating the operation of the electro-optical device. [Figure 15] FIG. 10 is a diagram showing a pixel circuit according to a second embodiment. [Figure 16A] 10A and 10B are diagrams illustrating display distortion in an electro-optical device. [Figure 16B] 10A and 10B are diagrams illustrating display distortion in an electro-optical device. [Figure 16C] 10A and 10B are diagrams illustrating display distortion in an electro-optical device. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, electro-optical devices according to embodiments of the present invention will be described with reference to the drawings. In each drawing, the dimensions and scale of each part are appropriately different from the actual ones. Furthermore, the embodiments described below are preferred examples, and therefore various technically preferable limitations are applied, but the scope of the present invention is not limited to these embodiments unless otherwise specified in the following description to the effect that the present invention is limited.

[0008] First Embodiment 1 is a block diagram showing the configuration of a head-mounted display system 1, which is an electronic device to which an electro-optical device according to a first embodiment is applied. As shown in this figure, the head-mounted display system 1 includes a main controller 5 and a headset 300. The headset 300 includes electro-optical devices 10L and 10R and a timing controller 350.

[0009] The electro-optical device 10L is for the left eye, and the electro-optical device 10R is for the right eye, and each is a microdisplay that displays a color image. The electro-optical devices 10L and 10R have a plurality of pixel circuits and a drive circuit for driving the pixel circuits formed on a semiconductor substrate. The semiconductor substrate is typically a silicon substrate, but other semiconductor substrates may also be used.

[0010] The main controller 5 outputs video data Vid_L representing an image to be viewed by the left eye, video data Vid_R representing an image to be viewed by the right eye, and a control signal Ctr. The video data Vid_L and Vid_R specify the gradation level of pixels in the image to be displayed, for example, in 8 bits.

[0011] The timing controller 350 receives a control signal Ctr and video data Vid_L and Vid_R from the main controller 5 and generates timing signals for driving the electro-optical devices 10L and 10R based on the received signals. The timing signals Sync are signals for vertically and horizontally scanning the electro-optical devices 10L and 10R, and specifically include a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. Of these, the vertical synchronization signal specifies the start of vertical scanning in the electro-optical devices 10L and 10R, and the horizontal synchronization signal specifies the start of horizontal scanning in the electro-optical devices 10L and 10R. The clock signal is used as a synchronization signal when transferring the video data Vid_L to the electro-optical device 10L and the video data Vid_R to the electro-optical device 10R. Furthermore, the timing controller 350 transfers the received video data Vid_L to the electro-optical device 10L, and transfers the received video data Vid_R to the electro-optical device 10R.

[0012] FIG. 2 is a perspective view showing a headset of a head-mounted display system, and FIG. 3 is a diagram showing the optical configuration of the headset. As shown in Fig. 2, the headset 300 has temples 310, a bridge 320, and lenses 301L and 301R in appearance similar to ordinary eyeglasses. As shown in Fig. 3, the headset 300 is provided with an electro-optical device 10L for the left eye and an electro-optical device 10R for the right eye near the bridge 320 and behind the lenses 301L and 301R (below in the figure). A timing controller 350 is built into the headset 300 and generates a timing signal Sync for driving the electro-optical devices 10L and 10R based on a signal received from the main controller 5 via a cable 7.

[0013] The image display surface of the electro-optical device 10L is disposed on the left side in FIG. 3. As a result, the image displayed by the electro-optical device 10L is emitted in the 9 o'clock direction in the figure via the optical lens 302L. The half mirror 303L reflects the image displayed by the electro-optical device 10L in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction. The image display surface of the electro-optical device 10R is disposed on the right side, opposite the electro-optical device 10L. As a result, the image displayed by the electro-optical device 10R is emitted in the 3 o'clock direction in the figure via the optical lens 302R. The half mirror 303R reflects the image displayed by the electro-optical device 10R in the 6 o'clock direction while transmitting light incident from the 12 o'clock direction.

[0014] In this configuration, a user wearing the headset 300 can observe the images displayed by the electro-optical devices 10L and 10R in a see-through state, superimposed on the outside scenery. Furthermore, in the headset 300, when the image for the left eye is displayed on the electro-optical device 10L and the image for the right eye is displayed on the electro-optical device 10R among the binocular images with parallax, the wearer can perceive the displayed images as if they have depth and a three-dimensional effect. However, if there is no need to perceive a three-dimensional effect, the video data Vid_L and Vid_R may be shared and the same video may be displayed.

[0015] Since the electro-optical devices 10L and 10R have the same configuration, in the following description, no distinction will be made between the electro-optical devices 10L and 10R, and the suffixes L and R will be omitted and the reference number will simply be 10, and the video data Vid_L and Vid_R will also be simply referred to as video data Vid.

[0016] Fig. 4 is a perspective view showing the electro-optical device 10, and Fig. 5 is a block diagram showing the electrical configuration of the electro-optical device 10. The electro-optical device 10 includes light-emitting elements formed on a semiconductor substrate or a glass substrate. In this embodiment, an OLED is used as an example of the light-emitting element. 4, the electro-optical device 10 is housed in a frame-shaped case 192 that is open in the display region 100. The electro-optical device 10 is connected to one end of an FPC board 194. FPC is an abbreviation for Flexible Printed Circuits.

[0017] The other end of the FPC board 194 is provided with a plurality of terminals 196 that are connected to a timing controller 350. As shown in Figure 5, the electro-optical device 10 is supplied with video data Vid, a timing signal Sync, and the like via the FPC board 194. In the figure, the X direction indicates the direction in which the scanning lines extend in the electro-optical device 10, and the Y direction indicates the direction in which the data lines extend. The two-dimensional plane defined by the X and Y directions is the substrate surface of the semiconductor substrate. The Z direction is perpendicular to the X and Y directions and indicates the emission direction of light emitted from the light-emitting element.

[0018] As shown in FIG. 5, the electro-optical device 10 is roughly divided into a control circuit 30, a data signal output circuit 50, a display area 100, and a scanning line driving circuit 120. In the display area 100, m rows of scanning lines 12 are arranged along the X direction in the figure, and n columns of data lines 14 are arranged along the Y direction in the figure so as to be electrically insulated from each other. Note that m and n are integers of 2 or more.

[0019] In the display area 100, pixel circuits 110 are provided corresponding to the intersections of m rows of scanning lines 12 and n columns of data lines 14. Therefore, the pixel circuits 110 are arranged in a matrix of m rows and n columns in the figure. To distinguish the rows in the matrix arrangement, they may be referred to as 1, 2, 3, ..., (m-1), mth row from the top in the figure. Similarly, to distinguish the columns in the matrix, they may be referred to as 1, 2, 3, ..., (n-1), nth column from the left in the figure. In order to generalize and explain the scanning lines 12, an integer i of 1 or more and m or less will be used. Similarly, in order to generalize and explain the data lines 14, an integer j of 1 or more and n or less will be used.

[0020] The control circuit 30 controls each component based on the video data Vid and timing signal Sync supplied from the main controller 5 and timing controller 350. As described above, the video data Vid specifies the gradation level of a pixel in, for example, 8 bits, but the brightness characteristics indicated by the gradation level of a pixel in an image to be displayed do not match the luminance of the pixel circuit 110 corresponding to that pixel, or more specifically, the luminance characteristics of the OLED included in the pixel circuit 110. Therefore, in order to make the OLED emit light at a brightness corresponding to the gradation level specified by the video data Vid, the control circuit 30 up-converts the 8 bits of the video data Vid to, for example, 10 bits in this embodiment, and outputs the up-converted data as video data Vdata that specifies the brightness of the OLED. For such up-conversion, a look-up table is used that stores in advance the correspondence between the 8 bits of input video data Vid and the 10 bits of output video data Vdata. The control circuit 30 also generates various control signals to control each section, as will be described in detail later.

[0021] The scanning line driving circuit 120 is arranged in m rows and n columns under the control of the control circuit 30. The scanning line driving circuit 120 is a circuit for driving the pixel circuits 110 for each row. , 3, ..., (m-1), the m-th scanning line 12 is sequentially supplied with a scanning signal Scan _ (1) Scan _ (2)... , Scan _ (m-1), Scan _ (m) is supplied to the i-th scanning line 12. The scanning signal is Scan _ It is written as (i). In addition, Fig. 5 In order to avoid complicating the drawing, one scanning line 12 is shown as one line. In reality, the number of scanning lines per row is "2". The two scanning lines 12 corresponding to the i-th row The scanning signal supplied to _ can_a(i) and S _ can_b(i).

[0022] The data signal output circuit 50 is a circuit that outputs a data signal of a voltage according to brightness to the pixel circuits 110 located in the row selected by the scanning line driving circuit 120 . In detail, the data signal output circuit 50 latches one row of video data Vdata supplied from the control circuit 30, converts the latched one row of video data Vdata into an analog data signal, and outputs it as a data signal to the corresponding data line 14. The potentials of the data lines 14 in the 1st, 2nd, ..., (n-1), and nth columns are respectively represented as Vd(1), Vd(2), ..., Vd(n-1), and Vd(n). In general, the potential of the data line 14 in the jth column is represented as Vd(j). In this explanation, the reference for zero voltage is the L level (ground potential) of the logical level, but except for the voltage between two points (threshold voltage), the terms potential and voltage are not used strictly in this explanation. Also, in this explanation, power supply refers to a voltage or potential that is almost constant over time.

[0023] 6 is a diagram showing a pixel circuit 110. The pixel circuits 110 arranged in m rows and n columns are electrically identical to one another. For this reason, the pixel circuits 110 will be described by taking the pixel circuit 110 located in the ith row and jth column as a representative.

[0024] As shown in the figure, the pixel circuit 110 includes an OLED 130, p-channel MOS transistors 121, 122a, 122b, 123a, 123b, and 124, and capacitance elements C1a and C1b (MOS is an abbreviation for Metal-Oxide-Semiconductor field-effect transistor). A scanning signal Scan_a(i) is supplied to the pixel circuit 110 in the i-th row via one scanning line 12a of the two scanning lines 12 corresponding to the i-th row, and a scanning signal Scan_b(i) is supplied via the other scanning line 12b. Furthermore, the control circuit 30 commonly supplies the selection signals Sel_a, Sel_b and the control signal Enb to all of the pixel circuits 110 in the 1st to mth rows.

[0025] The OLED 130 is a light-emitting element in which a light-emitting functional layer 132 is sandwiched between a pixel electrode 131 and a common electrode 133. The pixel electrode 131 functions as an anode, and the common electrode 133 functions as a cathode. The common electrode 133 is light-reflective and light-transmissive. In the OLED 130, when a current flows from the anode to the cathode, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer 132 to generate excitons, thereby emitting white light.

[0026] In the case of a color display, the generated white light resonates in an optical resonator composed of, for example, a reflective layer and a semi-reflective semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to one of the colors R (red), G (green), and B (blue). A color filter corresponding to the color is provided on the light exit side of the optical resonator. Therefore, the light emitted from the OLED 130 is colored by the optical resonator and color filter before being viewed by the observer. Note that the optical resonator is not shown. Furthermore, when the electro-optical device 10 simply displays a monochromatic image with only light and dark, the color filter is omitted.

[0027] In the pixel circuit 110 in the ith row and jth column, the source node of the transistor 122a is connected to the jth column data line 14, the drain node is connected to one end of the capacitance element C1a and the source node of the transistor 123a, and the gate node is connected to the scanning line 12a. The source node of the transistor 122b is connected to the jth column data line 14, the drain node is connected to one end of the capacitance element C1b and the source node of the transistor 123b, and the gate node is connected to the scanning line 12b. The other end of the capacitance element C1a and the other end of the capacitance element C1b are connected to the power supply wiring 116 to which a high power supply potential ELvdd is supplied.

[0028] The gate node of the transistor 123a is connected to the control line 13a through which the selection signal Sel_a is supplied. The gate node of the transistor 123b is connected to the control line 13b through which the selection signal Sel_b is supplied. The drain nodes of the transistors 123a and 123b are connected to the gate node g of the transistor 121.

[0029] In the transistor 121, a source node s is connected to the power supply wiring 116, and a drain node d is connected to the source node of the transistor 124. In the transistor 124, a control signal Enb is supplied to the gate node, and a drain node is connected to the pixel electrode 131 of the OLED 130. In the OLED 130, a low power supply potential ELvss is supplied to the common electrode 133 via the power supply wiring 118.

[0030] In this description, "electrically connected" or simply "connected" means a direct or indirect connection or coupling between two or more elements, and includes, for example, a connection between two or more elements in a semiconductor substrate via different wiring layers and contact holes, even if the connection is not direct.

[0031] FIG. 7 is a timing chart for explaining the operation of the electro-optical device 10. As shown in FIG. The operation of the electro-optical device 10 is divided into odd-numbered frames V_odd and even-numbered frames V_eve. The odd-numbered frame V_odd and the even-numbered frame V_eve are merely used for convenience to distinguish between consecutive frames. In this description, a frame refers to the period required to display one frame of an image specified by the video data Vid. If the length of one frame is the same as the vertical synchronization period, for example, if the frequency of the vertical synchronization signal included in the timing signal Sync is 60 Hz, then the period is 16.7 milliseconds, which corresponds to one cycle of the vertical synchronization signal.

[0032] In the odd-numbered frame V_odd, the scan signals Scan_a(1), Scan_a(2), ..., Scan_a(m-1), Scan(m)_a sequentially and exclusively go to the L level for each horizontal scanning period H. In the even-numbered frame V_eve, the scan signals Scan_b(1), Scan_b(2), ..., Scan_b(m-1), Scan(m)_b sequentially and exclusively go to the L level for each horizontal scanning period H.

[0033] After the scan signal Scan_a(m) changes to the H level, the scan signal Scan_b(1) changes to the L level. and the period from when the scan signal Scan_b(m) changes to the H level to when the scan signal Scan_a( 1) changes to L level is the vertical scanning blanking period V _ It's blnk. In this embodiment, the control signal Enb is applied to the vertical scanning blanking period V _ H level in blnk become. In the odd frame V_odd, the scanning signal Scan_a(1) is changed to the L level and then the scanning signal During the period until the signal Scan_a(m) changes to the H level and during the even frame V_eve After the scan signal Scan_b(1) changes to the L level, the scan signal Scan_b(m) changes to the H level. In this embodiment, for convenience, the period from the odd frame to the The horizontal effective scanning period in the even frame V_odd is made to coincide with the light emission period L_eve, and The horizontal effective scanning period in is made to coincide with the light emission period L_odd. In this embodiment, the control signal Enb is at the L level during the light emission periods L_eve and L_odd. becomes.

[0034] The vertical scanning blanking period V before the odd frame V_odd begins _In blnk, the selection signal Sel_ a changes from L to H level first, and the selection signal Sel_b changes from H to L level later. Also, during the vertical scanning blanking period V before the even frame V_eve starts, _ On blnk In this case, the selection signal Sel_b changes from L to H level first, and the selection signal Sel_a changes from L to H level first. After that, it changes from H to L level. That is, the selection signals Sel_a and Sel_b are in a phase shifted relationship of 180 degrees.

[0035] First, the operation of the odd-numbered frame V_odd will be described. When the scan signal Scan_a(i) goes low in the odd-numbered frame V_odd, the transistor 122a in the pixel circuit 110 at row i and column j is turned on. During the period when the scan signal Scan_a(i) goes low, the scan signal Scan_b(i) is high, so the transistor 122b in the pixel circuit 110 at row i and column j is turned off.

[0036] In this description, the "on state" of a switching element or transistor means that both ends of the switching element or the source and drain nodes of a transistor are electrically closed, resulting in a low impedance state, while the "off state" of a switching element or transistor means that both ends of the switching element or the source and drain nodes are electrically open, resulting in a high impedance state.

[0037] During the period in which the scan signal Scan_a(i) is at L level in the odd-numbered frame V_odd, the data signal output circuit 50 converts the grayscale levels of the pixels in the ith row, column 1 to the ith row, column n indicated by the video data Vdata into analog potentials Vd(1) to Vd(n) and outputs them as data signals to the first to nth data lines 14. In terms of the jth column, the data signal output circuit 50 converts the grayscale level of the pixel in the ith row, column j to analog signal potential Vd(j) and outputs it as a data signal to the jth data line 14.

[0038] The data signal of the potential Vd(j) is held in the capacitance element C1a via the data line 14 in the jth column and the transistor 122a in the pixel circuit 110 in the i-th row and j-th column in this order. Although the pixel circuit 110 in the ith row and jth column has been described here, the data signal is also held in the capacitive element C1a in pixel circuits 110 in the ith row other than the jth column. In addition, in the odd frame V_odd, even in rows other than the i-th row, the scan signals Scan_a(1) to Scan_a(m) sequentially become L level, causing a data signal of a potential corresponding to the gradation level of the pixel to be held in the capacitive element C1a.

[0039] During the light emission period L_eve of the odd-numbered frame V_odd, the selection signal Sel_a is at H level, so the transistors 123a are turned off in all pixel circuits 110. Also, during the light emission period L_eve, the selection signal Sel_b is at L level, so the transistors 123b are turned on in all pixel circuits 110. Therefore, in all pixel circuits 110, one end of the capacitance element C1b is electrically connected to the gate node g of the transistor 121 via the transistor 123b, and the voltage held in the capacitance element C1b is applied between the gate node and the source node of the transistor 121. Furthermore, during the light emission period L_eve, the control signal Enb is at the L level, so that the transistor 124 is in the ON state.

[0040] Therefore, in the light emission period L_eve, in all pixel circuits 110, the transistor 121 passes a current corresponding to the voltage between the gate node and the source node, that is, the gray level of the pixel, to the OLED 130. The voltage held in the capacitance element C1b in the light emission period L_eve is based on the data signal supplied via the data line 14 in the even frame V_eve preceding the odd frame V_odd. Therefore, in the light emitting period L_eve of the odd-numbered frame V_odd, the OLEDs 130 in all pixel circuits 110 emit light with a luminance according to the data signal supplied in the previous even-numbered frame V_eve.

[0041] Next, the operation of the even frame V_eve will be described. When the scan signal Scan_b(i) goes low in the even frame V_eve, the transistor 122b in the pixel circuit 110 at row i and column j is turned on. During the period when the scan signal Scan_b(i) goes low, the scan signal Scan_a(i) is high, so the transistor 122a in the pixel circuit 110 at row i and column j is off.

[0042] During the period in which the scan signal Scan_b(i) is at L level in the even-numbered frame V_eve, the data signal output circuit 50 converts the grayscale levels of the pixels in the ith row, column 1 to the ith row, column n indicated by the video data Vdata into analog potentials Vd(1) to Vd(n) and outputs them as data signals to the first to nth data lines 14. In terms of the jth column, the data signal output circuit 50 converts the grayscale level of the pixel in the ith row, column j to an analog signal potential Vd(j) and outputs it as a data signal to the jth data line 14.

[0043] The data signal of the potential Vd(j) is held in the capacitance element C1b via the data line 14 in the jth column and the transistor 122b in the pixel circuit 110 in the i-th row and j-th column in this order. Although the pixel circuit 110 in the ith row and jth column has been described here, the data signal is also held in the capacitive element C1b in pixel circuits 110 in the ith row other than the jth column. In addition, in the even frame V_eve, even in rows other than the i-th row, the scan signals Scan_b(1) to Scan_b(m) sequentially become L level, causing a data signal of a potential corresponding to the gradation level of the pixel to be held in the capacitive element C1b.

[0044] During the light emission period L_eve, the selection signal Sel_b is at H level, so the transistors 123b are turned off in all pixel circuits 110. During the light emission period L_odd, the selection signal Sel_a is at L level, so the transistors 123a are turned on in all pixel circuits 110. Therefore, in all pixel circuits 110, one end of the capacitance element C1a is electrically connected to the gate node g of the transistor 121 via the transistor 123a, and the voltage held in the capacitance element C1a is applied between the gate node and the source node of the transistor 121. Furthermore, during the light emission period L_odd, the control signal Enb is at the L level, so that the transistor 124 is turned on.

[0045] In the light emission period L_odd, in all pixel circuits 110, the transistor 121 passes a voltage between the gate node and the source node, that is, a current according to the gray level of the pixel, to the OLED 130. The voltage held in the capacitive element C1a during the light emission period L_odd is based on the data signal supplied via the data line 14 during the previous odd-numbered frame V_odd, as described above. Therefore, in the light emitting period L_odd, the OLEDs 130 in all pixel circuits 110 emit light with a luminance according to the data signal supplied in the previous odd-numbered frame V_odd.

[0046] In this embodiment, in an odd-numbered frame V_odd, the potential of the data signal is held in the capacitive elements C1a sequentially from the first row to the mth row, and in the next even-numbered frame V_eve, the control signal Enb becomes L level, causing the OLEDs 130 in all pixel circuits 110 from the first row to the mth row to emit light simultaneously. On the other hand, in the even frame V_eve, the potential of the data signal is held in the capacitive elements C1b sequentially from the first row to the mth row, and in the next odd frame V_odd, the control signal Enb becomes L level, causing the OLEDs 130 in all pixel circuits 110 from the first row to the mth row to emit light simultaneously. In this manner, in this embodiment, the OLEDs 130 in all pixel circuits 110 emit light simultaneously in accordance with the voltage held in the previous frame.

[0047] Therefore, in this embodiment, high-speed operation is not required to hold the potential of the data signal in the capacitance element C1a or C1b from the first row to the mth row, and since the horizontal effective scanning period can be secured as the light emitting period L_eve or Lodd, the displayed image does not become dark.

[0048] Furthermore, according to this embodiment, when a user wearing the head-mounted display system 1 views an image displayed by the electro-optical device 10 superimposed on an actual landscape, the displayed image can be prevented from being distorted when the user shakes his or her head. This point will be described below.

[0049] 16A, 16B, and 16C are diagrams for explaining that a display image is visually distorted in a conventional configuration in which an OLED is made to emit light in a line-sequential manner. Note that a configuration in which an OLED is made to emit light in a line-sequential manner refers to a configuration in which an OLED is made to emit light almost simultaneously with a data signal being stored in a capacitive element by selecting a scan line, that is, a configuration in which an OLED is made to emit light for each scan line (line).

[0050] In these figures, the box T indicates the field of view of the user wearing the headset 300. In the field of view T, the electro-optical device 10 is a rectangular Condition Let's assume that we want to display object Dj. In this case, as shown in the order of Figures 16A, 16B, and 16C, When the user turns his head to the right and the field of view T moves suddenly, the OLEDs are illuminated in a line-sequential manner. In this configuration, the timing at which the object Dj starts to emit light differs for each line. , the upper edge of the object Dj moves relative to the scenery by shaking the head. The in (row) Lns is the first to start emitting light, and is located at the middle line Ln c is from line Lns The lowermost line Lnf also starts to emit light with a delay, and the lowermost line Lnf starts to emit light last. In this way, the lower the object Dj is, the more the line moves relative to the moving scene. Since the start timing of the image is delayed, the user will notice that the object Dj, which is displayed as a rectangle, The shape appears distorted like Djp.

[0051] In contrast, in this embodiment, the timing at which the OLED 130 starts emitting light does not differ for each line, but is executed simultaneously for all pixel circuits 110. Therefore, in this embodiment, it is possible to prevent the displayed image from being distorted when the user shakes their head.

[0052] <Modification of the first embodiment> The first embodiment described above can be modified as follows.

[0053] In the first embodiment, as shown in FIG. 7, when the scan signal Scan_b(m) changes to the H level, After that, the selection signal Sel_a changes from L to H level, and then the selection signal Sel_b changes from H to L. After the scan signal Scan_a(m) changes to H level, the selection signal Sel_b changes from L to Then, the selection signal Sel_a changes from H to L. Ta. The present invention is not limited to this configuration. As shown in FIG. 8, when the scan signal Scan_b(m) changes to the H level, The timing when the selection signal Sel_a changes from L to H coincides with the timing when the selection signal Sel_a changes from L to H. The timing when the scan signal Scan_a(m) changes to H level and the timing when the selection signal Sel_b changes from L to H level That is, the timing at which the vertical scanning blanking period V _ b The timing of the start of lnk and the capacitance element C1a or C1b connected until then are The timing of disconnection from the gate node g of the star 121 may be synchronized. .

[0054] 9, the selection signal Sel_a or Sel_b may be changed to H level before the timing at which the control signal Enb changes to H level. That is, the capacitance element C1a or C1b may be disconnected from the gate node g of the transistor 121 before the timing at which the OLED 130 is turned off.

[0055] In the first embodiment, the period in which the scan signals Scan_a(1) to Scan_a(m) are sequentially set to L level and the period in which the scan signals Scan_b(1) to Scan_b(m) are sequentially set to L level, i.e., the entire horizontal effective scanning period, is set to the light emitting period, and the control signal Enb is set to L level, i.e., the OLED 130 is made to emit light. 10, the light-emitting period of the OLED 130 may be shortened by narrowing the light-emitting period during which the control signal Enb is at the L level. When the light-emitting period of the OLED 130 is shortened by such a configuration, the display characteristics of the electro-optical device 10 become closer to a so-called impulse response, thereby reducing the afterimage effect in moving image display. Furthermore, dark gradation levels can be expressed even darker by the pixel circuit 110. When a part of the horizontal effective scanning period is set as the light emitting period, the light emitting period may be shifted forward in time as shown in FIG. 10, shifted backward in time, or may be intermittent.

[0056] In the first embodiment and the modified example of the first embodiment described above, the pixel circuit 110 can be understood as having a configuration as shown in FIG. The transistors 122a and 122b in Fig. 6 can be understood as the first selector 122 as shown in Fig. 11. In detail, in an odd-numbered frame V_odd, if the scanning line 12a is selected and the scanning signal Scan_a(i) becomes L level, the first selector 122 electrically connects one end of the capacitive element C1a to the j-th column data line 14, and in an even-numbered frame V_eve, if the scanning line 12b is selected and the scanning signal Scan_b(i) becomes L level, the first selector 122 electrically connects one end of the capacitive element C1b to the j-th column data line 14.

[0057] 6 can be understood as a second selector 123 as shown in Fig. 11. In detail, the second selector 123 electrically connects one end of the capacitance element C1b to the gate node g of the transistor 121 when the selection signal Sel_a is at H level and the selection signal Sel_b is at L level in an odd-numbered frame V_odd, and electrically connects one end of the capacitance element C1a to the gate node g when the selection signal Sel_a is at L level and the selection signal Sel_b is at H level in an even-numbered frame V_eve.

[0058] That is, the transistor 121 is an example of a drive transistor, the transistor 122a is an example of a first switching element, the transistor 122b is an example of a second switching element, the transistor 123a is an example of a third switching element, and the transistor 123b is an example of a fourth switching element. Also, the capacitance element C1a is an example of a first capacitance element, and the capacitance element C1b is an example of a second capacitance element.

[0059] Second Embodiment A configuration may be adopted in which the threshold voltage of the transistor 121 that controls the current flowing through the OLED 130 is compensated for. Therefore, a second embodiment in which the threshold voltage of the transistor 121 is compensated for will be described. The second embodiment differs from the first embodiment only in the configuration of the pixel circuit 110. Therefore, the differences in the pixel circuit 110 of the second embodiment will be mainly described.

[0060] Fig. 12 is a diagram showing a pixel circuit 110 in an electro-optical device 10 according to a second embodiment. Compared to Fig. 6, the pixel circuit 110 shown in Fig. 12 additionally includes a capacitive element C2 and p-channel MOS transistors 125 and 126. 12, the drain node of transistor 123a and the drain node of transistor 123b are connected to the drain node of transistor 125 and one end of capacitive element C2. The other end of capacitive element C2 is connected to the gate node g of transistor 121 and the drain node of transistor 126. The source node of transistor 125 is connected to power supply line 116, and a control signal Yb is supplied to the gate node. The source node of transistor 126 is connected to the drain node d of transistor 121, and a control signal Ya is supplied to the gate node.

[0061] FIG. 13 is a timing chart for explaining the operation of the electro-optical device 10 according to the second embodiment. It is a chart. The control signals Ya and Yb are supplied to a control circuit 30 (see FIG. 5 ) for all pixel circuits 110. The control signals Ya and Yb are supplied in common to the vertical scanning retrace line as shown in FIG. Period V _ In detail, it becomes L level during the vertical scanning blanking period V _ Controlled in blnk After the signal Yb goes low, the control signal Ya goes low. After the signal Yb becomes H level first, the control signal Ya H It becomes a level.

[0062] In this embodiment, the selection signals Sel_a and Sel_b are phase shifted by 180 degrees. However, the selection signals Sel_a and Sel_b are in the same relationship as in the first embodiment. The timing when changes to H level is during the vertical scanning blanking period V _ It's the start of blnk The timing of the change to L level is after the control signal Ya has changed to H level. Direct scanning blanking period V _ Before the end of blnk.

[0063] Vertical scanning blanking period V _ In blnk, when the control signal Yb becomes L level, the transistor Since the capacitor C125 is turned on, one end of the capacitor C2 is at the power supply potential ELvdd. When the control signal Ya becomes L level, the transistor 126 is turned on. In the star 121, the drain node and the gate node are connected, i.e., Therefore, the gate node of the transistor 121 The voltage between the g and source node s converges to the threshold voltage of the transistor 121. The value voltage is held in the capacitance element C2. When the control signal Ya becomes H level, the transistor 126 is turned off, and the control signal When Yb becomes H level, the transistor 125 is turned off.

[0064] Vertical scanning blanking period V _ After the end of blnk, if it is the light emitting period L_eve, transistor 123 b is turned on, the capacitance elements C1b and C2 are connected to the power supply wiring 116 and the transistor Therefore, in the previous even frame V_eve, The threshold voltage is added to the voltage corresponding to the gradation level supplied in the The voltage is applied to the gate node g of the transistor 121. Vertical scanning blanking period V _ After the end of blnk, the light emission period L_odd in the even frame V_eve begins. R In this case, the transistor 123a is turned on, and the capacitance elements C1a and C2 are connected to the power supply line. A series connection is formed between the line 116 and the gate node g of the transistor 121. The threshold voltage is added to the voltage according to the gray level supplied in the previous odd frame V_odd. The sum voltage is applied to the gate node g of the transistor 121.

[0065] FIG. 14 is a flowchart showing the operation of the electro-optical device 10 according to the second embodiment. Here, if step S1 is the operation of the light emission period L_eve of the odd frame V_odd, then step In the step S1, the voltage of the data signal corresponding to the gradation level is held in the capacitance element C1a in a line-sequential manner. The threshold voltage of the transistor 121 is increased by the operation of the capacitors C1b and C2. The light emitting operation of causing a current to flow through the OLED 130 by compensating for the voltage is performed in parallel. In the next step S2, the vertical scanning blanking period V _ OLED130 is turned off. At the same time, an operation of holding the threshold voltage of the transistor 121 in the capacitive element C2 is executed.

[0066] In step S3, the voltage of the data signal corresponding to the gray level is applied to the capacitance element C1b line-sequentially. The holding operation and the holding voltage of the capacitance elements C1a and C2 cause the transistor 121 The threshold voltage of the OLED 130 is compensated for to allow a current to flow through the OLED 130, and a light emitting operation is performed in parallel. In the next step S4, the vertical scanning blanking period V _ OLED130 is turned off. At the same time, an operation of holding the threshold voltage of the transistor 121 in the capacitive element C2 is executed. Thereafter, the operations of steps S1 → S2 → S3 → S4 → (S1) are repeatedly executed.

[0067] According to the second embodiment, in both the odd frame V_odd and the even frame V_eve, the transistor 121 passes a current according to the gradation level to the OLED 130 with the threshold voltage compensated, thereby enabling a high-quality display with little variation for each pixel circuit 110. In the second embodiment, as described with reference to FIG. 10, the period during which the control signal Enb is at L level may be shortened to shorten the light emitting period of the OLED 130.

[0068] In the second embodiment described above, the pixel circuit 110 has a structure as shown in FIG. This can be understood as a composition. The transistor 126 in FIG. 12 is connected to the control signal Ya as shown in FIG. Direct scanning blanking period V _ If blnk is at L level, the gate node of transistor 121 The drain node g and the drain node d are electrically shorted to make the transistor 121 a diode. That is, the transistor 12 functions as a switching element that switches the power supply to the on-state. 6 is an example of a sixth switching element.

[0069] Furthermore, the capacitive element C2 holds the threshold voltage of the transistor 121 when the transistors 125 and 126 are turned on. The capacitive element C2 holding the threshold voltage is electrically connected between one end of the capacitive element C1b and the gate node g of the transistor 121 if the transistors 125 and 126 are turned off, the selection signal Sel_a is at H level, and the selection signal Sel_b is at L level in the odd-numbered frame V_odd, and is electrically connected between one end of the capacitive element C1a and the gate node g of the transistor 121 if the transistors 125 and 126 are turned off, the selection signal Sel_a is at L level, and the selection signal Sel_a is at H level in the even-numbered frame V_eve. That is, the capacitive element C2 is an example of a third capacitive element. In this description, "electrically inserted" means inserted between two or more elements when viewed from the perspective of an electric circuit.

[0070] <Application examples and variations> The first and second embodiments (hereinafter referred to as "embodiments, etc.") described above can be applied or modified in various ways. Specific modified aspects that can be applied to the embodiments, etc. are exemplified below. Two or more aspects arbitrarily selected from the following examples may be combined to the extent that they are not mutually contradictory.

[0071] In the electro-optical device 10 according to the embodiment and the like, the transistor 124 is provided between the transistor 121 and the OLED 130, but the location where the transistor 124 is provided is not limited to this. The function of the transistor 124 is to block the path through which the current controlled by the transistor 121 flows to the OLED 130, so it is sufficient that the transistors 121 and 124 are connected in series between the power supply wirings 116 and 118. The transistor 124 is an example of a fifth switching element.

[0072] In the first place, in the electro-optical device 10, the transistor 124 is provided in the pixel circuit 110. However, in the embodiment and the like, since the light emission period of the OLED 130 in all the pixel circuits 110 is common, for example, a power supply circuit (not shown) may be configured to supply the power supply potential ELvdd to the power supply wiring 116 in accordance with the light emission period.

[0073] Although the OLED 130 has been described as an example of a light-emitting element in the embodiments, other light-emitting elements may be used. For example, LEDs (Light Emitting Diodes), mini LEDs, micro LEDs, etc. may be used as light-emitting elements.

[0074] The channel types of the transistors 121, 122a, 122b, 123a, 123b, 124, 125, and 126 are not limited to those in the embodiment, etc. Furthermore, these transistors, except for the transistor 121, may be replaced with transmission gates as appropriate.

[0075] Electronic devices including the electro-optical device 10 can be applied not only to the head-mounted display system 1, but also to projection systems and all other devices that allow users to view an image displayed by the electro-optical device 10 superimposed on a real-world scene.

[0076] <Additional Notes> From the above description, for example, preferred embodiments of the present disclosure can be understood as follows: Note that, in order to facilitate understanding of each embodiment, reference numerals in the drawings are written in parentheses for convenience, but this is not intended to limit the present invention to the embodiments shown in the drawings.

[0077] <Appendix 1> An electro-optical device (10) according to one aspect (aspect 1) includes a plurality of pixel circuits (110) provided corresponding to intersections between a data line (14) and a plurality of scanning lines (12), each pixel circuit (110) including a first selector (122), a second selector (123), a first capacitance element (C1a), a second capacitance element (C1b), a driving transistor (121), and a light-emitting element (130), the driving transistor (121) being capable of supplying a current to the light-emitting element (130) according to the potential of a gate node (g), the plurality of scanning lines (12) being selected in sequence in a first frame (V_odd), and the first selector (122) in one pixel circuit (110) of the plurality of pixel circuits (110) being capable of supplying a current to the light-emitting element (130) according to the potential of the gate node (g), the plurality of scanning lines (12) being selected in sequence in a first frame (V_odd), and the first selector (122) in one pixel circuit (110) of the plurality of pixel circuits (110) being capable of supplying a current to the one pixel circuit (110) according to the potential of the one pixel circuit (110), the plurality of scanning lines (12) being selected in sequence in a first frame (V_odd), and the first selector (122) in one pixel circuit (110) being capable of supplying a current to the one pixel circuit (110) according to the potential of the one pixel circuit (110), the plurality of scanning lines (12) being selected in sequence in a first frame (V_odd), and the first selector (123 ... ), when a scanning line (12) corresponding to one of the scanning lines (12) is selected, the first selector (122) in one of the pixel circuits (110) electrically connects one end of the first capacitance element (C1a) to the data line (14), and the second selector (123) in one of the pixel circuits (110) electrically connects one end of the second capacitance element (C1b) to the gate node (g). In a second frame (V_eve) different from the first frame (V_odd), the multiple scanning lines (12) are selected in sequence, and when a scanning line (12) is selected, the first selector (122) in one of the pixel circuits (110) electrically connects one end of the second capacitance element (C1b) to the data line (14), and the second selector (123) in one of the pixel circuits (110) electrically connects one end of the first capacitance element (C1a) to the gate node (g).

[0078] According to the first aspect, in the first frame (V_odd), the potential of the data line (14) is held in the first capacitance element (C1a) in a line-sequential manner, and in the second frame (V_eve), one end of the first capacitance element (C1a) is connected to the gate node (g) of the driving transistor (121), so that the OLEDs (130) are simultaneously lit. That is, after the line-sequential holding operation in the first frame (V_odd), in the second frame (V_eve), the light-emitting elements (130) can simultaneously emit light based on the held voltage. Therefore, according to aspect 1, it is possible to ensure a long light emission period without increasing the speed of the line-sequential holding operation. Also, since the light-emitting elements (130) can emit light simultaneously, it is possible to prevent the display image from being distorted due to line-sequential light emission.

[0079] <Appendix 2> In an electro-optical device (10) according to a specific embodiment (embodiment 2) of embodiment 1, the first selector (122) includes a first switching element (122a) that is turned on or off between the data line (14) and one end of the first capacitance element (C1a), and a second switching element (122b) that is turned on or off between the data line (14) and one end of the second capacitance element (C1b), and the second selector (123) includes a third switching element (123a) that is turned on or off between one end of the first capacitance element (C1a) and the gate node (g), and a fourth switching element (123b) that is turned on or off between one end of the second capacitance element (C1b) and the gate node (g). According to embodiment 2, the first selector (122) and the second selector (123) can be specifically configured.

[0080] <Appendix 3> In an electro-optical device (10) according to a specific embodiment (embodiment 3) of embodiment 2, the pixel circuit (110) includes a fifth switching element (124) connected in series with the driving transistor (121) between the high-level power supply wiring (116) and the low-level power supply wiring (118). According to embodiment 3, the driving transistor (121) can supply a current corresponding to the potential of the gate node (g) to the light-emitting element (130) by turning on the fifth switching element (124).

[0081] <Appendix 4> In an electro-optical device (10) according to a specific aspect (Aspect 4) of Aspect 2 or Aspect 3, the pixel circuit (110) includes a third capacitance element (C2) that holds the threshold voltage of the driving transistor (121), and the third capacitance element (C2) is interposed between one end of the second capacitance element (C1b) and the gate node (g) in the first frame (V_odd), and between one end of the second capacitance element (C2) and the gate node (g) in the second frame (V_eve). According to Aspect 4, the threshold voltage of the driving transistor (121) can be compensated.

[0082] <Appendix 5> In an electro-optical device (10) according to a specific aspect (aspect 5) of aspect 4, the pixel circuit (110) includes a sixth switching element (126) that puts the driving transistor (121) into a diode-connected state. According to aspect 5, compensation for the threshold voltage of the driving transistor (121) can be specifically configured.

[0083] <Appendix 6> In an electro-optical device (10) according to a specific embodiment (embodiment 6) of embodiment 3, 4, or 5, the fifth switching element (124) is turned on during all or part of the period (L_odd or L_eve) during which the plurality of scanning lines (12) are sequentially selected one by one. According to embodiment 6, the light-emitting period caused by current flowing through the OLED 130 can be controlled. Specifically, by lengthening the light-emitting period, the brightness of the displayed image can be ensured, and by shortening the light-emitting period, the blurring of moving images can be reduced.

[0084] <Appendix 7> An electronic device according to a specific aspect (aspect 7) of any of aspects 1 to 6 includes an electro-optical device according to any of the above aspects. According to aspect 7, it is possible to ensure a long light-emitting period without increasing the speed of the line-sequential holding operation, and to prevent the image from being distorted. [Explanation of symbols]

[0085] 1...head mounted display, 10...electro-optical device, 12...scanning line, 14...data Line, 100... display area, 110... pixel circuit, 116... power supply wiring (high-level power supply wiring), 118 ...power supply wiring (low-level power supply wiring), 121...transistor (drive transistor), 122 a...transistor (first switching element), 122b...transistor (second switching element) switching element), 123a...transistor (third switching element), 123b...transistor 124...transistor (fourth switching element), 125...transistor (fifth switching element) , 126...transistor (sixth switching element), 300...headset, C1a... Capacitor element (first capacitor element), C1b... capacitor element (second 2 C1...capacitance element (third capacitance element).

Claims

1. a plurality of pixel circuits provided corresponding to intersections of the data lines and the plurality of scanning lines; Each pixel circuit is a first selector, a second selector, a first capacitance element, a second capacitance element, a driving transistor, and a light emitting element; the driving transistor is capable of supplying a current corresponding to a voltage of a gate node to the light emitting element; In the first frame, The plurality of scan lines are selected in sequence; a first selector in one pixel circuit among the plurality of pixel circuits electrically connects one end of the first capacitance element to the data line when a scanning line corresponding to the one pixel circuit is selected; a second selector in the one pixel circuit electrically connects one end of the second capacitance element to the gate node; In a second frame different from the first frame, The plurality of scan lines are selected in sequence; a first selector in the one pixel circuit electrically connects one end of the second capacitance element to the data line when the one scanning line is selected; a second selector in the one pixel circuit electrically connecting one end of the first capacitance element to the gate node; Electro-optical device.

2. The first selector is a first switching element that is turned on or off between the data line and one end of the first capacitance element; a second switching element that is turned on or off between the data line and one end of the second capacitive element; Including, The second selector is a third switching element that is turned on or off between one end of the first capacitance element and the gate node; a fourth switching element that is turned on or off between one end of the second capacitance element and the gate node; The electro-optical device according to claim 1 , comprising:

3. The pixel circuit a fifth switching element connected in series with the driving transistor between the high-level power supply wiring and the low-level power supply wiring; The electro-optical device according to claim 2 .

4. The pixel circuit a third capacitance element in which a threshold voltage of the driving transistor is held; The third capacitance element is In the first frame, a second capacitance element connected between one end of the second capacitance element and the gate node; In the second frame, a first capacitance element connected between one end of the first capacitance element and the gate node; The electro-optical device according to claim 2 .

5. The pixel circuit a sixth switching element for switching the driving transistor into a diode-connected state; 5. The electro-optical device according to claim 4.

6. The pixel circuit a third capacitance element in which a threshold voltage of the driving transistor is held; The third capacitance element is In the first frame, a second capacitance element connected between one end of the second capacitance element and the gate node; In the second frame, a first capacitance element connected between one end of the first capacitance element and the gate node; The electro-optical device according to claim 3 .

7. The pixel circuit a sixth switching element for switching the driving transistor into a diode-connected state; 7. The electro-optical device according to claim 6.

8. The fifth switching element is turned on during all or part of a period during which the plurality of scanning lines are selected one by one in sequence.

8. The electro-optical device according to claim 3, 6 or 7.

9. 7. An electronic device comprising the electro-optical device according to claim 1.

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