Analog-to-digital converter and image sensor

Abstract

To provide an analog-to-digital converter, an image sensor, and an analog-to-digital conversion method that can achieve a wide dynamic range at low voltage.SOLUTION: A comparator 120 compares a signal voltage of an analog signal to be converted with a threshold voltage, and samples the analog signal to be converted to a first capacitor Ca, and then compares the signal voltage stored in the first capacitor Ca with a reference voltage that increases or decreases in a full scale of a voltage range when the signal voltage is larger than the threshold voltage, and compares the signal voltage of the analog signal to be converted, which is input to the comparator 120 with the reference voltage that increases or decreases within a part of the voltage range when the signal voltage is smaller than the threshold voltage. A time digital converter such as a counter 130 starts and stops time measurement using a clock on the basis of the comparison result of the comparator 120, and outputs the measured time information as a converted digital signal of the analog signal to be converted.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an analog-to-digital converter, an image sensor using the same, and an analog-to-digital conversion method. [Background technology]

[0002] There are time domain A / D converters that perform analog-to-digital (A / D) conversion by converting voltage information into time information and measuring the time. The simplest time domain A / D converter is the integral A / D converter shown in Figure 9, which is mainly used as a column ADC (column analog-to-digital converter) for CMOS (complementary metal oxide semiconductor) image sensors (see, for example, Patent Document 1 and Non-Patent Document 1).

[0003] In Figure 9, a ramp signal whose voltage changes linearly over time is used as the reference voltage, and the input signal voltage V SIG is compared with a reference voltage by a comparator 210. The output of the comparator 210 becomes a stop signal for a counter that counts the number of clocks. SIG When the voltage drops below this, a stop signal is output from comparator 210, stopping the counter. The output of this counter or other time-to-digital converter 220 becomes a converted digital signal, which is then A / D converted. This integral A / D converter has a simple circuit, is easy to design, and in principle has excellent DNL (Differential Nonlinearity), so it is widely used as a column ADC in CMOS image sensors. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2019 / 073663 [Non-patent literature]

[0005] [Non-Patent Document 1] S. Yoshihara, et al., “A 1 / 1.8-inch 6.4 MPixel 60 frames / s CMOS Image Sensor With Seamless Mode Change,” IEEE Journal of Solid-State Circuits, December 2006, Vol. 41, No. 12, pp. 2998-3006 Summary of the Invention [Problem to be solved by the invention]

[0006] However, conventional integral A / D converters used in CMOS image sensors use an operating voltage of 2.8 to 3.3 V to ensure a wide dynamic range corresponding to the image sensor output signal. While logic circuits have reduced power consumption by using a low voltage of around 1.2 V as elements become more miniaturized, these converters have not yet been designed to lower voltages.

[0007] This poses the problem that the power consumption of the comparator cannot be reduced, and that it is difficult to achieve the fine circuit pitch and area reduction required for CMOS image sensors because fine transistors with low voltage resistance cannot be used.

[0008] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an analog-to-digital converter, an image sensor, and an analog-to-digital conversion method that can achieve a wide dynamic range at a low voltage. [Means for solving the problem]

[0009] In order to solve the above-mentioned problems, the present inventors have studied comparators in integral A / D converters that perform A / D conversion on analog signals to be converted, such as pixel signals of an image sensor, and have found that it is possible to reduce the voltage required for the comparator by sampling the analog signal to be converted before performing the A / D conversion.Furthermore, to address the issue of increased noise caused by sampling the analog signal to be converted, the present inventors have found that by distinguishing the analog signal to be converted based on its magnitude, and if the signal voltage of the analog signal to be converted is low, the analog signal to be converted is directly A / D converted without being sampled, and if the signal voltage is high, the analog signal to be converted is sampled before A / D conversion, it is possible to reduce the voltage required for the comparator while preventing an increase in noise for low-level signals that are highly susceptible to noise, and have arrived at the present invention.

[0010] That is, the analog-to-digital converter of the present invention is an analog-to-digital converter that receives an analog signal to be converted and a reference voltage that increases or decreases in voltage over time, and includes a comparator that compares the signal voltage of the analog signal to be converted with the reference voltage, and a time-to-digital converter that starts and stops time measurement using a clock based on the comparison result of the comparator and outputs the measured time information as a converted digital signal of the analog signal to be converted, wherein the comparator compares the signal voltage of the analog signal to be converted with a threshold voltage, and if the signal voltage is greater than the threshold voltage, samples the analog signal to be converted into a capacitor and then compares the signal voltage stored in the capacitor with the reference voltage that increases or decreases within a full-scale voltage range, and if the signal voltage is smaller than the threshold voltage, compares the signal voltage of the analog signal to be converted that is input to the comparator with the reference voltage that increases or decreases within a partial voltage range. An image sensor according to the present invention includes an analog-to-digital converter having the above-described features.

[0011] Furthermore, an analog-to-digital conversion method according to the present invention is an analog-to-digital conversion method comprising: a comparison step in which an analog signal to be converted and a reference voltage whose voltage increases or decreases over time are input, and the signal voltage of the analog signal to be converted is compared with the reference voltage; and a measurement step in which time measurement using a clock is started and stopped based on the comparison result of the comparison step, and the measured time information is output as a converted digital signal, wherein the comparison step compares the signal voltage of the analog signal to be converted with a threshold voltage, and if the signal voltage is greater than the threshold voltage, the signal voltage stored in the capacitance is sampled, and then the signal voltage is compared with the reference voltage whose voltage increases or decreases within a full-scale voltage range, and if the signal voltage is smaller than the threshold voltage, the signal voltage of the input analog signal to be converted with the reference voltage whose voltage increases or decreases within a partial voltage range. [Effects of the Invention]

[0012] According to the present invention, A / D conversion is performed on high-level signals after sampling, and A / D conversion is performed on low-level signals without sampling, thereby making it possible to prevent an increase in noise in low-level signals that are significantly affected by noise, while achieving a wide dynamic range at a low voltage. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram showing a configuration of an A / D converter according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram of a comparator that constitutes an integral A / D converter. [Figure 3A] FIG. 4 is a diagram illustrating a first operation step according to the first embodiment. [Figure 3B] FIG. 10 is a diagram illustrating a second operation step according to the first embodiment. [Figure 3C] FIG. 10 is a diagram illustrating a third operation step according to the first embodiment. [Figure 3D] FIG. 10 is a diagram illustrating a fourth operation step according to the first embodiment. [Figure 3E] FIG. 10 is a diagram illustrating a fifth operation step according to the first embodiment. [Figure 3F] FIG. 10 is a diagram illustrating a sixth operation step according to the first embodiment. [Figure 3G] FIG. 10 is a diagram illustrating a seventh operation step according to the first embodiment. [Figure 4A] FIG. 10 is a diagram illustrating a first state according to a comparative example. [Figure 4B] FIG. 10 is a diagram illustrating a second state according to a comparative example. [Figure 5] 3A and 3B are diagrams illustrating a converted analog signal and a reference voltage according to the first embodiment. [Figure 6] FIG. 2 is a diagram illustrating the structure of a switch. [Figure 7] 10 is a diagram illustrating a converted analog signal and a reference voltage in Modification 1. FIG. [Figure 8A] FIG. 10 is a diagram illustrating a third operation step according to the second modification. [Figure 8B] FIG. 10 is a diagram illustrating an additional step according to Modification 2. [Figure 9] FIG. 1 is a block diagram showing a configuration of a conventional integral A / D converter. DETAILED DESCRIPTION OF THE INVENTION

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0015] (First embodiment) A description will be given of an analog-to-digital converter (hereinafter, analog-to-digital conversion will be referred to as A / D conversion) 100 according to a first embodiment of the present invention. The A / D converter 100 is an integral type A / D converter used in an image sensor or the like.

[0016] [A / D converter configuration] 1 is a block diagram of an A / D converter 100 according to this embodiment. A differential amplifier 110 used in a comparator of the A / D converter 100 has a first input terminal 111, a second input terminal 112, a first output terminal 113, and a second output terminal 114. The first output terminal 113 outputs an inverted amplified signal between the first input terminal 111 and the second input terminal 112, and the second output terminal 114 outputs a non-inverted amplified signal between the first input terminal 111 and the second input terminal 112.

[0017] The circuit configuration of the differential amplifier 110 may be any configuration used in a comparator of a conventional integral A / D converter. Fig. 2 is an example of a circuit diagram of a comparator of an integral A / D converter. As shown in Fig. 2, the differential amplifier 110 is a pair of transistors M whose sources are connected to each other and convert a differential input voltage into a differential current. 1a ,M 1b and is biased at a constant current by a transistor M0 operating as a current source. 2a ,M 2b and converts the differential current into a differential voltage.

[0018] As shown in FIG. 1, the comparator 120 of the A / D converter 100 has a first signal input terminal 101 and a second signal input terminal 102. The first signal input terminal 101 is connected to a first capacitance C a and the second signal input terminal 102 is connected to the first input terminal 111 of the differential amplifier 110 via a second capacitance C b The comparator 120 is connected to the second input terminal 112 of the differential amplifier 110 via a switch S 1a (first switch) and switch S 1b (second switch), and the first input terminal 111 and the first output terminal 113 are connected to the switch S 1a The second input terminal 112 and the second output terminal 114 are connected to a switch S 1b The switch S 1a and switch S 1b When the switch S is closed, 1a ,S 1b The connection end has a common output voltage V c occurs.

[0019] In the circuit shown in FIG. 2, the voltage at the first output terminal 113 is a substantially constant voltage V c and the output signal of comparator 120 used for time measurement in the time-to-digital converter is generated at second output terminal 114. Although this circuit does not provide a completely differential output, the polarity of second output terminal 114 as seen from first output terminal 113 is determined by the polarity of the differential input signal, so the circuit shown in FIG. 2 can be used as differential amplifier 110 that constitutes comparator 120.

[0020] As shown in Fig. 1, the A / D converter 100 has a counter 130 that functions as a time-to-digital converter. The counter 130 counts the number of clocks, starts and stops counting based on the output of the comparator 120, and outputs the stopped count value as an A / D converted value. Note that instead of the counter 130, any other time-to-digital converter may be used, and the time-to-digital converter may start and stop measuring time using a clock based on the output of the comparator 120, and output the measured time information as a converted digital signal of the converted analog signal. In this embodiment, a case will be described in which the time-to-digital converter is the counter 130.

[0021] The A / D converter 100 also has a subtractor 140, which calculates the difference between the converted digital signal of the converted analog signal and the converted reference digital signal of the reference analog signal, thereby obtaining an output that has been subjected to correlated double sampling (CDS). When multiple conversions are performed and an average value is to be calculated, an averaging circuit is further added. The first capacitance C a Switch S 2a is connected, and the second capacitance C b Switch S 2b ,S 3b is connected to allow selection of the input voltage. 2a is not necessarily required, but the switch S 2a ,S 2b ,S 3bIt is often used to suppress the differential offset voltage by balancing the offset voltage caused by charge injection from the capacitor to the switch S. 2a The configuration includes these switches S 1a ,S 1b ,S 2a ,S 2b ,S 3b is controlled by a logic circuit 150 that receives the output signal of the comparator 120. 1a ,S 1b ,S 2a ,S 2b ,S 3b The control of the A / D converter 100, including the switching of the signal input to the comparator 120, may be realized by the logic circuit 150, a computer such as a microcomputer, or any control unit in which these cooperate with each other.

[0022] The operation of the A / D converter 100 having the above-described configuration will be described for each operation step with reference to FIGS.

[0023] [First operation step] In the first operation step, as shown in FIG. 3A, the switch S 2a ,S 2b is closed, and the signal voltage V of the reference analog signal is commonly applied to the first signal input terminal 101 and the second signal input terminal 102. RST is input. Switch S 1a The first input terminal 111 and the first output terminal 113 of the differential amplifier 110 are short-circuited by the 1b The second input terminal 112 and the second output terminal 114 of the differential amplifier 110 are short-circuited by the first capacitance C a , second capacity C b The voltage stored in both is expressed by the following equation (1).

[0024]

number

[0025] [Second operation step] In the second operation step, as shown in FIG. 3B, the switch S 1a ,S 1b is opened and switch S 2b is opened and switch S 3b is closed, and a reference voltage V R At this time, the voltage V of the first input terminal 111 of the differential amplifier 110 is a and the voltage V of the second input terminal 112 b is the voltage expressed by the following equation (2).

[0026]

number

[0027] Therefore, V R and V RST When V and V are equal in voltage, the output polarity of the differential amplifier 110 is reversed, stopping the counter 130, and the reference analog signal is converted into a digital signal. RST The fluctuation range of is small, about 0.1V at most, and when the output polarity is inverted, the voltage at the input terminal of the differential amplifier 110 is V c Therefore, it is not necessary to provide a large power supply voltage margin for the comparator 120 to cope with large fluctuations in the input terminal of the differential amplifier 110.

[0028] [Third operation step] In the third operation step, as shown in FIG. 3C, the switch S 2a ,S 3b is closed, and the signal voltage V of the reference analog signal is input to the first signal input terminal 101. RST is input, and the reference voltage V is input to the second signal input terminal 102. R0 is input. Switch S 1a The first input terminal 111 and the first output terminal 113 of the differential amplifier 110 are short-circuited by 1b The second input terminal 112 and the second output terminal 114 of the differential amplifier are short-circuited by the first capacitance C a , second capacity Cb A voltage expressed by the following equation (3) is held in

[0029]

number

[0030] [Fourth operation step] In the fourth operation step, as shown in FIG. 3D, the switch S 1a ,S 1b is opened, and the signal voltage V of the converted analog signal is input to the first signal input terminal 101. SIG is input, and the second signal input terminal 102 receives a threshold voltage V TH At this time, the voltage V at the first input terminal 111 of the differential amplifier 110 a and the voltage V of the second input terminal 112 b is the voltage expressed by the following equation (4).

[0031]

number

[0032] Therefore, the voltage difference V between the first input terminal 111 and the second input terminal 112 a -V b is expressed as the following formula (5), and V SIG -V RST and V TH -V R0 The magnitudes are compared.

[0033]

number

[0034] At this time, if the voltage magnitude of the input converted analog signal is small and satisfies the following formula (6), proceed to the fifth operation step, and if the voltage magnitude of the converted analog signal is large and does not satisfy the following formula (6), proceed to the sixth operation step.

[0035]

number

[0036] [5th ​​operation step] In the fifth operating step, as shown in FIG. 3E, a reference voltage V , which rises or falls within a partial voltage range relative to the full scale, is applied to the second signal input terminal 102. R The voltage V at the first input terminal 111 of the differential amplifier 110 is a and the voltage V at the second input terminal 112 b When these values ​​match, the output state of the differential amplifier 110 changes, the counter 130 is stopped, and the A / D converted value of the converted analog signal is obtained. a and the voltage V at the second input terminal 112 b is expressed as the following formula (7).

[0037]

number

[0038] The subtractor 140 subtracts the voltage V a and V b A correlated double sampled (CDS) A / D converted value can be obtained by subtracting the converted reference digital signal of the reference analog signal obtained in the second operation step from the converted digital signal of the converted analog signal obtained by the comparison.

[0039] [6th operation step] In the sixth operating step, as shown in FIG. 3F, switch S 2a ,S 2b is closed, and the analog signal to be converted is input to both the first signal input terminal 101 and the second signal input terminal 102. 1a The first input terminal 111 and the first output terminal 113 of the differential amplifier 110 are short-circuited by the 1b The second input terminal 112 and the second output terminal 114 of the differential amplifier 110 are short-circuited by the first capacitance C a , second capacity C b Together (V SIG -Vc ) voltage is stored.

[0040] [7th operation step] In the seventh operating step, as shown in FIG. 3G, the switch S 1a ,S 1b is opened, and the second signal input terminal 102 receives a reference voltage V R At this time, the voltage V of the first input terminal 111 of the differential amplifier 110 is a and the voltage V of the second input terminal 112 b is expressed by the following formula (8).

[0041]

number

[0042] Therefore, V R and V SIG become the same voltage, the output polarity of the differential amplifier 110 is reversed and the counter is stopped, thereby obtaining the A / D converted value of the converted analog signal. The subtractor 140 can obtain the A / D converted value that has been subjected to correlated double sampling (CDS) by subtracting the converted reference digital signal of the reference analog signal obtained in the second operation step from the converted digital signal of the converted analog signal.

[0043] [Comparator operating voltage] Here, the operating voltage of the comparator 120 in this embodiment will be described using a comparative example. As a comparative example, the operation when there is no function to sample the converted analog signal is shown in FIGS.

[0044] In the first state of FIG. 4A, switch S 1a and switch S 1b is closed, and the pixel reset signal voltage V RST and the common voltage of the comparator, V c The difference voltage between the first capacitance C a Similarly, the reference voltage V R0 and V cThe difference voltage between the second capacitance C b Next, in the second state of FIG. 4B, the switch S 1a and switch S 1b is opened and the first capacitance C a is the pixel signal voltage V SIG is applied, and the second capacitance C b is the reference voltage V R is applied to the two input terminals of the comparator, V a and V b When they match, the output state of the comparator changes and the counter stops. The output value of the counter at this time becomes the A / D converted value. The voltage V at the input terminal in this comparison state a and V b is expressed by the following formula (9).

[0045]

number

[0046] The voltage V at which the comparator operates normally a and V b The condition is that in the comparator circuit shown in Figure 2, V GS is the gate-source voltage of an NMOS (n-channel Metal Oxide Semiconductor) transistor, V TN is the threshold voltage, V eff is the effective gate voltage of the MOS transistor (V eff =V GS -V TN ), all the transistors must operate in the saturation region, so the following formula (10) must be satisfied.

[0047]

number

[0048] Also, |V TP When | is the threshold voltage of a PMOS (p-channel Metal Oxide Semiconductor) transistor, V c is expressed by the following formula (11).

[0049]

number

[0050] From the above relationship, the true signal voltage ΔV SIG When expressed as the following formula (12), the relationship of the following formula (13) can be derived from formulas (9) and (10).

[0051]

number

[0052]

number

[0053] The true signal voltage ΔV of the converted pixel signal output by the CMOS image sensor SIG is usually 0V to -1V, and V TN is 0.4V, and V eff is about 0.2V, so V c requires 1.8V or more, and V TP If we set V to 0.4V, then V DD It can be seen that a voltage of 2.4V is required.

[0054] Therefore, until now, comparators in column ADCs in CMOS image sensors have used voltages of 2.8V to 3.3V, and while peripheral logic circuits have reduced power consumption by using low voltages of around 1.2V as elements have become more miniaturized, no efforts have been made to lower the voltage of the comparators.

[0055] Next, the operating voltage of this embodiment will be described. In this embodiment, if the voltage of the converted analog signal is smaller than the threshold voltage, in the fifth operating step, the voltage V of the first input terminal 111 in the comparison state is a and the voltage V at the second input terminal 112 bis expressed by the above-mentioned formula (7). In this case, the voltage of the converted analog signal and the reference voltage V R is small and has the relationship expressed by the following formula (14).

[0056]

number

[0057] where |V TN -V R0 | is set to 100mV or less, so V a ,V b is V c The voltage will be reduced by up to about 100mV.

[0058] In addition, in this embodiment, if the voltage of the converted analog signal is greater than the threshold voltage, in the seventh operation step, the voltage Va of the first input terminal 111 and the voltage V of the second input terminal 112 in the comparison state are b is expressed by the above-mentioned formula (8), but the voltage V at the first input terminal 111 of the differential amplifier 110 when the output polarity is inverted is a and the voltage V of the second input terminal 112 b are both voltage V c Therefore, the voltage condition under which the differential amplifier circuit shown in FIG. 2 operates normally is expressed by the following equation (15).

[0059]

number

[0060] where |V TP |=V TN =0.4V, V eff = 0.2V, the minimum operating voltage V DDmin Therefore, since it operates at an operating voltage that is 1.0 V lower than the minimum operating voltage of 2.4 V of the comparative example that does not perform sampling as described above, not only can power consumption be reduced, but also finer transistors with lower voltage resistance can be used, making it easier to achieve narrower pitches and reducing the area of ​​the A / D converter.

[0061] Furthermore, in this embodiment, when the voltage obtained by subtracting the reference analog signal from the converted analog signal is small, the converted voltage value obtained by subtracting the reference analog signal from the converted analog signal can be obtained without going through the sixth and seventh operation steps. This makes it possible to prevent the generation of thermal noise known as kT / C noise, which occurs when sampling the converted analog signal in the sixth operation step. Therefore, it is possible to prevent degradation of the SNR (Signal to Noise Ratio) during A / D conversion of low-level signals, where kT / C noise has a strong effect on image quality, and it is possible to achieve lower voltages without degrading image quality.

[0062] Figure 5 shows the converted analog signal voltage V SIG and the reference voltage V R After the reset conversion with the reference analog signal as input, the converted analog signal is input and the threshold voltage V TH During signal conversion, the signal is not sampled for small signals, and the reference voltage V is used in a limited voltage range. R For large signals, the signal is sampled and the full-scale reference voltage V R This makes it possible to perform A / D conversion with low voltage and low noise for analog signals with a wide dynamic range.

[0063] In this embodiment, it is possible to reduce the voltage of the comparator 120. 1a ,S 1b A PMOS is usually used as the switch as shown in FIG. DD When the switch is off, the gate voltage V G is V DD Either the drain or source of the PMOS is V c and the other is V b In the seventh operation step, V b is expressed by the following formula (16) from formula (8).

[0064]

number

[0065] Here, V c is expressed by the following formula (17), and therefore the above formula (16) is expressed by the following formula (18).

[0066]

number

[0067]

number

[0068] If the potential difference between the N well and the source-drain terminal of the P layer of the PMOS transistor is not positive, the parasitic diode turns on and the second capacitance C b Since the charge stored in the capacitor fluctuates, the following equation (19) must be satisfied to prevent this phenomenon from occurring.

[0069]

number

[0070] For normal pixel signals, V SIG ,V R Since V is expressed by the following formula (20), SIG = 1.0V and V R If is 1.6 V or more, the condition of the above formula (19) cannot be satisfied.

[0071]

number

[0072] So, switch S 1a ,S 1b The well voltage V of the PMOS transistor that constitutes Wand gate voltage V G The power supply voltage V of the comparator 120 DD By setting it higher than the second capacitance C b This can suppress fluctuations in the charge stored in the capacitor.

[0073] [Variation 1] In the fifth operating step, the second signal input terminal 102 is supplied with a reference voltage V that continuously rises or falls over time in a certain voltage range. R is applied, and the time information of the clock is recorded multiple times at the timing when the output state of the differential amplifier 110 transitions, and the average value is taken as the reference analog signal voltage V RST and the converted analog signal voltage V SIG Alternatively, the differential voltage may be an A / D converted value.

[0074] In addition, in the second operation step, the second signal input terminal 102 is supplied with a reference voltage V that continuously rises or falls over time in a certain voltage range multiple times. R may be applied, and the time information of the clock may be recorded multiple times at the timing when the output state of the differential amplifier 110 transitions, and the average value may be used as the A / D conversion value of the reference analog signal. Furthermore, by combining the operations of A / D conversion based on the average value in the second operation step and the fifth operation step, it is possible to perform A / D conversion with even lower noise.

[0075] Figure 7 shows the converted analog signal voltage V SIG and the reference voltage V R During reset conversion, the reference voltage V R performs multiple voltage sweeps within a limited voltage range and multiple A / D conversions. Then, the analog signal to be converted is input and the threshold voltage V TH During signal conversion, the signal is not sampled for small signals, and the reference voltage V is used in a limited voltage range. R For large signals, the signal is sampled and the full-scale reference voltage V is applied only once. RThis allows for low-noise A / D conversion.

[0076] [Variation 2] 8A and 8B show the third operation step and an additional step of the second modification. After the third operation step shown in FIG. 8A, which is the same as the first embodiment, the switch S 1a and switch S 1b is open, and the second signal input terminal 102 is supplied with a reference voltage V R At this time, the voltage Va at the first input terminal 111 and the voltage V at the second input terminal 112 are b is expressed by the following equation (21).

[0077]

number

[0078] Reference voltage V R is swept, and time information such as the number of clock counts is recorded at the timing when the output state of differential amplifier 110 transitions, to obtain the A / D converted value of the reference analog signal for the reset period. Thereafter, the fifth to seventh operation steps shown in Figures 3E to 3G are performed, and time information of the clock is recorded at the timing when the output state of differential amplifier 110 transitions, to be used as the A / D converted value of the converted analog signal, and the value obtained by subtracting the A / D converted value of the reference analog signal from this value is used as the A / D converted output.

[0079] This allows analog correlated double sampling and digital correlated sampling to be performed simultaneously, enabling higher quality A / D conversion with less noise. In this case as well, by performing the reference voltage sweep and A / D conversion multiple times as described in Modification 1 and using the average value as the A / D conversion value of the reference analog signal during the reset period, A / D conversion with even lower noise can be performed. [Explanation of symbols]

[0080] 100 A / D converters 101 First signal input terminal 102 second signal input terminal 110 Differential Amplifier 111 First input terminal 112 Second input terminal 113 First output terminal 114 Second output terminal 120 Comparator 130 counters 140 Subtractor 150 Logic Circuits 210 Comparator 220 Time-to-Digital Converter

Claims

1. a comparator that receives an analog signal to be converted and a reference voltage that increases or decreases over time, and compares the signal voltage of the analog signal to be converted with the reference voltage; a time-to-digital converter that starts and stops time measurement using a clock based on the comparison result of the comparator, and outputs the measured time information as a converted digital signal of the converted analog signal; An analog-to-digital converter comprising: The comparator a differential amplifier having a first input terminal, a second input terminal, a first output terminal for outputting an inverted amplified signal between the first input terminal and the second input terminal, and a second output terminal for outputting a non-inverted amplified signal between the first input terminal and the second input terminal; a first signal input terminal, a second signal input terminal, a first capacitance inserted between the first input terminal and the first signal input terminal of the differential amplifier, a second capacitance inserted between the second input terminal and the second signal input terminal of the differential amplifier, a first switch inserted between the first input terminal and the first output terminal, and a second switch inserted between the second input terminal and the second output terminal; a comparison circuit for comparing a signal voltage of the converted analog signal with a threshold voltage, and if the signal voltage of the converted analog signal is greater than the threshold voltage, the converted analog signal is input to both the first signal input terminal and the second signal input terminal, the first switch and the second switch are closed to sample the converted analog signal using the first capacitor and the second capacitor, and then the first switch and the second switch are opened to output a comparison result between the signal voltage and the reference voltage when the reference voltage that increases or decreases within a full-scale voltage range is input to the second signal input terminal; and if the signal voltage of the converted analog signal is less than the threshold voltage, the first switch and the second switch are opened to output a comparison result between the signal voltage and the reference voltage when the converted analog signal is input to the first signal input terminal and the reference voltage that increases or decreases within a partial voltage range is input to the second signal input terminal. Analog-to-digital converter.

2. the comparator outputs a comparison result between a voltage of the reference analog signal and the reference voltage when a reference analog signal is input to both the first signal input terminal and the second signal input terminal, the comparator closes the first switch and the second switch to sample the reference analog signal using the first capacitor and the second capacitor, and then opens the first switch and the second switch to input the reference voltage that rises or falls within the partial voltage range to the second signal input terminal; the time-to-digital converter outputs time information measured by a clock as a conversion reference digital signal based on the output of the comparator; 2. The analog-to-digital converter according to claim 1, further comprising a subtractor that outputs a digital signal obtained by subtracting the conversion reference digital signal from the converted digital signal of the converted analog signal output by the time-to-digital converter.

3. 3. The analog-to-digital converter according to claim 2, wherein the comparator, after comparing the voltage of the reference analog signal with the reference voltage, determines whether the signal voltage of the converted analog signal is greater than or less than the threshold voltage by comparing a difference voltage between the signal voltage of the converted analog signal and the voltage of the reference analog signal with a difference voltage between the threshold voltage and the reference reference voltage when the reference reference voltage is input to the second signal input terminal, the first switch and the second switch are closed to sample the reference reference voltage using the second capacitor, and then the first switch and the second switch are opened to input the converted analog signal to the first signal input terminal and a threshold voltage is input to the second signal input terminal.

4. the comparator, after comparing the voltage of the reference analog signal with the reference voltage, inputs the reference reference voltage to the second signal input terminal, closes the first switch and the second switch to sample the reference reference voltage using the second capacitor, then opens the first switch and the second switch to input the reference analog signal to the first signal input terminal, inputs the reference voltage that increases or decreases the part of the voltage range over time to the second signal input terminal, and outputs a comparison result between the voltage of the reference analog signal and the reference voltage; the time-to-digital converter outputs the time information measured by the time-to-digital converter as a conversion reference digital signal for a reset period based on the output of the comparator; 3. The analog-to-digital converter according to claim 2, further comprising a subtractor that outputs a digital signal obtained by subtracting the converted reference digital signal from the converted digital signal output by the time-to-digital converter.

5. the comparator, when the signal voltage of the converted analog signal is smaller than the threshold voltage, executes a comparison between the signal voltage of the converted analog signal and the reference voltage a plurality of times when the reference voltage that rises or falls within the partial voltage range is input a plurality of times; The analog-to-digital converter according to any one of claims 1 to 4, wherein the time-to-digital converter records multiple pieces of time information measured by a clock multiple times based on the comparison result of the comparator, and outputs the average value of the multiple pieces of time information as a converted digital signal.

6. the comparator performs a comparison between the voltage of the reference analog signal and the reference voltage multiple times when the reference voltage that rises or falls within the partial voltage range is input multiple times; The analog-to-digital converter according to claim 2, wherein the time-to-digital converter records multiple pieces of time information measured by a clock multiple times based on the comparison result of the comparator, and outputs the average value of the multiple pieces of time information as a conversion reference digital signal.

7. the comparator performs a comparison between the voltage of the reference analog signal and the reference voltage multiple times when the reference voltage that rises or falls within the partial voltage range is input multiple times; The analog-to-digital converter according to claim 4, wherein the time-to-digital converter records multiple pieces of time information measured by a clock multiple times based on the comparison result of the comparator, and outputs an average value of the multiple pieces of time information as the conversion reference digital signal during the reset period.

8. 5. The analog-to-digital converter according to claim 1, wherein the first switch and the second switch are PMOS transistors, and the voltage of an N-well surrounding the PMOS transistor and the gate voltage of the PMOS transistor are set higher than the power supply voltage of the differential amplifier.

9. An image sensor comprising an analog-to-digital converter according to any one of claims 1 to 8.

Images