Semiconductor device and semiconductor module

Abstract

To provide a semiconductor device capable of reducing an induced current from electromagnetic induction due to electric connection between a capacitor and a semiconductor chip to suppress a fault of the semiconductor chip.SOLUTION: A semiconductor device includes: a semiconductor chip including first and second chip electrodes; a capacitor element including first and second electrodes: a support part supporting the capacitor element and the semiconductor chip and including a support portion having a main surface; first and second conductors extended so as to connect the first and second electrodes of the capacitor element to the first and second chip electrodes of the semiconductor chip, respectively; and a sealing body for surrounding the capacitor element, the semiconductor chip, the first conductor, the second conductor, and the support portion. The first and second chip electrodes of the semiconductor chip, the first and second electrodes of the capacitor element, the first conductor and the second conductor are arranged in the inside from the outer edge of the main surface in the support portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a semiconductor module, and more particularly to a semiconductor device that seals a semiconductor chip, and a semiconductor module in which a semiconductor device is mounted on a printed circuit board. [Background technology]

[0002] Patent Document 1 discloses that a capacitor is disposed near a semiconductor chip on a die pad. The semiconductor chip and the capacitor are molded with a molding resin to form a semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 8-162607 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, when a semiconductor device is configured with a semiconductor chip including a plurality of pad electrodes, a capacitor element, and a plurality of conductors electrically connecting the semiconductor chip and the capacitor element via the pad electrodes, the electrical connection consisting of one pad electrode of the semiconductor chip, one conductor, one terminal of the capacitor element, the capacitor dielectric, the other terminal of the capacitor element, the other conductor, and the other pad electrode of the semiconductor chip may function as an antenna. In this regard, the semiconductor element of Patent Document 1 does not disclose an antenna resulting from one conductor electrically connecting one terminal of the capacitor element and the semiconductor chip, and another conductor electrically connecting the other terminal of the capacitor element and the semiconductor chip.

[0005] When one pad electrode and another pad electrode of the semiconductor chip are connected to an internal circuit, the antenna forms an electrical loop. Such a loop antenna generates electromagnetic noise, which can cause problems in the semiconductor chip. For example, electromagnetic induction occurs in response to changes in the magnetic flux passing through the loop antenna, generating an induced current that can cause problems in the semiconductor chip.

[0006] An object of the present invention is to provide a semiconductor device and a semiconductor module that reduce induced current from electromagnetic induction caused by electrical connection between a capacitor element and a semiconductor chip, thereby suppressing defects in the semiconductor chip. [Means for solving the problem]

[0007] In order to solve the above problem, the semiconductor device of the present invention comprises a semiconductor chip including a first chip electrode and a second chip electrode, a capacitor element having the first electrode and the second electrode, a support portion including a support portion having a main surface that supports the capacitor element and the semiconductor chip, a first conductor and a second conductor extending to connect the first electrode and the second electrode of the capacitor element to the first chip electrode and the second chip electrode of the semiconductor chip, respectively, and a sealing body that surrounds the capacitor element, the semiconductor chip, the first conductor, the second conductor, and the support portion, wherein the first chip electrode and the second chip electrode of the semiconductor chip, the first electrode and the second electrode of the capacitor element, the first conductor, and the second conductor are arranged inside the outer edge of the main surface of the support portion.

[0008] In order to solve the above problem, the semiconductor module of the present invention comprises a semiconductor device and a printed circuit board having a main surface including a mounting area for mounting the semiconductor device, wherein the printed circuit board, the semiconductor chip, and the support portion are arranged in this order toward a first axis direction perpendicular to the main surface of the printed circuit board, the printed circuit board has a conductive layer, and the first chip electrode, the second chip electrode of the semiconductor chip, the first electrode, the second electrode, the first conductor, and the second conductor of the capacitor element are provided between the conductive layer of the printed circuit board and the support portion. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a semiconductor device and a semiconductor module that reduce induced current from electromagnetic induction caused by electrical connection between a capacitor element and a semiconductor chip, thereby suppressing defects in the semiconductor chip. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, taken along the line II-II shown in FIG. [Figure 3] FIG. 3 is a schematic diagram showing one form of a capacitor element for a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 4 is a schematic diagram showing another embodiment of a capacitor element for a semiconductor device according to an embodiment of the present invention. [Figure 5] FIG. 5 is a plan view showing a semiconductor module according to an embodiment of the present invention. [Figure 6] FIG. 6 is a cross-sectional view showing a semiconductor module according to an embodiment of the present invention, taken along the line VI-VI shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view showing a semiconductor module according to an embodiment of the present invention. [Figure 8] FIG. 8 is a plan view showing a main surface of a printed circuit board of a semiconductor module according to an embodiment of the present invention. [Figure 9] FIG. 9 is a plan view showing a main surface of a printed circuit board of a semiconductor module according to one embodiment of the present invention and a conductive layer provided on this main surface. [Figure 10] FIG. 10 is a plan view showing a main surface of a printed circuit board of a semiconductor module according to one embodiment of the present invention and a conductive layer provided on this main surface. [Figure 11] FIG. 11 is a plan view showing a main surface of a printed circuit board of a semiconductor module according to one embodiment of the present invention and a conductive layer provided on this main surface. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0012] [First embodiment] A semiconductor device according to the present embodiment will be described with reference to Figures 1 and 2. In Figure 2, hatching indicating a cross section is not drawn to avoid complicating the drawing.

[0013] 1 is a plan view of a semiconductor device 11 according to this embodiment. The semiconductor device 11 includes a semiconductor chip 13, a capacitor element 15, a support 17, a first conductor 19a, a second conductor 19b, a sealing body 23, and a third conductor 19c.

[0014] The semiconductor chip 13 includes a semiconductor integrated circuit 25 integrating multiple semiconductor elements, and may be, for example, a silicon large-scale integrated (LSI) chip. The semiconductor chip 13 includes multiple chip electrodes 27a, 27b, and 27c. The multiple chip electrodes 27a and 27b are connected to the semiconductor integrated circuit 25 via conductors, and the chip electrode 27c is connected to the support portion 17 via a conductor. Each of the multiple chip electrodes 27a, 27b, and 27c may be, for example, a pad electrode. In one embodiment, as shown in FIG. 1 , the semiconductor integrated circuit 25 of the semiconductor chip 13 may include an internal circuit 25a and another internal circuit 25b (e.g., a built-in voltage regulator) for supplying power to the internal circuit 25a. The built-in regulator has an output connected to the first chip electrode 27a of the semiconductor chip 13. Furthermore, for example, the internal circuit 25a has an output connected to the third chip electrode 27c.

[0015] Capacitor element 15 has a first electrode 29a and a second electrode 29b, with first electrode 29a separated from second electrode 29b by a dielectric of capacitor element 15. Capacitor element 15 may have a capacitance of, for example, several microfarads, specifically 0.1 to 4.7 microfarads. In one embodiment, as shown in FIG. 1, capacitor element 15 is connected to the output of the built-in regulator and to a reference potential line (e.g., ground) via first conductor 19a.

[0016] The support section 17 includes a support portion 31, which has a main surface 31a that supports the semiconductor chip 13 and the capacitor element 15. The semiconductor chip 13 and the capacitor element 15 are fixed to the main surface 31a with an adhesive. The support portion 31 is a metal body. The support portion 31 may have any shape, such as a substantially square or a substantially rectangular shape, in top view, as long as it can support the semiconductor chip 13 and the capacitor element 15. An example of the support portion 17 is a lead frame. The support portion 17 will be described in detail later.

[0017] The first conductor 19a extends to electrically connect the first electrode 29a of the capacitor element 15 to the first chip electrode 27a of the semiconductor chip 13. The second conductor 19b extends to electrically connect the second electrode 29b of the capacitor element 15 to the second chip electrode 27b of the semiconductor chip 13. The third conductor 19c extends to electrically connect the support portion 17 to the third chip electrode 27c of the semiconductor chip 13. The first conductor 19a and the second conductor 19b are interconnects that electrically connect the first chip electrode 27a and the second chip electrode 27b of the semiconductor chip 13 to the first electrode 29a and the second electrode 29b of the capacitor element 15, respectively. The third conductor 19c is an interconnect that electrically connects the third chip electrode 27c of the semiconductor chip 13 to the support portion 17.

[0018] The encapsulant 23 surrounds the semiconductor chip 13, the capacitor element 15, the first conductor 19a, the second conductor 19b, the third conductor 19c, and the support portion 31. The encapsulant 23 will be described in detail later.

[0019] In this semiconductor device 11, the semiconductor chip 13 and the capacitor element 15 are supported by and disposed on the main surface 31a of the support portion 31. The first conductor 19a and the second conductor 19b are both connected from one side of the semiconductor chip 13 to the other side of the capacitor element 15 so as to electrically connect the semiconductor chip 13 and the capacitor element 15 to each other.

[0020] With this connection, the electrical connection including the first chip electrode 27a of the semiconductor chip 13, the first conductor 19a, the first electrode 29a of the capacitor element 15, the second electrode 29b of the capacitor element 15, the second conductor 19b, and the second chip electrode 27b of the semiconductor chip 13 is electrically closed by the semiconductor integrated circuit 25 in the semiconductor chip 13, forming a loop-shaped antenna. Hereinafter, such a loop-shaped antenna will be referred to as a loop antenna. The support portion 31 shields electromagnetic noise, such as external magnetic flux, in a direction from the support portion 31 toward the capacitor element 15. This can reduce, for example, the amount of external magnetic flux penetrating the loop antenna.

[0021] If the first conductor 19a and the second conductor 19b, which are part of the loop antenna, are arranged inside the outer edge of the main surface 31a of the support portion 31, the influence of electromagnetic induction acting on the semiconductor integrated circuit 25 by the support portion 31 can be reduced.

[0022] The semiconductor device 11 can reduce induced current due to electromagnetic induction caused by the electrical connection between the semiconductor chip 13 and the capacitor element 15. It can also reduce electromagnetic induction applied to the power supply system of the internal circuit 25a from the antenna via the output of another internal circuit 25b such as a voltage regulator. This makes it possible to suppress malfunctions of the semiconductor chip 13 caused by the generation of induced current due to electromagnetic induction.

[0023] Fig. 2 is a cross-sectional view of the semiconductor device 11 taken along line II-II in Fig. 1. Referring to Fig. 2, the capacitor element 15 and the support portion 31 are arranged along an axis Ax1 extending in a direction perpendicular to the main surface 31a of the support portion 31. On the main surface 31a of the support portion 31, the semiconductor chip 13 and the capacitor element 15 are arranged spaced apart from each other, but are preferably arranged close to each other to reduce the size of the loop antenna. In Fig. 2, the first conductor 19a electrically connecting the capacitor element 15 and the semiconductor chip 13 is indicated by a dashed line.

[0024] The support portion 31 has a main surface 31a extending along a reference plane REF1 perpendicular to the axis Ax1. It can also be said that the semiconductor chip 13 and the capacitor element 15 are disposed along the reference plane REF1.

[0025] 2, the first conductor 19a is arranged such that the entire first conductor 19a is encompassed by the main surface 31a of the support portion 31 when viewed in the direction of axis Ax1 intersecting the reference plane REF1, i.e., the direction perpendicular to the main surface 31a of the support portion 31. Similarly to the first conductor 19a, the second conductor 19b is also arranged such that the entire second conductor 19b is encompassed by the main surface 31a of the support portion 31 when viewed in the direction perpendicular to the main surface 31a of the support portion 31 (not shown). In other words, the loop antenna, which is an electrical connection including the first chip electrode 27a of the semiconductor chip 13, the first conductor 19a, the first electrode 29a of the capacitor element 15, the second electrode 29b of the capacitor element 15, the second conductor 19b, and the second chip electrode 27b of the semiconductor chip 13, is arranged such that the entire loop antenna is encompassed by the main surface 31a of the support portion 31 when viewed in the direction perpendicular to the main surface 31a of the support portion 31. In this embodiment, the direction intersecting the reference plane REF1 is a vertical direction that is perpendicular to the reference plane REF1 and the main surface 31a of the support portion 31.

[0026] Therefore, when viewed from a direction perpendicular to the main surface 31a of the support portion 31, the loop antenna is positioned so that it is encompassed by the main surface 31a of the support portion 31, and the support portion 31 prevents magnetic flux from penetrating in the direction from the support portion 31 toward the capacitor element 15 and prevents electromagnetic noise from entering.

[0027] Next, a lead frame will be described as an example of the support portion 17 in the semiconductor device according to the present embodiment with reference to FIGS.

[0028] As shown in FIG. 2, the support portion 17 includes, for example, a lead frame 33. The lead frame 33 includes a die pad 33a as the support portion 31 and multiple lead terminals 33b as connection terminals for the support portion 17. The die pad 33a and the lead terminals 33b are arranged along a reference plane REF1. The die pad 33a may be, for example, a flat metal body. The lead terminals 33b are spaced apart from the die pad 33a and may be made of metal. At least some of the multiple lead terminals 33b, and in this embodiment, all of the lead terminals 33b, are bent in a direction from the die pad 33a toward the capacitor element 15. Here, the direction from the die pad 33a toward the capacitor element 15 refers to a direction downward of the first axis Ax1 in FIG. 6.

[0029] At least some of the lead terminals 33b may be arranged along one side of the die pad 33a. Referring to Fig. 1, the lead terminals 33b are arranged along any one of the four sides of the die pad 33a.

[0030] According to this semiconductor device 11, the lead frame 33 mounts the semiconductor chip 13 and the capacitor element 15, and the die pad 33a can shield against electromagnetic noise such as external magnetic fields.

[0031] Furthermore, as shown in FIG. 2, at least one of the plurality of lead terminals 33b can be provided so as to be bent in the direction from the support portion 17 toward the capacitor element 15 (and the semiconductor chip 13) inside and / or outside the sealing body.

[0032] The encapsulant 23 encapsulates the semiconductor chip 13, the capacitor element 15, the first conductor 19a, the second conductor 19b, and the die pad 33a. In this embodiment, the encapsulant 23 may include a resin body such as an epoxy resin. The die pad 33a is enclosed within the resin body of the encapsulant 23 together with the semiconductor chip 13, the capacitor element 15, the first conductor 19a, and the second conductor 19b, while at least a portion of the lead terminals 33b protrudes from the resin body of the encapsulant 23. Specifically, each of the plurality of lead terminals 33b has a first portion 33c protruding from the resin body and a second portion 33d extending within the resin body.

[0033] Each of the first conductor 19a and the second conductor 19b may include a member having the shape of a metal conductor wire, such as a bonding wire, which may be a thin gold wire. Since the bonding wire is a thin metal conductor wire, it has inductance. The loop antenna includes a series connection of an inductor and a capacitor.

[0034] Specifically, the bonding wire of the first conductor 19a extends to form part or all of the electrical connection path between the first chip electrode 27a of the semiconductor chip 13 and the first electrode 29a of the capacitor element 15. Furthermore, the bonding wire of the second conductor 19b extends to form part or all of the electrical connection path between the second chip electrode 27b of the semiconductor chip 13 and the second electrode 29b of the capacitor element 15. If necessary, at least one of the first electrode 29a and the second electrode 29b of the capacitor element 15 can be connected to the lead terminal 33b.

[0035] 1, the semiconductor chip 13 has, in addition to the plurality of chip electrodes 27a and 27b shown by way of example, a third chip electrode 27c depicted as one of the plurality of chip electrodes. The third chip electrode 27c is formed by a third conductor 19c and is connected to one of the lead terminals 33b by, for example, a bonding wire.

[0036] Next, capacitor element 15 will be described with reference to FIGS.

[0037] Referring to FIG. 3, a capacitor element 151 is shown as one embodiment of the capacitor element 15 shown in FIGS. 1 and 2. The capacitor element 151 includes a body 15a in addition to a first electrode 29a and a second electrode 29b. The body 15a of the capacitor element 151 has a main surface 15b and a back surface 15c opposite the main surface 15b. In the capacitor element 151, the first electrode 29a and the second electrode 29b can be provided on the same surface of the body 15a, for example, the main surface 15b. The back surface 15c of the capacitor element 151, like the semiconductor chip 13, is fixed to the support portion 31, for example, the main surface 31a of the die pad 33a, with an adhesive. A first conductor 19a includes a bonding wire that directly connects the first chip electrode 27a of the semiconductor chip 13 to the first electrode 29a of the capacitor element 151. Where possible, the second conductor 19 b may include a bonding wire that directly connects the second chip electrode 27 b of the semiconductor chip 13 to the second electrode 29 b of the capacitor element 151 .

[0038] Referring to FIG. 4, a capacitor element 152 is shown as another embodiment of the capacitor element 15 of FIGS. 1 and 2. The capacitor element 152 includes a body 15a in addition to a first electrode 29a and a second electrode 29b. The body 15a of the capacitor element 152 has a main surface 15b and a back surface 15c opposite the main surface 15b. In the capacitor element 152, the first electrode 29a and the second electrode 29b may be provided on the main surface 15b and the back surface 15c, respectively. The second electrode 29b of the capacitor element 152 is connected to the support portion 31, for example, the main surface 31a of the die pad 33a, by a conductive adhesive. The other of the first conductor 19a and the second conductor 19b, for example, the second conductor 19b, may include a bonding wire that directly connects the second chip electrode 27b of the semiconductor chip 13 to the support portion 31, for example, the main surface 31a of the die pad 33a.

[0039] [Second embodiment] A semiconductor module according to this embodiment will be described with reference to Figures 5, 6, and 7. In Figures 6 and 7, hatching indicating cross sections is not used to avoid cluttering the drawings. In Figures 6 and 7, first conductors 19a are indicated by dashed lines, similar to the cross section in Figure 2.

[0040] For the convenience of the following description, a second axis Ax2 and a third axis Ax3 are introduced as shown in Fig. 5. The second axis Ax2 is perpendicular to the first axis Ax1, and the third axis Ax3 is perpendicular to the first axis Ax1 and the second axis Ax2. In this embodiment, the second axis Ax2 and the third axis Ax3 are oriented along a pair of sides 13a, 13b and another pair of sides 13c, 13d of the semiconductor chip 13, respectively.

[0041] 5 is a plan view of a semiconductor module 41 according to the present embodiment. The semiconductor module 41 includes the semiconductor device 11 according to the first embodiment and a printed circuit board 43. The semiconductor device 11 is given the same reference numeral as the semiconductor device 11 according to the first embodiment, and redundant explanations will be omitted.

[0042] FIG. 6 is a cross-sectional view showing a semiconductor module 41 according to this embodiment. The printed circuit board 43 has a main surface 43a and a back surface 43b. The main surface 43a includes a mounting area 43c on which the semiconductor device 11 is mounted and a wiring area 43d surrounding the mounting area 43c. The printed circuit board 43, the semiconductor chip 13, and the support portion 31 are arranged in this order in the mounting area 43c toward the direction of a first axis Ax1 that is perpendicular to the main surface 31a of the support portion 31 and the main surface 43a of the printed circuit board 43. The printed circuit board 43 includes a conductor layer 44 for interconnection that is provided in the wiring area 43d. The conductor layer 44 is connected to the lead terminals 33b of the semiconductor device 11 mounted on the printed circuit board 43.

[0043] 5 and 6, in the semiconductor module 41, the printed circuit board 43 may have a conductive layer 45. The capacitor element 15, the first conductor 19a, and the second conductor 19b are provided between the conductive layer 45 and the support portion 31 of the printed circuit board 43.

[0044] In this semiconductor module 41, electrical connections including the first chip electrode 27a of the semiconductor chip 13, the first conductor 19a, the first electrode 29a of the capacitor element 15, the second electrode 29b of the capacitor element 15, the second conductor 19b, and the second chip electrode 27b of the semiconductor chip 13 are electrically closed by the semiconductor integrated circuit 25 in the semiconductor chip 13, forming a loop antenna. The main surface 31a of the support portion 31 supports the capacitor element 15 and the semiconductor chip 13, and the first conductor 19a and the second conductor 19b are connected from one side of the semiconductor chip 13 to the other side of the capacitor element 15. Therefore, the support portion 31 shields electromagnetic noise, such as external magnetic flux, from the support portion 31 toward the capacitor element 15. This makes it possible to reduce the amount of external magnetic flux and electromagnetic noise penetrating the loop antenna.

[0045] Furthermore, the support portion 31, the semiconductor chip 13, and the printed circuit board 43 are arranged in this order along a first axis Ax1 that is perpendicular to the main surface 31a of the support portion 31 (the main surface 43a of the printed circuit board 43). With this arrangement, the first chip electrode 27a and the second chip electrode 27b of the semiconductor chip 13, the first electrode 29a and the second electrode 29b of the capacitor element 15, the first conductor 19a, and the second conductor 19b that constitute the loop antenna within the semiconductor device 11 are positioned between the conductive layer 45 and the support portion 31. Placing the loop antenna between the conductive layer 45 and the support portion 31 can reduce the amount of external magnetic flux and external electromagnetic noise that penetrate the loop antenna.

[0046] When the first conductor 19a and the second conductor 19b, which are part of the loop antenna, are positioned inside the outer edge of the main surface 31a of the support portion 31 in top view, the influence of electromagnetic induction acting on the semiconductor integrated circuit 25 by the support portion 31 can be reduced.

[0047] Furthermore, by arranging the first conductor 19a and the second conductor 19b, which are part of the loop antenna, inside the outer edge of the main surface 31a of the support portion 31 and the outer edge of the conductive layer 45 when viewed from above, the influence of electromagnetic induction acting on the semiconductor integrated circuit 25 by the support portion 31 and the conductive layer 45 can be reduced.

[0048] Therefore, the semiconductor module 41 can reduce induced current from electromagnetic induction caused by the electrical connection between the semiconductor chip 13 and the capacitor element 15 due to the positional relationship between the first conductor 19a and the second conductor 19b and the support portion 31. Furthermore, the semiconductor module 41 can reduce induced current from electromagnetic induction caused by the electrical connection between the semiconductor chip 13 and the capacitor element 15 due to the positional relationship between the first conductor 19a and the second conductor 19b and the conductive layer 45. This makes it possible to suppress defects in the semiconductor chip 13 caused by the generation of induced current.

[0049] When the semiconductor device 11 has a lead frame 33 as the support portion 17, at least some of the multiple lead terminals 33b are bent in a direction from the die pad 33a toward the capacitor element 15, as shown in FIG. 6. Here, the direction from the die pad 33a toward the capacitor element 15 refers to the direction toward the printed circuit board 43 along the first axis Ax1 in FIG. 6. When the semiconductor device 11 is mounted on the printed circuit board 43, the bending direction, which is the direction from the die pad 33a toward the capacitor element 15 and the semiconductor chip 13, enables the die pad 33a, which is an example of the support portion 31, the first conductor 19a and the second conductor 19b, the capacitor element 15, and the conductive layer 45 of the printed circuit board 43 to be arranged in this order.

[0050] 7 is a cross-sectional view showing a semiconductor module 40 according to the present embodiment. The cross section of the semiconductor module 40 in FIG. 7 is taken so that the cross section of the semiconductor device 11 in FIG. 7 matches the cross section of the semiconductor device 11 in FIG. 6. The semiconductor module 40 includes the semiconductor device 11 according to the first embodiment and a printed circuit board 42. The semiconductor device 11 is given the same reference numeral as the semiconductor device 11 according to the first embodiment, and redundant explanations will be omitted.

[0051] The printed circuit board 42 has a main surface 42a and a back surface 42b. The main surface 42a includes a mounting area 42c on which the semiconductor device 11 is mounted and a wiring area 42d surrounding the mounting area 42c. The printed circuit board 42, the semiconductor chip 13, and the support portion 31 are arranged in this order in the mounting area 42c along a first axis Ax1 that is perpendicular to the main surface 31a of the support portion 31 and the main surface 42a of the printed circuit board 42. The printed circuit board 42 includes a conductor layer 44 for interconnection that is provided in the wiring area 42d. The conductor layer 44 is connected to the lead terminals 33b of the semiconductor device 11 mounted on the printed circuit board 42. The printed circuit board 42 differs from the printed circuit board 43 shown in FIGS. 5 and 6 in that the printed circuit board 42 does not include a conductive layer 45.

[0052] When the semiconductor device 11 has a lead frame 33 as the support portion 17, at least some of the multiple lead terminals 33b are bent in a direction from the die pad 33a toward the capacitor element 15, as shown in Fig. 7. The direction from the die pad 33a toward the capacitor element 15 here refers to the direction toward the printed circuit board 42 along the first axis Ax1 in Fig. 7. When the semiconductor device 11 is mounted on the printed circuit board 43, the bending direction, which is the direction from the die pad 33a toward the capacitor element 15 and the semiconductor chip 13, enables the die pad 33a, which is an example of the support portion 31, the first conductor 19a and the second conductor 19b, the capacitor element 15, and the printed circuit board 42 to be arranged in this order.

[0053] 8 to 11, several examples of printed circuit boards 43 are shown. The printed circuit boards 43 shown in Figures 9 to 11 include a conductive layer 45, which differs from the printed circuit board 42 shown in Figure 8. The first axis Ax1, the second axis Ax2, and the third axis Ax3 are also depicted in Figures 8 to 11.

[0054] Fig. 8 is a plan view showing the printed circuit board 42 shown in Fig. 7. Referring to Fig. 8, the printed circuit board 42 according to one embodiment is shown, and the outline of the main surface 42a of the printed circuit board 42, the first conductors 19a, and the second conductors 19b are drawn with solid lines. The semiconductor chip 13, the capacitor element 15, the encapsulant 23, the support portion 31, and the mounting area 42c are drawn with dashed lines.

[0055] The encapsulant 23 encapsulates the capacitor element 15, the semiconductor chip 13, the first conductors 19a, the second conductors 19b, and the support portion 31 (or the die pad 33a).

[0056] In this embodiment, the semiconductor chip 13 and the capacitor element 15 are supported by and disposed on the main surface 31a of the support portion 31. The first conductor 19a and the second conductor 19b are connected from one side of the semiconductor chip 13 to the other side of the capacitor element 15 to electrically connect the semiconductor chip 13 and the capacitor element 15 to each other. This connection electrically connects the first chip electrode 27a of the semiconductor chip 13, the first conductor 19a, the first electrode 29a of the capacitor element 15, the second electrode 29a of the capacitor element 15, the second conductor 19b, and the second chip electrode 27b of the semiconductor chip 13, electrically closed by the semiconductor integrated circuit 25 in the semiconductor chip 13, forming a loop antenna. The support portion 31 shields electromagnetic noise, such as external magnetic flux, from the support portion 31 toward the capacitor element 15. This can reduce the amount of external magnetic flux penetrating the loop antenna, for example.

[0057] If the first conductor 19a and the second conductor 19b, which are part of the loop antenna, are arranged inside the outer edge of the main surface 31a of the support portion 31, the influence of electromagnetic induction acting on the semiconductor integrated circuit 25 by the support portion 31 can be reduced.

[0058] Furthermore, this embodiment can reduce the induced current from electromagnetic induction caused by the electrical connection between the semiconductor chip 13 and the capacitor element 15. This makes it possible to suppress defects in the semiconductor chip 13 caused by the generation of induced current.

[0059] 9, 10, and 11, the main surface 43a of the printed circuit board 43 is shown, and the outlines of the printed circuit board 43 and the conductive layer 45, as well as the first conductors 19a and second conductors 19b, are drawn with solid lines. The outlines of the semiconductor chip 13, the capacitor element 15, the encapsulant 23, and the support portion 31 are drawn with dashed lines.

[0060] The encapsulant 23 encapsulates the capacitor element 15, the semiconductor chip 13, the first conductor 19a, the second conductor 19b, and the support portion 31 (or the die pad 33a). The encapsulant 23 has a first size SZ1 in the direction of the second axis Ax2 and a second size SZ2 in the direction of the third axis Ax3.

[0061] (Variation 1) 9, the outer edge of the conductive layer 45 of the printed circuit board 43 has a dimension in the direction of the second axis Ax2 that is smaller than the first size SZ1 and a dimension in the direction of the third axis Ax3 that is smaller than the second size SZ2. The capacitor element 15, the first conductor 19a, and the second conductor 19b are disposed between the conductive layer 45 and the support portion 31. Specifically, the outer edge of the conductive layer 45, when viewed from above in the direction of the first axis Ax1, contains a loop antenna that includes the outer edge of the capacitor element 15 and the first conductor 19a and the second conductor 19b, and overlaps with a portion of the semiconductor chip 13.

[0062] 5 and 6. Referring to FIG. 10, the outer edge of the conductive layer 45 of the printed circuit board 43 has a dimension equal to or larger than the first size SZ1 in the direction of the second axis Ax2 and a dimension equal to or larger than the second size SZ2 in the direction of the third axis Ax3. In the semiconductor module 41, the encapsulant 23 is located inside the outer edge of the simply connected conductive film 45a in a top view from the direction of the first axis Ax1. The capacitor element 15, the semiconductor chip 13, the first conductor 19a, and the second conductor 19b are disposed between the simply connected conductive film 45a and the support portion 31.

[0063] 9 and 10 , in the printed circuit board 43, the conductive layer 45 can be a single-connected conductive film 45a provided in the mounting area 43c. The first conductor 19a and the second conductor 19b are provided between the conductive film 45a and the support portion 31 of the printed circuit board 43. According to this semiconductor module 41, the single-connected conductive film 45a can be provided as the conductive layer 45 in a size that is a part of the size of the support portion 31 or that is larger than the size of the support portion 31.

[0064] The single-connected conductive film 45a can shield magnetic flux and electromagnetic noise directed from the printed circuit board 43 toward the capacitor element 15 (and / or the semiconductor chip 13).

[0065] Furthermore, the conductive film 45a and the support portion 31 of the printed circuit board 43 can reduce component costs and improve electromagnetic noise resistance without restricting the physical layout on the printed circuit board 43.

[0066] (Variation 2) Referring to FIG. 11 , the conductive layer 45 may have one or more openings. An example conductive layer 45, such as a conductive film 45b, may have, on the main surface 43a of the printed circuit board 43, a plurality of first conductive stripes 45d extending in the direction of the second axis Ax2 and a plurality of second conductive stripes 45e extending in the direction of the third axis Ax3. At least a portion of the first conductive stripes 45d intersects at least a portion of the second conductive stripes 45e. The first conductors 19a and the second conductors 19b are provided between the conductive layer 45 and the support portion 31 of the printed circuit board 43. The shape of the conductive layer 45 shown in FIG. 11 is referred to as a grid-shaped conductive film 45b. The size of one side of the grid opening may be, for example, 1 to 5 millimeters.

[0067] According to this semiconductor module 41, the conductive layer 45 is a lattice-shaped conductive film 45b, and can be provided to occupy a part of the size of the support portion 31 or to be larger than the size of the support portion 31.

[0068] The grid-like conductive film 45b can shield magnetic flux and electromagnetic noise directed from the printed circuit board 43 toward the capacitor element 15 (and / or the semiconductor chip 13).

[0069] Furthermore, the conductive film 45b of the printed circuit board 43 and the supporting portion 31 can reduce component costs and improve electromagnetic noise resistance without restricting the physical layout on the printed circuit board 43.

[0070] The outer edge of the lattice-shaped conductive film 45b can have a first size SZ1 in the direction of the second axis Ax2 and a second size SZ2 in the direction of the third axis Ax3. According to this semiconductor module 41, the sealing body 35 is located inside the outer edge of the lattice-shaped conductive film 45b in a top view from the direction of the first axis Ax1. The capacitor element 15, the semiconductor chip 13, the first conductors 19a, and the second conductors 19b are disposed between the lattice-shaped conductive film 45b and the support portion 31.

[0071] 9, the outer edge of the lattice-shaped conductive film 45b can have a dimension smaller than the first size SZ1 in the direction of the second axis Ax2 and a dimension smaller than the second size SZ2 in the direction of the third axis Ax3. The capacitor element 15, the first conductor 19a, and the second conductor 19b are disposed between the conductive film 45b and the support portion 31. Specifically, the outer edge of the conductive film 45b (conductive layer 45) contains a loop antenna including the outer edge of the capacitor element 15 and the first conductor 19a and second conductor 19b, and overlaps with a portion of the semiconductor chip 13, when viewed from above in the direction of the first axis Ax1. [Explanation of symbols]

[0072] 11 Semiconductor devices 13 Semiconductor chips 15 Capacitor element 15a main body 15b Main surface 15c back side 17 Support part 19a First Conductor 19b Second conductor 19c Third Conductor 23 Sealing body 25 Semiconductor Integrated Circuits 25a Internal circuit 25b Another internal circuit 27a First tip electrode 27b Second tip electrode 27c Third tip electrode 29a 1st electrode 29b 2nd electrode 31 Support part 31a Main surface 33 Lead Frame 33a Die pad 33b Lead terminal 40 41 Semiconductor Module 42 43 Printed Circuit Board 42a 43a Main surface 42b 43b Back side 42c 43c Mounting area 45 Conductive layer 45a, 45b Conductor film 45d First conductive stripe 45e Second conductive stripe Ax1 1st axis Ax2 2nd axis Ax3 3rd axis REF1 Reference plane SZ1, SZ2 dimensions

Claims

1. A semiconductor chip including a semiconductor integrated circuit, a first chip electrode, and a second chip electrode; a capacitor element having a first electrode and a second electrode; a support part including a support portion having a main surface for supporting the capacitor element and the semiconductor chip; a first conductor and a second conductor extending to connect the first electrode and the second electrode of the capacitor element to the first chip electrode and the second chip electrode of the semiconductor chip, respectively; an encapsulant that surrounds the capacitor element, the semiconductor chip, the first conductor, the second conductor, and the support portion; Equipped with the semiconductor integrated circuit includes an internal circuit and a voltage regulator that supplies power to the internal circuit; the voltage regulator has an output connected to the first tip electrode; the first chip electrode, the second chip electrode of the semiconductor chip, the first electrode, the second electrode, the first conductor, and the second conductor of the capacitor element are arranged inside an outer edge of the main surface of the support portion in a top view, an electrical connection including the first chip electrode, the first conductor, the first electrode of the capacitor element, the second electrode of the capacitor element, the second conductor, and the second chip electrode is electrically closed by the semiconductor integrated circuit; Semiconductor device.

2. the support includes a lead frame; the lead frame includes a die pad serving as the support portion and a plurality of lead terminals spaced apart from the die pad; the sealing body includes a resin that seals the capacitor element, the semiconductor chip, the first conductor, the second conductor, and the die pad; 2. The semiconductor device according to claim 1.

3. At least one of the plurality of lead terminals is bent in a first direction from the die pad toward the capacitor element.

3. The semiconductor device according to claim 2.

4. All of the plurality of lead terminals are bent in a first direction from the die pad toward the capacitor element.

3. The semiconductor device according to claim 2.

5. the first conductor includes a bonding wire that directly connects the first chip electrode of the semiconductor chip and the first electrode of the capacitor element; 5. The semiconductor device according to claim 1.

6. the second conductor includes a bonding wire that directly connects the second chip electrode of the semiconductor chip and the main surface of the support portion; the second electrode of the capacitor element is connected to the main surface of the support portion by a conductive adhesive; the second conductor includes a bonding wire that directly connects the second chip electrode of the semiconductor chip and the second electrode of the capacitor element; 6. The semiconductor device according to claim 1.

7. An interconnect that connects the capacitor element to the outside is arranged inside the outer edge of the main surface of the support portion when viewed from above.

6. The semiconductor device according to claim 1.

8. A semiconductor device according to any one of claims 1 to 7; a printed circuit board having a main surface including a mounting area for mounting the semiconductor device; Including, the first chip electrode, the second chip electrode of the semiconductor chip, the first electrode, the second electrode, the first conductor, and the second conductor of the capacitor element are provided between the printed circuit board and the support portion; Semiconductor module.

9. A semiconductor device according to any one of claims 1 to 7; a printed circuit board having a main surface including a mounting area for mounting the semiconductor device; Including, the printed circuit board, the semiconductor chip, and the support portion are arranged in this order along a first axis perpendicular to the main surface of the printed circuit board; the printed circuit board has a conductive layer; the first chip electrode, the second chip electrode of the semiconductor chip, the first electrode, the second electrode, the first conductor, and the second conductor of the capacitor element are provided between the conductive layer and the support portion of the printed circuit board; Semiconductor module.

10. the conductive layer has a plurality of first conductive stripes extending in a first direction on the main surface of the printed circuit board and a plurality of second conductive stripes extending in a second direction intersecting the first direction; At least a portion of the first conductive stripe intersects at least a portion of the second conductive stripe.

10. The semiconductor module according to claim 9.

11. the conductive layer is a single-connected conductive film provided on the mounting area; 10. The semiconductor module according to claim 9.

12. The outer edge of the conductive layer includes the outer edge of the capacitor element, the first conductor, and the second conductor in the direction of the first axis, and overlaps with a part of the semiconductor chip. The semiconductor module according to claim 11.

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