METAL FILM, METAL FILM MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Abstract

To provide a metal film and a method for manufacturing the metal film, a semiconductor device, and a method for manufacturing the semiconductor device that have high crack resistance (high hardness) during wire bonding.SOLUTION: A metal film MF includes a plurality of first metal crystal grains GR2, GR3, and GR4, and a plurality of second metal crystal grains GR1 and GR5. Each of the plurality of first metal crystal grains GR2, GR3, and GR4 has a dislocation DL. Each of the plurality of second metal crystal grains GR1 and GR5 does not have dislocations DL. The number of first metal crystal grains GR2, GR3, and GR4 having dislocations DL is greater than the number of second metal crystal grains GR1 and GR5 not having dislocations DL.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a metal film, a method for manufacturing a metal film, a semiconductor device, and a method for manufacturing a semiconductor device. [Background technology]

[0002] In Japanese Patent Laid-Open Publication No. 2007-165663 (Patent Document 1), a stress relaxation film is formed on a conductive film to reduce warpage of a semiconductor wafer. The conductive film serves as a gate pad or a source pad and is made of aluminum (Al) or the like. The conductive film is formed by sputtering. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-165663 Summary of the Invention [Problem to be solved by the invention]

[0004] Aluminum pads are required to have high crack resistance (high hardness) during wire bonding.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] In the metal film according to one embodiment, the number of first metal crystal grains having dislocations is greater than the number of second metal crystal grains having no dislocations.

[0007] A semiconductor device according to one embodiment has the metal film as a bonding pad or wiring.

[0008] According to a method for manufacturing a metal film according to one embodiment, after point defects are introduced into the metal film, annealing is performed to recrystallize the metal crystal grains, thereby forming dislocations in the metal film.

[0009] According to a method for manufacturing a semiconductor device according to one embodiment, the metal film is formed as a bonding pad or wiring. [Effects of the Invention]

[0010] According to the above-described embodiment, a metal film having high crack resistance (high hardness) during wire bonding, a method for manufacturing a metal film, a semiconductor device, and a method for manufacturing a semiconductor device are realized. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 2 is a cross-sectional view showing the configuration of a metal film according to an embodiment. [Figure 2] 2 is a cross-sectional view showing the configuration of an IGBT (Isolated Gate Bipolar Transistor) having the metal film shown in FIG. [Figure 3] 3 is a cross-sectional view showing the configuration of a semiconductor package having the IGBT shown in FIG. 2. [Figure 4] 1 is a cross-sectional view showing a first step of a method for manufacturing a metal film according to an embodiment. [Figure 5] FIG. 4 is a cross-sectional view showing a second step of the method for manufacturing a metal film according to the embodiment. [Figure 6] FIG. 4 is a cross-sectional view showing a third step of the method for manufacturing a metal film according to the embodiment. [Figure 7] FIG. 10 is a plan view showing the configuration of a photoresist mask for selectively implanting ions into a region for wire bonding. [Figure 8] FIG. 10 is a diagram showing a cross section of a metal film according to a comparative example in which ion implantation is not performed. [Figure 9] FIG. 1 is a diagram showing a cross section of a metal film into which aluminum ions have been implanted. [Figure 10]FIG. 1 is a diagram showing a cross section of a metal film into which silicon ions have been implanted. [Figure 11] FIG. 10 is a diagram showing a cross-sectional view of a metal film according to a comparative example that is annealed without ion implantation. [Figure 12] FIG. 1 is a diagram showing a cross-sectional view of a metal film that has been annealed after aluminum ion implantation. [Figure 13] FIG. 10 is a diagram showing a cross-sectional view of a metal film that has been annealed after silicon ion implantation. [Figure 14] FIG. 10 is a diagram showing the degree of relaxation of internal stress in a metal film due to ion implantation. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the specification and drawings, the same or corresponding components are designated by the same reference numerals, and redundant explanations will not be repeated. In addition, in the drawings, for the sake of convenience, configurations or manufacturing methods may be omitted or simplified.

[0013] In this specification, "planar view" refers to a viewpoint seen from a direction perpendicular to the first surface FS of the semiconductor substrate, "planar shape" refers to a shape in a planar view, and "opening area" refers to the area of ​​an opening in a planar view.

[0014] <Metal film composition> First, the configuration of a metal film according to an embodiment of the present disclosure will be described with reference to FIG.

[0015] 1, the metal film MF is made of a material containing one or more selected from the group consisting of aluminum, tungsten (W), copper (Cu), cobalt (Co), and nickel (Ni). The metal film MF is made of a material containing aluminum, such as pure aluminum, an alloy of aluminum and silicon (Si), an alloy of aluminum and copper, or an alloy of aluminum, silicon, and copper. The metal film MF has a thickness of, for example, 1 μm or more and 4 μm or less.

[0016] The metal film MF has a plurality of metal crystal grains GR. The plurality of metal crystal grains GR include first metal crystal grains GR2, GR3, and GR4 having dislocations DL and second metal crystal grains GR1 and GR5 having no dislocations DL. The number of metal crystal grains GR2, GR3, and GR4 having dislocations DL is greater than the number of metal crystal grains GR1 and GR5 not having dislocations DL.

[0017] The metal film MF has a first surface FS and a second surface SS that face each other. Each of the plurality of metal crystal grains GR extends from the first surface FS toward the second surface SS and reaches the second surface SS. The density of dislocations DL in each of the plurality of first metal crystal grains GR2, GR3, and GR4 is 60 / μm 2 The density of dislocations DL in each of the plurality of first metal crystal grains GR2, GR3, and GR4 is 75 / μm 2 It may be more than that.

[0018] The plurality of metal crystal grains GR have an average crystal grain size of 1 μm or more and 5 μm or less. The plurality of metal crystal grains GR may have an average crystal grain size of 1.7 μm or less. The metal film MF has a hardness of 0.96 GPa or more. The metal film MF may also have a hardness of 1.17 GPa or more.

[0019] The metal film MF may have third metal crystal grains GRA. The third metal crystal grains GRA are located at grain boundaries GB of the metal crystal grains GR. The third metal crystal grains GRA may be disposed away from both the first surface FS and the second surface SS of the metal film MF. One third metal crystal grain GRA may be located at one grain boundary GB, or multiple third metal crystal grains GRA may be located at one grain boundary GB. Furthermore, a third metal crystal grain GRA may be located at each of multiple grain boundaries GB.

[0020] The third metal crystal grains GRA are made of a different material from the first metal crystal grains GR2, GR3, GR4 and the second metal crystal grains GR1, GR5. When the first metal crystal grains GR2, GR3, GR4 and the second metal crystal grains GR1, GR5 are each made of a material containing aluminum, the third metal crystal grains GRA may be made of a material containing silicon or copper, for example. <Configuration of semiconductor device> Next, the configuration of an IGBT will be described as an example of a semiconductor device having the metal film MF of this embodiment with reference to FIGS. 2 and 3. FIG.

[0021] 2, the electric element formed on the semiconductor substrate SB is, for example, an IGBT. + Collector region CR and n + Region HR and n - A drift region DRI, a p-type base region BR, and a p + Contact area CON and n + It mainly has an emitter region ER and a gate electrode GE.

[0022] p + The collector region CR is disposed on the first main surface FMS of the semiconductor substrate SB. + On the collector region CR (p + On the second main surface (SMS side) with respect to the collector region (CR) + Area HR is located. n + The area HR is p + It forms a pn junction with the collector region CR.

[0023] n + On area HR(n + On the second principal surface (SMS side) relative to the region HR - The drift region DRI is located. - The drift region DRI is n + It borders the region HR. - The drift region DRI is n + The n-type impurity concentration is lower than that of the region HR.

[0024] n- On the drift region DRI (n - A p-type base region BR is disposed on the second main surface SMS side with respect to the drift region DRI. - It forms a pn junction with the drift region DRI.

[0025] On the p-type base region BR (on the second main surface SMS side with respect to the p-type base region BR), + Contact areas CON and n + The emitter region ER is located. + Contact areas CON and n + Each of the emitter regions ER is disposed on the second main surface SMS of the semiconductor substrate SB.

[0026] p + The contact region CON is in contact with the p-type base region BR. + The contact region CON has a p-type impurity concentration higher than the p-type impurity concentration of the p-type base region BR. + The emitter region ER is p + A pn junction is formed with each of the contact region CON and the p-type base region BR.

[0027] The semiconductor substrate SB is provided with a trench TR. The trench TR extends from the second main surface SMS to the n + The emitter region ER and the p-type base region BR are penetrated by n - The trench TR reaches the drift region DRI. A gate insulating layer GI is arranged along the inner wall of the trench TR. The inside of the trench TR is filled with a gate electrode GE. The gate electrode GE faces the p-type base region BR with the gate insulating layer GI interposed therebetween. This forms an IGBT having an insulated gate field effect transistor portion.

[0028] Through the contact hole CH of the interlayer insulating layer IL, + Emitter region ER and p +An emitter electrode EE is disposed so as to be electrically connected to each of the contact regions CON. The emitter electrode EE has a barrier metal layer BM and a metal film MF. The barrier metal layer BM is electrically connected to the n-type contact region MC through the contact holes CH. + Emitter region ER and p + The metal film MF is in contact with each of the contact regions CON. The metal film MF is in contact with the barrier metal layer BM.

[0029] A collector electrode CE is disposed on the first main surface FMS of the semiconductor substrate SB. + By contacting the collector region CR, + It is electrically connected to the collector region CR.

[0030] The metal film MF shown in Fig. 1 is used as, for example, the metal film MF of the IGBT shown in Fig. 2. The metal film MF shown in Fig. 2 functions as an emitter pad (bonding pad) and wiring in the IGBT. Therefore, the metal film MF shown in Fig. 1 is used as a bonding pad and wiring in the IGBT shown in Fig. 2. The metal film MF shown in Fig. 1 may also be used for other bonding pads such as a gate pad and other wiring in the IGBT.

[0031] The metal film MF shown in FIG. 1 may be used for bonding pads and wiring such as source pads and gate pads of a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) other than the IGBT shown in FIG.

[0032] 3, the semiconductor device SD according to this embodiment is, for example, a semiconductor package in which a semiconductor chip SC is sealed with a sealing resin SRE. The semiconductor device SD according to this embodiment has a chip mounting portion RB, a semiconductor chip SC, lead portions RD1 and RD2, bonding wires BW (BW1 and BW2), and the sealing resin SRE.

[0033] The semiconductor chip SC has an IGBT and a metal film MF shown in Fig. 2. The semiconductor chip SC has an emitter pad EP electrically connected to the emitter region ER (Fig. 2) of the IGBT, and a gate pad GP electrically connected to the gate electrode GE. Each of the emitter pad EP and the gate pad GP is made of the metal film MF shown in Fig. 1.

[0034] The semiconductor chip SC is mounted on the chip mounting portion RB with solder SOL interposed therebetween. Each of the lead portions RD1 and RD2 is disposed at a distance from the chip mounting portion RB. A bonding wire BW1 electrically connects the emitter pad EP of the semiconductor chip SC to the lead portion RD1. Although only one bonding wire BW1 is shown for simplicity of illustration, multiple bonding wires BW1 may be connected between the emitter pad EP and the lead portion RD1. A bonding wire BW2 electrically connects the gate pad GP of the semiconductor chip SC to the lead portion RD2.

[0035] The sealing resin SRE seals the chip mounting portion RB, the semiconductor chip SC, the lead portions RD1 and RD2, the clip conductor CC, and the bonding wires BW (BW1 and BW2). Parts of the chip mounting portion RB and the lead portions RD1 and RD2 are exposed from the sealing resin SRE. The sealing resin SRE is made of, for example, a thermosetting resin material and may also contain a filler (for example, a filler made of silica particles).

[0036] <Metal Film and Semiconductor Device Manufacturing Method> Next, a method for manufacturing a metal film and a semiconductor device according to an embodiment of the present disclosure will be described with reference to FIGS.

[0037] 4, a metal film MF is formed from a material containing one or more elements selected from the group consisting of aluminum, tungsten, copper, cobalt, and nickel. The metal film MF is formed from a material containing aluminum, such as pure aluminum, an alloy of aluminum and silicon, an alloy of aluminum and copper, or an alloy of aluminum, silicon, and copper.

[0038] The metal film MF is formed by, for example, sputtering. The metal film MF is formed to a thickness of, for example, 1 μm or more and 4 μm or less. The metal film MF is formed to have a plurality of metal crystal grains GR. Large internal stress is generated inside the metal film MF.

[0039] 5, for example, vacancies V are introduced as point defects into the metal film MF. It is believed that the vacancies V introduced into the metal film MF are diffused by the large internal stress within the metal film MF.

[0040] The vacancies V are introduced by, for example, implanting metal ions into the metal film MF. This ion implantation is performed at a rate of, for example, 1×10 16 cm -2 More than 1×10 18 cm -2 The ion implantation is performed at a dose of less than 100 keV. The implantation energy is, for example, 100 keV or more, but can be changed appropriately depending on the implantation depth, etc. The metal ions to be implanted are, for example, any one of aluminum, silicon, copper, tungsten, cobalt, and nickel, or any combination thereof.

[0041] The vacancies V may be introduced into the metal film MF by, for example, irradiating the metal film MF with an electron beam. Alternatively, the vacancies V may be introduced into the metal film MF by a combination of ion implantation and electron beam irradiation.

[0042] As shown in FIG. 6, after the point defects (vacancies V) are introduced, the metal film MF is annealed. This annealing is performed, for example, in an inert gas atmosphere at a heating temperature of 300° C. to 400° C. for a heating time of less than two hours. The annealing recrystallizes a plurality of metal crystal grains GR in the metal film MF. The recrystallization of the metal crystal grains GR generates dislocations DL in the metal film MF.

[0043] The annealing causes plastic deformation of the metal film MF, and it is believed that this plastic deformation is accelerated by point defects (vacancies V), causing vacancies to gather in some metal crystal grains and generating dislocations DL.

[0044] As a result, first metal crystal grains GR12 and GR13 having dislocations DL and second metal crystal grains GR11 without dislocations DL are generated among the plurality of metal crystal grains GR. Also, the number of first metal crystal grains GR12 and GR13 having dislocations DL becomes greater than the number of second metal crystal grains GR11 without dislocations DL.

[0045] The metal film MF of this embodiment is manufactured by the above steps. In the ion implantation shown in Fig. 5, silicon or the like is implanted into the metal film MF made of a material containing aluminum, for example. In this case, the implanted silicon or the like diffuses due to the heat and implantation energy during the ion implantation. The diffused silicon or the like diffuses into the grain boundaries GB of the metal crystal grains GR as shown in Fig. 1 and precipitates as third metal crystal grains GRA.

[0046] 5 may be performed on the entire surface of the metal film MF, or may be performed on only a partial region of the metal film MF. The ion implantation may be selectively performed, for example, on a portion of the metal film MF where a bonding wire BW is to be connected.

[0047] In this case, as shown in Figure 7, ion implantation is performed with a photoresist mask PM formed on the metal film MF. This photoresist mask PM has a plurality of openings PRA that expose the surface of the metal film MF. Each of the plurality of openings PRA has, for example, a rectangular planar shape. Each of the plurality of openings PRA may have, for example, a circular planar shape. The opening areas of the plurality of openings PRA may be the same as or different from each other.

[0048] The surface of the metal film MF exposed by the opening PRA is the portion to which the bonding wire BW is connected. By performing the annealing process after at least performing ion implantation into the portion to which the bonding wire BW is connected, the portion to which the bonding wire BW is connected can be locally hardened, thereby improving crack resistance.

[0049] When ion implantation is performed selectively in this way, the number of metal crystal grains with dislocations DL is greater than the number of metal crystal grains without dislocations DL in the region of the metal film MF where ion implantation has been selectively performed. On the other hand, when ion implantation is performed on the entire surface of the metal film MF, the number of metal crystal grains with dislocations DL is greater than the number of metal crystal grains without dislocations DL throughout the entire metal film MF.

[0050] The method for manufacturing the metal film MF of this embodiment is also used to manufacture the semiconductor device shown in Fig. 2. For example, the metal film MF of this embodiment is formed as a bonding pad or wiring, thereby manufacturing the semiconductor device shown in Fig. 2.

[0051] Specifically, as shown in FIG. 2, for example, an IGBT is formed on the semiconductor substrate SB. After the IGBT is formed, an interlayer insulating layer IL is formed on the second main surface SMS of the semiconductor substrate SB. A contact hole CH is formed in the interlayer insulating layer IL by photolithography and etching techniques. The contact hole CH has an n + Emitter region ER and p +The contact holes are formed in the interlayer insulating layer IL so as to expose the surfaces of the contact regions CON. Although not shown in the drawing, contact holes are also formed in the interlayer insulating layer IL so as to expose parts of the gate electrodes GE.

[0052] Through the contact hole CH + Emitter region ER and p + A barrier metal layer BM is formed on the interlayer insulating layer IL so as to contact each of the contact regions CON. A barrier metal layer is also formed so as to contact the gate electrode GE through the contact hole. A metal film MF that will become wiring and a bonding pad (emitter pad or gate pad) is formed so as to contact the barrier metal layer BM. This metal film MF is the metal film MF manufactured by the method shown in FIGS. 4 to 6.

[0053] <Effects> Next, the effects of this embodiment will be described together with the findings of the inventors of the present disclosure.

[0054] First, the inventors of the present disclosure formed a metal film MF made of aluminum-copper (AlCu) by sputtering, prepared a sample in which ions were not implanted into the metal film MF, and a sample in which ions were implanted, and observed their cross sections.

[0055] As a result, no dense point defects were observed in the sample without ion implantation, as shown in Figure 8. In contrast, as shown in Figure 9, when the implantation energy was 100 keV and the dose was 1 × 10 16 cm -2 In the sample implanted with aluminum ions under the conditions, dense point defects were observed from the surface of the metal film MF to a depth of 300 nm to 400 nm (dotted line DOL). As shown in Figure 10, when the implantation energy was 100 keV and the dose was 1 × 10 16 cm -2 Even in the sample in which silicon ions were implanted under the conditions, dense point defects were confirmed from the surface of the metal film MF to a depth of 300 nm to 400 nm (dotted line DOL).

[0056] The inventors of the present disclosure also annealed a sample of a metal film MF made of aluminum and copper, one without ion implantation and the other with ion implantation, and observed their cross sections. The annealing was performed in an inert gas atmosphere at a heating temperature of 300°C to 400°C for a heating time of less than two hours.

[0057] As a result, as shown in Figure 11, in the sample without ion implantation, dislocations were observed, but the number of metal crystal grains with dislocations was extremely small. On the other hand, as shown in Figure 12, in the sample with implantation energy of 180 keV and dose of 1 × 10 16 cm -2 In the sample implanted with aluminum ions under the conditions, dislocations occurred in many metal crystal grains, and it was found that the dislocation density was higher than that of the sample without ion implantation. Also, as shown in Figure 13, when the implantation energy was 180 keV and the dose was 1×10 16 cm -2 It was found that even in the sample where silicon ions were implanted under the conditions, dislocations occurred in many metal crystal grains, and the dislocation density was higher than in the sample where ion implantation was not performed. Furthermore, it was found that in the sample where ion implantation was performed as shown in Figures 12 and 13, the number of metal crystal grains with dislocations was greater than the number of metal crystal grains without dislocations.

[0058] The inventors of the present disclosure also investigated the relationship between the presence or absence of ion implantation into the metal film MF and stress relaxation, and the results are shown in FIG.

[0059] 14, it was found that Samples 1 and 2, which had undergone ion implantation into the metal film MF, had less warpage than the comparative sample, which did not undergo ion implantation into the metal film MF, and that the internal stress in the metal film MF was alleviated. In particular, it was found that the warpage of Sample 2 after annealing was 34% smaller than the warpage of the comparative sample after annealing.

[0060] In addition, all of Sample 1, Sample 2, and the comparative example are metal films MF made of aluminum formed to a thickness of 1 μm by sputtering at a temperature of 250° C. Sample 1 is formed by implanting ions at an implant energy of 180 keV and a dose of 1×10 16 cm -2 The sample 2 was implanted with aluminum ions at an implantation energy of 180 keV and a dose of 1×10 16 cm -2 The sample was implanted with silicon ions under the following conditions: Annealing was performed in an inert gas atmosphere at a heating temperature of 400°C for 30 minutes.

[0061] The inventors of the present disclosure also investigated the dislocation density and hardness of Sample 1, Sample 2, and the comparative example after annealing in Figure 14. As a result, the dislocation density of the comparative example was 28 / µm 2 The hardness was 0.92 GPa. In contrast, the dislocation density of sample 1 was 60 / μm 2 The hardness was 0.96 GPa. The dislocation density of sample 2 was 75 / μm 2 The hardness was 1.17 GPa.

[0062] The inventors of the present disclosure also confirmed that the crystal orientation and resistance of a metal film MF that has been annealed for recrystallization are equivalent to the crystal orientation and resistance of a metal film that has not been subjected to ion implantation, and that this poses no practical problems.

[0063] Dislocation density can be determined by observing the cross section of the metal film MF with a TEM (transmission electron microscope) and counting the number of dislocations. Crystal grain size can be determined by observing the metal film MF from above with a SEM (scanning electron microscope) to determine the area of ​​the crystal grains and then calculating the diameter of a perfect circle corresponding to that area.

[0064] Based on the above, the inventors of the present disclosure have discovered that high-density dislocations occur in the metal film MF by injecting metal ions into the metal film MF to introduce point defects (vacancies V) and then performing recrystallization annealing. The reason for the high-density dislocations is thought to be that the metal film MF undergoes plastic deformation upon annealing, and the introduced point defects (vacancies V) accelerate this plastic deformation and become concentrated in some crystal grains. The inventors of the present disclosure have also discovered that the high-density dislocations harden the metal film MF, increasing its strength, thereby improving the crack resistance of wire bonding.

[0065] In this embodiment, the number of first metal crystal grains GR2, GR3, and GR4 having dislocations DL is greater than the number of second metal crystal grains GR1 and GR5 having no dislocations DL, which increases the strength of the metal film MF and improves the crack resistance of wire bonding.

[0066] In this embodiment, the metal film MF is made of a material containing one or more selected from the group consisting of aluminum, tungsten, copper, cobalt, and nickel. This allows the metal film MF to be used for wiring and bonding pads. Furthermore, using a material containing aluminum for the metal film MF can provide even higher crack resistance during wire bonding.

[0067] In this embodiment, the density of dislocations DL in each of the plurality of first metal crystal grains GR2, GR3, and GR4 is 60 / μm 2 This makes it possible to prevent cracks from occurring during wire bonding.

[0068] In this embodiment, the average grain size of the metal crystal grains GR, including the first metal crystal grains GR2, GR3, and GR4 and the second metal crystal grains GR1 and GR5, is 1 μm or more and 5 μm or less. If the average grain size is less than 1 μm, the number of grain boundaries increases, resulting in reduced electromigration resistance and stress migration resistance. If the average grain size exceeds 5 μm, the hardness decreases.

[0069] In this embodiment, the average grain size of the metal grains GR is 1.7 μm or less, which improves hardness.

[0070] 1, the third metal crystal grains GRA are located at the grain boundaries GB of a plurality of metal crystal grains GR, including metal crystal grains GR2, GR3, and GR4 and second metal crystal grains GR1 and GR5. The presence of the third metal crystal grains GRA at the grain boundaries GB makes it difficult for metal elements in the metal film MF to move. This improves the electromigration resistance and stress migration resistance.

[0071] In this embodiment, the metal crystal grains GR2, GR3, and GR4 and the second metal crystal grains GR1 and GR5 are each made of a material containing aluminum, and the third metal crystal grains GRA are made of a material containing silicon or copper, which allows the third metal crystal grains GRA to precipitate at the grain boundaries of the plurality of metal crystal grains GR.

[0072] In this embodiment, after point defects (vacancies V) are introduced into the metal film MF as shown in Fig. 5, dislocations DL are generated in the metal film MF by performing annealing to recrystallize a plurality of metal crystal grains GR as shown in Fig. 6. This makes it possible to generate high-density dislocations, which increases the strength of the metal film MF and improves the crack resistance of wire bonding.

[0073] In this embodiment, the step of introducing point defects (vacancies V) into the metal film MF includes at least one of the steps of injecting metal ions into the metal film MF and irradiating the metal film MF with an electron beam, thereby introducing point defects (vacancies V) into the metal film MF.

[0074] Furthermore, aluminum wiring is required to have high resistance to electromigration and stress migration when large currents flow in power devices. With aluminum films formed by conventional sputtering, it is difficult to achieve both crack resistance and resistance to electromigration and stress migration.

[0075] However, according to this embodiment, as described above, it is easy to achieve both crack resistance and electromigration and stress migration resistance.

[0076] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0077] BM barrier metal layer, BR p-type base region, BW, BW1, BW2 bonding wires, CE collector electrode, CH contact hole, CL conductive layer, CON contact region, CR collector region, DL dislocation, DOL dotted line, DRI n - Drift region, EP Emitter pad, ER n + Emitter region, FMS first principal surface, FS first surface, GE gate electrode, GI gate insulating layer, GP gate pad, GR metal crystal grain, GR1, GR5 second metal crystal grain, GR2, GR3, GR4 first metal crystal grain, GRA third metal crystal grain, HR n + Area, IL interlayer insulating layer, MF metal film, PM photoresist mask, PRA opening, RB chip mounting area, RD1, RD2 lead area, SB semiconductor substrate, SC semiconductor chip, SD semiconductor device, SMS second main surface, SRE sealing resin, SS second surface, TR trench, V vacancy.

Claims

1. a plurality of first metal grains, each having a dislocation; and second metal grains having no dislocations, the dislocations are formed by plastic deformation of the metal film; The number of the first metal crystal grains is greater than the number of the second metal crystal grains.

2. 2. The metal film according to claim 1, which is made of a material containing at least one selected from the group consisting of aluminum, tungsten, copper, cobalt, and nickel.

3. The density of the dislocations in each of the plurality of first metal crystal grains is 60 / μm 2 The metal film according to claim 1 .

4. The metal film according to claim 1 , wherein the average crystal grain size of the plurality of metal crystal grains including the first metal crystal grains and the second metal crystal grains is 1 μm or more and 5 μm or less.

5. The metal film according to claim 4 , wherein the average crystal grain size of the plurality of metal crystal grains is 1.7 μm or less.

6. The metal crystalline grains further include third metal crystal grains located at grain boundaries of the plurality of metal crystal grains including the first metal crystal grains and the second metal crystal grains, The metal film according to claim 1 , wherein the third metal crystal grains are made of a material different from that of the first metal crystal grains and the second metal crystal grains.

7. each of the first metal crystal grains and the second metal crystal grains is made of a material containing aluminum; The metal film according to claim 6 , wherein the third metal crystal grains are made of a material containing silicon or copper.

8. A semiconductor device having the metal film according to claim 1 as a bonding pad or wiring.

9. forming a metal film having a plurality of metal crystal grains; introducing point defects into the metal film; and after the introduction of the point defects, performing annealing to recrystallize the plurality of metal crystal grains, thereby plastically deforming the metal film and generating dislocations in the metal film.

10. the annealing forms a plurality of first metal crystal grains having dislocations and a plurality of second metal crystal grains not having dislocations in the metal film; The method for manufacturing a metal film according to claim 9 , wherein the number of the first metal crystal grains is greater than the number of the second metal crystal grains.

11. 10. The method for manufacturing a metal film according to claim 9, wherein the step of introducing point defects into the metal film includes at least one of the steps of implanting metal ions into the metal film and irradiating the metal film with an electron beam.

12. A method for manufacturing a semiconductor device, comprising forming the metal film as a bonding pad or wiring by the method for manufacturing a metal film according to claim 9.

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