Semiconductor Devices

Abstract

To further suppress an A / D conversion error that is caused by an IR drop in an external power supply voltage and become particularly noticeable in low illuminance in a column ADC.SOLUTION: In a voltage comparator 30 for a column ADC, a differential amplifier 31 operates with a first power supply voltage VDDA supplied from the outside, and amplifies and outputs the differential voltage between a reference voltage Vramp and a detection voltage Vpix. A single-ended amplifier 32 operates on a second power supply voltage VDDC, and receives the differential voltage amplified by the differential amplifier 31 as input. A voltage conversion circuit 50 generates the second power supply voltage VDDC by stepping down the first power supply voltage VDDA. The voltage conversion circuit 50 operates to keep the second power supply voltage VDDC constant regardless of fluctuations in the first power supply voltage VDDA.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, which is suitable for use in, for example, a column ADC (Analog-to-Digital Converter). [Background technology]

[0002] CMOS (Complementary Metal Oxide Semiconductor) image sensors generally use column ADCs that operate in parallel for each column. In recent years, column ADCs have adopted a double-clamp method in which the comparators of each ADC are configured with two amplifier stages in order to reduce area and noise.

[0003] The inventors of this paper, F. Morishita et al. (Non-Patent Document 1), have disclosed a technique for further reducing the area and noise. Specifically, in the column ADC described in this document, the first-stage amplifier is configured as a fully differential amplifier, while the second-stage amplifier is configured as a single-ended amplifier. Furthermore, to suppress IR drop in the power supply line and ground line, a current compensation circuit is provided that operates complementarily with the second-stage amplifier. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] F. Morishita et al., "A CMOS Image Sensor and an AI Accelerator for Realizing Edge-Computing-Based Surveillance Camera Systems," 2021 Symposium on VLSI Circuits, 2021, pp. 1-2, doi: 10.23919 / VLSICircuits52068.2021.9492514. Summary of the Invention [Problem to be solved by the invention]

[0005] According to Figure 6 of the above-mentioned Non-Patent Document 1, the output reduction caused by IR drop (so-called shading noise) has been suppressed more than before. However, the improvement in A / D conversion error in low illuminance (night vision) is not sufficient, and non-negligible errors are observed.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A voltage comparator for a column ADC according to one embodiment includes a voltage conversion circuit that reduces a first power supply voltage supplied from an external source to a first-stage differential amplifier and generates a second power supply voltage supplied to a second-stage single-ended amplifier. The voltage conversion circuit operates to keep the second power supply voltage constant regardless of fluctuations in the first power supply voltage. [Effects of the Invention]

[0008] According to the above embodiment, it is possible to suppress A / D conversion errors that are caused by an IR drop in the external power supply voltage and that become noticeable particularly in the case of low illuminance. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a configuration of a CMOS image sensor 10 as a semiconductor device according to a first embodiment. [Figure 2] 2 is an equivalent circuit diagram showing an example of the configuration of each pixel 25 that configures the pixel array 11 of FIG. 1. FIG. [Figure 3] 2 is a diagram illustrating the configuration of the column ADC 12 in FIG. 1 in more detail. [Figure 4] 3 is a timing diagram conceptually showing an example of input and output signals of a voltage comparator 30. FIG. [Figure 5]10 is a diagram for explaining the supply of a power supply voltage VDD and a ground voltage GND to each voltage comparator 30 that constitutes the column ADC 12. FIG. [Figure 6] 2 is a circuit diagram showing a detailed configuration example of a voltage comparator 30 of the present embodiment. FIG. [Figure 7] FIG. 10 is a timing diagram for explaining the operation of the column ADC. [Figure 8] FIG. 10 is a block diagram showing a configuration of a column ADC 12A according to a second embodiment. [Figure 9] 9 is a circuit diagram showing the configuration of each voltage comparator 30A in FIG. 8. FIG. [Figure 10] 9 is a circuit diagram showing a configuration of a voltage conversion circuit 60 of FIG. 8. DETAILED DESCRIPTION OF THE INVENTION

[0010] Each embodiment will be described in detail below with reference to the drawings. While the following description will primarily focus on a voltage comparator used in a column ADC in an image sensor, the technology of the present disclosure is not limited to image sensors. For example, the column ADC of the present disclosure can also be applied to a capacitance sensor. In the following description, identical or corresponding parts are denoted by the same reference numerals, and their description may not be repeated.

[0011] First Embodiment [Example of CMOS image sensor configuration] 1 is a block diagram showing the configuration of a CMOS image sensor 10 as a semiconductor device according to a first embodiment. Note that the semiconductor device in this disclosure may refer to the entire semiconductor integrated circuit formed on a semiconductor chip, or may refer to a part of the circuit. For example, a column ADC may be considered a semiconductor device, or a voltage comparator included in each ADC may be considered a semiconductor device.

[0012] The configuration and operation of the CMOS image sensor 10 will be described below, divided into (1) a part for acquiring pixel signals, (2) a part for A / D converting the acquired pixel signals, and (3) other parts.

[0013] (1. Acquiring pixel signals) 1, a CMOS image sensor 10 includes a pixel array 11 including a plurality of pixels arranged in a matrix, and a vertical scanning circuit (V-scanner) 17. The row direction of the pixel array 11 is also referred to as the X direction or horizontal direction, and the column direction is also referred to as the Y direction or vertical direction. As will be described later, vertical signal lines 26 are provided corresponding to the columns of the pixel array 11, and horizontal signal lines TX, RX, and SL are provided corresponding to the rows of the pixel array 11. The configuration and operation of each pixel will be briefly described below.

[0014] FIG. 2 is an equivalent circuit diagram showing an example configuration of each pixel 25 constituting the pixel array 11 of FIG. 1. As shown in FIG. 2, each pixel 25 includes a photodiode (photoelectric conversion element) 3, a floating diffusion 7, a transfer transistor 2, and a reset transistor 1. The photodiode 3 converts an optical signal into an electrical signal (charge). The floating diffusion 7 accumulates the charge generated by the photodiode 3 and has a voltage corresponding to the amount of charge generated. The transfer transistor 2 transfers the charge generated by the photodiode 3 to the floating diffusion 7. The reset transistor 1 resets the floating diffusion 7 to a predetermined voltage level (for example, a power supply voltage VDD).

[0015] Each pixel 25 further includes an amplification transistor 4 and a selection transistor 5. The amplification transistor 4 extracts the voltage generated in the floating diffusion 7 in source follower mode. The selection transistor 5 transmits the voltage extracted by the amplification transistor 4 to the corresponding vertical signal line 26. The sources of the selection transistors 5 of each pixel 25 provided in the same column are connected to the vertical signal line 26 corresponding to that column.

[0016] The gates of the reset transistors 1 of the pixels 25 in the same row are connected to the horizontal signal line RX corresponding to that row. Similarly, the gates of the transfer transistors 2 of the pixels 25 in the same row are connected to the horizontal signal line TX corresponding to that row. The gates of the selection transistors 5 of the pixels 25 in the same row are connected to the horizontal signal line SL corresponding to that row.

[0017] 1 controls the voltages of the horizontal signal lines TX, RX, and SL to sequentially select each row and extract the electrical signals obtained by photoelectric conversion from the pixels of the selected row. Specifically, the following control is executed for each row.

[0018] First, the vertical scanning circuit 17 controls the transfer transistor 2 to be turned off, the selection transistor 5 to be turned on, and the reset transistor 1 to be turned on, thereby resetting the charge in the floating diffusion 7.

[0019] Next, the vertical scanning circuit 17 turns off the reset transistor 1. Then, the potential of the floating diffusion 7 at this time is read out as a dark signal via the vertical signal line 26 by the column ADC 12, which will be described later.

[0020] Next, the vertical scanning circuit 17 turns on the transfer transistor 2 to transfer the charge accumulated in the photodiode 3 to the floating diffusion 7 in response to the optical signal. The potential of the floating diffusion 7 at this time is read out as a bright signal by the column ADC 12 (described later) via the vertical signal line 26. The signal of each pixel corresponds to the difference between the bright signal and the dark signal. This method of extracting pixel signals with suppressed reset noise (i.e., kTC noise) is called CDS (Correlated Double Sampling).

[0021] (2. A / D conversion of pixel signals) 1 again, the CMOS image sensor 10 further includes single-slope column ADCs 12 that perform AD conversion for each column of the pixel array 11. Specifically, the column ADCs 12 include a voltage comparator 30 and a latch circuit (Latch) 13 that are provided for each column of the pixel array 11. The column ADCs 12 further include a counter circuit (Global Counter) 14, a ramp voltage generator (Ramp) 15, and a bias voltage generator (Bias / BGR) 16 that are common to all columns.

[0022] Fig. 3 is a diagram showing in more detail the configuration of the column ADC 12 of Fig. 1. Fig. 3 shows an example in which n voltage comparators 30_1 to 30_n and n latch circuits 13_1 to 13_n are provided, where n is the number of columns of the pixel array 11. The n voltage comparators 30_1 to 30_n and the n latch circuits 13_1 to 13_n operate in parallel.

[0023] 3, each voltage comparator 30 includes a differential amplifier 31, a single-ended amplifier 32, and a binarization circuit 33. A two-stage series configuration (a so-called double clamp system) consisting of the differential amplifier 31 and the single-ended amplifier 32 enables a small area and low noise. Furthermore, by using the single-ended amplifier 32 as the second-stage amplifier, further reductions in area and power consumption are achieved.

[0024] Specifically, a non-inverting input node of the differential amplifier 31 is connected to the vertical signal line 26 of the corresponding column via a capacitance element C1. As a result, a detection voltage (pixel voltage Vpix in the case of FIG. 3) from a pixel (Pix) 25 of a row selected by the vertical scanning circuit 17 of FIG. 1 is input to the non-inverting input node of the differential amplifier 31. The lower the illuminance, the higher the pixel voltage Vpix, and the higher the illuminance, the lower the pixel voltage Vpix. An inverting input node of the differential amplifier 31 is connected to a voltage supply line 36 via a capacitance element C2 for receiving a common reference voltage (ramp voltage Vramp in the case of FIG. 3). The differential amplifier 31 amplifies the difference voltage between the pixel voltage Vpix and the ramp voltage Vramp, and outputs the amplified difference voltage.

[0025] The output voltage of the differential amplifier 31 is input to the single-ended amplifier 32. The single-ended amplifier 32 further amplifies the input voltage and outputs it to the binarization circuit 33. The binarization circuit 33 outputs a high level ("1") or low level ("0") signal according to the voltage level of the voltage input from the single-ended amplifier 32.

[0026] The ramp voltage generator 15 generates a ramp voltage Vramp whose voltage value decreases in proportion to the elapsed time, and outputs the generated ramp voltage Vramp to a voltage supply line 36. The ramp voltage generator 15 outputs the ramp voltage Vramp in synchronization with the digital code output from the counter circuit 14.

[0027] 3, the ramp voltage generator 15 includes a D / A (Digital-to-Analog) converter 34 and a unity-gain buffer 35. The ramp voltage generator 15 outputs the ramp voltage Vramp generated by the D / A converter 34 to a voltage supply line 36 via the unity-gain buffer 35.

[0028] The latch circuit 13 holds the digital code output from the counter circuit 14 when the output signal of the binarization circuit 33 of the voltage comparator 30 for the corresponding column changes from low to high. The digital code held in the latch circuit 13 is output to the logic circuit 20 shown in Fig. 1. Based on this digital code, the logic circuit 20 determines the voltage level of the ramp voltage Vramp when the pixel voltage Vpix and the ramp voltage Vramp intersect.

[0029] FIG. 4 is a timing diagram conceptually illustrating an example of input and output signals of the voltage comparator 30. The timing diagram of FIG. 4 shows the waveforms of the input signals (Inputs of Comparator) of the voltage comparator 30, i.e., the ramp voltage Vramp and the pixel voltage Vpix. Furthermore, the timing diagram of FIG. 4 shows the waveform of the output signal (Output of Comparator) of the voltage comparator 30. The horizontal axis of FIG. 4 represents the digital code output from the counter circuit 14. The digital code output from the counter circuit 14 corresponds to the elapsed time.

[0030] 4, after the digital code output from the counter circuit 14 is reset to 0, when the digital code is Ct1, the ramp voltage Vramp output from the ramp voltage generator 15 starts to decrease. When the pixel voltage Vpix and the ramp voltage Vramp intersect, the output signal of the voltage comparator 30 switches from low (L) level to high (H) level.

[0031] Each latch circuit 13 holds the digital code Ct2 output from the counter circuit 14 in response to switching of the output signal of the corresponding voltage comparator 30. Therefore, the digital value of the pixel voltage Vpix can be detected based on the difference between the digital codes Ct2 and Ct1.

[0032] 3 again, the bias voltage generator (Bias / BGR) 16 generates a bias current that is commonly used by each voltage comparator 30. The generated bias current is distributed to each voltage comparator 30 using a current mirror.

[0033] 3, the bias voltage generator 16 includes a constant current source 37 and a diode-connected NMOS (N-channel MOS) transistor 38. The constant current source 37 is configured using a reference voltage circuit with a band gap reference (BGR) for temperature compensation. The NMOS transistor 38 is connected between the constant current source 37 and a ground line to which a ground voltage GND is applied. The gate of the NMOS transistor 38 is connected to the gate of the NMOS transistor provided in each voltage comparator 30 via a common bias line 39, thereby configuring a current mirror.

[0034] The bias voltage generator 16 may include a constant current source and a diode-connected PMOS (P-channel MOS) transistor. In this case, the diode-connected PMOS transistor is connected between the constant current source and a power supply line to which the power supply voltage VDD is applied. A current mirror is formed by connecting the gate of the PMOS transistor to the gate of the PMOS transistor provided in each voltage comparator 30 via a common bias line.

[0035] (3. Other) Referring back to FIG. 1, the CMOS image sensor 10 further includes a regulator circuit (Regulator) 18, a high-speed interface (High-Speed ​​I / F) 19, and a logic circuit 20.

[0036] The regulator circuit 18 is a circuit for stabilizing the power supply voltage. The high-speed interface 19 converts the A / D converted pixel signals for n columns into serial signals by parallel-serial conversion and then outputs them to the outside of the CMOS image sensor 10. The high-speed interface 19 also receives commands and the like from the outside. The logic circuit 20 controls the overall operation of the CMOS image sensor 10 in accordance with the commands given from the outside.

[0037] [Problems with power supply voltage to column ADC] FIG. 5 is a diagram for explaining the supply of the power supply voltage VDD and the ground voltage GND to each voltage comparator 30 constituting the column ADC 12. In FIG.

[0038] FIG. 5A is a diagram illustrating the connections between the power supply terminal 40, the ground terminal 41, the power supply line 44, and the ground line 45 and each voltage comparator 30. Typically, as shown in FIG. 5A, the power supply terminal 40 and the ground terminal 41 are provided at both ends of the arrangement direction of n (n is, for example, several thousand) voltage comparators 30 arranged in the row direction X. Alternatively, the power supply terminal 40 and the ground terminal 41 may be provided at only one end of the arrangement direction of the n voltage comparators 30. The power supply line 44 and the ground line 45 are connected to the power supply terminal 40 and the ground terminal 41, respectively, and extend in the row direction X. Each voltage comparator 30 is connected to the common power supply line 44 and ground line 45.

[0039] 5B is a diagram for explaining IR drops occurring in the power supply line 44 and the ground line 45. The horizontal axis of the diagram represents the column position, and the vertical axis represents the voltages of the power supply line 44 and the ground line 45.

[0040] A bias current flows steadily through each voltage comparator 30 of the column ADC 12, and the magnitude of this current is approximately 10 μA per voltage comparator 30. Because the column ADC 12 is provided with several thousand voltage comparators 30, the IR drop occurring in the power supply line 44 and the ground line 45 becomes significant.

[0041] 5B, assume that 3.0 V is externally supplied as the power supply voltage for the analog circuit and 1.2 V is externally supplied as the power supply voltage for the logic circuit. In this case, the power supply voltage near the center of power line 44 may drop by about 0.1 V due to IR drop. Also, the ground voltage near the center of ground line 45 may rise by about 0.1 V due to IR drop.

[0042] The decrease in power supply voltage and increase in ground voltage caused by the IR drop described above reduces the bias current near the center in the row direction X. As a result, errors occur in the A / D conversion of the column ADCs 12 near the center. The errors become particularly large when capturing images in low illumination.

[0043] Furthermore, when the CMOS image sensor 10 is integrated with other functional blocks on a semiconductor chip, the power supply lines for the entire chip are not optimized for supplying power to the column ADC 12. As a result, the IR drop becomes more pronounced. The circuit configuration of the voltage comparator described below aims to solve the above problem.

[0044] [Voltage comparator circuit configuration] 6 is a circuit diagram showing a detailed configuration example of the voltage comparator 30 of this embodiment. Referring to Fig. 6, the voltage comparator 30 includes a voltage conversion circuit 50 and a repeater circuit 57 in addition to the differential amplifier 31, single-ended amplifier 32, and binarization circuit 33 described with reference to Fig. 3.

[0045] Furthermore, the voltage comparator 30 is provided with a power supply line 51 for supplying an externally applied power supply voltage VDDA for the analog circuit, and a ground line 52 for supplying a ground voltage GNDA for the analog circuit. The voltage comparator 30 is also provided with a power supply line 53 for supplying an externally applied power supply voltage VDDL for the logic circuit, and a ground line 54 for supplying a ground voltage GNDL for the logic circuit. The voltage comparator 30 is also provided with a local power supply line 56 for supplying a power supply voltage VDDC converted from the power supply voltage VDDA by the voltage conversion circuit 50.

[0046] The power supply voltage VDDL is lower than the power supply voltage VDDA, and the power supply voltage VDDC is set to a voltage equal to the power supply voltage VDDL. For example, the power supply voltage VDDA is 3.0 V, and the power supply voltages VDDL and VDDC are 1.2 V.

[0047] An example configuration of the differential amplifier 31 will be described below. As shown in Fig. 6, the differential amplifier 31 includes PMOS transistors PM1, PM2, and PM3, NMOS transistors NM1 and NM2, and switch elements AZ1 and AZ2. A power supply voltage VDDA for the analog circuit and a ground voltage GNDA for the analog circuit are supplied to the differential amplifier 31. The connections of the elements constituting the differential amplifier 31 will be briefly described below.

[0048] The PMOS transistor PM1 and the NMOS transistor NM1 are connected in series in this order between the intermediate node N1 and the ground line 52. The PMOS transistor PM2 and the NMOS transistor NM2 are connected in series in this order between the intermediate node N1 and the ground line 52 in parallel with the MOS transistors PM1 and NM1 connected in series.

[0049] The PMOS transistors PM1 and PM2 form an input transistor pair. A ramp voltage Vramp is input to the gate of the PMOS transistor PM1 via a capacitance element C2. A pixel voltage Vpix is ​​input to the gate of the PMOS transistor PM2 via a capacitance element C1. The gate of the NMOS transistor NM1 is connected to its own drain and the gate of the NMOS transistor NM2. As a result, the NMOS transistors NM1 and NM2 form a current mirror circuit.

[0050] The PMOS transistor PM3 is connected between the power supply line 51 and the intermediate node N1. A common bias voltage Vbias is supplied to the gate of the PMOS transistor PM3, causing the PMOS transistor PM3 to function as a constant current source.

[0051] A connection node N3 between the PMOS transistor PM2 and the NMOS transistor NM2 is connected as an output node of the differential amplifier 31 to a single-ended amplifier 32 at the next stage.

[0052] The switch element AZ1 is connected between a connection node N2 of the MOS transistors PM1 and NM1 and the gate of the PMOS transistor PM1. The switch element AZ2 is connected between a connection node N3 of the MOS transistors PM2 and NM2 and the gate of the PMOS transistor PM2. By turning on the switch elements AZ1 and AZ2, the input offset of the differential amplifier 31 is removed. After that, the switch elements AZ1 and AZ2 are turned off, and the counter circuit 14 starts counting up and sweeping the ramp voltage Vramp.

[0053] Next, a configuration example of the single-ended amplifier 32 will be described. As shown in Fig. 6, the single-ended amplifier 32 includes a PMOS transistor PM4, an NMOS transistor NM3, a capacitive element C3, and a switch element AZ3. A local power supply voltage VDDC and a ground voltage GNDA for the analog circuit are supplied to the single-ended amplifier 32. The connections of the elements that make up the single-ended amplifier 32 will be briefly described below.

[0054] The PMOS transistor PM4 and the NMOS transistor NM3 are connected in series in this order between the power supply line 56 and the ground line 52. The capacitance element C3 is connected between the gate and source of the PMOS transistor PM4. The switch element AZ3 is connected between the gate and source of the PMOS transistor PM4. The switch element AZ3 is controlled to a closed state when a predetermined voltage is charged to the capacitance element C3, and is controlled to an open state while the voltage comparator 30 is operating.

[0055] The charging voltage of the capacitance element C3 is biased to the gate of the PMOS transistor PM4, so that the PMOS transistor PM4 is used as a current source for passing the current i1. Therefore, the NMOS transistor NM3 functions as a source-grounded amplifier circuit with the current source as a load.

[0056] The gate of the NMOS transistor NM3, which is the input node of the single-ended amplifier 32, is connected to a connection node N3, which is the output node of the preceding differential amplifier 31. A connection node N4 between the PMOS transistor PM4 and the NMOS transistor NM3 is connected to the binarization circuit 33 in the next stage as the output node of the single-ended amplifier 32.

[0057] Here, it is possible to supply the bias voltage of the PMOS transistor PM4 via a bias line common to each voltage comparator 30. However, because the output voltage of the single-ended amplifier 32 changes abruptly, noise called rush current is carried on the common bias line. Therefore, a self-bias circuit using a capacitance element C3 is used to prevent kickback to the other voltage comparators 30.

[0058] As shown in FIG. 6, the voltage conversion circuit 50 includes a PMOS transistor PM5 and a differential amplifier L1.

[0059] The PMOS transistor PM5 is connected between a power supply line 51 to which a power supply voltage VDDA for the analog circuit is supplied from the outside and a local power supply line 56. The output node of the differential amplifier L1 is connected to the gate of the PMOS transistor PM5, and the non-inverting input node of the differential amplifier L1 is connected to the power supply line 56. The power supply voltage VDDL for the logic circuit is applied to the inverting input node of the differential amplifier L1.

[0060] According to the above configuration, the voltage conversion circuit 50 generates a power supply voltage VDDC that is lower than the power supply voltage VDDA. Even if the power supply voltage VDDA drops due to an IR drop, the voltage conversion circuit 50 can maintain the value of the power supply voltage VDDC at a constant value that is approximately equal to the power supply voltage VDDL for the logic circuit. As a result, the current i1 flowing through the PMOS transistor PM4 can also be maintained approximately constant, eliminating the need for a current compensation circuit such as that disclosed in Non-Patent Document 1.

[0061] The binarization circuit 33 includes a PMOS transistor PM6 and an NMOS transistor NM4. The transistors PM6 and NM4 are connected in series in this order between a power supply line 56 for supplying the power supply voltage VDDC generated by the voltage conversion circuit 50 and a ground line 54 for the logic circuit. The gate of the PMOS transistor PM6 is connected to a connection node N4, which is the output node of the single-ended amplifier 32, as an input node of the binarization circuit 33. A connection node N5 between the PMOS transistor PM6 and the NMOS transistor NM4 is connected to a repeater circuit 57 in the next stage as an output node of the binarization circuit 33.

[0062] The operation of the binarization circuit 33 can be briefly explained as follows. Before the voltage comparator 30 operates, a reset signal RSP is input to the gate of the NMOS transistor NM4, causing the NMOS transistor NM4 to enter a conductive state. This resets the connection node N5 to the ground voltage GNDL. This state corresponds to the L state of the binarization circuit 33. Thereafter, the binarization circuit 33 changes to the H state in response to the input signal to the gate of the PMOS transistor PM6 (corresponding to times t4 and t9 in FIG. 7, which will be described later).

[0063] The repeater circuit 57 includes cascaded inverters L2 and L3, and operates on a power supply voltage VDDL for the logic circuit and a ground voltage GNDL for the logic circuit. The input node of the inverter L2 is connected to the connection node N5, which is the output node of the binarization circuit 33, as the input node of the repeater circuit 57.

[0064] In the configuration of the voltage comparator 30 described above, the NMOS transistor NM3 of the differential amplifier 31, the voltage conversion circuit 50, and the single-ended amplifier 32 must have a breakdown voltage equal to or greater than the power supply voltage VDDA. Therefore, these parts (parts not enclosed by the dashed-dotted line 58 in FIG. 6) are configured with so-called thick-film transistors, which have relatively thick gate insulating films and relatively high threshold voltages. On the other hand, the breakdown voltage of the binarization circuit 33, the repeater circuit 57, and the PMOS transistor PM4 of the single-ended amplifier 32 only needs to be lower than the power supply voltage VDDA and higher than the power supply voltage VDDL (equal to VDDC). Therefore, these parts (parts enclosed by the dashed-dotted line 58 in FIG. 6) are configured with so-called thin-film transistors, which have relatively thin gate insulating films and relatively low threshold voltages.

[0065] By using the transistor PM6 with a relatively low breakdown voltage as described above, the PMOS transistor PM6 can be made sufficiently conductive even when the output of the single-ended amplifier 32 has a low amplitude due to a low-illumination image signal. As a result, the output signal Cout of the binarization circuit 33 can be changed to the H level relatively sharply, thereby reducing A / D conversion errors.

[0066] [Column ADC operation] 7 is a timing diagram for explaining the operation of the column ADC. Figure 7 shows digital CDS operation. The operation of the column ADC 12 will be explained below, summarizing the explanation so far with reference to Figure 6. The following operation of the column ADC 12 is controlled by the logic circuit 20 in Figure 1.

[0067] In FIG. 7, in the waveforms of the power supply voltage VDDC and the output voltage Cout of the binarization circuit 33, the solid line indicates the case of the column ADC 12 of this embodiment, and the dashed line indicates the case of the prior art (Non-Patent Document 1).

[0068] Up to time t5 in FIG. 7, reset conversion for detecting the pixel voltage Vpix in the reset state is shown.

[0069] Specifically, at time t1, the counter circuit 14 starts counting. At this time t1, the output voltage of the ramp voltage generator 15 is the maximum voltage (power supply voltage VDD). Also, since the NMOS transistor NM3 is in a non-conductive state, the current i1 flowing through the PMOS transistor PM4 is zero.

[0070] At the next time t2, the output voltage (ramp voltage Vramp) of the ramp voltage generator 15 starts to decrease.

[0071] At the next time t3, the ramp voltage Vramp intersects with the reset-state pixel voltage Vpix, causing the NMOS transistor NM3 to conduct and current i1 to begin flowing through the PMOS transistor PM4. This causes a sudden voltage change due to IR drop in the power supply voltage VDDA for the analog circuit and the ground voltage GNDA for the analog circuit. However, because these power supply voltages VDDA and GNDA are used in the differential amplifier 31, they do not affect the operation of the voltage comparator 30. Meanwhile, the IR drop in the power supply voltage VDDC used in the single-ended amplifier 32 is significantly improved compared to the prior art.

[0072] At the next time t4, the output voltage Cout of the binarization circuit 33 switches from L level to H level. The latch circuit 13 stores the digital code output from the counter circuit 14 at that time as reset data Dr. In this embodiment, the output voltage Cout of the binarization circuit 33 rises sharply, which reduces A / D conversion errors.

[0073] After time t5 in FIG. 7, signal conversion is shown, which detects a pixel voltage Vpix corresponding to a pixel signal.

[0074] Specifically, at time t6, the counter circuit 14 starts counting. At this time t6, the output voltage of the ramp voltage generator 15 is the maximum voltage (power supply voltage VDD). Also, since the NMOS transistor NM3 is in a non-conductive state, the current i1 flowing through the PMOS transistor PM4 is zero.

[0075] At the next time t7, the output voltage (ramp voltage Vramp) of the ramp voltage generator 15 starts to decrease.

[0076] At the next time t8, the ramp voltage Vramp intersects with the pixel voltage Vpix of the pixel signal, causing the NMOS transistor NM3 to become conductive and causing a current i1 to start flowing through the PMOS transistor PM4. The IR drop in the power supply voltage VDDC used in the single-ended amplifier 32 is improved compared to the prior art.

[0077] At the next time t9, the output voltage Cout of the binarization circuit 33 switches from L level to H level. The latch circuit 13 stores the digital code output from the counter circuit 14 at that time as signal data Ds.

[0078] [Effects of the First Embodiment] As described above, the column ADC 12 of the first embodiment is provided with the voltage conversion circuit 50 as a local regulator for generating the power supply voltage VDDC. This allows real-time compensation for current changes in the single-ended amplifier 32 of the voltage comparator 30, thereby suppressing IR drop in the power supply voltage VDDC. As a result, the A / D conversion characteristics for low-illumination images can be improved. Furthermore, the current compensation circuit required in the prior art (Non-Patent Document 1) can be eliminated.

[0079] Furthermore, according to the column ADC 12 of the first embodiment, the PMOS transistor PM4 of the single-ended amplifier 32 and the binarization circuit 33 can be configured using so-called thin-film transistors with relatively thin gate insulating films. This allows the power supply voltage VDDL (or VDDC) for the logic circuit to be used for all signal propagation after the single-ended amplifier 32. This prevents delays even in the case of low-amplitude pixel signals generated in low-illumination images, and does not degrade the A / D conversion characteristics.

[0080] Furthermore, as described above, the current compensation circuit is not required, and the single-end amplifier 32 and binarization circuit 33 can be configured using thin film transistors, which allows the circuit area to be reduced.

[0081] Furthermore, by providing the voltage conversion circuit 50 as a local regulator, excessive restrictions imposed on the layout of power supply wiring to suppress IR drop are eliminated, making it easier to provide circuit wiring information for the voltage comparator alone and the column ADC as intellectual property (IP).

[0082] <Second embodiment> In the first embodiment, a voltage conversion circuit 50 was provided for each voltage comparator 30. In the column ADC 12A of the second embodiment, one voltage conversion circuit 60 is provided for multiple voltage comparators 30, so that the voltage conversion circuits 60 are distributed. This makes it possible to further reduce the circuit area of ​​the column ADC. This will be described in detail below with reference to the drawings.

[0083] 8 is a block diagram showing the configuration of a column ADC 12A according to the second embodiment. In the example shown in FIG. 8, a voltage conversion circuit 60 serving as a local regulator is provided for each of eight voltage comparators 30A. The voltage conversion circuit 60 is disposed between the arrays of eight latch circuits 13 corresponding to the eight voltage comparators 30A. A power supply voltage VDDC output from the voltage conversion circuit 60 is supplied to the corresponding voltage comparator 30A via a local power supply line 56 extending in the row direction X.

[0084] Other points in FIG. 8 are similar to those in FIG. 3, so the same or corresponding parts are given the same reference numerals and description thereof will not be repeated.

[0085] Figure 9 is a circuit diagram showing the configuration of each voltage comparator 30A in Figure 8. Voltage comparator 30A in Figure 9 differs from voltage comparator 30 in Figure 6 in that it does not include voltage conversion circuit 50. Other points in Figure 9 are the same as those in Figure 6, so the same or corresponding parts are given the same reference characters and description thereof will not be repeated.

[0086] Fig. 10 is a circuit diagram showing the configuration of the voltage conversion circuit 60 of Fig. 8. The voltage conversion circuit 60 of Fig. 10 corresponds to the voltage conversion circuit 50 of Fig. 6. Specifically, the voltage conversion circuit 60 includes a PMOS transistor PM7 and a differential amplifier L4.

[0087] The PMOS transistor PM7 is connected between a power supply line 61 to which a power supply voltage VDDA for the analog circuit is supplied from the outside and a local power supply line 56. The output node of the differential amplifier L4 is connected to the gate of the PMOS transistor PM7, and the non-inverting input node of the differential amplifier L4 is connected to the power supply line 56. The power supply voltage VDDL for the logic circuit is applied to the inverting input node of the differential amplifier L4.

[0088] According to the above configuration, the power supply voltage VDDC of the power supply line 56 can be kept constant regardless of changes in the power supply voltage VDDA. When a current i1 flows through the corresponding eight voltage comparators 30A, 8×i1 flows through the PMOS transistor PM7 of the voltage conversion circuit 60. Fluctuations in this current 8×i1 can be suppressed.

[0089] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0090] 1 reset transistor, 2 transfer transistor, 3 photodiode, 4 amplification transistor, 5 selection transistor, 7 floating diffusion, 10 image sensor, 11 pixel array, 12, 12A column ADC, 13 latch circuit, 14 counter circuit, 15 ramp voltage generator, 16 bias voltage generator, 17 vertical scanning circuit, 18 regulator circuit, 19 high-speed interface, 20 logic circuit, 25 pixel, 26 vertical signal line, 30, 30A voltage comparator, 31 differential amplifier, 32 single-ended amplifier, 33 binarization circuit, 34 D / A converter, 35 buffer, 36 voltage supply line, 37 constant current source, 38, NM1 to NM4, PM1 to PM7 MOS transistors, 39 bias line, 40 power supply terminal, 41 ground terminal, 44, 51, 53, 56, 61 power supply line, 45, 52, 54 Ground line, 50,60 voltage conversion circuit, 57 repeater circuit, AZ1,AZ2,AZ3 switch elements, C1,C2,C3 capacitance elements, Cout output signal, GND,GNDA,GNDL ground voltage, L1,L4 differential amplifier, L2,L3 inverter, RSP reset signal, RX,SL,TX horizontal signal line, VDD,VDDA,VDDC,VDDL power supply voltage, Vbias bias voltage, Vpix pixel voltage, Vramp ramp voltage.

Claims

1. A semiconductor device comprising: a voltage comparator that compares a reference voltage with a detection voltage, the voltage comparator comprising: a differential amplifier that operates on a first power supply voltage supplied from an external source, has a first input node to which the reference voltage is input and a second input node to which the detection voltage is input, and amplifies and outputs a differential voltage between the reference voltage and the detection voltage; a single-ended amplifier that operates on a second power supply voltage and to which the differential voltage amplified by the differential amplifier is input; the semiconductor device further includes a voltage conversion circuit that generates the second power supply voltage by stepping down the first power supply voltage; The voltage conversion circuit operates to keep the second power supply voltage constant regardless of fluctuations in the first power supply voltage.

2. a counter circuit that outputs a digital code; a ramp voltage generator that generates, as the reference voltage, a ramp voltage that changes in synchronization with changes in the digital code; 2. The semiconductor device according to claim 1, further comprising: a latch circuit that holds said digital code as a value corresponding to a digitally converted value of said detection voltage in response to a change in the output signal of said voltage comparator.

3. The single-ended amplifier a first transistor of a first conductivity type, the differential voltage amplified by the differential amplifier being input to a control electrode thereof; a second transistor of a second conductivity type opposite to the first conductivity type, the second transistor being connected between the first transistor and a power supply line to which the second power supply voltage is supplied, the second transistor having a control electrode to which a constant voltage is input; the plurality of transistors constituting the differential amplifier and the first transistor are thick-film transistors having a breakdown voltage higher than the first power supply voltage, 2. The semiconductor device according to claim 1, wherein said second transistor is a thin film transistor having a breakdown voltage lower than said first power supply voltage and higher than said second power supply voltage.

4. the voltage comparator further includes a binarization circuit that receives the signal amplified by the single-ended amplifier and operates on the second power supply voltage; 4. The semiconductor device according to claim 3, wherein the transistors constituting the binarization circuit are thin film transistors.

5. The single-ended amplifier 4. The semiconductor device according to claim 3, further comprising a capacitive element connected between said control electrode of said second transistor and a power supply line to which said second power supply voltage is supplied, said capacitive element holding said constant voltage input to said control electrode.

6. A semiconductor device comprising n (n is an integer of 2 or more) voltage comparators that compare a common reference voltage with a corresponding detection voltage, and each of the n voltage comparators: a differential amplifier that operates on a common first power supply voltage supplied from an external source, has a first input node to which the reference voltage is input and a second input node to which the corresponding detection voltage is input, and amplifies and outputs a difference voltage between the reference voltage and the corresponding detection voltage; a single-ended amplifier that receives the differential voltage amplified by the differential amplifier and operates on a second power supply voltage; the semiconductor device further includes a plurality of voltage conversion circuits each provided corresponding to one or more differential amplifiers; each of the plurality of voltage conversion circuits generates the second power supply voltage by stepping down the first power supply voltage, and supplies the generated second power supply voltage to the corresponding one or more differential amplifiers; Each of the plurality of voltage conversion circuits operates to keep the second power supply voltage constant regardless of fluctuations in the first power supply voltage.

7. a counter circuit that outputs a digital code; a ramp voltage generator that generates, as the reference voltage, a ramp voltage that changes in synchronization with changes in the digital code; further comprising n latch circuits respectively corresponding to the n voltage comparators; 7. The semiconductor device according to claim 6, wherein each of said n latch circuits holds said digital code as a value corresponding to a digitally converted value of said corresponding detection voltage in response to a change in the output signal of said corresponding voltage comparator.

8. the n voltage comparators are arranged in a first direction; The semiconductor device includes: one or two power supply terminals provided at one or both ends of the n voltage comparators in an arrangement direction, for receiving the first power supply voltage from an external source; one or two ground terminals provided at one or both ends of the n voltage comparators in an arrangement direction, for receiving a ground voltage supplied to the n voltage comparators from an external source; a metal power supply wiring connected to the one or two power supply terminals and extending in the first direction; 8. The semiconductor device according to claim 7, further comprising: a metal ground wiring connected to said one or two ground terminals and extending in said first direction.

9. a pixel array in which pixels are arranged in m rows (m is an integer of 2 or more) and n columns; a scanning circuit for selecting one pixel row out of the m rows constituting the pixel array, the n voltage comparators are arranged adjacent to each other in a column direction of the pixel array, and are provided corresponding to the n pixel columns, respectively; 8. The semiconductor device according to claim 7, wherein each of the n voltage comparators is configured to compare a pixel signal from a row selected by the scanning circuit among a corresponding pixel column with the ramp voltage as the corresponding detection voltage.

10. The single-ended amplifier a first transistor of a first conductivity type, the differential voltage amplified by the differential amplifier being input to a control electrode thereof; a second transistor of a second conductivity type opposite to the first conductivity type, the second transistor being connected between the first transistor and a power supply line to which the second power supply voltage is supplied, the second transistor having a control electrode to which a constant voltage is input; the plurality of transistors constituting the differential amplifier and the first transistor are thick-film transistors having a breakdown voltage higher than the first power supply voltage, 7. The semiconductor device according to claim 6, wherein said second transistor is a thin film transistor having a breakdown voltage lower than said first power supply voltage and higher than said second power supply voltage.

11. each of the n voltage comparators further includes a binarization circuit that receives the signal amplified by the single-ended amplifier and operates on the second power supply voltage; 11. The semiconductor device according to claim 10, wherein the transistors constituting the binarization circuit are the thin film transistors.

12. The single-ended amplifier 12. The semiconductor device according to claim 11, further comprising a capacitive element connected between the control electrode of the second transistor and a power supply line to which the second power supply voltage is supplied, the capacitive element holding the constant voltage input to the control electrode.

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