Digital Isolator

Abstract

To provide a digital isolator capable of reducing current consumption.SOLUTION: A digital isolator according to an embodiment includes: an edge detection circuit configured to detect an edge of a pulse of a signal based on an input signal input and to output a first detection signal and a second detection signal; a driving buffer circuit configured to output a first drive signal based on the first detection signal and to output a second drive signal based on the second detection signal; an isolation element configured to receive to output a first edge signal based on the first drive signal from a first output on a secondary side and to output a second edge signal based on the second drive signal from a second output on the secondary side; a receiving inverter circuit configured to output a first reception signal corresponding to the first edge signal and a second reception signal corresponding to the second edge signal; a latch circuit configured to output an output signal on the basis of the pulse of the first received signal and the pulse of the second received signal to an output terminal; a switch circuit configured to switch a state of conduction between a reference potential and the first output and a state of conduction between the reference potential and the second output; and a control circuit configured to control a switching operation of the switch circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present embodiment relates to a digital isolator. [Background technology]

[0002] Some conventional edge transmission digital isolators use a comparator circuit to perform waveform shaping on the secondary output of the isolation element to restore a specified digital signal. However, the comparator circuit in this conventional digital isolator is a differential high-gain analog amplifier that always requires a certain amount of current consumption, and must have sufficient high-frequency characteristics to support the maximum transmission rate of the transmission signal.

[0003] Therefore, such conventional digital isolators have the problem that they cannot reduce current consumption, because they require current consumption to maintain high-frequency characteristics that can always accommodate the maximum transmission rate, even when the transmission rate of the transmission signal is slow or there is no change in the transmission signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-147538 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one embodiment is to provide a digital isolator that can reduce current consumption. [Means for solving the problem]

[0006] A digital isolator according to one embodiment is an edge transmission type digital isolator, an edge detection circuit that detects edges of pulses of a signal based on an input signal input via an input terminal, and outputs a first detection signal corresponding to an edge of a first polarity of the detected pulse and a second detection signal corresponding to an edge of a second polarity opposite to the first polarity of the detected pulse; a driving buffer circuit that outputs a first driving signal based on the first detection signal and a second driving signal based on the second detection signal; an isolation element to which the first drive signal and the second drive signal are input on a primary side, which outputs a first edge signal based on the first drive signal from a first output on a secondary side, and which outputs a second edge signal based on the second drive signal from a second output on the secondary side; a receiving inverter circuit having a first gate to which the first edge signal is input and a second gate to which the second edge signal is input, and which outputs a first receiving signal corresponding to the first edge signal and a second receiving signal corresponding to the second edge signal; a latch circuit that latches data based on the pulses of the first received signal and the pulses of the second received signal, and outputs an output signal to an output terminal in accordance with the data; a switch circuit that switches a conduction state between a reference potential and the first output of the isolation element, and switches a conduction state between the reference potential and the second output of the isolation element; and a control circuit that controls the switching operation of the switch circuit using a control signal generated based on the output signal. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram illustrating an example of the configuration of a digital isolator according to the first embodiment. [Figure 2] FIG. 2 is a waveform diagram for explaining an example of the operation of the digital isolator shown in FIG. [Figure 3] FIG. 3 is a diagram illustrating an example of the configuration of a digital isolator according to the second embodiment. [Figure 4]FIG. 4 is a waveform diagram for explaining an example of the operation of the digital isolator shown in FIG. [Figure 5] FIG. 5 is a diagram illustrating an example of the configuration of a digital isolator according to the third embodiment. [Figure 6] FIG. 6 is a diagram illustrating an example of the configuration of a digital isolator according to the fourth embodiment. [Figure 7] FIG. 7 is a waveform diagram for explaining an example of the operation of the digital isolator shown in FIG. [Figure 8] FIG. 8 is a diagram illustrating an example of the configuration of a digital isolator according to the fifth embodiment. [Figure 9] FIG. 9 is a diagram illustrating an example of the configuration of a digital isolator according to the sixth embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a digital isolator according to the seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Digital isolators according to embodiments will be described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0009] (First embodiment) [Digital isolator] Fig. 1 is a diagram illustrating an example of the configuration of a digital isolator according to a first embodiment, and Fig. 2 is a waveform diagram illustrating an example of the operation of the digital isolator illustrated in Fig. 1.

[0010] The digital isolator 100 according to the first embodiment is an edge transmission type digital isolator.

[0011] The digital isolator 100 according to the first embodiment includes, for example, an edge detection circuit 1, a driving buffer circuit 2, an isolation element 3, a receiving inverter circuit 4, a latch circuit 5, a control circuit 6, and a switch circuit 7, as shown in FIG.

[0012] As will be described later, each component of the digital isolator 100 according to the first embodiment shown in FIG. 1 is not a circuit block through which current flows constantly regardless of whether a transmission signal is present or not, and therefore current consumption can be significantly reduced when there is no signal or when the transmission rate is low.

[0013] Each component of the digital isolator 100 according to the first embodiment will be described below.

[0014] [Edge detection circuit] The edge detection circuit 1 detects the edge of a pulse of a signal based on an input signal IN input via an input terminal Tin (the input signal IN in the example of FIG. 1).

[0015] The edge detection circuit 1 outputs a first detection signal corresponding to an edge of a first polarity of the detected pulse (in the example of FIG. 2, the positive edge of the rising edge of the pulse of the signal). Furthermore, the edge detection circuit 1 outputs a second detection signal corresponding to an edge of a second polarity opposite to the first polarity of the detected pulse (in the example of FIG. 2, the negative edge of the falling edge of the pulse of the signal).

[0016] Here, as shown in FIG. 1, the edge detection circuit 1 includes, for example, a detection delay circuit 1X, a first detection inverter 1a, a second detection inverter 1b, a first detection AND circuit 1d, and a second detection AND circuit 1e.

[0017] The detection delay circuit 1X receives the input signal IN and outputs a signal obtained by delaying the input signal IN by a first delay time d1.

[0018] The first detection inverter 1a outputs a signal obtained by inverting the signal output by the detection delay circuit 1X.

[0019] The second detection inverter 1b outputs a signal obtained by inverting the input signal IN.

[0020] The first detection AND circuit 1d receives the input signal IN and the signal output from the first detection inverter 1a, and outputs a first detection signal.

[0021] The second detection AND circuit 1e receives the signal output from the detection delay circuit 1X and the signal output from the first detection inverter 1a, and outputs a second detection signal.

[0022] [Drive buffer] The driving buffer circuit 2 outputs a first driving signal PE based on the first detection signal output by the edge detection circuit 1. Furthermore, the driving buffer circuit 2 outputs a second driving signal NE based on the second detection signal output by the edge detection circuit 1.

[0023] As shown in FIG. 1, the driving buffer circuit 2 includes, for example, a first driving buffer 2a and a second driving buffer 2b.

[0024] The first driving buffer 2a receives the first detection signal output by the edge detection circuit 1 as an input, and outputs a first driving signal PE, as shown in FIG.

[0025] Also, the second driving buffer 2b receives the second detection signal output by the edge detection circuit 1 as an input, for example, as shown in FIG. 1, and outputs a second driving signal NE.

[0026] [Isolation element] 1, the isolation element 3 is configured to receive, at its primary side, the first drive signal PE and the second drive signal NE output by the drive buffer circuit 2. Furthermore, the isolation element 3 outputs a first edge signal PEO based on the first drive signal PE from a first output 31 on the secondary side, and outputs a second edge signal NEO based on the second drive signal NE from a second output 32 on the secondary side.

[0027] As shown in FIG. 1, the isolation element 3 includes, for example, a primary coil 3a and a secondary coil 3b.

[0028] The primary coil 3a has, for example, one end (connected to the output of the first driving buffer 2a) to which the first driving signal PE is input, and the other end (connected to the output of the second driving buffer 2b) to which the second driving signal NE is input, as shown in FIG.

[0029] The secondary coil 3b has, for example, as shown in FIG. 1, one end connected to a first output 31 from which the first edge signal PEO is output, and the other end connected to a second output 32 from which the second edge signal NEO is output.

[0030] The primary coil 3a and the secondary coil 3b form a transformer.

[0031] [Receiving inverter circuit] 1, the receiving inverter circuit 4 has a first gate G1 connected to the first output 31 of the isolation element 3 and receiving the first edge signal PEO, and a second gate G2 connected to the second output 32 of the isolation element 3 and receiving the second edge signal NEO. The receiving inverter circuit 4 outputs a first receiving signal PG corresponding to the first edge signal PEO and a second receiving signal NG corresponding to the second edge signal NEO.

[0032] As shown in FIG. 1, the receiving inverter circuit 4 includes, for example, a first receiving inverter 4a and a second receiving inverter 4b.

[0033] The first receiving inverter 4a receives the first edge signal PEO via a first gate G1, and outputs a first receiving signal PG, as shown in FIG.

[0034] Also, as shown in FIG. 1, the second receiving inverter 4b receives the second edge signal NEO via the second gate G2 and outputs the second receiving signal NG.

[0035] [Latch circuit] The latch circuit 5 latches data based on the pulses of the first receiving signal PG and the pulses of the second receiving signal NG output by the receiving inverter circuit 4, and outputs an output signal OUT to the output terminal Tout in accordance with the data.

[0036] As shown in FIG. 1, the latch circuit 5 includes, for example, a first output inverter 5a, a second output inverter 5b, a first NOR circuit 5c, a second NOR circuit 5d, and a third output inverter 5e.

[0037] The first output inverter 5a receives the first reception signal PG output from the first reception inverter 4a.

[0038] The second output inverter 5b receives the second reception signal NG output from the second reception inverter 4b.

[0039] In addition, the first NOR circuit 5c receives the signal output by the first output inverter 5a and the signal output by the second NOR circuit 5d, and outputs signals to the third output inverter 5e and the input section of the second NOR circuit 5d.

[0040] The second NOR circuit 5d receives the signal output by the second output inverter 5b and the signal output by the first NOR circuit 5c, and outputs a signal to the input section of the first NOR circuit 5c.

[0041] The third output inverter 5e receives the signal output by the first NOR circuit 5c and outputs an output signal OUT.

[0042] [Switch circuit] The switch circuit 7 switches the state of conduction between a reference potential and a first output 31 of the isolation element 3, and switches the state of conduction between a reference potential and the second output 32 of the isolation element 3.

[0043] The reference potential is, for example, a ground potential connected to the receiving inverter circuit 4, the latch circuit 5, and the control circuit 6 that constitute the receiving circuit.

[0044] Here, as shown in FIG. 1, the switch circuit 7 includes, for example, a first resistor 7rp, a first switch element 7swp, a second resistor 7rn, and a second switch element 7swn.

[0045] The first resistor 7rp has one end connected to the first output 31 (the first gate G1 of the receiving inverter circuit 4) of the isolation element 3, and the other end connected to the reference potential.

[0046] The first switch element 7swp has one end connected to the first output 31 (the first gate G1 of the receiving inverter circuit 4) of the isolation element 3, and the other end connected to a reference potential. The first switch element 7swp is controlled to be turned on or off by a first control signal PGS.

[0047] When the first switch element 7swp is turned on, the first output 31 of the isolation element 3 is connected to the reference potential, and the potential of the first output 31 is fixed to the reference potential. On the other hand, when the first switch element 7swp is turned off, the first output 31 of the isolation element 3 is cut off from the reference potential (insulation is achieved by the first resistor 7rp or the resistance becomes a predetermined value).

[0048] The second resistor 7rn has one end connected to the second output 32 of the isolation element 3 (the second gate G2 of the receiving inverter circuit 4) and the other end connected to the reference potential.

[0049] The second switch element 7swn has one end connected to the second output 32 (the second gate G2 of the receiving inverter circuit 4) of the isolation element 3, and the other end connected to a reference potential. The second switch element 7swn is controlled to be turned on or off by a second control signal NGS.

[0050] When the second switch element 7swn is turned on, the second output 32 of the isolation element 3 is connected to the reference potential, and the potential of the second output 32 is fixed to the reference potential. On the other hand, when the second switch element sw2 is turned off, the second output 32 of the isolation element 3 is cut off from the reference potential (insulation is achieved by the second resistor 7rn or a predetermined resistance value is achieved).

[0051] [Control circuit] The control circuit 6 controls the switching operation of the switch circuit 7 by using control signals PGS and NGS generated based on the output signal OUT. In particular, in the example shown in Fig. 1, the control circuit 6 generates the control signals PGS and NGS based on a signal obtained by delaying the output signal OUT, and controls the switching operation of the switch circuit 7.

[0052] For example, in the example shown in Figure 1, the control circuit 6 generates a first control signal PGS for switching the state of conduction between the reference potential and the first output 31 of the isolation element 3, and generates a second control signal NGS for switching the state of conduction between the reference potential and the second output 32 of the isolation element 3.

[0053] Here, the control circuit 6 includes, for example, a control delay circuit 6X and a control inverter 6a as shown in FIG.

[0054] The control delay circuit 6X receives the output signal OUT, delays the received output signal OUT by a second delay time d2, and outputs the delayed signal as the first control signal PGS.

[0055] The control inverter 6a receives the signal (first control signal PGS) output by the control delay circuit 6X, and outputs an inverted signal of this signal as the second control signal NGS.

[0056] Here, for example, when the level of the signal obtained by delaying the output signal OUT is a first level (e.g., a "HiGh" level) based on the pulse of the first received signal PG latched by the latch circuit 5, the control circuit 6 controls the switch circuit 7 (i.e., turns on the first switch element 7swp) using a control signal (first control signal PGS) so that the first output 31 is connected (fixed) to the reference potential.

[0057] Furthermore, when the level of the signal obtained by delaying the output signal OUT is the first level ("HiGh" level) based on the pulse of the first received signal PG latched by the latch circuit 5, the control circuit 6 controls the switch circuit 7 (i.e., turns off the second switch element 7swn) using a control signal (second control signal NGS) so that the second output 32 is disconnected from the reference potential (is insulated or has a predetermined resistance value).

[0058] On the other hand, when the level of the signal obtained by delaying the output signal OUT is a second level (for example, a "Low" level) different from the first level based on the pulse of the second received signal NG latched by the latch circuit 5, the control circuit 6 controls the switch circuit 7 (i.e., turns on the second switch element 7swn) using a control signal (second control signal NGS) so that the second output 32 is connected (fixed) to the reference potential.

[0059] Furthermore, when the level of the signal obtained by delaying the output signal OUT is the second level ("Low" level) based on the pulse of the second received signal NG latched by the latch circuit 5, the control circuit 6 controls the switch circuit 7 (i.e., turns off the first switch element 7swp) using a control signal (first control signal PGS) so that the first output 31 is disconnected from the reference potential (is insulated or has a predetermined resistance value).

[0060] Next, an example of the operation of the digital isolator 100 according to the first embodiment having the above configuration will be described. As already mentioned, Fig. 2 is a waveform diagram for explaining an example of the operation of the digital isolator shown in Fig. 1.

[0061] 2, when the input signal IN goes to the "HiGh" level at time t1, a pulse having a width equal to the first delay time d1 of the first drive signal PE is output (until time t2). At this time, the second drive signal NE remains unchanged.

[0062] Here, from time t1 to time t3 (during the second delay time d2), the level of the signal obtained by delaying the output signal OUT is the second level ("Low" level), and therefore the control circuit 6 turns off the first switch element 7swp using the first control signal PGS to disconnect the first output 31 from the reference potential. As a result, based on the pulse of this first drive signal PE, the isolation element 3 outputs a first edge signal PEO corresponding to this pulse from the first output 31 on the secondary side (from time t1 to time t2).

[0063] Furthermore, during the period from time t1 to time t3 (during the second delay time d2), the level of the delayed output signal OUT is the second level ("Low" level), so the control circuit 6 turns on the second switch element 7swn by the second control signal NGS so that the second output 32 is fixed to the reference potential, thereby fixing the second edge signal NEO to the reference potential.

[0064] Thereafter, from time t3 to time t4, the control circuit 6 turns on the first switch element 7swp by the first control signal PGS so that the first output 31 is fixed to the reference potential, since the level of the signal obtained by delaying the output signal OUT becomes the first level ("HiGh" level).

[0065] Furthermore, from time t3 to time t4, the level of the signal obtained by delaying the output signal OUT becomes the first level ("HiGh" level), and therefore the control circuit 6 turns off the second switch element 7swn using the second control signal NGS to disconnect the second output 32 from the reference potential.

[0066] This allows the edge signals (first edge signal PEO and second edge signal NEO) from the isolation element 3 to be fully received by the gates (first receiving inverter 4a and second receiving inverter 4b of the receiving inverter circuit 4).

[0067] After that, at time t4, when the input signal IN goes low, a pulse of the second drive signal NE having a width of the first delay time d1 is output (until time t5). At this time, the second drive signal NE does not change.

[0068] Here, from time t4 to time t6 (during the second delay time d2), the level of the signal obtained by delaying the output signal OUT is the first level ("HiGh" level), so the control circuit 6 turns off the second switch element 7swn using the second control signal NGS to disconnect the second output 32 from the reference potential. As a result, based on the pulse of the second drive signal NE, the isolation element 3 outputs a second edge signal NEO corresponding to the pulse from the second output 32 on the secondary side (from time t4 to time t5).

[0069] Furthermore, during the period from time t4 to time t6 (during the second delay time d2), the level of the delayed output signal OUT is the first level ("HiGh" level), so the control circuit 6 turns on the first switch element 7swp using the first control signal PGS so that the first output 31 is fixed to the reference potential, thereby fixing the first edge signal PEO to the reference potential.

[0070] Thereafter, the digital isolator 100 repeats the same operation in response to the input signal IN.

[0071] As mentioned above, the digital isolator 100 does not have a circuit block such as a comparator through which current always flows, and the above-mentioned operation of the digital isolator 100 allows the gate (receiving inverter circuit 4) to receive an edge signal from the isolation element 3 and transmit a specified digital signal.

[0072] Therefore, the digital isolator 100 according to the first embodiment does not require a circuit block through which current always flows, regardless of whether a transmission signal is present or not, and therefore can significantly reduce current consumption when there is no signal or when the transmission rate is low.

[0073] That is, the digital isolator 100 according to the first embodiment can reduce current consumption.

[0074] In the first embodiment, an example of the configuration of a digital isolator has been described. However, the configuration of this digital isolator is not limited to this. Therefore, in the following second to seventh embodiments, other examples of the configuration of a digital isolator will be described.

[0075] (Second embodiment) Next, a digital isolator according to a third embodiment will be described with reference to Fig. 3. Fig. 3 is a diagram showing an example of the configuration of the digital isolator according to the second embodiment. Fig. 4 is a waveform diagram for explaining an example of the operation of the digital isolator shown in Fig. 3.

[0076] In the following description, among the components shown in Fig. 3, the same components as those shown in Fig. 1 will be assigned the same reference numerals as those shown in Fig. 1, and the description thereof will be omitted. Furthermore, among the waveforms shown in Fig. 4, the same portions as those shown in Fig. 2 are the same as those in the first embodiment, and therefore the description thereof will be omitted.

[0077] In edge transmission type digital isolators, it may be preferable to periodically refresh data in order to prevent the latch of the latch circuit from becoming unstable immediately after power is turned on and to prevent data corruption when there is no change in the data for a long period of time.

[0078] Therefore, in the second embodiment, a countermeasure circuit for periodically refreshing data is added to the circuit on the transmitting side of the digital isolator.

[0079] That is, compared to the digital isolator 100 of the first embodiment, the digital isolator 200 of the second embodiment may further include an input delay circuit 10, a refresh circuit 8, and an adder circuit 9 as configurations for periodic refreshing of data.

[0080] The configuration of the digital isolator 200 according to the second embodiment will be described below, focusing on the configuration for periodic refreshing of data.

[0081] [Input delay circuit] 3, the input delay circuit 10 delays the input signal IN (by a third delay time d3) and outputs the delayed input signal IND to the edge detection circuit 1 (for example, from time t21 to time t1 and from time t25 to time t4 in FIG. 4). In this case, the edge detection circuit 1 detects edges of the delayed input signal IND (a signal based on the input signal IN) and outputs a first detection signal PEI and a second detection signal NEI corresponding to the detected edges of the pulses of the delayed input signal IND (for example, from time t1 to time t2 and from time t4 to time t5 in FIG. 4).

[0082] That is, in the digital isolator 200 according to the second embodiment, the edge detection circuit 1 detects the edge of the delayed input signal IND and outputs a first detection signal PEI and a second detection signal NEI according to the edge of the pulse of the detected delayed input signal IND.

[0083] [Refresh circuit] For example, as shown in FIG. 3, the refresh circuit 8 detects that the input signal IN does not change for a preset time St, and outputs a first refresh signal PRE and a second refresh signal NRE for refreshing data based on this detection result and the delayed input signal IND (for example, from time t1 to time t2, from time t22 to time t23, from time t24 to time t25, and from time t4 to time t5 in FIG. 4).

[0084] As shown in FIG. 3, the refresh circuit 8 includes a refresh signal generating circuit 8a and a polarity setting circuit 8b.

[0085] When the refresh signal generating circuit 8a detects that the input signal IN does not change for a preset time St, it outputs a refresh pulse signal REF (for example, from time t22 to time t23, or from time t24 to time t25 in FIG. 4).

[0086] The polarity setting circuit 8b receives the refresh pulse signal REF and the delayed input signal IND as inputs, and outputs the signals obtained by setting the polarity of the refresh pulse signal REF to switch based on the polarity of the delayed input signal IND as the first refresh signal RRE and the second refresh signal NRE.

[0087] As shown in FIG. 3, the polarity setting circuit 8b includes, for example, a first polarity setting AND circuit 8b1, a second polarity setting AND circuit 8b2, and a polarity setting inverter 8b3.

[0088] The polarity setting inverter 8b3 receives the delayed input signal IND and outputs a signal obtained by inverting the delayed input signal IND.

[0089] The first polarity setting AND circuit 8b1 receives the refresh pulse signal REF and the delayed input signal IND, and outputs a first refresh signal PRE.

[0090] The second polarity setting AND circuit 8b2 receives the refresh pulse signal REF and the signal output from the polarity setting inverter 8b3, and outputs a second refresh signal NRE.

[0091] [Adder circuit] 3, the adder circuit 9 outputs a signal obtained by adding the first refresh signal PRE to the first detection signal PEI (in other words, the first detection signal PEI to which the first refresh signal PRE has been added) to the drive buffer circuit 2 (first drive buffer 2a) (for example, from time t1 to t2, from time t22 to time t23, and from time t24 to time t25 in FIG. 4). Furthermore, the adder circuit 9 outputs a signal obtained by adding the second detection signal NEI to the second refresh signal NRE (in other words, the second detection signal NEI to which the second refresh signal NRE has been added) to the drive buffer circuit 2 (second drive buffer 2b).

[0092] As shown in FIG. 3, the adder circuit 9 includes a first adder OR circuit 9a and a second adder OR circuit 9b.

[0093] The first addition OR circuit 9a is configured to receive the first detection signal PEI and the first refresh signal PRE as input, for example, as shown in FIG. 3, and output a signal obtained by adding the first refresh signal PRE to the first detection signal PEI (in other words, the first detection signal PEI to which the first refresh signal PRE has been added).

[0094] In addition, the second adding OR circuit 9b is configured to output a signal obtained by adding the second refresh signal NRE to the second detection signal NEI (in other words, the second detection signal NEI to which the second refresh signal NRE has been added), for example, as shown in FIG. 3.

[0095] In the digital isolator 200 according to the second embodiment, the driving buffer circuit 2 (first driving buffer 2a) outputs a first driving signal PE based on a signal (first detection signal PEI to which a first refresh signal PRE has been added) output by the adding circuit 9 (first adding OR circuit 9a). Furthermore, the driving buffer circuit 2 (second driving buffer 2b) outputs a second driving signal NE based on a signal (second detection signal NEI to which a second refresh signal NRE has been added) output by the adding circuit 9 (second adding OR circuit 9b).

[0096] In this way, in the digital isolator 200 according to the second embodiment, a pulse based on the first refresh signal PRE is added to the first drive signal PE output from the transmitting side, and a pulse based on the second refresh signal NRE is added to the second drive signal NE. Therefore, the first and second edge signals PEO and NEO based on these pulses determine the latch of the latch circuit 5 immediately after the power is turned on, or data corruption can be avoided when there is no change in the data for a long period of time.

[0097] In the edge transmission type digital isolator 200 having the above configuration, the configuration for periodic data refresh (for example, the input delay circuit 10, the refresh circuit 8, and the adder circuit 9) prevents the latch of the latch circuit from becoming unstable immediately after the power is turned on, and performs periodic data refresh to avoid data corruption when there is no change in the data for a long period of time.

[0098] The rest of the configuration and operation of the digital isolator 200 of the second embodiment is similar to the configuration and operation of the digital isolator 100 of the first embodiment.

[0099] The digital isolator 200 according to the second embodiment also does not have a circuit block such as a comparator through which current always flows, and the operation of the digital isolator 200 allows the gate (receiving inverter circuit 4) to receive an edge signal from the isolation element 3 and transmit a predetermined digital signal.

[0100] Therefore, the digital isolator 200 of the second embodiment does not require a circuit block through which current flows at all times, regardless of whether a transmission signal is present or not. Therefore, although current consumption occurs due to periodic refreshing, by setting an appropriate refresh rate, current consumption when there is no signal or when the transmission rate is low can be significantly reduced.

[0101] That is, the digital isolator according to the second embodiment can reduce current consumption.

[0102] (Third embodiment) Next, a digital isolator according to a third embodiment will be described with reference to Fig. 5. Fig. 5 is a diagram showing an example of the configuration of the digital isolator according to the third embodiment.

[0103] In the following description, among the components shown in FIG. 5, the same components as those shown in FIG. 3 are denoted by the same reference numerals as those shown in FIG. 3, and description thereof will be omitted.

[0104] Here, for example, in the digital isolator 200 according to the second embodiment described above, if the driving force of the driving buffer circuit 2 (first and second driving buffers 2a, 2b) that drives the transformer of the isolation element 3 is insufficient, it may be preferable to take measures against erroneous inversion of the latch that occurs during refresh.

[0105] If the driving buffer circuit 2 (first and second driving buffers 2a and 2b) that drives the transformer of the isolation element 3 does not have sufficient driving force, the output waveform (pulses of the first and second edge signals PEO and NEO) from the secondary side of the transformer will not be an ideal rectangular shape but will be sagging (attenuated). This sagging portion of the output waveform results in the generation of outputs of opposite phase to the pulses of the first and second edge signals PEO and NEO after the pulses of the first and second edge signals PEO and NEO end. Furthermore, when transmitting pulses based on the first and second refresh signals PRE and NRE, the receiving inverter circuit 4 receives the pulses in a state where it is waiting for the opposite phase pulses, making it highly sensitive to the opposite phase pulses. Therefore, the opposite phase output component after the edge pulses end may cause erroneous latch inversion in the latch circuit 5.

[0106] Therefore, in the third embodiment, a function for suppressing erroneous inversion of the latch circuit when periodic data refresh is performed is added to the receiving-side circuit of the digital isolator.

[0107] That is, in the digital isolator 300 according to the third embodiment, in comparison with the digital isolator 200 according to the second embodiment, for example, in order to suppress erroneous inversion of the latch circuit, the control circuit 6 may be configured to control the switching operation of the switch circuit 7 based on the first received signal PG and the second received signal NG in addition to the signal obtained by delaying the output signal OUT.

[0108] The configuration of the digital isolator 300 according to the third embodiment will be described below, focusing on the configuration and operation of the control circuit 6 for suppressing erroneous inversion of the latch circuit.

[0109] Here, the control circuit 6 of the digital isolator 300 according to the third embodiment generates a first control signal PGS based on the delayed output signal OUT and the first received signal PG, and generates a second control signal NGS based on the delayed output signal OUT and the second received signal NG.

[0110] For example, as shown in FIG. 5, the control circuit 6 of the digital isolator 300 according to the third embodiment includes a control delay circuit 6X, a control inverter 6a, a first control NAND circuit 6p, and a second control NAND circuit 6n.

[0111] The control delay circuit 6X receives the output signal OUT and outputs a delay signal obtained by delaying the input output signal OUT by a second delay time d2.

[0112] The control inverter 6a receives the delayed signal output by the control delay circuit 6X and outputs a signal obtained by inverting this delayed signal.

[0113] In addition, the first control NAND circuit 6p receives the first receiving signal PG output by the first receiving inverter 4a of the receiving inverter circuit 4 and the signal output by the control inverter 6a, and outputs the first control signal PGS.

[0114] For example, when the first edge signal PEO includes a pulse based on the first refresh signal PRE, i.e., a refresh pulse, the first control NAND circuit 6p of this control circuit 6 outputs a first control signal PGS to turn on the first switch element 7swp of the switch circuit 7 (fix the potential of the first output 31 to the reference potential) based on the first receiving signal PG output by the first receiving inverter 4a.

[0115] The second control NAND circuit 6n receives the second reception signal NG output by the second reception inverter 4b and the signal output by the control delay circuit 6, and outputs a second control signal NGS.

[0116] For example, when the second edge signal NEO includes a pulse based on the second refresh signal NRE, i.e., a refresh pulse, the second control NAND circuit 6n of this control circuit 6 outputs a second control signal NGS to turn on the second switch element 7swn of the switch circuit 7 (fix the potential of the second output 32 to the reference potential) based on the second receiving signal NG output by the second receiving inverter 4b.

[0117] That is, when pulses based on the first and second refresh signals PRE and NRE, i.e., refresh pulses, are included, the control circuit 6 having the above configuration controls the switching operation of the switch circuit 7 based on the first received signal PG and the second received signal NG in addition to the signal obtained by delaying the output signal OUT.

[0118] Therefore, when pulses based on the first and second refresh signals PRE and NRE, i.e., refresh pulses, are included, the first and second switch elements 7swp and 7swn of the switch circuit 7 are turned on, thereby preventing the latch of the latch circuit 5 from being erroneously inverted due to the negative-phase output component after receiving the refresh pulse.

[0119] Other configurations and operations of the digital isolator of the third embodiment are similar to those of the digital isolator 200 of the second embodiment.

[0120] That is, the digital isolator according to the third embodiment can reduce current consumption.

[0121] (Fourth embodiment) Next, a digital isolator according to a fourth embodiment will be described with reference to Fig. 6. Fig. 6 is a diagram showing an example of the configuration of the digital isolator according to the fourth embodiment. Fig. 7 is a waveform diagram for explaining an example of the operation of the digital isolator shown in Fig. 6.

[0122] In the following description, among the components shown in Fig. 6, the same components as those shown in Fig. 1 are denoted by the same reference numerals as those shown in Fig. 1, and description thereof will be omitted. Furthermore, among the waveforms shown in Fig. 7, the same portions as those shown in Fig. 2 are the same as those in the first embodiment, and description thereof will be omitted.

[0123] As shown in FIG. 6, the control circuit 6 of the digital isolator 400 according to the fourth embodiment may include a first control delay circuit 6X1, a second control delay circuit 6X2, a control OR circuit 61a, and a control NAND circuit 61b.

[0124] The first control delay circuit 6X1 receives the output signal OUT and outputs a first delay signal obtained by delaying the input output signal OUT by a first delay time d1.

[0125] The second control delay circuit 6X2 receives the first delay signal, and outputs a second delay signal obtained by delaying the input first delay signal by a second delay time d2.

[0126] In addition, the control OR circuit 61a receives the first delay signal output by the first control delay circuit 6X1 and the second delay signal output by the second control delay circuit 6X2, and outputs the first control signal PGS based on these first and second delay signals.

[0127] The control OR circuit 61a of this control circuit 6 is configured to output a first control signal PGS based on the first and second delay signals so as to keep the first switch element 7swp of the switch circuit 7 on (fix the potential of the first output 31 to the reference potential), for example, between times t5 and t6 in FIG. 7 (i.e., the second delay time d2).

[0128] In addition, the control NAND circuit 61b receives the first delay signal output by the first control delay circuit 6X1 and the second delay signal output by the second control delay circuit 6X2, and outputs a second control signal NGS based on these first and second delay signals.

[0129] The NAND circuit 61b of this control circuit 6 is configured to output the second control signal NGS based on the first and second delay signals so as to keep the second switch element 7swn of the switch circuit 7 on (fix the potential of the second output 32 to the reference potential), for example, between times t2 and t3 in FIG. 7 (i.e., the second delay time d2).

[0130] The control circuit 6 of the digital isolator 400 according to the fourth embodiment having such a configuration keeps the switch element of the switch circuit 7 on on the negative phase side until the interval of the second delay time d2 in which the negative phase aliasing occurs (time t2 to time t3, time t5 to time t6 in FIG. 7), thereby suppressing the inversion on the negative phase side due to the negative phase aliasing that occurs during the interval of the second delay time d2.

[0131] Other configurations and operations of the digital isolator of the fourth embodiment are similar to those of the digital isolator 100 of the first embodiment.

[0132] That is, the digital isolator according to the fourth embodiment can reduce current consumption.

[0133] (Fifth embodiment) Next, a digital isolator according to a fifth embodiment will be described with reference to Fig. 8. Fig. 8 is a diagram showing an example of the configuration of the digital isolator according to the fifth embodiment.

[0134] In the following description, among the components shown in FIG. 8, the components that are the same as the components shown in FIG. 6 of the fourth embodiment will be assigned the same reference numerals as those shown in FIG. 6 of the fourth embodiment, and their description will be omitted.

[0135] As shown in FIG. 8, the control circuit 6 of the digital isolator 500 according to the fifth embodiment controls the switching operation of the switch circuit 7 based on the first received signal PG and the second received signal NG in addition to the delayed output signal OUT.

[0136] Here, as shown in FIG. 8, the control circuit 6 includes, for example, a first control delay circuit 6X1, a second control delay circuit 6X2, a third control delay circuit 6X3, a fourth control delay circuit 6X4, a first control OR circuit 61a, a control NAND circuit 61b, a first control inverter 61n, a second control inverter 61p, a second control OR circuit 61c, and a third control OR circuit 61d.

[0137] The first control delay circuit 6X1 receives the output signal OUT and outputs a first delay signal obtained by delaying the input output signal OUT by a first delay time d1.

[0138] The second control delay circuit 6X2 receives the first delay signal, and outputs a second delay signal obtained by delaying the input first delay signal by a second delay time d2.

[0139] In addition, the first control OR circuit 61a receives the first delay signal output by the first control delay circuit 6X1 and the second delay signal output by the second control delay circuit 6X2, and outputs a signal based on these first and second delay signals.

[0140] In addition, the control NAND circuit 61b receives the first delay signal output by the first control delay circuit 6X1 and the second delay signal output by the second control delay circuit 6X2, and outputs a signal based on these first and second delay signals.

[0141] In addition, the third control delay circuit 6X3 receives the first receiving signal PG output by the first receiving inverter 4a and outputs a signal that is the first receiving signal PG delayed by the first delay time d1.

[0142] In addition, the fourth control delay circuit 6X4 receives the second receiving signal NG output by the second receiving inverter 4b and outputs a signal that is the input second receiving signal NG delayed by the first delay time d1.

[0143] The first control inverter 61n receives the signal output by the third control delay circuit 6X3 and outputs an inverted version of the received signal.

[0144] The second control inverter 61p receives the signal output by the fourth control delay circuit 6X4 and outputs an inverted version of the received signal.

[0145] In addition, the second control OR circuit 61c receives the signal output by the first control OR circuit 61b and the signal output by the second control inverter 61p, and outputs the first control signal PGS based on these signals.

[0146] This second control OR circuit 61c is configured to output the first control signal PGS so as to keep the first switch element 7swp of the switch circuit 7 on (fix the potential of the first output 31 to the reference potential), for example, during the period from time t5 to t6 in FIG. 7 (i.e., the second delay time d2).

[0147] In addition, the third control OR circuit 61d receives the signal output by the control AND circuit 61a and the signal output by the first control inverter 61n, and outputs the second control signal NGS based on these signals.

[0148] This third control OR circuit 61d is configured to output the second control signal NGS so as to keep the second switch element 7swn of the switch circuit 7 on (fix the potential of the second output 32 to the reference potential), for example, during the time period from t2 to t3 in Figure 7 (i.e., the second delay time d2).

[0149] The control circuit 6 of the digital isolator 500 according to the fifth embodiment having such a configuration keeps the switch element of the switch circuit 7 on on the negative phase side until the interval of the second delay time d2 in which the negative phase aliasing occurs (time t2 to time t3, time t5 to time t6 in FIG. 7), thereby suppressing the inversion on the negative phase side due to the negative phase aliasing that occurs during the interval of the second delay time d2.

[0150] In particular, in the fifth embodiment, the output of the receiving inverter is also used to generate a control signal on the negative phase side to prevent inversion of the negative phase side due to folding back of the negative phase that occurs during the second delay time d2, thereby reducing the number of logic circuit stages between the receiving inverter and the driver of the switch circuit and reducing the influence of timing deviation due to gate delay.

[0151] Other configurations and operations of the digital isolator 500 of the fifth embodiment are similar to those of the digital isolator 400 of the fourth embodiment.

[0152] That is, the digital isolator according to the fifth embodiment can reduce current consumption.

[0153] (Sixth embodiment) Next, a digital isolator according to a sixth embodiment will be described with reference to Fig. 9. Fig. 9 is a diagram showing an example of the configuration of the digital isolator according to the sixth embodiment.

[0154] In the following description, among the components shown in FIG. 9, the components that are the same as the components shown in FIG. 6 of the fourth embodiment are assigned the same reference numerals as those shown in FIG. 6 of the fourth embodiment, and the description thereof will be omitted.

[0155] Here, the switch circuit 7 of the digital isolator 600 according to the sixth embodiment further includes a third switch element 71swp and a fourth switch element 71swn, compared to the switch circuit 7 of the digital isolator 400 according to the fourth embodiment, for example.

[0156] The third switch element 71swp has one end connected to the first output 31 (first gate G1 of the receiving inverter circuit 4) of the isolation element 3, and the other end connected to a reference potential. The third switch element 71swp is controlled to be turned on or off by a third control signal output by the control circuit 6 based on the second receiving signal NG.

[0157] The fourth switch element 71swn has one end connected to the second output 32 (the second gate G2 of the receiving inverter circuit 4) of the isolation element 3, and the other end connected to a reference potential. The fourth switch element 71swn is controlled to be turned on or off by a fourth control signal output by the control circuit 6 based on the first receiving signal PG.

[0158] Furthermore, as shown in FIG. 9, the control circuit 6 of the digital isolator 600 according to the sixth embodiment further includes, for example, a third control delay circuit 6X3, a fourth control delay circuit 6X4, a first control inverter 61n, and a second control inverter 61p, compared to the control circuit 6 of the digital isolator 400 according to the fourth embodiment.

[0159] In addition, the third control delay circuit 6X3 receives the first receiving signal PG output by the first receiving inverter 4a and outputs a signal that is the first receiving signal PG delayed by the first delay time d1.

[0160] In addition, the fourth control delay circuit 6X4 receives the second receiving signal NG output by the second receiving inverter 4b and outputs a signal that is the input second receiving signal NG delayed by the first delay time d1.

[0161] The first control inverter 61n also receives the signal output by the third control delay circuit 6X3 and outputs a fourth control signal for controlling the fourth switch element 71swn based on the signal.

[0162] This first control inverter 61n is configured to output a fourth control signal to turn on the fourth switch element 71swn of the switch circuit 7 (fix the potential of the second output 32 to the reference potential), for example, during the period from time t2 to t3 in FIG. 7 (i.e., the second delay time d2).

[0163] The second control inverter 61p receives the signal output by the fourth control delay circuit 6X4 and outputs a third control signal for controlling the third switch element 71swp based on the signal.

[0164] This second control inverter 61p is configured to output a third control signal to turn on the third switch element 71swp of the switch circuit 7 (fix the potential of the first output 31 to the reference potential), for example, during the period from time t5 to t6 in Figure 7 (i.e., the second delay time d2).

[0165] In the digital isolator 600 according to the sixth embodiment, the control circuit 6 also turns on the switch element of the switch circuit 7 on the negative phase side until the interval of the second delay time d2 in which the negative phase aliasing occurs (time t2 to time t3, time t5 to time t6 in FIG. 7), thereby suppressing the inversion on the negative phase side due to the negative phase aliasing that occurs during the interval of the second delay time d2.

[0166] The other configurations and operations of the digital isolator of the sixth embodiment are similar to those of the digital isolator 400 of the fourth embodiment.

[0167] That is, the digital isolator according to the sixth embodiment can reduce current consumption.

[0168] (Seventh embodiment) Next, a digital isolator according to a seventh embodiment will be described with reference to Fig. 10. Fig. 10 is a diagram showing an example of the configuration of the digital isolator according to the seventh embodiment.

[0169] In the following description, among the components shown in Figure 10, the components that are the same as the components shown in Figure 9 relating to the sixth embodiment will be assigned the same symbols as those shown in Figure 9, and their description will be omitted.

[0170] Here, in the digital isolator 600 according to the sixth embodiment already described, the delay circuit that delays the signal by the first delay time d1 corresponding to the explicit edge pulse may be designed to be omitted so that the delay that is originally required for the pulse width of the edge pulse is covered by the transmission delay amount of the gate.

[0171] That is, as shown in FIG. 10, the control circuit 6 of the digital isolator 700 according to the seventh embodiment may be configured such that, compared to the control circuit 6 of the digital isolator 600 according to the sixth embodiment, the first control delay circuit 6X1, the third control delay circuit 6X3, and the fourth control delay circuit 6X4 are omitted, for example.

[0172] In the digital isolator 700 according to the seventh embodiment, the control circuit 6 also turns on the switch element of the switch circuit 7 on the negative phase side until the interval of the second delay time d2 in which the negative phase aliasing occurs (time t2 to time t3, time t5 to time t6 in FIG. 7), thereby suppressing the inversion on the negative phase side due to the negative phase aliasing that occurs during the interval of the second delay time d2.

[0173] Other configurations and operations of the digital isolator of the seventh embodiment are similar to those of the digital isolator 600 of the sixth embodiment.

[0174] That is, the digital isolator according to the seventh embodiment can reduce current consumption.

[0175] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0176] 100, 200, 300, 400, 500, 600, 700 Digital Isolators 1 Edge detection circuit 2. Drive buffer circuit 3 Isolation elements 4 Receiving inverter circuit 5 Latch Circuit 6 Control Circuit 7 Switch Circuit 8 Refresh Circuit 9 Addition Circuit 10 Input delay circuit

Claims

1. An edge transmission type digital isolator, an edge detection circuit that detects edges of pulses of a signal based on an input signal input via an input terminal, and outputs a first detection signal corresponding to an edge of a first polarity of the detected pulse and a second detection signal corresponding to an edge of a second polarity opposite to the first polarity of the detected pulse; a driving buffer circuit that outputs a first driving signal based on the first detection signal and a second driving signal based on the second detection signal; an isolation element to which the first drive signal and the second drive signal are input on a primary side, and which outputs a first edge signal based on the first drive signal from a first output on a secondary side and a second edge signal based on the second drive signal from a second output on the secondary side; a receiving inverter circuit having a first gate to which the first edge signal is input and a second gate to which the second edge signal is input, and which outputs a first receiving signal corresponding to the first edge signal and a second receiving signal corresponding to the second edge signal; a latch circuit that latches data based on the pulses of the first received signal and the pulses of the second received signal, and outputs an output signal to an output terminal in accordance with the data; a switch circuit that switches a conduction state between a reference potential and the first output of the isolation element, and switches a conduction state between the reference potential and the second output of the isolation element; a control circuit that controls the switching operation of the switch circuit using a control signal generated based on the output signal.

2. The control circuit generates the control signal based on a signal obtained by delaying the output signal, and controls the switching operation of the switch circuit.

2. The digital isolator according to claim 1 .

3. The control circuit controls the switching operation of the switch circuit based on the delayed output signal as well as the first received signal and the second received signal.

3. The digital isolator according to claim 2.

4. The control circuit when the level of the signal obtained by delaying the output signal is a first level based on the pulse of the first received signal latched by the latch circuit, controlling the switch circuit by the control signal so that the first output is connected to the reference potential; When the level of the signal obtained by delaying the output signal is a second level different from the first level based on the pulse of the second received signal latched by the latch circuit, the control signal controls the switch circuit so that the second output is connected to the reference potential.

3. The digital isolator according to claim 2.

5. The control circuit when the level of the signal obtained by delaying the output signal is the first level based on the pulse of the first received signal latched by the latch circuit, controlling the switch circuit by the control signal so that the second output and the reference potential are disconnected; When the level of the signal obtained by delaying the output signal is the second level based on the pulse of the second received signal latched by the latch circuit, the control signal controls the switch circuit so that the first output and the reference potential are disconnected.

5. The digital isolator according to claim 4.

Images