RF amplifier device and method of manufacture

Abstract

To provide a structure for an integrated circuit device packaging.SOLUTION: Transistor device comprises: a transistor die having a gate terminal, a drain terminal, and a source terminal; a circuit module that is provided on the transistor die and is electrically coupled to the gate terminal, the drain terminal, and / or the source terminal; and one or more passive electric components that are provided on a first front surface of the circuit module. The one or more passive electric components are electrically coupled between the gate terminal and a first lead wire of the transistor device and / or between the drain terminal and a second lead wire of the transistor device.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to integrated circuit devices, and more particularly to structures for integrated circuit device packaging. [Background technology]

[0002] RF power amplifiers are used in a variety of applications, such as base stations for wireless communication systems, multistage and multipath amplifiers (e.g., Doherty amplifiers). Signals amplified by RF power amplifiers often include signals with modulated carriers having frequencies ranging from megahertz (MHz) to gigahertz (GHz). Electrical circuits requiring high power handling capabilities while operating at high frequencies, such as the R-band (0.5-1 GHz), S-band (3 GHz), X-band (10 GHz), Ku-band (12-18 GHz), K-band (18-27 GHz), Ka-band (27-40 GHz), and V-band (40-75 GHz), are becoming more prevalent. In particular, there is currently a high demand for radio frequency ("RF") transistor amplifiers, used to amplify RF signals at frequencies above 500 MHz (including microwave frequencies). These RF transistor amplifiers may be required to exhibit high reliability, good linearity, and handle high output power levels.

[0003] Many RF power amplifier designs utilize semiconductor switching devices as amplifying devices. Examples of these switching devices include power transistor devices such as MOSFETs (metal-oxide-semiconductor field-effect transistors), DMOS (double-diffused metal-oxide-semiconductor) transistors, HEMTs (high-electron-mobility transistors), MESFETs (metal-semiconductor field-effect transistors), and LDMOS (latently diffused metal-oxide-semiconductor) transistors.

[0004] RF amplifiers are typically formed as semiconductor integrated circuit chips. Most RF amplifiers are implemented in silicon or using wide-bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV), such as silicon carbide ("SiC") and Group III nitride materials. As used herein, the term "Group III nitride" refers to semiconductor compounds formed between nitrogen and Group III elements of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). The term also refers to ternary and quaternary compounds, such as AlGaN and AlInGaN. These compounds have an empirical formula of one mole of nitrogen combined with one mole of total Group III elements.

[0005] Silicon-based RF amplifiers are typically implemented using LDMOS transistors and can exhibit high levels of linearity with relatively inexpensive fabrication. III-nitride-based RF amplifiers are typically implemented using HEMTs, primarily in applications requiring high power and / or high frequency operation where LDMOS transistor amplifiers may have inherent performance limitations.

[0006] An RF transistor amplifier can include one or more amplification stages, each typically implemented as a transistor amplifier. To increase output power and current handling capabilities, RF transistor amplifiers are typically implemented in a "unit cell" configuration, where multiple individual "unit cell" transistors are electrically arranged in parallel. An RF transistor amplifier may be implemented as a single integrated circuit chip or "die," or may include multiple dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or parallel.

[0007] RF transistor amplifiers often include matching circuits, such as impedance matching circuits designed to improve the impedance match between the active transistor die (e.g., including MOSFETs, HEMTs, LDMOS, etc.) and the transmission lines connected thereto for RF signals at the fundamental operating frequency, and harmonic termination circuits designed to at least partially terminate harmonic products that may be generated during device operation, such as second and third harmonic products. Termination of harmonic products also affects the generation of intermodulation distortion products.

[0008] The RF amplifier transistor die and the impedance matching circuit and harmonic termination circuit may be encapsulated within a device package. A die or chip may refer to a small block of semiconductor material or other substrate on which electronic circuit elements are fabricated. Integrated circuit packaging may refer to the encapsulation of one or more dies within a support case or package that protects the die from physical damage and / or corrosion and supports electrical contacts for connection to external circuitry. The input and output impedance matching circuits within the integrated circuit device package typically include LC networks that provide at least a portion of the impedance matching circuit configured to match the impedance of the active transistor die to a fixed value. Electrical leads may extend from the package to electrically connect the RF amplifier to external circuit elements, such as input and output RF transmission lines and bias voltage sources.

[0009] Some conventional methods for assembling RF power devices may include assembling the transistor die and some of the matching network components in a ceramic or overmolded package on a CPC (copper, copper-molybdenum, copper laminate) or copper flange. The transistor die, capacitors, and input / output leads may be interconnected with wires, such as gold and / or aluminum wires. Such an assembly process may be slow and serial (e.g., one package is bonded at a time), and assembly costs may be high (e.g., due to the cost of gold wire and expensive wire bonding machines). Summary of the Invention

[0010] According to some embodiments, a radio frequency ("RF") transistor amplifier includes a semiconductor layer structure including first and second major surfaces and a plurality of unit cell transistors on the first major surface electrically connected in parallel, each unit cell transistor including a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger, wherein the semiconductor layer structure does not include vias to the source fingers on the second major surface.

[0011] In some embodiments, the RF transistor amplifier further includes a coupling element on the first major surface, the coupling element including a gate connection pad configured to be connected to the gate manifold, a drain connection pad configured to be connected to the drain manifold, and a source connection pad configured to be connected to one of the source fingers.

[0012] In some embodiments, the RF transistor amplifier further includes a carrier substrate on the second major surface of the semiconductor layer structure.

[0013] In some embodiments, the RF transistor amplifier further includes a thermally conductive layer and / or an electrically conductive layer on the second major surface of the semiconductor layer structure between the semiconductor layer structure and the carrier substrate.

[0014] In some embodiments, the RF transistor amplifier further includes a circuit module on the semiconductor layer structure, the circuit module including a gate lead connection pad electrically coupled to the gate manifold and a drain lead connection pad electrically coupled to the drain manifold.

[0015] In some embodiments, the RF transistor amplifier further includes an input lead electrically coupled to the gate lead bond pad, the input lead configured to extend externally from the package containing the RF transistor amplifier, and an output lead electrically coupled to the drain lead bond pad, the output lead configured to extend externally from the package containing the RF transistor amplifier.

[0016] In some embodiments, the RF transistor amplifier further includes one or more circuit elements mounted on the first side and / or the second side of the circuit module.

[0017] In some embodiments, the RF transistor amplifier further includes a thermally and / or electrically conductive auxiliary spacer layer on one or more circuit elements.

[0018] In some embodiments, the semiconductor layer structure further comprises a high electron mobility transistor (HEMT) or a laterally diffused metal oxide semiconductor (LDMOS) transistor.

[0019] According to some embodiments, a transistor amplifier includes a III-nitride based amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die, and a circuit module on the first surface of the amplifier die overlying and electrically coupled to the gate, drain, and source terminals of the amplifier die, the circuit module including one or more circuit elements coupled between the gate terminal and a first lead of the transistor amplifier and / or between the drain terminal and a second lead of the transistor amplifier, the circuit module having a first surface and a second surface opposite the first surface of the circuit module, the first surface of the circuit module being adjacent to the first surface of the amplifier die.

[0020] In some embodiments, one or more circuit elements are attached to the first surface and / or the second surface of the circuit module.

[0021] In some embodiments, the transistor amplifier further includes a thermally and / or electrically conductive auxiliary spacer layer on one or more circuit elements.

[0022] In some embodiments, one or more circuit elements are formed in a circuit module.

[0023] In some embodiments, the first and / or second leads are coupled to a second surface of the circuit module.

[0024] In some embodiments, the first and / or second leads are coupled to a first surface of the circuit module.

[0025] In some embodiments, the circuit module comprises a first interconnect pad and a second interconnect pad on a first surface of the circuit module, the first interconnect pad configured to be coupled to a gate terminal of the amplifier die and the second interconnect pad configured to be coupled to a drain terminal of the amplifier die.

[0026] In some embodiments, the circuit module further comprises a third interconnect pad on the first surface of the circuit module configured to be coupled to the source terminal of the amplifier die.

[0027] In some embodiments, the transistor amplifier further includes a coupling element between the amplifier die and the circuit module.

[0028] According to some embodiments, a radio frequency (“RF”) transistor amplifier includes: an RF transistor amplifier die having a first major surface and a second major surface, the RF transistor amplifier die including a gate terminal, a drain terminal, and a source terminal on the first major surface; a circuit module on the first major surface of the RF transistor amplifier die, the circuit module including a gate lead connection pad electrically coupled to the gate terminal and a drain lead connection pad electrically coupled to the drain terminal; a carrier substrate on the second major surface of the RF transistor amplifier die; and a thermally and / or electrically conductive spacer layer between the RF transistor amplifier die and the carrier substrate.

[0029] In some embodiments, the circuit module comprises a first side adjacent to the first major surface of the RF transistor amplifier die and a second side opposite the first side, and the circuit module comprises one or more circuit elements coupled to the gate terminal and / or the drain terminal.

[0030] In some embodiments, one or more circuit elements are attached to the first side and / or the second side of the circuit module.

[0031] In some embodiments, the RF transistor amplifier further includes a thermally and / or electrically conductive auxiliary spacer layer on one or more circuit elements.

[0032] In some embodiments, the spacer layer and the auxiliary spacer layer form an integral spacer layer.

[0033] In some embodiments, the RF transistor amplifier further includes an input lead and / or an output lead coupled to a second side of the circuit module.

[0034] In some embodiments, the RF transistor amplifier further includes a coupling element between the RF transistor amplifier die and the circuit module, the coupling element having a bottom surface adjacent to the first major surface of the RF transistor amplifier die and a top surface opposite the bottom surface, the top surface of the coupling element including a gate connection pad configured to be connected to a first interconnect pad of the circuit module, a drain connection pad configured to be connected to a second interconnect pad of the circuit module, and a source connection pad configured to be connected to a third interconnect pad of the circuit module.

[0035] In some embodiments, the RF transistor amplifier further includes a sidewall and a lid, the carrier substrate, the sidewall, and the lid defining an internal cavity, and the RF transistor amplifier die is within the internal cavity.

[0036] In some embodiments, the RF transistor amplifier further includes an overmolding material over the circuit module and the RF transistor amplifier die.

[0037] In some embodiments, the RF transistor amplifier die is a III-nitride based RF transistor amplifier die.

[0038] In some embodiments, the operating frequency of the RF transistor amplifier is in the R-band, S-band, X-band, Ku-band, K-band, Ka-band, and / or V-band.

[0039] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon examination of the following figures and detailed description. Any and all combinations of the above embodiments, as well as all such additional embodiments, are intended to be included within this description, be within the scope of the present invention, and be protected by the accompanying claims. [Brief explanation of the drawings]

[0040] [Figure 1A]1 is a schematic cross-sectional view of a conventional high electron mobility transistor. [Figure 1B] 1 is a schematic side view of a conventional packaged III-nitride based RF transistor amplifier. [Figure 1C] 1C is a schematic cross-sectional view taken along line 1C-1C of FIG. 1B, illustrating the top metallization structure of an RF transistor amplifier die included in the RF transistor amplifier of FIG. 1B. [Figure 1D] FIG. 1 is a schematic side view of another conventional III-nitride based RF transistor amplifier. [Figure 2A] 1 is a schematic side view of a III-nitride based RF transistor amplifier according to some embodiments of the present invention. [Figure 2B] 2B is a schematic plan view of an RF transistor amplifier die that is part of the III-nitride based RF transistor amplifier of FIG. 2A taken along line 2B-2B of FIG. 2A. [Figure 2C] FIG. 2C is a cross-sectional view taken along line 2C-2C of FIG. 2B. [Figure 2D] FIG. 2D is a cross-sectional view taken along line 2D-2D of FIG. 2B. [Figure 2E] FIG. 2E is a cross-sectional view taken along line 2E-2E of FIG. 2B. [Figure 2F] FIG. 2F is a cross-sectional view taken along line 2F-2F of FIG. 2B. [Figure 2G] FIG. 10 is a cross-sectional view of an additional embodiment of the present invention. [Figure 2H] FIG. 10 is another cross-sectional view of an additional embodiment of the present invention. [Figure 2I] FIG. 10 is yet another cross-sectional view of an additional embodiment of the present invention. [Figure 2J] FIG. 10 is yet another cross-sectional view of an additional embodiment of the present invention. [Figure 2K] FIG. 10 is yet another cross-sectional view of an additional embodiment of the present invention. [Figure 2L] FIG. 10 is yet another cross-sectional view of an additional embodiment of the present invention. [Figure 3A] 1 is a schematic cross-sectional view of an RF transistor amplifier coupled to a circuit module in accordance with some embodiments of the present invention. [Figure 3B] 1 is a schematic cross-sectional view of an RF transistor amplifier die coupled to a circuit module in accordance with some embodiments of the present invention. [Figure 3C] 1 is a schematic cross-sectional view of an RF transistor amplifier die incorporating a redistribution layer coupled to a circuit module according to some embodiments of the present invention. [Figure 3D] 1 is a schematic cross-sectional view of a circuit module coupled to multiple RF transistor amplifiers according to some embodiments of the present invention. [Figure 3E] 1 is a schematic cross-sectional view of a circuit module coupled to multiple RF transistor amplifier dies in accordance with some embodiments of the present invention. [Figure 4A] 1 is a schematic cross-sectional view of an RF transistor amplifier and circuit module coupled to a carrier substrate according to some embodiments of the present invention. [Figure 4B] 1 is a schematic cross-sectional view of an RF transistor amplifier and circuit module coupled to a carrier substrate without a coupling element, according to some embodiments of the present invention. [Figure 4C] 1 is a schematic cross-sectional view of multiple RF transistor amplifier dies coupled to a circuit module and disposed on a carrier substrate, according to some embodiments of the present invention. [Figure 5A] 1A-1C are schematic diagrams of various packaging options for RF transistor amplifiers, according to some embodiments of the present invention. [Figure 5B] 1 is another schematic diagram of various packaging options for an RF transistor amplifier, according to some embodiments of the present invention. [Figure 5C] 10A-10C are yet further schematic diagrams of various packaging options for RF transistor amplifiers, according to some embodiments of the present invention. [Figure 6A] 10A-10C are schematic cross-sectional views of additional embodiments of RF transistor amplifiers coupled to circuit modules in accordance with some embodiments of the present invention. [Figure 6B]10 is another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier coupled to a circuit module in accordance with some embodiments of the present invention. [Figure 6C] 10 is yet another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier coupled to a circuit module, in accordance with some embodiments of the present invention. [Figure 7A] 1 is a schematic diagram illustrating a method of coupling a circuit module and an RF transistor amplifier die in accordance with certain embodiments of the present invention. [Figure 7B] FIG. 10 is another schematic diagram illustrating a method of coupling a circuit module and an RF transistor amplifier die in accordance with certain embodiments of the present invention. [Figure 7C] FIG. 10 is yet another schematic diagram illustrating a method of coupling a circuit module and an RF transistor amplifier die in accordance with certain embodiments of the present invention. [Figure 7D] FIG. 10 is yet another schematic diagram illustrating a method of coupling a circuit module and an RF transistor amplifier die in accordance with certain embodiments of the present invention. [Figure 7E] FIG. 10 is yet another schematic diagram illustrating a method of coupling a circuit module and an RF transistor amplifier die in accordance with certain embodiments of the present invention. [Figure 8A] 1A-1C are schematic cross-sectional views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 8B] 1A-1C are cross-sectional schematic views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 9A] FIG. 2 is a plan view of one embodiment of a circuit module, according to some embodiments of the present invention. [Figure 9B] FIG. 9B is a cross-sectional view taken along line 9B-9B of FIG. 9A. [Figure 9C] FIG. 9C is a cross-sectional view taken along line 9C-9C of FIG. 9A. [Figure 9D] 9B is a cross-sectional view of the circuit module of FIG. 9A mounted on a substrate according to some embodiments of the present invention. [Figure 10A]1A-1C are schematic cross-sectional views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 10B] 1A-1C are cross-sectional schematic views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 11A] 1 is a schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module, according to some embodiments of the present invention. [Figure 11B] 1 is another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module, according to some embodiments of the present invention. [Figure 11C] 1 is yet another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module, according to some embodiments of the present invention. [Figure 11D] 1 is yet another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module, according to some embodiments of the present invention. [Figure 12A] 10A-10C are schematic cross-sectional views of additional embodiments of RF transistor amplifier dies coupled to circuit modules in accordance with some embodiments of the present invention. [Figure 12B] 10 is another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module in accordance with some embodiments of the present invention. [Figure 12C] 10 is yet another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module in accordance with some embodiments of the present invention. [Figure 12D] 10 is yet another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module in accordance with some embodiments of the present invention. [Figure 13A] 10A-10C are schematic cross-sectional views of additional embodiments of RF transistor amplifier dies coupled to circuit modules and incorporating spacers in accordance with some embodiments of the present invention. [Figure 13B]10 is another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module and incorporating a spacer, in accordance with some embodiments of the present invention. [Figure 13C] 10 is yet another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module and incorporating a spacer, in accordance with some embodiments of the present invention. [Figure 13D] 10 is yet another schematic cross-sectional view of an additional embodiment of an RF transistor amplifier die coupled to a circuit module and incorporating a spacer, in accordance with some embodiments of the present invention. [Figure 14A] 1A-1C are schematic cross-sectional views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 14B] 1A-1C are cross-sectional schematic views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 14C] 10A-10C are yet other schematic cross-sectional views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 14D] 10A-10C are yet other schematic cross-sectional views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 15A] 10 is a schematic cross-sectional view of an additional RF transistor amplifier embodiment including a circuit module and incorporating a mechanism for coupling to first and second circuit elements, according to some embodiments of the present invention. [Figure 15B] 10 is another schematic cross-sectional view of an additional RF transistor amplifier embodiment including a circuit module and incorporating mechanisms for coupling to first and second circuit elements, according to some embodiments of the present invention. [Figure 15C] 10 is yet another schematic cross-sectional view of an additional RF transistor amplifier embodiment including a circuit module and incorporating mechanisms for coupling to first and second circuit elements, according to some embodiments of the present invention. [Figure 15D]10 is yet another schematic cross-sectional view of an additional RF transistor amplifier embodiment including a circuit module and incorporating mechanisms for coupling to first and second circuit elements, according to some embodiments of the present invention. [Figure 16A] 1A-1C are schematic cross-sectional views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 16B] 1A-1C are cross-sectional schematic views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 16C] 10A-10C are yet other schematic cross-sectional views of various packaging options for circuit modules according to some embodiments of the present invention. [Figure 16D] 10A-10C are yet other schematic cross-sectional views of various packaging options for circuit modules according to some embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0041] In the following detailed description, numerous specific details are set forth to provide a thorough understanding of embodiments of the present disclosure. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In some instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present disclosure. It is intended that all embodiments disclosed herein can be practiced separately or combined in any manner and / or combination. Aspects described with respect to one embodiment may be incorporated into a different embodiment even if not specifically described therein. That is, all embodiments and / or features of any embodiment can be combined in any manner and / or combination.

[0042] According to embodiments of the present invention, a III-nitride-based RF transistor amplifier is provided, including an RF transistor amplifier die having gate, drain, and source terminals all located on the topside of the RF transistor amplifier die. In some embodiments, the RF transistor amplifier may not include bond wires for the gate and drain connections, thereby reducing the amount of inductance present in the circuit. Topside contacts may allow coupling elements to be directly coupled to the gate, drain, and source terminals of the RF transistor amplifier die. The coupling elements may be further connected to additional circuitry, such as harmonic termination circuits, input impedance matching circuits, and / or output impedance matching circuits, in an advantageous manner. In certain embodiments, where the substrate of the transistor die has high thermal conductivity, such as a SiC growth substrate for III-nitride-based HEMTs, the die may be mounted with the substrate on a thermally conductive carrier substrate or submount, such as a metal slug, lead frame, or flange, to improve thermal dissipation of heat generated by the die from the amplifier package.

[0043] 1A is a schematic cross-sectional view of a conventional high electron mobility transistor 10. As shown in FIG. 1A, the high electron mobility transistor 10 may be formed on a substrate 22, such as, for example, silicon carbide, silicon, or sapphire. A channel layer 24 is formed on the substrate 22. A barrier layer 26 is formed on the channel layer 24 on the opposite side of the substrate 22. The channel layer 24 may include, for example, gallium nitride (GaN), and the barrier layer 26 may include, for example, aluminum gallium nitride (AlGaN).

[0044] Together, the channel layer 24 and the barrier layer 26 may form a semiconductor structure 90 on the substrate 22. The source contact 56 and the drain contact 54 are formed on an upper surface of the barrier layer 26 and are laterally spaced apart from each other. The source contact 56 and the drain contact 54 may form ohmic contacts to the barrier layer 26.

[0045] A gate contact 52 is formed on the top surface of the barrier layer 26 between the source contact 56 and the drain contact 54. When the HEMT device 10 is biased to its conducting or "on" state, a two-dimensional electron gas (2DEG) layer is formed at the junction between the channel layer 24 and the barrier layer 26. The 2DEG layer acts as a highly conductive layer that allows current to flow between the source and drain regions of the device underlying the source and drain contacts 56 and 54, respectively.

[0046] The source contact 56 may be coupled to a reference signal, such as a ground voltage. The coupling to the reference signal may be provided by a via 66 extending from the lower surface 22A of the substrate 22 through the substrate 22 to the upper surface 26A of the barrier layer. The via 66 may expose the lower surface 56A of the source contact 56. A back metal layer 35 may be formed on the lower surface 22A of the substrate 22 and on the sidewalls of the via 66. The back metal layer 35 may be in direct contact with the source contact 56. Thus, the back metal layer 35, and the signal coupled thereto, may be electrically connected to the source contact 56.

[0047] In some embodiments, one or more insulating layers 50 may directly contact the top surface of semiconductor structure 90 (e.g., contact top surface 26A of barrier layer 26). One or more insulating layers 50 may function as a passivation layer for HEMT device 10. In some embodiments, additional metal contacts (not shown) may be provided to contact gate contact 52 and / or drain contact 54.

[0048] As described above, III-nitride-based RF amplifiers, including the HEMT device shown in FIG. 1A, are often used in high-power and / or high-frequency applications. Typically, high levels of heat are generated within the III-nitride-based RF amplifier die during operation. If the RF die becomes too hot, the performance (e.g., output power, efficiency, linearity, gain, etc.) of the RF amplifier may be degraded and / or the RF amplifier die may be damaged. Therefore, III-nitride-based RF amplifiers are typically mounted in packages that may be optimized for heat removal. FIGS. 1B and 1C illustrate a conventional packaged III-nitride-based RF amplifier. In particular, FIG. 1B is a schematic side view of a conventional packaged III-nitride-based RF amplifier 100, and FIG. 1C is a schematic cross-sectional view of an RF transistor amplifier die included in the packaged III-nitride-based RF amplifier 100, the cross-section taken along line 1C-1C in FIG. 1B. It will be understood that FIGS. 1B-1C (and various other figures) are highly simplified diagrams, and that an actual RF amplifier may include many unit cells and various circuits and elements not shown in the simplified diagrams herein.

[0049] As shown in FIG. 1B , the III-nitride-based RF amplifier 100 includes an RF amplifier die 110 mounted within a package 170. The package 170 includes a gate lead 172, a drain lead 174, a carrier substrate 176, and a housing 178. The RF transistor amplifier die 110 is mounted on the top surface of the carrier substrate 176, which may include, for example, a metal flange. The RF amplifier die 110 has a topside 112 and a bottomside 114. The RF amplifier die 110 includes a sequentially stacked bottomside (also referred to as the “backside”) metallization structure 120, a semiconductor layer structure 130, and a topside metallization structure 140. The backside metallization structure 120 includes a source terminal 126. The RF amplifier 100 may be a HEMT-based RF amplifier as shown in FIG. 1A , in which case the semiconductor layer structure 130 may include at least a channel layer and a barrier layer, typically formed on a semiconductor or insulating growth substrate (such as a SiC, silicon, or sapphire substrate). Even though the growth substrate is formed of a non-semiconductor material, it may be considered to be part of the semiconductor layer structure 130. The topside metallization structure 140 includes, among other things, a gate terminal 142 and a drain terminal 144.

[0050] An input matching circuit 190 and / or an output matching circuit 192 may also be mounted within the housing 178. The matching circuits 190, 192 may be impedance matching circuits that match the impedance of the fundamental component of the RF signal input to or output from the RF transistor amplifier 100 to the impedance at the input or output of the RF transistor amplifier die 110, respectively, and / or harmonic termination circuits configured to short-circuit harmonics of the fundamental RF signal, such as second or third harmonics, that may be present at the input or output of the RF transistor amplifier die 110. As shown schematically in FIG. 1B , the input and output matching circuits 190, 192 may be mounted to the metal flange 176. The gate lead 172 may be connected to the input matching circuit 190 by one or more first bond wires 182, and the input matching circuit 190 may be connected to the gate terminal 142 of the RF amplifier die 110 by one or more second bond wires 183. Similarly, the drain lead 174 may be connected to an output matching circuit 192 by one or more fourth bond wires 185, and the output matching circuit 192 may be connected to the drain terminal 144 of the RF amplifier die 110 by one or more third bond wires 184. The source terminal 126 of the RF transistor amplifier die 110 may be directly attached to the metal flange 176. The metal flange 176 may provide an electrical connection to the source terminal 126 and may also function as a heat dissipation structure. The first through fourth bond wires 182 through 185 may form part of the input and / or output matching circuit. The housing 178 may include a ceramic housing, and the gate lead 172 and the drain lead 174 may extend through the housing 178. The housing 178 may include multiple components, such as a frame that forms the lower sidewall and supports the gate and drain leads 172, 174, and a lid disposed on top of the frame. The interior of the device may have an air-filled cavity.

[0051] 1C is a schematic cross-sectional view of the RF amplifier die 110 through a portion of the topside metallization structure 140. The dielectric layers that insulate the various conductive elements of the topside metallization structure 140 from one another are not shown in FIG. 1C for simplicity of illustration.

[0052] As shown in FIG. 1C , the RF transistor amplifier die 110 includes a III-nitride-based HEMT RF transistor amplifier having multiple unit cell transistors 116, each including a gate finger 152, a drain finger 154, and a source finger 156. The gate fingers 152 are electrically connected to a common gate manifold 146, and the drain fingers 154 are electrically connected to a common drain manifold 148. The gate manifold 146 is electrically connected to a gate terminal 142 (e.g., via a conductive via extending upward from the gate manifold 146), which may be implemented as a gate bond pad (see FIG. 1B ), and the drain manifold 148 is electrically connected to a drain terminal 144 (e.g., via a conductive via extending upward from the drain manifold 148), which may be implemented as a drain bond pad (see FIG. 1B ). The source fingers 156 are electrically connected to the source terminal 126 through multiple conductive source vias 166 extending through the semiconductor layer structure 130. The conductive source vias 166 may include metal plated vias that extend completely through the semiconductor layer structure 130 .

[0053] 1B , the carrier substrate 176 (here a metal flange) can act as a heat sink to dissipate heat generated within the RF amplifier die 110. The heat is primarily generated at the top of the RF amplifier die 110, where, for example, a relatively high current density is generated in the channel region of the unit cell transistor 116. This heat may be transferred to the carrier substrate 176 through both the source vias 166 and the semiconductor layer structure 130.

[0054] FIG. 1D is a schematic side view of a conventional packaged III-nitride-based RF transistor amplifier 100′ similar to the RF transistor amplifier described above with reference to FIG. 1B. The RF transistor amplifier 100′ differs from the RF transistor amplifier 100 in that it includes a different package 170′. The package 170′ includes a metal submount 176 (which acts as a metal heat sink and can be implemented as a metal slug) and gate and drain leads 172′, 174′. In some embodiments, a metal lead frame can be formed, which is then processed to provide the metal submount 176 and / or the gate and drain leads 172′, 174′. The RF transistor amplifier 100′ also includes a plastic overmold 178′ that at least partially surrounds the RF transistor amplifier die 110, the leads 172′, 174′, and the metal submount 176. The plastic overmold 178′ replaces the ceramic sidewall and lid 178 included in the RF transistor amplifier 100.

[0055] Depending on the embodiment, the packaged transistor amplifier 100′ may include, for example, a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die 110, where the RF transistor amplifier die 110 incorporates multiple individual devices. In some embodiments, the packaged RF transistor amplifier 100 may include multiple RF transistor amplifier dies connected in series to form a multi-stage RF transistor amplifier, and / or multiple transistor dies arranged in multiple paths (e.g., in parallel) to form multiple RF transistor amplifier dies and an RF transistor amplifier with multiple paths, such as in a Doherty amplifier configuration.

[0056] In other cases, III-nitride-based RF amplifiers may be implemented as MMIC devices in which one or more RF amplifier dies, along with their associated impedance matching circuits and harmonic termination circuits, are implemented on a single integrated circuit die. Examples of such III-nitride-based RF amplifiers are disclosed, for example, in U.S. Pat. No. 9,947,616, the entire contents of which are incorporated herein by reference. When the RF transistor amplifier die 110 is an MMIC implementation, the input matching circuit 190 and / or the output matching circuit 192 may be omitted (as they may instead be implemented within the RF transistor amplifier die 110), and the bond wires 182 and / or 185 may extend directly from the gate and drain leads 172′, 174′ to the gate and drain terminals 142, 144.

[0057] Conventional III-nitride-based RF transistor amplifiers, such as the RF transistor amplifier 100 of FIGS. 1A-1D, can use bond wires 182, 184 to connect the RF transistor amplifier die 110 to other portions of the package. These bond wires 182, 184 have inherent inductance that can be used to implement some of the inductors in the RF transistor amplifier's impedance matching circuit and / or harmonic termination circuit. The amount of inductance provided can be varied by changing the length and / or cross-sectional area (e.g., diameter) of the bond wires 182, 184 so that the bond wires 182, 184 provide the desired amount of inductance. Unfortunately, as applications move to higher frequencies, the inductance of the bond wires 182, 184 can exceed the desired amount of inductance for the impedance matching circuit and / or harmonic termination circuit. When this happens, bond wires 182, 184 that are very short and / or have a large cross-sectional area can be used in an attempt to reduce the inductance to an appropriate level. However, very short bond wires 182, 184 can be difficult to solder in place, potentially increasing manufacturing costs and / or resulting in higher device failure rates. Bond wires 182, 184 with large cross-sectional areas can require larger gate and drain bond pads on the RF transistor amplifier die, potentially increasing the overall size of the RF transistor amplifier die, which is also undesirable. Furthermore, in some high-frequency applications, even very short bond wires 182, 184 with large cross-sectional areas can have excessive inductance, preventing the matching network from properly terminating, for example, second or third harmonics. To avoid the problem of excessive inductance in the bond wires 182, 184, RF transistor amplifiers can be implemented as MMIC devices, but MMIC RF amplifiers are more expensive to manufacture and can only be used within the frequency range of the matching circuit, reducing flexibility.

[0058] Additionally, wire bonding equipment typically used in high-volume manufacturing can have a tolerance of + / - 1 mil, meaning that the length of any particular wire bond can vary by 2 mils (i.e., + / - 1 mil at each end of the bond wire). In high-frequency applications, the inductance variation associated with a 2-mil wire bond can be significant, and therefore, matching circuit performance can be degraded if the bond wire is 1-2 mils too short or too long from the desired nominal length. By forming the gate and drain terminals on the top side of the device and using coupling elements to connect these terminals to additional circuitry, this process variation can be largely eliminated, resulting in improved performance.

[0059] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings.

[0060] 2A-2G illustrate a III-nitride-based RF transistor amplifier 200 in accordance with certain embodiments of the present invention. In particular, FIG. 2A is a schematic side view of the III-nitride-based RF transistor amplifier 200. FIG. 2B is a schematic plan view of an RF transistor amplifier die 210 that is part of the III-nitride-based RF transistor amplifier 200 of FIG. 2A, taken along line 2B-2B of FIG. 2A. FIGS. 2C-2F are schematic cross-sectional views of the RF transistor amplifier die 210, taken along lines 2C-2C to 2F-2F of FIG. 2B, respectively. FIG. 2G is an alternative embodiment of the source terminal shown in FIG. 2D. FIGS. 2H-2L are cross-sectional views of additional embodiments of III-nitride-based RF transistor amplifiers 200′, 200″, in accordance with certain embodiments of the present invention.

[0061] As shown in FIG. 2A , in some embodiments, a III-nitride-based RF transistor amplifier 200 can include an RF transistor amplifier die 210 attached to a bottom surface of a coupling element 270. The RF transistor amplifier die 210 has a topside 212 and a backside 214. The RF transistor amplifier die 210 includes a topside metallization structure 220, a semiconductor layer structure 230, and a bottomside thermal layer 240, which are sequentially stacked. The topside metallization structure 220 includes a gate terminal 222, a drain terminal 224, and one or more source terminals 226. The RF transistor amplifier 200 can be a HEMT-based RF transistor amplifier, in which case the semiconductor layer structure 230 can include at least a channel layer and a barrier layer, as described in more detail with reference to FIGS. 2C and 2D . In some configurations, the coupling element 270 can be omitted from the RF transistor amplifier 200, as described further herein.

[0062] The coupling element 270 may be configured to couple to the gate terminal 222, the drain terminal 224, and one or more source terminals 226. In some cases, the coupling element 270 may include a redistribution layer (RDL) stack structure and / or an interposer. The RDL stack structure refers to a substrate having a conductive layer pattern and / or conductive vias. The RDL stack structure can be fabricated using semiconductor processing techniques by depositing conductive and insulating layers and / or patterns on a substrate and by forming vias and routing patterns (e.g., from copper) within the structure for transmitting signals through the RDL stack structure. For example, as shown in FIG. 2A, the coupling element 270 may include a conductive pattern 273 formed within an encapsulation structure 277.

[0063] The upper surface of the coupling element 270 is provided with a gate connection pad 272, a drain connection pad 274, and a source connection pad 276. Each of these connection pads 272, 274, and 276 may comprise, for example, an exposed copper pad, although the invention is not limited thereto. The gate connection pad 272 may be electrically coupled to the gate terminal 222 by one or more conductive patterns 273 within the coupling element 270. Similarly, the drain connection pad 274 may be electrically coupled to the drain terminal 224 by one or more conductive patterns 273 within the coupling element 270, and the source connection pad 276 may be electrically coupled to the source terminal 226 by one or more conductive patterns 273 within the coupling element 270.

[0064] In some embodiments, the conductive pattern 273 of the coupling element 270 may be configured in a fan-out (FO) configuration. The FO configuration may allow for increased spacing between connections to the respective source, gate, and drain terminals, allowing for increased separation of the connections. However, the present invention is not limited to FO connections. In some embodiments, fan-in connections, fan-in and fan-out configurations, or other configurations may be used.

[0065] In some embodiments, the coupling element 270 and / or the RDL stack structure may be formed as part of a wafer-level processing (WLP) operation, although the invention is not limited thereto. For example, the coupling element 270 may be formed by disposing conductive pillars on the gate terminal 222, the drain terminal 224, and one or more source terminals 226. In some embodiments, the conductive pillars may comprise copper. For example, the conductive pillars may be formed by electroplating a copper seed using one or more masks to form a pattern. The conductive pillars may form a conductive pattern 273. Also, the gate connection pad 272, the drain connection pad 274, and the source connection pad 276 may be formed on the conductive pattern 273. The conductive pattern 273, the gate connection pad 272, the drain connection pad 274, and the source connection pad 276 may be at least partially disposed within an encapsulation structure 277, which may include an overmold material. Examples of overmold materials include silicon oxide, silicon nitride, an oxide of the conductive pattern 273, a polymer, a molding compound, and / or combinations thereof. The overmold material may be processed (e.g., planarized) to expose the gate connection pad 272, the drain connection pad 274, and / or the source connection pad 276. In some embodiments, the formation of the coupling element 270 may be performed at the wafer level, and the RF transistor amplifier die 210 and / or individual RF transistor amplifier dies 200 may be isolated from the wafer.

[0066] In some embodiments, the bonding element 270 may be formed in a chip-first or chip-last process. In a chip-first process, the RDL structure may be formed on the die 210 (or a wafer including the die 210). For example, a seed layer may be deposited (e.g., on one or more of the gate terminal 222, the drain terminal 224, and the one or more source terminals 226). The seed may then be patterned and electroplated to form a layer of conductive material. This process may be repeated multiple times from the conductive patterns 273 of the bonding element 270. These conductive patterns 273 may then be encapsulated within an encapsulation structure 277 to form the bonding element 270.

[0067] In a chip-last process, the RDL layer of the bonding element 270 can be formed on a temporary carrier layer. The conductive pattern 273 may be formed on the temporary carrier layer similarly to a chip-first process. When completed, the bonding element 270 may be separated from the temporary carrier layer and then rebonded to the die 210. For example, the bonding element 270 may be bonded (e.g., via solder) to one or more of the gate terminal 222, the drain terminal 224, and one or more source terminals 226.

[0068] Other coupling elements 270 may alternatively be used, such as, for example, a printed circuit board (e.g., a multilayer printed circuit board), a ceramic substrate including conductive vias and / or pads, or any coupling structure for the RF transistor amplifier die 210 that can make an electrical connection to the top surface 212 of the RF transistor amplifier die 210.

[0069] The arrangement of conductive pattern 273 shown in Figure 2A is merely an example, and other arrangements are possible without departing from this invention. For example, in some embodiments, conductive pattern 273 of coupling element 270 may extend adjacent to a side surface of RF transistor amplifier die 210. In some embodiments, coupling element 270 may have terminals other than those shown in Figure 2A.

[0070] The thermal layer 240 may be on the backside 214 of the RF transistor amplifier die 210. The thermal layer 240 may be a thermally conductive layer configured to facilitate heat transfer between the RF transistor amplifier die 210 and a carrier substrate to which the RF transistor amplifier die 210 is attached. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, the thermal layer 240 may be a die-attach layer, such as a eutectic layer. The thermal layer 240 may be on the transistor amplifier die 210 and / or may extend over the encapsulation structure 277. The thermal layer 240 may be a metal layer for forming a eutectic bond or other metallurgical bond. In some embodiments, the thermal layer 240 may be a thermal adhesive.

[0071] The RF transistor amplifier die 210 may comprise a III-nitride based HEMT RF transistor amplifier including a plurality of unit cell transistors 216 electrically connected in parallel with one another. This can be best seen in FIG. 2B, which schematically illustrates a top view of the RF transistor amplifier die 210 beneath a topside metallization structure 220. The topside metallization structure 220, including a gate terminal 222, a drain terminal 224, and one or more source terminals 226, is shown in dashed lines in FIG. 2B.

[0072] 2B , RF transistor amplifier die 210 may include gate manifold 242, drain manifold 244, multiple gate fingers 252, multiple drain fingers 254, and multiple source fingers 246, all of which may be formed on the top surface of semiconductor layer structure 230. Gate manifold 242 and gate fingers 252 are part of the gate electrode of RF transistor amplifier die 210. Gate manifold 242 and gate fingers 252 may be implemented as a first monolithic metal pattern, although the invention is not limited thereto. Drain manifold 244 and drain fingers 254 are part of the drain electrode of RF transistor amplifier die 210 and may be implemented as a second monolithic metal pattern, although the invention is not limited thereto.

[0073] The gate fingers 252 may be formed of a material capable of forming a Schottky contact with a III-nitride-based semiconductor material, such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN. The drain fingers 254 and source fingers 246 may include a metal (e.g., TiAlN, TiSiNi, etc.) capable of forming an ohmic contact with a III-nitride-based material. A dielectric layer (or series of dielectric layers) that helps isolate the gate manifolds / fingers 242, 252, the drain manifolds / fingers 244, 254, and the source fingers 246 from one another is not shown in FIG. 2B to better illustrate the elements of the RF transistor amplifier die 210.

[0074] The gate terminal 222, the drain terminal 224, and the source terminal 226 may be provided on the top surface of the RF transistor amplifier die 210. The gate terminal 222 may be physically and electrically connected to the gate manifold 242 (e.g., by a conductive via), the source terminal 226 may be physically and electrically connected to the source fingers 246 (e.g., by a conductive via), and the drain terminal 224 may be physically and electrically connected to the drain manifold 244 (e.g., by a conductive via). While the various terminals are shown as being directly connected to the gate / drain manifolds and / or source fingers, it will be understood that in some embodiments, intermediate elements may be present. For example, in some embodiments, capacitors, inductors, resistors, etc. may be coupled between the terminals and the respective manifolds and / or fingers. As an example, a capacitor may be formed on the surface of the RF transistor amplifier die 210 coupled to the drain manifold 244, and the drain terminal 224 may be coupled to the capacitor.

[0075] 2B also shows one of the unit cell transistors 216. As shown, the unit cell transistor 216, along with an underlying portion of the semiconductor layer structure 230, includes a gate finger 252, a drain finger 254, and a source finger 246. It can be seen that the unit cell transistors 216 are all electrically connected in parallel, with all of the gate fingers 252 electrically connected to a common gate manifold 242, all of the drain fingers 254 electrically connected to a common drain manifold 244, and all of the source fingers 246 electrically connected to each other via source terminals 226 (described below).

[0076] The unit cell transistor 216 may be a HEMT device. Suitable structures for Group III nitride-based HEMT devices that can utilize embodiments of the present invention are described, for example, in commonly assigned U.S. Patent Application Publication No. 2002 / 0066908A1, published June 6, 2002, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having a Gate Contact on a Gallium Nitride-Based Cap Segment and Methods of Fabricating the Same," U.S. Patent Application Publication No. 2002 / 0167023A1, published November 14, 2002, entitled "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer," and U.S. Patent Application Publication No. 2004 / 0061129, published April 1, 2004, entitled "Nitride-Based Transistors and Methods of Fabrication Thereof Using Non-Etched Contacts." No. 7,906,799, issued on March 15, 2011, entitled "Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess," and U.S. Pat. No. 6,316,793, issued on November 13, 2001, entitled "Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates," the disclosures of which are incorporated herein by reference in their entireties.

[0077] 2C and 2D, semiconductor layer structure 230 includes multiple semiconductor layers. In the illustrated embodiment, a total of two semiconductor layers are shown: a channel layer 234 and a barrier layer 236 on the upper surface of channel layer 234. Semiconductor layer structure 230 can include additional semiconductor and / or non-semiconductor layers. For example, semiconductor layer structure 230 can include a growth substrate 232 on which other semiconductor layers are grown. Growth substrate 232 can be a semi-insulating silicon carbide (SiC) substrate, which can be, for example, a 4H polytype of silicon carbide. Other candidate silicon carbide polytypes include 3C, 6H, and 15R polytypes. Growth substrate 232 can also be a high-purity semi-insulating (HPSI) substrate available from Cree, Inc. The term "semi-insulating" is used herein descriptively and not in an absolute sense.

[0078] In some embodiments of the present invention, the silicon carbide bulk crystal of growth substrate 232 has a crystallinity of about 1×10 at room temperature. 5 The SiC substrate may have a resistivity of ohm-cm or greater. Exemplary SiC substrates that may be used in some embodiments of the present invention are manufactured, for example, by Cree, Inc. of Durham, NC, the assignee of the present invention, and methods for manufacturing such substrates are described, for example, in U.S. Reissue Patent No. 34,861, U.S. Pat. No. 4,946,547, U.S. Pat. No. 5,200,022, and U.S. Pat. No. 6,218,680, the disclosures of which are incorporated herein by reference in their entireties. While silicon carbide may be used as the substrate material, embodiments of the present application may utilize any suitable substrate, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The growth substrate 232 may be a silicon carbide wafer, and the RF transistor amplifier 200 may be formed, at least in part, by wafer-level processing, after which the wafer may be diced to provide a plurality of individual RF transistor amplifiers 200.

[0079] SiC has a much closer crystal lattice match to III-nitrides than sapphire (Al2O3) or silicon, which are very common substrate materials for III-nitride devices. SiC's closer lattice match can result in higher quality III-nitride films than those commonly available on sapphire or silicon. SiC also has very high thermal conductivity, so the total output power of III-nitride devices on silicon carbide is not typically limited by the heat dissipation of the substrate, as is the case for the same devices formed on sapphire. The availability of semi-insulating SiC substrates can also provide device isolation and reduced parasitic capacitance.

[0080] Optional buffer, nucleation, and / or transition layers (not shown) may be provided on the growth substrate 232 below the channel layer 234. For example, an AlN buffer layer may be included to provide a suitable crystal structure transition between the SiC growth substrate 232 and the remainder of the semiconductor layer structure 230. Additionally, a strain balancing transition layer may be provided, as described, for example, in commonly assigned U.S. Patent Application Publication No. 2003 / 0102482 A1, published June 5, 2003, entitled "Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors," the disclosure of which is incorporated herein by reference as if fully set forth herein.

[0081] In some embodiments, the channel layer 234 and the barrier layer 236 may each be formed by epitaxial growth. Techniques for epitaxial growth of Group III nitrides are described, for example, in U.S. Pat. Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are also incorporated herein by reference in their entireties. The channel layer 234 may have a bandgap smaller than that of the barrier layer 236, and the channel layer 234 may also have a greater electron affinity than the barrier layer 236. The channel layer 234 and the barrier layer 236 may include a Group III nitride-based material.

[0082] In some embodiments, the channel layer 234 comprises Al, provided that the energy of the conduction band edge of the channel layer 234 is less than the energy of the conduction band edge of the barrier layer 236 at the interface between the channel layer 234 and the barrier layer 236. x Ga 1-x In one embodiment, the channel layer 234 is a III-nitride material such as GaN, where 0≦x<1. In a particular embodiment of the present invention, x=0, indicating that the channel layer 234 is gallium nitride ("GaN"). The channel layer 234 may also be other III-nitrides such as InGaN, AlInGaN, etc. The channel layer 234 may be undoped or unintentionally doped, and may be grown to a thickness of greater than about 2 nm, for example. The channel layer 234 may also be a multi-layer structure, such as a superlattice or a combination of GaN, AlGaN, etc.

[0083] Channel layer 234 may have a bandgap smaller than the bandgap of at least a portion of barrier layer 236, and channel layer 234 may also have a greater electron affinity than barrier layer 236. In certain embodiments, barrier layer 236 is AlN, AlInN, AlGaN, or AlInGaN having a thickness of about 0.1 nm to about 10 nm or more. In certain embodiments, barrier layer 236 is sufficiently thick and has a sufficiently high Al composition and doping to induce a significant carrier concentration at the interface between channel layer 234 and barrier layer 236.

[0084] The barrier layer 236 may be a group III nitride and may have a bandgap larger than that of the channel layer 234 and an electron affinity smaller than that of the channel layer 234. Thus, in certain embodiments of the present invention, the barrier layer 236 can include AlGaN, AlInGaN, and / or AlN, or combinations of those layers. The barrier layer 236 may have a thickness, for example, of from about 0.1 nm to about 30 nm. In certain embodiments, the barrier layer 236 is either undoped or doped with an n-type dopant to a concentration of less than about 10 19 cm -3 -. In some embodiments of the present invention, the barrier layer 236 is Al x Ga 1-x N, where 0 < x < 1. In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 236 includes AlGaN having an aluminum concentration of from about 5% to about 100%. In certain embodiments of the present invention, the aluminum concentration exceeds about 10%.

[0085] Due to the difference in bandgap between the barrier layer 236 and the channel layer 234 and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234, a two-dimensional electron gas (2DEG) is induced in the channel layer 234 at the junction between the channel layer 234 and the barrier layer 236. The 2DEG acts as a highly conductive layer that enables conduction between the source region and its associated drain region of each unit cell transistor 216. The source region is the portion of the semiconductor layer structure 230 directly under the source finger 246, and the drain region is the portion of the semiconductor layer structure 230 directly under the corresponding drain finger 254.

[0086] Although semiconductor structure 230 is shown with channel layer 234 and barrier layer 236 for illustrative purposes, semiconductor structure 230 may include additional layers / structures / elements, such as a buffer and / or nucleation layer between channel layer 234 and substrate 232, and / or a cap layer on barrier layer 236. HEMT structures including substrates, channel layers, barrier layers, and other layers are described, by way of example, in U.S. Pat. Nos. 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, 7,548,112, and 7,709,269, the disclosures of which are incorporated herein by reference in their entireties. For example, an AlN buffer layer can be formed on the top surface of the silicon carbide substrate 232 to provide a suitable crystal structure transition between the silicon carbide substrate 232 and the remainder of the RF transistor amplifier 200. Additionally, a strained balanced transition layer can also and / or alternatively be provided, for example, as described in commonly assigned U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference as if fully set forth herein. The optional buffer / nucleation / transition layer may be deposited by MOCVD, MBE, and / or HVPE.

[0087] An interlayer insulating layer 238 is formed above the gate fingers 252, the drain fingers 254, and the source fingers 246. The interlayer insulating layer 238 may include a dielectric material such as SiN, SiO2, or the like.

[0088] The coupling element 270 may be on and / or coupled to the semiconductor layer structure 230. For example, the conductive pattern 273 may be coupled between the gate connection pad 272 and the gate terminal 222, between the drain connection pad 274 and the drain terminal 224, and between the source connection pad 276 and the source terminal 226, respectively. In FIG. 2C , the encapsulation structure 277 of the coupling element 270 is omitted for ease of illustration. The gate connection pad 272, the drain connection pad 274, and the source connection pad 276 of the coupling element 270 may extend perpendicular to the gate finger 252 and the drain finger 254.

[0089] By locating all terminals on the topside of the RF transistor amplifier die 210, RF transistor amplifier 200 according to certain embodiments of the present invention can omit vias to the backside of the RF transistor amplifier die 210. Without vias on the backside of the RF transistor amplifier die 210 connecting the source to a grounded conductive submount, the conductive submount does not need to be electrically active. Furthermore, the backside of the substrate 232 of the RF transistor amplifier die 210 may be thermally coupled to a thermally conductive submount, such as a heat sink or flange (not shown), to improve heat dissipation. In some embodiments, a thermal layer 240 can facilitate this thermal coupling. When SiC is used as the substrate material, the thermal properties of the package can be further improved due to the improved thermal conductivity of SiC.

[0090] Furthermore, locating all terminals on the top side of RF transistor amplifier die 210 enables the use of coupling elements 270 that can bring all of the transistor connections to their respective connection pads, which allows RF transistor amplifier die 210 to be further coupled to other elements of the circuit (e.g., other routing elements, grounding elements, harmonic and / or input / output impedance matching elements) using connection methods that avoid bond wires, such as solder.

[0091] FIG. 2D shows an example of connections between various source fingers 246 and source terminals 226. As shown in FIG. 2D, each of the source fingers 246 may be coupled to a respective source terminal 226, although the invention is not limited thereto. In some embodiments, one or more source terminals 226 may be coupled to two or more source fingers 246. For example, as shown in FIG. 2G, in some embodiments, a single source terminal 226 may be provided, and the source terminal 226 may be connected to each individual source finger 246. In some embodiments, multiple source terminals 226 may be provided, each connected to multiple source fingers 246. One or more source terminals 226 may be coupled to a source connection pad 276 by a conductive pattern 273 of a coupling element 270.

[0092] 2E shows an example of a connection between the gate manifold 242 and the gate terminal 222. As shown in FIG. 2E, the gate manifold 242 may be coupled to the gate terminal 222 by, for example, multiple vias. FIG. 2F shows an example of a connection between the drain manifold 244 and the drain terminal 224. As shown in FIG. 2E, the drain manifold 244 may be coupled to the drain terminal 224 by, for example, multiple vias. In both FIG. 2E and FIG. 2F, the gate terminal 222 and / or the drain terminal 224 may be coupled to the gate connection pad 272 and / or the drain connection pad 274 of the coupling element 270, respectively, by one or more conductive patterns 273.

[0093] 2C, 2E, and 2F illustrate embodiments in which the gate manifold 242 and the gate terminal 222 are separate elements, and the drain-gate manifold 244 and the drain terminal 224 are separate elements (e.g., connected by vias), although the invention is not limited thereto. For example, FIGS. 2H-2J illustrate examples in which the gate / drain manifold and terminal are a single element. For example, with reference to FIGS. 2H and 2I, device 200′ may be configured such that gate manifold 242 extends to the surface of RF transistor amplifier die 210 to function as gate terminal 222. Similarly, FIGS. 2H and 2J illustrate that device 200′ can be configured such that drain manifold 244 extends to the surface of RF transistor amplifier die 210 to function as drain terminal 224.

[0094] In some embodiments, additional conductive elements and / or separate circuit components may be formed as part of the RF transistor amplifier die. FIG. 2K illustrates an additional embodiment of an RF transistor amplifier die 210′ ​​in accordance with some embodiments of the present invention. FIG. 2K illustrates an embodiment shown from the perspective of line 2C-2C of FIG. 2A , modified as described herein. For example, as shown in FIG. 2K , the RF transistor amplifier die 210′ ​​may utilize several conductive patterns 223 between the gate manifold 242 and the gate terminal 222, between the drain-gate manifold 244 and the drain terminal 222, and / or between one or more of the source fingers 246 and the source terminal 246. The conductive patterns 223 may be formed within the interlayer insulating layer 238 of the RF transistor amplifier die 210′.

[0095] The conductive pattern 223 may be utilized to form individual circuit elements integrated into the RF transistor amplifier die 210′. For example, the conductive pattern 223 may form an RDL within the RF transistor amplifier die 210′. FIG. 2K illustrates a fan-in configuration that couples the gate / drain manifolds 242, 244 and source fingers 246 to the gate, drain, and source terminals 222, 224, 226, respectively. However, the invention is not limited thereto. In some embodiments, the conductive pattern 223 may also be coupled to individual circuit elements within the interlayer dielectric layer 238, such as in an MMIC configuration. The use of an on-die RDL can enable more flexible packaging options and the integration of specific circuit functions, such as impedance matching and / or harmonic termination.

[0096] FIG. 2L shows that RF transistor amplifier die 210′ ​​may be used with a coupling element 270 in RF transistor amplifier 200″. The embodiment of FIG. 2L may include a first RDL as part of RF transistor amplifier die 210′ ​​and a second RDL as part of coupling element 270. In some embodiments, conductive pattern 223 of RF transistor amplifier die 210′ ​​may provide one or more additional integrated circuits, such as impedance matching or harmonic termination, and conductive pattern 273 of coupling element 270 may provide fan-in, fan-out, or other configurations. In some embodiments, the combination of coupling element 270 and RF transistor amplifier die 210′ ​​may be encapsulated within an encapsulating structure (not shown).

[0097] 2A-2L illustrate semiconductor layer structure 230 including a HEMT, it will be understood that other types of semiconductor devices can be formed within semiconductor layer structure 230 without departing from the present invention. For example, semiconductor layer structure 230 can include MOSFETs, DMOS transistors, MESFETs, and / or LDMOS transistors. Those skilled in the art will recognize that locating all source / drain / gate contacts on one side of semiconductor layer structure 230, including the use of coupling elements 270, can improve connectivity and improve thermal performance.

[0098] By locating the gate, drain, and source contacts on the same side of RF transistor amplifier 200, connection options that were not previously possible can be utilized. These connection options can also enable embodiments that can better utilize the improved thermal conductivity of SiC material.

[0099] 3A is a schematic cross-sectional view of RF transistor amplifier 200 coupled to circuit module 310, in accordance with some embodiments of the present invention. FIG. 3A includes elements of RF transistor amplifier 200 previously described. Therefore, the description of FIG. 3A will focus on portions of the embodiment that differ from those described with respect to previous figures.

[0100] 3A , the circuit module 310 may be configured to couple to the gate connection pad 272, the drain connection pad 274, and the source connection pad 276 of the coupling element 270. For example, the circuit module 310 may expose interconnect pads 322, 324, 326, which may be configured to be coupled to the gate connection pad 272, the drain connection pad 274, and the source connection pad 276. For example, the first interconnect pad 322 may be configured to couple to the gate connection pad 272, the second interconnect pad 324 may be configured to couple to the drain connection pad 274, and the third interconnect pad 326 may be configured to couple to the source connection pad 276. In some embodiments, the first, second, and third interconnect pads 322, 324, 326 may be coupled to the gate connection pad 272, the drain connection pad 274, and the source connection pad 276, respectively, using bonding elements (e.g., solder balls and / or bumps 320). Although shown as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads 322, 324, 326 may include multiple pads.

[0101] Each of the first, second, and third interconnect pads 322, 324, 326 may be coupled to one or more conductive patterns 373 within the circuit module 310. The conductive patterns 373 may provide various routing and / or circuitry within the circuit module 310. For example, the conductive patterns 373 may connect the first interconnect pad 322 to one or more first surface connection pads 372 and one or more gate lead connection pads 382. Thus, the gate connection pad 272 may be electrically coupled to one or more first surface connection pads 372 and one or more gate lead connection pads 382. The conductive patterns 373 may also connect the second interconnect pad 324 to one or more second surface connection pads 374 and one or more drain lead connection pads 384. Thus, the drain connection pad 274 may be electrically coupled to one or more second surface connection pads 374 and one or more drain lead connection pads 384. The conductive pattern 373 may also connect the third interconnect pad 326 to one or more third surface connection pads 376 and one or more source lead connection pads 386. Thus, the source connection pad 276 may be electrically coupled to one or more third surface connection pads 376 and one or more source lead connection pads 386. Thus, the circuit module 310 may have a surface (e.g., a top surface) having a plurality of first surface connection pads 372, each coupled to a gate connection pad 272 of the coupling element 270, a plurality of second surface connection pads 374, each coupled to a drain connection pad 274 of the coupling element 270, and a plurality of third surface connection pads 376, each coupled to a source connection pad 276 of the coupling element 270.

[0102] The conductive patterns 373 may be contained within an isolation material 315. In some embodiments, the isolation material 315 may include, for example, silicon oxide, silicon nitride, an oxide of the conductive patterns 273, a polymer, a molding compound, or a combination thereof. In some embodiments, the circuit module 310 may be formed as a printed circuit board (PCB). In a PCB embodiment, the isolation material 315 may be a substrate of the PCB, and the conductive patterns 373 may be traces formed within the substrate.

[0103] The presence of the conductive pattern 373 and the first, second, and third surface connection pads 372, 374, 376 may allow several different circuits to be coupled to the RF transistor amplifier 200. For example, the circuit element 350 may be coupled (e.g., via solder or other bonds) between two or more of the first, second, and third surface connection pads 372, 374, 376. The circuit element 350 may provide various electronic functions for the RF transistor amplifier 200. For example, the circuit element 350 may comprise impedances (e.g., including resistive, inductive, and capacitive elements) that may be used for impedance matching and / or harmonic termination. In some embodiments, the circuit element 350 may provide stripline components and / or baseband termination for the RF transistor amplifier 200.

[0104] Although shown as being on the surface of the circuit module 310, it will be understood that additional circuit elements 350 may be provided internally within the circuit module 310. For example, one or more ground planes may be formed as circuit elements 350 within the circuit module 310. Similarly, striplines may be formed within the circuit module 310 (e.g., in conjunction with one or more ground planes). The configuration of the conductive pattern 373 and circuit elements 350 shown in FIG. 3A is merely exemplary and is not intended to limit embodiments of the present invention. In some embodiments, the circuit elements 350 and / or the conductive pattern 373 may be configured to provide at least a portion of a harmonic termination circuit, a matching circuit, a splitting circuit, a combining circuit, and / or a bias circuit. Other configurations of the conductive pattern 373 and / or other types of circuit elements 350 may be used without departing from the scope of the present invention.

[0105] In some embodiments, the circuit module 310 and the circuit element 350 may optionally be housed within an encapsulation material 316. In some embodiments, the encapsulation material 316 may include, for example, silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof.

[0106] The gate lead connection pad 382, ​​the drain lead connection pad 384, and the source lead connection pad 386 can provide terminals for connecting signals to the respective gate, drain, and source of the RF transistor amplifier 200. For example, a connection for providing an input signal to the RF transistor amplifier 200 may be coupled to one or more of the gate lead connection pads 382. In some embodiments, a connection for receiving an output signal from the RF transistor amplifier 200 may be coupled to the drain lead connection pad 384. In some embodiments, a ground signal may be coupled to the source lead connection pad 386, although the invention is not limited in this respect. While the gate lead connection pad 382, ​​the drain lead connection pad 384, and the source lead connection pad 386 are shown as being on the bottom surface of the circuit module 310, this is merely an example and is not intended to limit the invention. In some embodiments, the various lead connections may be on the top surface or other surfaces of the circuit module 310.

[0107] By using the circuit module 310 in conjunction with the topside contacts of the RF transistor amplifier 200, additional functionality, such as impedance matching and / or harmonic termination, can be conveniently added to the RF transistor amplifier 200 without using extensive wirebonding. Thus, different functions and / or capabilities can be coupled to the RF transistor amplifier 200 simply by using different circuit modules 310. Because the connection points (e.g., terminals) of the RF transistor amplifier 200 are consistent, variations in the configuration of the RF transistor amplifier 200 can be achieved more efficiently than previously available. The reduction or elimination of the need for wirebonds can also enable a reduction in die size in some applications (where the size of the wirebond pads determines the die size), and thus, RF transistor amplifier dies according to embodiments of the present invention can also exhibit increased integration density. Thus, RF amplifier dies according to embodiments of the present invention can exhibit improved product assembly consistency, higher yields, increased product integration, reduced cost, and improved RF performance, particularly for products operating at high frequencies, such as millimeter-wave frequencies.

[0108] The techniques disclosed herein may be particularly beneficial in high-frequency applications because the inductance required for the matching circuit may be much lower in such applications, and therefore the use of conventional bond wires may introduce excessive inductance. Furthermore, bond wire length tolerances may have a greater impact at higher frequencies, and in high-frequency applications (especially at lower power), the size of the bond pads may dictate the size of the die. In some embodiments, any of the RF transistor amplifier dies disclosed herein may be configured to operate at frequencies greater than 1 GHz. In other embodiments, these RF transistor amplifier dies may be configured to operate at frequencies greater than 2.5 GHz. In yet other embodiments, these RF transistor amplifier dies may be configured to operate at frequencies greater than 3.1 GHz. In yet additional embodiments, these RF transistor amplifier dies may be configured to operate at frequencies greater than 5 GHz. In some embodiments, these RF transistor amplifier dies may be configured to operate in at least one of the 2.5-2.7 GHz, 3.4-4.2 GHz, or 5.1-5.8 GHz frequency bands or subportions thereof.

[0109] 3B is a schematic cross-sectional view of RF transistor amplifier die 210 coupled to circuit module 310, in accordance with some embodiments of the present invention. FIG. 3B includes the previously described circuit module 310, circuit element 350, and elements of RF transistor amplifier die 210. Thus, the description of FIG. 3B focuses on portions of the embodiment that differ from those described with respect to previous figures.

[0110] 3B shows an embodiment in which the circuit module 310 is directly connected to the RF transistor amplifier die 210 without an intervening coupling element 270. Thus, the circuit module 310 may be configured to couple to one or more of the gate terminal 222, the drain terminal 224, and the source terminal 226 of the RF transistor amplifier die 210. For example, the first interconnect pad 322 of the circuit module 310 may be configured to couple to the gate terminal 222, the second interconnect pad 324 of the circuit module 310 may be configured to couple to the drain terminal 224, and the third interconnect pad 326 of the circuit module 310 may be configured to couple to one or more of the source terminals 226. In some embodiments, bonding elements (e.g., solder balls and / or bumps) 320 may be used to couple the first, second, and third interconnect pads 322, 324, 326 to one or more of the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. Although shown as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads 322, 324, 326 may include multiple pads. The configuration shown in FIG. 3B may be useful when a fan-in or fan-out configuration of coupling elements 270 is not required to provide a connection between the RF transistor amplifier die 210 and the circuit module 310.

[0111] FIG. 3C illustrates an embodiment in which a circuit module 310 is directly connected to an RF transistor amplifier die 210′ ​​incorporating an on-die RDL utilizing conductive patterns 223 without an intervening coupling element 270. Accordingly, the circuit module 310 may be configured to couple to one or more of the gate terminal 222, the drain terminal 224, and the source terminal 226 of the RF transistor amplifier die 210′. The RF transistor amplifier die 210′ ​​in FIG. 3C is shown in cross section to illustrate an example of an internal conductive pattern (e.g., of an RDL) coupled to one or more of the gate terminal 222, the drain terminal 224, and the source terminal 226. In some embodiments, the RF transistor amplifier die 210′ ​​may be an MMIC. While shown without coupling elements 270, it will be understood that in some embodiments, coupling elements 270 may also be present between the RF transistor amplifier die 210′ ​​and the circuit module 310.

[0112] The use of coupling element 270 utilizing conductive pattern 273 (if present), on-die RDL utilizing conductive pattern 223 (if present), and circuit module 310 utilizing conductive pattern 373 can provide an interconnect structure between the gate, drain, and source of RF transistor amplifier die 210 and gate lead bond pad 382, ​​drain lead bond pad 384, and source lead bond pad 386. By utilizing various combinations of these elements and electrical bonding techniques, a semiconductor package can be provided that eliminates and / or reduces wire bonding.

[0113] Figure 3D is a schematic cross-sectional view of a circuit module 310' coupled to multiple RF transistor amplifier dies 210, in accordance with some embodiments of the present invention. Figure 3E is a schematic cross-sectional view of a circuit module 310' coupled to multiple RF transistor amplifier dies 210, in accordance with some embodiments of the present invention. Figures 3E and 3E include elements of the circuit module 310', circuit elements 350, RF transistor amplifier dies 210, and RF transistor amplifier 200 described above. Therefore, the description of Figures 3D and 3E will focus on portions of the embodiment that differ from those described with respect to the previous figures.

[0114] Referring to FIG. 3D , the circuit module 310′ may be configured to couple to two or more RF transistor amplifiers 200. FIG. 3D also illustrates that the conductive patterns 373, interconnect pads, and surface connection pads may be modified without departing from the scope of the present invention. For example, the circuit module 310′ may include multiple interconnect pads 327. The interconnect pads 327 may be configured to couple to terminals of the multiple RF transistor amplifiers 200. For example, the interconnect pads 327 of the circuit module 310′ may be configured to couple to one or more gate connection pads 272, drain connection pads 274, and / or source connection pads 276 of the multiple RF transistor amplifiers 200.

[0115] Similarly, circuit module 310′ may have surface connection pads 377 coupled to one or more of interconnect pads 327 via conductive pattern 373. Circuit elements 350 may be coupled to one or more of surface connection pads 377. By using conductive pattern 373, interconnect pads 327, surface connection pads 377, and / or circuit elements 350, various circuit connections between multiple RF transistor amplifiers 200 can be realized. It will be understood that the configuration shown in FIG. 3D is merely a schematic example, and that the routing and connections of various elements of circuit module 310′ can be variously altered to generate complex circuits including RF transistor amplifiers 200.

[0116] In some embodiments, the circuit module 310′ can include one or more gate lead connection pads 382, ​​one or more drain lead connection pads 384, and one or more source lead connection pads 386. Signals provided to the one or more gate lead connection pads 382, ​​one or more drain lead connection pads 384, and one or more source lead connection pads 386 may be distributed through the circuit module 310′ to various ones of the RF transistor amplifier 200 via the conductive patterns 373.

[0117] 3D illustrates an embodiment in which each of the multiple RF transistor amplifier dies 200 has its own coupling element 270, it will be appreciated that other configurations are possible. For example, in some embodiments, a single coupling element 270 may be coupled to multiple RF transistor amplifier dies 210. The use of a single coupling element 270 may enable the use of circuit modules 310′ with fewer interconnections to the transistor elements of the circuit.

[0118] FIG. 3D illustrates an embodiment in which a circuit module 310′ is coupled to a plurality of RF transistor amplifier dies 200, including a coupling element 270. However, the present invention is not limited thereto. In some embodiments, a circuit module 310′ may be directly coupled to a plurality of RF transistor amplifier dies 210, 210′ ​​without including a coupling element 270. FIG. 3E illustrates an embodiment in which a circuit module 310′ is coupled to a plurality of RF transistor amplifier dies 210. It will be appreciated that a circuit module 310′ may also be coupled to a plurality of RF transistor amplifier dies 210′ ​​(e.g., as shown in FIG. 2K) without departing from the present invention. The circuit module 310′ may be coupled to the RF transistor amplifier dies 210, 210′, for example, by bonding elements (e.g., solder balls and / or bumps) 320. It will be appreciated that a circuit module 310 may be coupled to a combination of RF transistor amplifier dies 200, including a coupling element 270 and an RF transistor amplifier dies 210, 210′.

[0119] The circuit module 310′ can be used to provide interconnections to the RF transistor amplifiers 200, which can be used to implement multi-stage and / or multi-path amplifier circuits, such as, for example, Doherty amplifiers. The conductive pattern 373 can provide the electrical connections of the multi-stage and / or multi-path amplifier circuits and can be coupled to one of the circuit elements 350 to provide capacitors, inductors, resistors, and / or other circuit elements used in the multi-stage and / or multi-path amplifier circuits. Thus, the circuit module 310′ can be configured to provide modular interconnections that can be easily coupled to multiple RF transistor amplifiers without the use of bond wires.

[0120] 3A-3E illustrate various combinations of circuit modules 310, 310′, coupling elements 270, and RF transistor amplifier dies 210, 210′, it will be understood that the present invention is not limited to the specific combinations shown in those figures. As will be understood by those skilled in the art, circuit modules 310, 310′, coupling elements 270, and RF transistor amplifier dies 210, 210′ ​​may be combined in multiple variations, including those not specifically shown, without departing from the present invention. For example, embodiments of the present invention include transistor amplifier dies 210, 210′ ​​directly coupled to circuit modules 310, 310′. Some embodiments of the present invention include transistor amplifier dies 210, 210′ ​​coupled to circuit modules 310, 310′ via coupling elements 270. The coupling elements 270 and / or circuit modules 310, 310′ may include traces on a PCB or metal-core PCB and patterned dielectric material. In some embodiments, the transistor amplifier die 210′ ​​can have conductive patterns such as RDLs at the die level, which can include fan-in and / or fan-out configurations that can be connected to other structures such as the coupling elements 270 or circuit modules 310, 310′.

[0121] Figure 4A is a schematic cross-sectional view of RF transistor amplifier 200 and circuit module 310 coupled to carrier substrate 410, in accordance with some embodiments of the present invention. Figure 4B is a schematic cross-sectional view of RF transistor amplifier 200 coupled to carrier substrate 410 without coupling element 270, in accordance with some embodiments of the present invention. Figures 4A and 4B include elements of RF transistor amplifier 200, coupling element 270, and circuit module 310 as previously described. Therefore, the description of Figures 4A and 4B will focus on portions of the embodiment that differ from those described with respect to the previous figures.

[0122] Referring to FIG. 4A , the RF transistor amplifier 200 may be disposed on a carrier substrate 410. The carrier substrate 410 may include any structure that provides a suitable mounting surface for the RF transistor amplifier 200. In some embodiments, the carrier substrate 410 may include a temperature-conductive element, such as a metal flange. In some embodiments, the carrier substrate 410 may include, for example, an RDL stackup structure or a PCB. In some embodiments, the carrier substrate 410 may include copper, molybdenum, and / or a combination thereof. In some embodiments, the carrier substrate 410 may be constructed of multiple layers and / or may include vias / interconnects. The carrier substrate 410 may be configured to facilitate packaging of the RF transistor amplifier 200. As shown in FIG. 4A , a circuit module 310 may be coupled to the RF transistor amplifier 200 as described herein.

[0123] In some embodiments, the thermal layer 240 may be disposed between the bottom surface of the RF transistor amplifier 200 and the carrier substrate 410. The thermal layer 240 may assist in the transfer of thermal energy from the RF transistor amplifier 200 to the carrier substrate 410. In embodiments in which SiC is utilized as part of the RF transistor amplifier 200, the superior thermal conductivity of SiC may enable the carrier substrate 410 to more efficiently dissipate heat from the device. In some embodiments, the thermal layer 240 may include or be replaced by a eutectic layer.

[0124] One or more leads 415 may be coupled to one or more gate lead connection pads 382, ​​one or more drain lead connection pads 384, and one or more source lead connection pads 386 of the circuit module 310. For example, a first input lead 415A may be coupled to one or more gate lead connection pads 382 (e.g., via a bonding layer 420A, such as solder) to provide an input signal to the RF transistor amplifier 200, and a second output lead 415B may be coupled to one or more drain lead connection pads 384 (e.g., via a bonding layer 420B, such as solder) to receive an output signal from the RF transistor amplifier 200, although the invention is not limited thereto.

[0125] The lead connections in FIG. 4A are merely examples, and other connections and / or connection pads are possible. For example, in FIG. 4A , one or more source lead connection pads 386 are shown as connected to both leads 415A and 415B. However, in some embodiments, one or more source lead connection pads 386 may not be coupled to the source of RF transistor amplifier 200 (e.g., via one or more source terminals 226). For example, in some embodiments, one or more of circuit elements 350 and / or conductive patterns 373 may be configured to control whether one or more source lead connection pads 386 are coupled to input lead 415A, output lead 415B, or neither. For example, circuit element 350 may be provided on circuit module 310 to connect source terminal 226 of RF transistor amplifier 200 to lead 415. Similarly, the circuit module 310 may be configured to allow a circuit element 350 (e.g., a resistor) to be removed to sever the coupling between the lead 415A or 415B and the source terminal 226 of the RF transistor amplifier 200.

[0126] 4A illustrates an embodiment with two leads 415A and 415B, this is merely an example and is not intended to limit the present invention. In some embodiments, multiple leads may be provided, each coupled to the gate lead connection pad 382, ​​the drain lead connection pad 384, the source lead connection pad 386, and / or combinations thereof. For example, in some embodiments, an additional lead configured to provide a ground connection to the source lead connection pad 386 may be provided. In some embodiments, the source lead connection pad 386 may be configured to couple to a lead of an RF semiconductor package, which may be coupled to ground, for example. As used herein, the combination of the RF transistor amplifier 200, the circuit module 310, the leads 415A, 415B, and the carrier substrate 410 may be referred to as a packaged RF transistor amplifier, an RF transistor amplifier package, or simply an RF transistor amplifier.

[0127] The leads 415A, 415B may be between the circuit module 310 and the carrier substrate 410, although the invention is not limited thereto. In some embodiments, the carrier substrate 410 may be below the leads 415A and 415B and, in some embodiments, have a pedestal 410p that supports the leads 415A and 415B, although the invention is not limited thereto. In some embodiments, the pedestal 410p may include an insulating material and / or may be separated from the leads 415A, 415B by an insulating layer 460. In some embodiments, the leads 415A, 415B may be supported by a portion of the package of the RF transistor amplifier 200, as described further herein.

[0128] While FIG. 4A illustrates the use of a coupling element 270, the present invention is not limited thereto. FIG. 4B illustrates an embodiment in which the coupling element is omitted. In the embodiment of FIG. 4B, the circuit module 310 can have first, second, and third interconnect pads 322, 324, 326 spaced apart from one another by a distance similar to that of the gate terminal 222, the drain terminal 224, and one or more source terminals 226. For example, the first interconnect pad 322 may be connected to the gate terminal 222 (e.g., via a bonding element such as a solder ball and / or bump 320), the second interconnect pad 324 may be connected to the drain terminal 224, and the third interconnect pad 326 may be connected to the source terminal 226. Direct connection to the circuit module 310 may be useful when adjustment of the spacing of the terminals of the RF transistor amplifier 200 (e.g., via a fan-in or fan-out structure) is not required. Thus, in some embodiments, the coupling element 270 is optional in the RF transistor amplifier 200.

[0129] FIG. 4C illustrates an embodiment in which multiple RF transistor amplifier dies 200 are coupled to a circuit module 310′ and disposed on a carrier substrate 410. For example, multiple RF transistor amplifier dies 210, 210′ ​​can be coupled to the circuit module 310′ as described herein with respect to FIGS. 3D and 3E. The multiple RF transistor amplifier dies 210, 210′ ​​may be coupled to the circuit module 310′ via coupling elements 270 or may be directly coupled to the circuit module 310′ (as shown in FIG. 3E). The RF transistor amplifier dies 210, 210′ ​​and / or the circuit module 310′ may further be disposed on a carrier substrate 410 to which leads 415A and 415B are coupled. In some embodiments, a thermal layer 240 may be disposed between the RF transistor amplifier dies 210, 210′ ​​and the carrier substrate 410.

[0130] 4A-4C illustrate various combinations of circuit modules 310, 310′, coupling elements 270, and RF transistor amplifier dies 210, 210′, it will be understood that the present invention is not limited to the specific combinations shown in those figures. As will be understood by those skilled in the art, circuit modules 310, 310′, coupling elements 270, and RF transistor amplifier dies 210, 210′ ​​may be combined in multiple variations, including those not specifically shown, without departing from the present invention. Each of these combinations may be disposed on a carrier substrate 410 with appropriate leads (e.g., leads 415A, 415B) connected thereto, as generally shown in FIGS. 4A-4C.

[0131] 5A-5C are schematic cross-sectional views of various packaging options 500a, 500b, 500c for RF transistor amplifier 200, according to some embodiments of the present invention. Figures 5A-5C include elements of RF transistor amplifier 200, coupling element 270, and circuit module 310, as previously described. Accordingly, the description of Figures 5A-5C focuses on portions of the embodiment that differ from those described with respect to the previous figures.

[0132] Referring to FIG. 5A , a semiconductor package 500a may incorporate the RF transistor amplifier 200 according to some embodiments of the present invention. The semiconductor package 500a may be, for example, an open-air or open-cavity package. The semiconductor package 500a may include a carrier substrate 410, sidewalls 520, and a lid 525. The carrier substrate 410, sidewalls 520, and lid 525 may define an internal cavity 530. The RF transistor amplifier 200 and the circuit module 310 may be disposed within the internal cavity 530. The term “semiconductor package” is not intended to be limiting. As mentioned above, the combination of the RF transistor amplifier 200, the circuit module 310, the leads 415A, 415B, and the carrier substrate 410 may be referred to as a packaged RF transistor amplifier, a semiconductor package, or simply an RF transistor amplifier.

[0133] The carrier substrate 410 may include a material configured to assist in thermal management of the semiconductor package 500a. For example, the carrier substrate 410 may include copper and / or molybdenum. In some embodiments, the carrier substrate 410 may be constructed from multiple layers and / or may include vias / interconnects. In an exemplary embodiment, the carrier substrate 410 may be a multi-layer copper / molybdenum / copper metal flange including a core molybdenum layer with copper cladding layers on either major surface. The provided examples of materials for the carrier substrate 410 are not intended to limit the present invention. In some embodiments, the thermal layer 240 may be between the RF transistor amplifier 200 and the carrier substrate 410.

[0134] In some embodiments, the sidewalls 520 and / or the lid 525 may be formed of or include an insulating material. For example, the sidewalls 520 and / or the lid 525 may be formed of or include a ceramic and / or a PCB. In some embodiments, the sidewalls 520 and / or the lid 525 may be formed of, for example, Al2O3. The lid 525 may be adhered to the sidewalls 520 using an epoxy adhesive. The sidewalls 520 may be attached to the carrier substrate 410 by, for example, brazing. The leads 415A, 415B may be configured to extend through the sidewalls 520, although the invention is not limited thereto.

[0135] In some embodiments, the RF transistor amplifier 200 may be disposed on a carrier substrate 410 and leads 415A, 415B, and the circuit module 310 may be disposed on the RF transistor amplifier 200. The leads 415A, 415B may be coupled to the circuit module 310 using, for example, a conductive die attach material. In some embodiments, the leads 415A, 415B may extend from the sidewall 520 to contact the circuit module 310. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier 200 to the leads 415A, 415B can be avoided and / or reduced.

[0136] Additional circuit elements 350 are attached to the circuit module 310. These additional components may include, for example, input and output matching components used for impedance matching at the fundamental frequency and / or terminating intermodulation products to ground. These circuit elements 350 may be passive RF components including, for example, integrated passive devices or resistors, capacitors, and / or inductors implemented (at least partially) on a printed circuit board. Leads 415A, 415B allow the RF transistor amplifier 200 to be connected to external devices / circuits / power sources. In the illustrated embodiment, the circuit module 310 is used to connect the conductive leads 415A, 415B to the circuit elements 350 on the circuit module 310. An RF signal input to the RF transistor amplifier 200 on first lead 415A may be passed through the circuit module 310 to the circuit element 350 and from there to the gate terminal 222 of the RF transistor amplifier die 210, and the amplified output RF signal may be passed from the drain terminal 224 of the RF transistor amplifier die 210 to the circuit element 350 and from there through the circuit module 310, and the RF signal is output on lead 415B.

[0137] 5B, a semiconductor package 500b may incorporate the RF transistor amplifier 200 according to an embodiment of the present invention. The semiconductor package 500b may be, for example, an overmolded plastic (OMP) package. The semiconductor package 500b may include a carrier substrate 410 on which the RF transistor amplifier 200 is disposed. A circuit module 310 may be disposed on the RF transistor amplifier 200.

[0138] The RF transistor amplifier 200 and the circuit module 310 may be housed within an overmold material 540. The overmold material 540 may be formed from a plastic or plastic polymer compound and is injection molded around the RF transistor amplifier 200 and / or the circuit module 310, thereby providing protection from the external environment.

[0139] A method for manufacturing an OMP semiconductor package 500b that can be modified to incorporate an RF transistor amplifier 200 and / or a circuit module 310 is described in U.S. Patent No. 9,515,011, entitled "Over-mold plastic packaged wide band-gap power transistors and MMICS," by Wood et al., issued December 6, 2016, the disclosure of which is incorporated herein by reference as if fully set forth herein. In a semiconductor package 500b according to the present invention, leads 415A, 415B may extend from outside the semiconductor package 500b into the overmold material 540 to connect to the circuit module 310. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier 200 to leads 415A, 415B can be avoided and / or reduced.

[0140] Similar to the semiconductor package 500a, the carrier substrate 410 of the semiconductor package 500b can include a material configured to assist in thermal management. For example, the carrier substrate 410 can include copper and / or molybdenum. In some embodiments, the carrier substrate 410 can be constructed from multiple layers and / or can include vias / interconnects. In some embodiments, the carrier substrate 410 can include a metal heat sink that is part of a lead frame or metal slug at least partially surrounded by a plastic overmold 540. The provided examples of materials for the carrier substrate 410 are not intended to limit the present invention. In some embodiments, a thermal layer 240 can be between the RF transistor amplifier 200 and the carrier substrate 410.

[0141] FIG. 5C is a schematic cross-sectional view of a packaged RF transistor amplifier 500c including an RF transistor amplifier die in a printed circuit board-based package. The packaged RF transistor amplifier 500c is very similar to the packaged RF transistor amplifier 500a described above with reference to FIG. 5A, except that the leads 415A, 415B of the packaged RF transistor amplifier 500c are replaced with a printed circuit board 522 including traces 415A, 415B that serve as input and output leads. The printed circuit board 522 may be attached to a carrier substrate 410, for example, via a conductive adhesive. The carrier substrate 410 may include, for example, a pedestal 410P. The pedestal 410P may be constructed of an insulating material and / or metal. The printed circuit board 652 may include a central opening, and the circuit module 310 is mounted within this opening on the carrier substrate (e.g., a metal flange) 410. The RF transistor amplifier 200 and circuit elements 350 are mounted on the circuit module 310.

[0142] 5A-5C illustrate the use of an RF transistor amplifier 200 having a coupling element 270, the invention is not limited thereto. In some embodiments, the semiconductor packages 500a, 500b, 500c may be configured to include a circuit module 310 coupled directly to the RF transistor amplifier die 210, as shown in FIGS. 3B, 3C, and 4B. In some embodiments, the semiconductor packages 500a, 500b, and 500c may be configured to include a circuit module 310 coupled to multiple RF transistor amplifiers 200, 200′ and / or multiple RF transistor amplifier dies 210, 210, as shown in FIGS. 3D, 3E, and 4C.

[0143] It will be understood that any of the RF transistor amplifiers according to the embodiments of the invention described herein may be mounted in a package, such as the packages shown in FIGS. 5A-5C. Accordingly, the RF transistor amplifier die 210, the coupling element 270, and / or the circuit module 310 shown in FIGS. 5A-5C can be replaced with the RF transistor amplifier die 210, 210′, the coupling element 270, and / or the circuit module 310, 310′ according to any of the embodiments of the invention described herein to provide many additional embodiments of packaged RF transistor amplifiers. Depending on the embodiment, the packaged RF transistor amplifier may include a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die, where the RF transistor amplifier die incorporates multiple individual circuits within a single integrated die. Additionally and / or alternatively, the package may include multiple RF transistor amplifier dies in a path connected in series to form a multi-stage RF transistor amplifier, and / or multiple RF transistor amplifier dies arranged in multiple paths (e.g., in parallel) to form an RF transistor amplifier with multiple transistor amplifier dies and multiple paths, such as in a Doherty amplifier configuration. In some embodiments, a packaged RF transistor amplifier may include an RF transistor amplifier die according to an embodiment of the present invention having conductive gate and / or conductive drain vias that provide electrical connection to a backside interconnect structure, as well as a conventional RF transistor amplifier die having gate and drain terminals that are connected to other structures via wire bonds.

[0144] In some embodiments described herein, circuit element 350 may be disposed on the top surface of circuit module 310, although embodiments described herein are not limited thereto. Figures 6A-6C are schematic cross-sectional views of additional embodiments of RF transistor amplifier 200 coupled to circuit module 310, according to some embodiments of the present invention. Figures 6A-6C correspond to the cross-section of Figure 3A. Figures 6A-6C include elements of RF transistor amplifier 200 previously described. Therefore, the description of Figures 6A-6C focuses on portions of the embodiment that differ from those described with respect to the previous figures.

[0145] 6A, the circuit module 610 may be configured to couple to the gate connection pad 272, the drain connection pad 274, and the source connection pad 276 of the coupling element 270. The coupling element 270 may be coupled to the RF transistor amplifier die 210, for example, as described herein with respect to FIGS.

[0146] For example, the circuit module 610 can have exposed interconnect pads 622, 624, 626 that can be configured to be coupled to the gate connection pad 272, the drain connection pad 274, and the source connection pad 276, respectively. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first, second, and third interconnect pads 622, 624, 626 to the gate connection pad 272, the drain connection pad 274, and the source connection pad 276, respectively. Although shown as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads 622, 624, 626 may include multiple pads.

[0147] The circuit module 610 may be coupled to the coupling element 270 at a first side 601 of the circuit module 610. A plurality of pads may be exposed at a second side 602 of the circuit module 610 opposite the first side 601. For example, a gate lead 682, a drain lead 684, and a source lead 686 may be exposed at the second side 602 of the circuit module 610. While only a single gate lead 682, drain lead 684, and source lead 686 is shown in FIG. 6A , it will be understood that multiple leads of each type may be provided. As described further herein, the gate lead 682, drain lead 684, and source lead 686 may be configured to be coupled to the gate terminal 222, drain terminal 224, and source terminal 226, respectively, of the RF transistor amplifier die 210. An encapsulant material 625 may be on the surface of the RF transistor amplifier die 210, the coupling element 270, and / or the circuit module 610. The encapsulating material 625 may be formed from a plastic or plastic polymer compound, although the invention is not limited thereto. In some embodiments, the encapsulating material 625 may be or include a polymer with a filler.

[0148] Each of the first, second, and third interconnect pads 622, 624, 626 may be coupled to one or more conductive patterns 673 within the circuit module 610. The conductive patterns 673 may provide various routing and / or circuitry within the circuit module 610. For example, the conductive patterns 673 may connect the first interconnect pad 622 to one or more first surface connection pads 672 and a gate lead 682. In some embodiments, the first surface connection pads 672 may be exposed at the first side 601 of the circuit module 610. In some embodiments, the first circuit element 650a may be coupled to one or more of the first surface connection pads 672 so as to be electrically coupled between the gate lead 682 and the first interconnect pad 622. In some embodiments, the first circuit element 650a may be coupled between the gate lead 682 and the gate terminal 222 of the RF transistor amplifier die 210 (e.g., via the coupling element 270). Thus, the first circuit element 650a may be electrically coupled between the gate of the RF transistor amplifier die 210 and the gate lead 682. In some embodiments, the first circuit element 650a may be coupled to the first side 601 of the circuit module 610. Thus, the first circuit element 650a may be coupled to the same side (e.g., first side 601) of the circuit module 610 as the coupling element 270.

[0149] Similarly, the conductive pattern 673 may connect the second interconnect pad 624 to one or more second surface connection pads 674 and the drain lead 684. In some embodiments, the second circuit element 650b may be coupled to one or more of the second surface connection pads 674 such that the second circuit element 650b is electrically coupled between the drain lead 684 and the second interconnect pad 624. In some embodiments, the second surface connection pad 674 may be exposed at the first side 601 of the circuit module 610. In some embodiments, the second circuit element 650b may be coupled between the drain lead 684 and the drain terminal 224 of the RF transistor amplifier die 210 (e.g., via the coupling element 270). Thus, the second circuit element 650b may be electrically coupled between the drain of the RF transistor amplifier die 210 and the drain lead 684.

[0150] The first circuit element 650a and / or the second circuit element 650b can provide various electronic functions for the RF transistor amplifier 200. For example, the first circuit element 650a and / or the second circuit element 650b can comprise impedances (e.g., including resistive, inductive, and capacitive elements) that can be used for impedance matching and / or harmonic termination. In some embodiments, the first circuit element 650a and / or the second circuit element 650b can be or include a surface-mount device. In some embodiments, the first circuit element 650a and / or the second circuit element 650b can be or include an integrated passive device (IPD). In some embodiments, the first circuit element 650a and / or the second circuit element 650b can be or include a harmonic and / or input / output impedance matching element.

[0151] For example, the first circuit element 650a may be configured to provide input matching capability. Due to its location between the gate lead 682 and the RF transistor amplifier die 210, the first circuit element 650a can affect and / or adjust the signal provided to the gate of the RF transistor amplifier die 210. Similarly, the second circuit element 650b may be configured to provide output matching capability. Due to its location between the drain lead 684 and the RF transistor amplifier die 210, the second circuit element 650b can affect and / or adjust the signal provided from the drain of the RF transistor amplifier die 210.

[0152] By using a circuit module 610 having exposed connection pads, such as first and second surface connection pads 672, 674, surface mount devices can be used to provide circuit elements that can be coupled to the RF transistor amplifier die 210. The surface mount devices can be substituted and / or configured as needed to provide more flexible solutions. For example, when different types of input / output matching and / or harmonic termination are required, the same circuit module 610 may be used, but the first and / or second circuit elements 650a, 650b may be swapped to provide different capabilities.

[0153] Although the first circuit element 650 a and the second circuit element 650 b are each shown as a single element, it will be understood that in some embodiments, the first circuit element 650 a and / or the second circuit element 650 b may include multiple individual devices. Similarly, the interconnections between the first and second circuit elements 650 a, 650 b and the RF transistor amplifier die 210 are merely examples, and different configurations of the conductive pattern 673 may be provided without departing from the invention.

[0154] The conductive pattern 673 may also connect the third interconnect pad 626 to one or more source leads 686. Thus, the source connection pad 276 may be electrically coupled to one or more source leads 686.

[0155] The conductive patterns 673 may be contained within an isolation material 615. In some embodiments, the isolation material 615 may include, for example, silicon oxide, silicon nitride, an oxide of the conductive patterns 673, a polymer, a molding compound, or a combination thereof. In some embodiments, the circuit module 610 may be formed as a printed circuit board (PCB). In a PCB embodiment, the isolation material 615 may be a substrate of the PCB, and the conductive patterns 673 may be traces formed within the substrate.

[0156] While Figure 6A illustrates the use of circuit module 610 to couple to RF transistor amplifier die 210 using coupling elements 270, the invention is not limited in this respect. As shown in Figure 6B, in some embodiments, RF transistor amplifier die 210 may be directly coupled to circuit module 610. For example, gate terminal 222, drain terminal 224, and source terminal 226 of RF transistor amplifier die 210 may be coupled to interconnect pads 622, 624, 626, respectively, of circuit module 610 using, for example, bonding elements 320.

[0157] Similarly, it will be understood that other configurations of the circuit module 610 and the RF transistor amplifier die 210 are possible, such as those shown in Figures 3C-3E. In some embodiments, the circuit module 610 may be configured to couple to an RF transistor amplifier die 210' that incorporates an internal conductive pattern, such as that shown in Figure 3C. In some embodiments, the circuit module 610 may be configured to couple to multiple RF transistor amplifier dies 210, such as those shown in Figures 3D and 3E.

[0158] It will also be appreciated that the RF transistor amplifier die 210 can have a variety of different configurations. For example, the RF transistor amplifier die 210 has topside gate, drain, and source terminals 222, 224, 226, but in some embodiments may also have one or more backside gate, drain, and source terminals 222′, 224′, 226′. Such a configuration is shown schematically in FIG. 6C, which is a schematic cross-sectional view of the RF transistor amplifier die 210″. As shown in FIG. 6C, gate vias 211, drain vias 213, and / or source vias 215 may be formed through the semiconductor layer structure 230 connecting to the respective gate, drain, and source terminals 222′, 224′, 226′. For example, as described in U.S. Provisional Patent Application No. 63 / 004,985, filed April 3, 2020 (the “’985 Application”), including gate and drain terminals on the backside of the RF transistor amplifier die can have various advantages, such as enabling more flexible implementation of impedance matching circuits. The entire contents of the '985 application are incorporated herein by reference. It will be understood that backside gate, drain and source terminals 222', 224', 226' and / or corresponding gate, drain and source vias 211, 213, 215 may be included in any of the RF transistor amplifier dies disclosed herein.

[0159] 3A-3E show embodiments in which circuit elements 350 are on the top surface of circuit module 310 (e.g., on the opposite side of circuit module 310 from RF transistor amplifier die 210), and FIGS. 6A-6C show embodiments in which circuit elements 650 are on the bottom surface of circuit module 610 (e.g., between circuit module 610 and RF transistor amplifier die 210), it will be understood that other combinations are also available. In some embodiments, circuit elements 350 / 650 may be on both sides of circuit module 310 / 610. In some embodiments, circuit elements 350 / 650 may be on the side of circuit module 310 / 610.

[0160] 6A-6C, multiple configurations of RF transistor amplifier die 210 and / or RF transistor amplifiers 200 may be coupled to circuit module 610. In subsequent figures, the description will focus on embodiments in which RF transistor amplifier die 210 is directly coupled to circuit module 610. However, it will be understood that this convention is merely for ease of explanation, and that the subsequent description related to circuit module 610 may equally apply to other types of interconnections between RF transistor amplifiers 210 (e.g., using coupling elements 270) and / or RF transistor amplifiers 200 without departing from the invention.

[0161] 7A-7E are schematic diagrams illustrating a method of coupling a circuit module and an RF transistor amplifier die according to certain embodiments of the present invention. As shown in FIG. 7A, a circuit module 610 can be provided. The circuit module 610 can have a first side 601 and a second side 602. In some embodiments, the first side 601 can expose first, second, and third interconnect pads 622, 624, 626, and first and second surface connection pads 672, 674. In some embodiments, the second side 602 can have an exposed gate lead 682, a drain lead 684, and a source lead 686.

[0162] 7B, a first circuit element 650a and a second circuit element 650b may be provided on a first side 601 of the circuit module 610. For example, a contact element (e.g., solder balls and / or bumps 320) may be used to couple the first circuit element 650a to a first surface connection pad 672. Similarly, a contact element (e.g., solder balls and / or bumps 320) may be used to couple the second circuit element 650b to a second surface connection pad 674.

[0163] 7C , the RF transistor amplifier die 210 may be provided on a first side 601 of the circuit module 610. For example, the gate terminal 222, the drain terminal 224, and the source terminal 226 of the RF transistor amplifier die 210 may be coupled to the first, second, and third interconnect pads 622, 624, 626, respectively, using bonding elements (e.g., solder balls and / or bumps 320). It will be understood that the order of FIGS. 7B and 7C can be reversed, such that the RF transistor amplifier die 210 is coupled to the circuit module 610 before the first and second circuit elements 650 a, 650 b.

[0164] 7D , a capillary underfill process can be used to inject an encapsulant material 625 between the RF transistor amplifier die 210, the first and second circuit elements 650 a, 650 b, and / or the conductive structures of the circuit module 610. The encapsulant material 625 can help prevent shorts, enhance the structural integrity of the resulting device, and provide proper impedance matching. In some embodiments, the encapsulant material 625 may also encapsulate the RF transistor amplifier die 210 within a protective material.

[0165] 7E shows an additional optional step in which a thermal layer 240 is disposed on the backside of the RF transistor amplifier die 210. In some embodiments, an additional thermal management structure 642, such as a metal flange, metal fin, heat sink, or other structure, can be provided on the thermal layer 240. In some embodiments, the thermal management structure 642 may be part of a larger semiconductor package (e.g., a carrier substrate), as described further herein. The thermal layer 240 may be a thermally conductive layer configured to facilitate heat transfer between the RF transistor amplifier die 210 and the thermal management structure 642 to which the RF transistor amplifier die 210 is attached. In some embodiments, the thermal layer 240 and / or the thermal management structure 642 may be omitted. In some embodiments, the thermal layer 240 may be a die-attach layer, such as a eutectic layer. The thermal layer 240 may be on the transistor amplifier die 210 and / or may extend over the encapsulation material 625 and / or the first and second circuit elements 650a, 650b. The thermal layer 240 may be a metal layer for forming a eutectic or other metallurgical bond, hi some embodiments, the thermal layer 240 may be a thermal adhesive.

[0166] The embodiment of Figures 6A-6C provides a common gate lead 682, drain lead 684, and source lead 686 on a common side (e.g., second side 602) of the circuit module 610. This allows the circuit module 610 to be mounted second side 602 up in a variety of different configurations. For example, Figures 8A and 8B are schematic cross-sectional views of various packaging options 800a, 800b for the circuit module 610 according to some embodiments of the present invention. Figures 8A and 8B include elements of the RF transistor amplifier die 210 and circuit module 610 described above. Therefore, the description of Figures 8A and 8B will focus on portions of the embodiment that differ from those described with respect to the previous figures.

[0167] 8A , the semiconductor package 800a may be similar to the semiconductor package 500a described herein with respect to FIG. 5A , and redundant description already provided with respect to that figure will be omitted. The semiconductor package 800a may be, for example, an open-air or open-cavity package. The semiconductor package 800a may include a carrier substrate 410, sidewalls 520, and a lid 525. The carrier substrate 410, sidewalls 520, and lid 525 may define an internal cavity 530. The RF transistor amplifier die 210 and the circuit module 610 may be disposed within the internal cavity 530. In some embodiments, a thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410.

[0168] The leads 415A, 415B may be configured to extend through the sidewall 520, although the invention is not limited thereto. In some embodiments, the RF transistor amplifier 210 may be disposed on the carrier substrate 410 and the leads 415A, 415B, and the circuit module 610 may be disposed on the RF transistor amplifier die 210. The leads 415A, 415B may be coupled to the circuit module 610 using, for example, a conductive die attach material. In some embodiments, the leads 415A, 415B may extend from the sidewall 520 to contact and / or connect to the circuit module 610. For example, the lead 415a may be coupled to the gate lead 682, and the lead 415b may be coupled to the drain lead 684. In some embodiments, additional leads and / or connections (not shown) may be coupled to the source lead 686. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier die 210 to the leads 415A, 415B can be avoided and / or reduced.

[0169] 8B, a semiconductor package 800b can incorporate the RF transistor amplifier 210 and the circuit module 610 according to an embodiment of the present invention. The semiconductor package 800b can be similar to the semiconductor package 500b described herein with respect to FIG. 5B, and redundant description already provided with respect to that figure will be omitted. The semiconductor package 800b can be, for example, an overmolded plastic (OMP) package.

[0170] In a semiconductor package 800b in accordance with the present invention, leads 415A, 415B may extend from outside the semiconductor package 800b into the overmold material 540 to connect to the circuit module 610. For example, lead 415a may be coupled to the gate lead 682, and lead 415b may be coupled to the drain lead 684. In some embodiments, additional leads and / or connections (not shown) may be coupled to the source lead 686. In some embodiments, a thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410 in the semiconductor package 800b.

[0171] It will be appreciated that in addition to the semiconductor packages 800a, 800b shown with respect to Figures 8A and 8B, other packaging configurations are possible without departing from the invention. For example, the circuit module 610 can be utilized in a semiconductor package similar to that of Figure 5C, as well as other configurations.

[0172] 6A-6C, circuit elements 650a, 650b and RF transistor amplifier die 210 are on the same side of circuit module 610, with gate, drain, and source leads 682, 684, 686 on opposite sides, although this embodiment is not limited thereto. FIG. 9A is a plan view of one embodiment of a circuit module 610B in accordance with some embodiments of the present invention, with leads 682, 684, 686, circuit elements 650a, 650b, and RF transistor amplifier die 210 all on the same side of circuit module 610B. FIG. 9B is a cross-sectional view taken along line 9B-9B in FIG. 9A. FIG. 9C is a cross-sectional view taken along line 9C-9C in FIG. 9A. FIGS. 9A-9C include elements of RF transistor amplifier die 210 and circuit module 610 previously described. Therefore, the description of FIGS. 9A-9C will focus on portions of the embodiment that differ from those described with respect to the previous figures.

[0173] 9A-9C, a circuit module 610B may be attached to the RF transistor amplifier die 210. The RF transistor amplifier die 210 is attached below the circuit module 610B in the schematic plan view of FIG. 9A and is therefore shown using dashed lines. The circuit module 610B may be configured to couple to the gate terminal 222, the drain terminal 224, and / or the source terminal 226 of the RF transistor amplifier die 210. While FIGS. 9A-9C show the circuit module 610B being directly coupled to the RF transistor amplifier die 210, it will be understood that other connection types are possible, such as other configurations of the RF transistor amplifier 200, including those shown with respect to FIGS. 2A-2L. For example, a coupling element 270 may be coupled between the circuit module 610B and the RF transistor amplifier die 210.

[0174] For example, the circuit module 610B may have exposed interconnect pads 622, 624, 626 that may be configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively, of the RF transistor amplifier die 210. For example, the first interconnect pad 622 may be configured to couple to the gate terminal 222, the second interconnect pad 624 may be configured to couple to the drain terminal 224, and the third interconnect pad 626 may be configured to couple to the source terminal 226. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first, second, and third interconnect pads 622, 624, 626 to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. While shown as single pads, in some embodiments, one or more of the first, second, and / or third interconnect pads 622, 624, 626 may include multiple pads.

[0175] The circuit module 610B may be coupled to the RF transistor amplifier die 210 at a first side 601 of the circuit module 610B. Additionally, a gate lead 682B, a drain lead 684B, and a source lead 686B may be exposed at the first side 601 of the circuit module 610B. As described further herein, the gate lead 682B, the drain lead 684B, and the source lead 686B may be configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively, of the RF transistor amplifier die 210. An encapsulant material 625 may be on a surface of the RF transistor amplifier die 201 and / or the circuit module 610B.

[0176] Each of the first, second, and third interconnect pads 622, 624, 626 may be coupled to one or more conductive patterns 673B within the circuit module 610B. The conductive patterns 673B can provide various routing and / or circuitry within the circuit module 610B. For example, the conductive patterns 673B may connect the first interconnect pad 622 to one or more first surface connection pads 672 and a gate lead 682B. In some embodiments, the first surface connection pads 672 may be exposed on the first side 601 of the circuit module 610B. In some embodiments, the first circuit element 650a may be coupled to one or more of the first surface connection pads 672 so as to be electrically coupled between the gate lead 682B and the first interconnect pad 622. In some embodiments, the first circuit element 650a may be coupled between the gate lead 682B and the gate terminal 222 of the RF transistor amplifier die 210. Thus, the first circuit element 650a may be electrically coupled between the gate of the RF transistor amplifier die 210 and the gate lead 682B. In some embodiments, the first circuit element 650a may be coupled to the first side 601 of the circuit module 610B. Thus, the first circuit element 650a may be coupled to the same side (e.g., first side 601) of the circuit module 610B as the RF transistor amplifier die 210 and the gate lead 682B.

[0177] Similarly, conductive pattern 673B may connect second interconnect pad 624 to drain terminal 224 and drain lead 684B. In some embodiments, second circuit element 650b may be coupled to one or more of second surface connection pads 674 such that second circuit element 650b is electrically coupled between drain lead 684B and second interconnect pad 624. In some embodiments, second surface connection pad 674 may be exposed at first side 601 of circuit module 610B. In some embodiments, second circuit element 650b may be coupled between drain lead 684B and drain terminal 224 of RF transistor amplifier die 210. Thus, second circuit element 650b may be electrically coupled between the drain of RF transistor amplifier die 210 and drain lead 684B.

[0178] The conductive pattern 673B may also connect the third interconnect pad 626 to one or more source leads 686B. The source leads 686B may be on the same first side 601 as the third interconnect pad 626 and the RF transistor amplifier die 210. In some embodiments, as shown in FIG. 9A , the gate lead 682B and the drain lead 684B may be on two opposing sides of the RF transistor amplifier die 210, and the source leads 686B may be on a different side of the RF transistor amplifier die 210 than the two opposing sides. In other words, in some embodiments, the gate lead 682B may be adjacent to a first side of the RF transistor amplifier die 210, the drain lead 684B may be adjacent to a second side of the RF transistor amplifier die 210, and one or more of the source leads 686B may be adjacent to a third side of the RF transistor amplifier die 210 that is different from the first and second sides of the RF transistor amplifier die 210.

[0179] 9A-9C may differ from the circuit module 610 of FIGS. 6A-6C in that the circuit module 610B provides the gate, drain, and source leads 682B, 684B, 686B on the same side as the RF transistor amplifier die 210 of the circuit module 610B. That is, the conductive pattern 673 of the circuit module 610B may be configured to allow the gate, drain, and source leads 682B, 684B, 686B to be exposed in different portions of the circuit module 610B. By shifting the side on which the gate, drain, and source leads 682B, 684B, 686B are located, additional packaging options are possible.

[0180] 9D is a cross-sectional view of the circuit module 610B of FIG. 9A mounted on a carrier substrate 410, according to some embodiments of the present invention. As shown in FIG. 9D, the circuit module 610B may be coupled onto the RF transistor amplifier die 210, which may in turn be on the carrier substrate 410.

[0181] In some embodiments, a thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410. In some embodiments, an additional thermal management structure 642, such as a metal flange, metal fin, heat sink, or other structure, may be provided on the thermal layer 240 and / or between the thermal layer 240 and the carrier substrate 410. The thermal layer 240 may be a thermally conductive layer configured to facilitate heat transfer between the RF transistor amplifier die 210 and the carrier substrate 410 to which the RF transistor amplifier die 210 is attached. In some embodiments, the thermal layer 240 and / or the thermal management structure 642 may be omitted. In some embodiments, the thermal layer 240 may be a die-attach layer, such as a eutectic layer. The thermal layer 240 may be on the RF transistor amplifier die 210 and / or may extend over the encapsulant material 625 and / or the first and second circuit elements 650a, 650b. The thermal layer 240 may be a metal layer for forming a eutectic bond or other metallurgical bond. In some embodiments, the thermal layer 240 may be a thermal adhesive.

[0182] In some embodiments, additional contacts may be provided in the carrier substrate 410, although the invention is not limited thereto. For example, a gate connector 982, a drain connector 984, and / or a source connector (not shown) may be provided on and / or in the carrier substrate 410. For example, the gate lead 682B of the circuit module 610B may be configured to be coupled to the gate connector 982 (e.g., via a joining element such as a solder ball and / or bump 320), the drain lead 684B may be configured to be coupled to the drain connector 984, and the source lead 686B may be configured to be coupled to the source connector (not shown).

[0183] It will be understood that the packaging example of FIG. 9B is merely an example, and the present invention is not limited thereto. In some embodiments, the circuit module 610B of FIGS. 9A-9C can be coupled into other semiconductor packages described herein, such as those described with respect to FIGS. 5A-5C and 8A-8B. For example, FIGS. 10A and 10B are schematic cross-sectional views of various packaging options 1000a, 1000b for the circuit module 610B according to some embodiments of the present invention. FIGS. 10A and 10B include the RF transistor amplifier die 210 and elements of the circuit module 610B described above. Therefore, the description of FIGS. 10A and 10B focuses on portions of the embodiment that differ from those described with respect to the previous figures.

[0184] 10A , a semiconductor package 1000a may be similar to the semiconductor packages 500a and 800a described herein with reference to FIGS. 5A and 8A , respectively, and redundant description already provided with reference to those figures will be omitted. The semiconductor package 1000a may be, for example, an open-air or open-cavity package. The semiconductor package 1000a may include a carrier substrate 410, sidewalls 520, and a lid 525. The carrier substrate 410, sidewalls 520, and lid 525 may define an internal cavity 530. The RF transistor amplifier die 210 and the circuit module 610B may be disposed within the internal cavity 530. In some embodiments, a thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410.

[0185] The leads 415A, 415B may be configured to extend through the sidewall 520, although the invention is not limited thereto. In some embodiments, the RF transistor amplifier 210 may be disposed on the carrier substrate 410 and the leads 415A, 415B, and the circuit module 610B may be disposed on the RF transistor amplifier die 210. The leads 415A, 415B may be coupled to the circuit module 610B using, for example, a conductive die attach material. For example, the lead 415a may be coupled to the gate lead 682B, and the lead 415b may be coupled to the drain lead 684B. In some embodiments, additional leads and / or connections (not shown) may be coupled to the source lead 686B. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier die 210 to the leads 415A, 415B may be avoided and / or reduced.

[0186] 10B, a semiconductor package 1000b can incorporate an RF transistor amplifier 210 and a circuit module 610B according to an embodiment of the present invention. The semiconductor package 1000b can be similar to the semiconductor packages 500b and 800b described herein with respect to FIGS. 5B and 8B, and redundant description already provided with respect to those figures will not be repeated. The semiconductor package 1000b can be, for example, an overmolded plastic (OMP) package.

[0187] In a semiconductor package 1000b in accordance with the present invention, leads 415A, 415B may extend from outside the semiconductor package 800b into the overmold material 540 to connect to the circuit module 610B. For example, lead 415a may be coupled to gate lead 682B, and lead 415b may be coupled to drain lead 684B. In some embodiments, additional leads and / or connections (not shown) may be coupled to source lead 686B.

[0188] It will be appreciated that in addition to the semiconductor packages 1000a, 1000b shown with respect to Figures 10A and 10B, other packaging configurations are possible without departing from the invention. For example, circuit module 610B can be utilized in semiconductor packages similar to that of Figure 5C, as well as other configurations.

[0189] As described herein, a circuit module can include circuit elements on its surface, but can also include circuit elements within the circuit module itself. Figures 11A-11D are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die 210 coupled to a circuit module 610C, according to some embodiments of the present invention. Figures 11A-11D include elements of the RF transistor amplifier die 210 and circuit module 610C described above. Therefore, the description of Figures 11A-11D focuses on portions of the embodiment that differ from those described with respect to the previous figures.

[0190] 11A, a circuit module 610C may be attached to the RF transistor amplifier die 210. The circuit module 610C may be configured to couple to the gate terminal 222, the drain terminal 224, and the source terminal 226 of the RF transistor amplifier die 210. While FIG. 11A shows the circuit module 610C being directly coupled to the RF transistor amplifier die 210, it will be understood that other connection types are possible, such as other configurations of the RF transistor amplifier 200, including those shown with respect to FIGS. 2A-2L. For example, a coupling element 270 may be coupled between the circuit module 610C and the RF transistor amplifier die 210.

[0191] The circuit module 610C may have exposed interconnect pads 622, 624, 626 that may be configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first, second, and third interconnect pads 622, 624, 626 to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. Although shown as single pads, in some embodiments, one or more of the first, second, and / or third interconnect pads 622, 624, 626 may include multiple pads.

[0192] The circuit module 610C may be coupled to the RF transistor amplifier die at a first side 601 of the circuit module 610C. Additionally, a gate lead 682C, a drain lead 684C, and a source lead (not shown) may be exposed at the first side 601 of the circuit module 610C. The gate lead 682C, the drain lead 684C, and the source lead may be configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226 of the RF transistor amplifier die 210, respectively.

[0193] The circuit module 610C may include one or more conductive patterns 1173, a first circuit element 1150a, and a second circuit element 1150b. The first and second circuit elements 1150a, 1150b are shown schematically in FIG. 11A. The circuit module 610C may differ from the circuit modules 610, 610B described herein in that the first and second circuit elements 1150a, 1150b may be incorporated into the structure of the circuit module 610C. For example, the conductive patterns 1173 in the circuit module 610C may be used to implement plate capacitors, interdigitated finger capacitors, and / or capacitors. Similarly, spiral inductors or other inductive elements may also be implemented in the circuit module 610C. Resistive elements may be formed on or within the circuit module 610C, for example, by forming trace segments or conductive vias using a more highly resistive conductive material.

[0194] In some embodiments, the first and second circuit elements 1150a, 1150b and / or the conductive pattern 1173 may be configured to provide at least a portion of a harmonic termination circuit, a matching circuit, a splitting circuit, a combining circuit, and / or a biasing circuit. Other configurations of the conductive pattern 1173 and / or other types of circuit elements 1150a, 1150b may be used without departing from the scope of the present invention. It will also be understood that the configuration of the conductive pattern 1173 and circuit elements 1150a, 1150b shown in FIG. 11A is merely an example and is not intended to limit embodiments of the present invention.

[0195] In some embodiments, the circuit module 610C may be formed as a PCB module, and the first and second circuit elements 1150a, 1150b may be formed from traces in a PCB. In some embodiments, the circuit module 610C may be formed from an insulating material 615, and the conductive pattern 1173 may be a conductive material in the insulating material 615, such as conductive pillars and / or vias (e.g., copper pillars).

[0196] Each of the first, second, and third interconnect pads 622, 624, 626 may be coupled to one or more conductive patterns 1173 within the circuit module 610C. The conductive patterns 1173 may provide various routing and / or circuitry within the circuit module 610C. For example, the conductive pattern 1173 may connect the first interconnect pad 622 to the gate lead 682C via the first circuit element 1150a. The first circuit element 1150a may provide input matching and / or harmonic termination functions between the gate lead 682C and the first interconnect pad 622.

[0197] Similarly, the conductive pattern 1173 may connect the second interconnect pad 624 to the drain lead 684C through the second circuit element 1150b, which may provide output matching and / or harmonic termination functions between the drain lead 684C and the second interconnect pad 624.

[0198] 11A, in some embodiments, an encapsulation material 1125 may be formed over the RF transistor amplifier die 210, the circuit module 610C, the gate lead 682C, and / or the drain lead 684C. The encapsulation material 1125 may help prevent short circuits, enhance the structural integrity of the resulting device, and provide proper impedance matching. In some embodiments, the encapsulation material 1125 may also encapsulate the RF transistor amplifier die 210 in a protective material.

[0199] In some embodiments, a through via 1115 may be formed in the encapsulation material 1125. The through via 1115 may comprise a conductive material and provide a conductive path to the gate lead 682C and / or the drain lead 684C. For example, the through via 1115 may expose a gate connection 1182 and / or a drain connection 1184 on a bottom surface of the encapsulation material 1125. The gate connection 1182 and / or the drain connection 1184 may provide a connection point for the gate lead 682C and the drain lead 684C, respectively.

[0200] In some embodiments, the gate connection 1182 and the drain connection 1184 may be substantially flush with each other. In some embodiments, the encapsulant 1125 may be configured to expose a bottom surface of the RF transistor amplifier die 210, and the gate connection 1182 and the drain connection 1184 may also be substantially flush with the bottom surface of the RF transistor amplifier die 210, although the invention is not limited thereto. While only the gate connection 1182 and the drain connection 1184 are shown in FIG. 11A , it will be understood that a source connection may be provided as well.

[0201] The use of gate connection 1182 and drain connection 1184 can enable the use of direct bonding between the combination of RF transistor amplifier die 210 and circuit module 610C and other pads and / or dies. For example, as shown in FIG. 11B , gate connection 1182 may be coupled to gate pad 1192 (e.g., via a bonding element such as solder), and drain connection 1184 may be coupled to gate pad 1194. In some embodiments, thermal layer 240 may be provided below RF transistor amplifier die 210, although the invention is not limited thereto. In some embodiments, thermal layer 240 may be omitted. In some embodiments, additional contacts may be provided to connect to third interconnect pad 626 and / or source terminal 226 of RF transistor amplifier die 210.

[0202] It will be understood that the packaging example of FIG. 11B is merely an example and that the present invention is not limited thereto. FIGS. 11C and 11D illustrate the use of packaging similar to that described herein with respect to FIGS. 5A-5C, 8A, 8B, 10A, and 10B. For example, the encapsulant 1125 containing the circuit module 610C, the RF transistor amplifier die 210, and the gate and drain connections 1182, 1184 may be disposed within an open-cavity semiconductor package 1100a (FIG. 11C) or an OMP package 1100b (FIG. 11D). Elements of the semiconductor package 1100a and the semiconductor package 1100b similar to those described above with respect to FIGS. 5A-5C, 8A, 8B, 10A, and 10B are omitted for brevity.

[0203] In some embodiments, the gate connection 1182 may be coupled to the gate lead 415A by a bonding element (e.g., a solder ball and / or a bump), and the drain connection 1184 may also be coupled to the drain lead 415B. The gate lead 415A and the drain lead 415B may be electrically insulated from the carrier substrate 410 (e.g., by an insulating layer and / or an overmold material 540). In some embodiments, a thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, the thermal layer 240 may be a die-attach layer, such as a eutectic layer. The thermal layer 240 may be on the transistor amplifier die 210 and / or may extend over the encapsulation material 1125. The thermal layer 240 may be a metal layer for forming a eutectic bond or other metallurgical bond. In some embodiments, the thermal layer 240 may be a thermal adhesive. Although not shown in FIGS. 11C and 11D, in some embodiments, additional thermal management structures may be used, such as those shown in FIGS. 7E and 9D.

[0204] 11C and 11D are merely examples intended to illustrate how circuit module 610C and RF transistor amplifier die 210 may be combined within a semiconductor package, it will be understood that multiple other possible configurations and / or orientations of the semiconductor package are possible without departing from the invention.

[0205] In some embodiments, the through vias 1115 and / or the encapsulation material 1125 may be omitted. For example, FIGS. 12A-12D are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die 210 coupled to a circuit module 610C according to some embodiments of the present invention. As shown in FIG. 12A, the circuit module 610C may be substantially similar to that shown in FIGS. 11A-11D, and therefore a redundant description will be omitted. The embodiment of FIG. 12A may, for example, omit the encapsulation material 1125, the through vias 1115, and / or the gate / drain connections 1182, 1184, directly exposing the gate lead 682C and the drain lead 684C. While FIG. 12A illustrates that all of the encapsulation material 1125 is removed, it will be understood that in some embodiments, some encapsulation material 1125 may be present. For example, in some embodiments, the encapsulant material 1125 may overlie the RF transistor amplifier die 210 and a portion of the circuit module 610C, but may expose the gate lead 682C and the drain lead 684C.

[0206] The embodiment shown in FIG. 12A can be utilized in multiple packaging configurations. FIGS. 12B and 12C illustrate the use of packaging similar to that described herein with respect to FIGS. 5A-5C, 8A, 8B, 10A, and 10B. For example, circuit module 610C and RF transistor amplifier die 210 may be disposed within open-cavity semiconductor package 1200a (FIG. 12B) or OMP package 1200b (FIG. 12C). Elements in FIGS. 12B and 12C of semiconductor package 1200a and semiconductor package 1200b similar to those described above with respect to FIGS. 5A-5C, 8A, 8B, 10A, and 10B are omitted for brevity. In some embodiments, gate lead 682C may be coupled to gate lead 415A by bonding elements (e.g., solder balls and / or bumps 320), and drain lead 684C may also be coupled to drain lead 415B. It will be appreciated that many other possible configurations and / or orientations of the semiconductor package are possible without departing from the invention.

[0207] While many of the embodiments described herein reduce and / or eliminate wire bonds, it will be appreciated that the present invention can further improve upon configurations that utilize wire bonds. For example, FIG. 12D illustrates a semiconductor package 1200c that utilizes a circuit module 610C that utilizes wire bonds. Referring to FIG. 12D, the semiconductor package 1200c may be, for example, an open-air or open-cavity package. The semiconductor package 1200c may include a carrier substrate 410, sidewalls 520, and a lid 525. The carrier substrate 410, sidewalls 520, and lid 525 may define an internal cavity 530. The RF transistor amplifier die 210 and the circuit module 610C may be disposed within the internal cavity 530.

[0208] The leads 415A, 415B may be configured to extend through the sidewall 520, although the invention is not limited thereto. In some embodiments, the circuit module 610C may be disposed on the carrier substrate 410 and the leads 415A, 415B, and the RF transistor amplifier die 210 may be disposed on the circuit module 610C. The leads 415A, 415B may be coupled to the circuit module 610C using, for example, wire bonds 1280. For example, the lead 415a may be coupled to the gate lead 682C, and the lead 415b may be coupled to the drain lead 684C. While the semiconductor package 1200c utilizes wire bonds 1280, there are still advantages to a direct connection between the RF transistor amplifier die 210 and the circuit module 610C. Additionally, the circuit module 610C incorporates first and second circuit elements 1150a, 1150b, which may enable additional internalized functions such as harmonic termination and / or input / output impedance matching. Additionally, the use of circuit module 610C allows for greater flexibility in that different performance characteristics (e.g., to address harmonics of different frequencies, different impedances, etc.) can be achieved simply by swapping out circuit module 610C.

[0209] Although FIG. 12D utilizes circuit module 610C, it will be understood that wire bonds 1280 may be incorporated into other semiconductor packaging configurations utilizing any of the circuit modules and / or RF transistor amplifiers described herein.

[0210] Referring again to FIGS. 6A-6C, various embodiments are shown providing an RF transistor amplifier die 210 coupled to a circuit module 610. In some embodiments, the RF transistor amplifier die 210 is directly coupled to the circuit module 610 (e.g., FIG. 6B), while in some embodiments, the RF transistor amplifier die 210 is coupled to the circuit module 610 via a coupling element 270 (e.g., FIG. 6A). In embodiments such as FIGS. 6A-6C, an encapsulation material 625 may be present on one or more sides of the RF transistor amplifier die 210 to protect / encapsulate the RF transistor amplifier die 210. In some embodiments, as shown in FIGS. 6A-6C, the bottom surface of the RF transistor amplifier die 210 may be exposed by the encapsulation material 625, although the invention is not limited thereto.

[0211] 13A-13D are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die 210 coupled to a circuit module 610 and incorporating a spacer, according to some embodiments of the present invention. The aforementioned portions of FIGS. 13A-13D will not be repeated here for the sake of brevity. Referring to FIG. 13A, in some embodiments, a spacer 245 may be disposed on the bottom surface 210a of the RF transistor amplifier die 210. An encapsulant material 625 may expose the bottom surface 245a of the spacer 245.

[0212] In some embodiments, the spacer 245 may be formed of an electrically conductive material, such as a metal, and / or a thermally conductive material. In some embodiments, the spacer 245 may be or include, but is not limited to, gold (Au) copper (Cu), a Cu alloy, gold tin (AuSn), and / or epoxy. In some embodiments, the spacer 245 may be or include, but is not limited to, an electrically insulating and / or dielectric material, such as, for example, silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof. In some embodiments, the spacer 245 may be thermally conductive. Thus, the spacer 245 may be configured to dissipate heat transferred from the RF transistor amplifier die 210. In some embodiments, the spacer 245 may be composed of multiple layers, but is not limited to this. In some embodiments, the spacer 245 may perform a similar function and / or be composed of a similar material as the thermal layer 240 described herein. Incorporating spacers 245 onto the RF transistor amplifier die 210 within the encapsulation material 625 can provide packaging options that are easier to distribute and attach. While FIG. 13A illustrates an embodiment in which the RF transistor amplifier die 210 is directly coupled to the circuit module 610, the invention is not limited thereto. In some embodiments, the transistor amplifier die 210 may be coupled to the circuit module 610 via coupling elements 270 similar to those shown in FIG. 6B. Similarly, in some embodiments, the RF transistor amplifier die 210 can incorporate an on-die RDL, such as the RF transistor amplifier die 210′ ​​of FIG. 3C.

[0213] 13A, the encapsulant material 625 may be on the RF transistor amplifier die 210 and on the first and second circuit elements 650a, 650b. However, the present invention is not limited to such a configuration. Depending on the electrical and thermal requirements of the first and second circuit elements 650a, 650b, alternative and / or additional terminal / bond / spacer structures may be utilized with at least one of the first and second circuit elements 650a, 650b to provide an electrical, thermally conductive, and / or mechanical interface to one of the first and second circuit elements 650a, 650b.

[0214] In some embodiments, surfaces of the first and second circuit elements 650 a, 650 b may be exposed and / or coupled to auxiliary spacers as part of the RF transistor amplifier. For example, FIG. 13B is a schematic cross-sectional view of an RF transistor amplifier die 210 coupled to a circuit module 610 in accordance with some embodiments of the present invention. As shown in FIG. 13B, the circuit module 610 and / or the RF transistor amplifier die 210 may be substantially similar to the previously described embodiments, and therefore, redundant description will be omitted. The embodiment shown in FIG. 13B may include, for example, a first auxiliary spacer 246 a and a second auxiliary spacer 246 b.

[0215] In some embodiments, the first auxiliary spacer 246a may be formed on the first circuit element 650a. In some embodiments, the second auxiliary spacer 246b may be formed on the second circuit element 650B. For example, the first auxiliary spacer 246a may be formed on and / or in contact with the first circuit element 650a, and the second auxiliary spacer 246b may be formed on and / or in contact with the second circuit element 650b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be formed of an electrically conductive and / or thermally conductive material, such as a metal. In some embodiments, surfaces of the first and / or second auxiliary spacers 246a, 246b may be exposed from the encapsulation material 625. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be or include gold (Au) copper (Cu), a Cu alloy, gold tin (AuSn), and / or epoxy, but the present invention is not limited thereto. The first and / or second auxiliary spacers 246a, 246b may be configured to be electrically coupled to the first and / or second circuit elements 650a, 650b, for example, to provide a mechanism through which a ground signal is provided to the first and / or second circuit elements 650a, 650b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be thermally conductive. Thus, the first and / or second auxiliary spacers 246a, 246b may be configured to dissipate heat transferred from the first and / or second circuit elements 650a, 650b. In some embodiments, the first and / or second auxiliary spacers 246 a, 246 b may be electrically insulating and / or may be or include a dielectric material such as, for example, but not limited to, silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof. In some embodiments, the first and / or second auxiliary spacers 246 a, 246 b may be composed of multiple layers, but the invention is not limited thereto.

[0216] In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of a similar material to the spacer 245, although the invention is not limited in this respect. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of a different material than the spacer 245. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be electrically disconnected from the spacer 245. Forming the first and / or second auxiliary spacers 246a, 246b from a different material than the spacer 245 and / or electrically disconnecting them from the spacer 245 can help limit current sharing and / or current eddies between the RF transistor amplifier die 210 and the first and / or second circuit elements 650a, 650b. While the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 are shown as separate, individual elements, the invention is not limited in this respect. In some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be connected to one another as a unitary layer (see, eg, FIG. 13C).

[0217] The material / thickness of the first and second auxiliary spacers 246a, 246b can be the same or different from that of the spacer 245. In some embodiments, the spacer 245 and the first and second auxiliary spacers 246a, 246b may have different thicknesses so that the bottoms of the first and second auxiliary spacers 246a, 246b are planar with the bottom of the spacer 245 to facilitate packaging / manufacturing / bonding of the RF transistor amplifier die 210 and the circuit module 610 to a package substrate or circuit board. In some embodiments, the spacer 245 and the first and second auxiliary spacers 246a, 246b are planar. In still other embodiments, the spacer 245 spans at least one or all of the RF transistor amplifier die 210 and the first and second circuit elements 650, 650b, for example, to provide the advantage of a planar interface surface.

[0218] Additional and / or intervening spacers, bonds, and other layers may be provided to provide the desired electrical, thermal, and mechanical interfaces. Depending on the desired electrical, thermal, and / or mechanical properties, the layers may be made of electrically conductive and / or thermally conductive and / or insulating materials. For example, in some embodiments, the spacer 245 may be thermally conductive and electrically insulating, and the first and second auxiliary spacers 246a, 246b may both be electrically conductive and thermally conductive. In some embodiments, only the spacer 245 may be present on the RF transistor amplifier die 210. In some embodiments, only the first auxiliary spacer 246a may be present on the first circuit element 650a. In some embodiments, only the second auxiliary spacer 246b may be present on the second circuit element 650b. In other embodiments, any combination of the spacer 245, the first auxiliary spacer 246a, and the second auxiliary spacer 246b may be present.

[0219] In some embodiments, the exposed surfaces of the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be substantially coplanar, i.e., the exposed surfaces of the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be configured to be attached to another substrate (e.g., via an attachment method such as solder).

[0220] It will be understood that the fabrication method for the embodiment of Figures 13A-13C can be similar to that shown with respect to Figures 7A-7D. For example, fabrication of an RF transistor amplifier device can include disposing a spacer 245 on the RF transistor amplifier die 210, disposing a first auxiliary spacer 246a on the first circuit element 650a, and disposing a second auxiliary spacer 246b on the second circuit element 650b. For example, the spacer 245 can be electrically and / or thermally connected to the RF transistor amplifier die 210 (e.g., via die attach material). For example, the first auxiliary spacer 246a and the second auxiliary spacer 246b can be electrically and / or thermally connected to the first and second circuit elements 650a, 650b, respectively (e.g., via die attach material). This step may be performed, for example, after disposing the first and second circuit elements 650a, 650b and the RF transistor amplifier die 210 on the circuit module 610 (as shown in connection with FIGS. 7B and 7C). In some embodiments, disposing the spacer 245, the first auxiliary spacer 246a, and the second auxiliary spacer 246b may be performed before or after forming the encapsulation material 625 on the RF transistor amplifier die 210 (as shown in connection with FIG. 7D). In some embodiments, deposition of the spacer 245 may be performed by a different process than the first auxiliary spacer 246a and / or the second auxiliary spacer 246b.

[0221] As mentioned above, in some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be interconnected and / or integrally formed. FIG. 13C shows an embodiment with an integral spacer layer 245′. The integral spacer layer 245′ may extend to connect to and / or contact the first circuit element 350a, the second circuit element 350b, and the RF transistor amplifier die 10 (e.g., the source terminal 26 of the RF transistor amplifier die 10). In some embodiments, the surface 245a′ of the integral spacer layer 245′ may be exposed from the encapsulation material 325. In some embodiments, the integral spacer layer 245′ may be formed of the same or similar material as the first auxiliary spacer 246a, the second auxiliary spacer 246b, and / or the spacer 245 described with respect to the previous embodiment. For example, the integral spacer layer 245′ may be formed of an electrically conductive material and / or a thermally conductive material, such as a metal. In some embodiments, the integral spacer layer 245′ may be or include, but is not limited to, gold (Au) copper (Cu), a Cu alloy, gold tin (AuSn), and / or epoxy. In some embodiments, the integral spacer layer 245′ may be or include, but is not limited to, an electrically insulating and / or dielectric material, such as, for example, silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof. In some embodiments, the integral spacer layer 245′ may be composed of multiple layers, but is not limited to this. As used herein, a “integral” spacer layer 245′ refers to a substantially continuous spacer layer 245′, although not necessarily of uniform composition. In some embodiments, different portions of the integral spacer layer 245′ may be composed of different materials. As an example, the portion of the integral spacer layer 245 ′ on the first auxiliary spacer 246 a and / or the second auxiliary spacer 246 b may be different from the portion of the integral spacer layer 245 ′ on the RF transistor amplifier die 210 .

[0222] Although integral spacer layer 245′ is shown as a uniform layer having a relatively flat upper surface 245b′, the invention is not limited in this respect. In some embodiments, upper surface 245b′ of integral spacer layer 245′ may be non-flat. For example, in some embodiments, first circuit element 650a, second circuit element 650b, and RF transistor amplifier die 210 may have different heights, and integral spacer layer 245′ may be formed to have an upper surface 245b′ having portions at the different heights of each of first circuit element 650a, second circuit element 650b, and RF transistor amplifier die 210.

[0223] 13D illustrates an example embodiment of an RF transistor amplifier device in which the first auxiliary spacer 246a and the second auxiliary spacer 246b are omitted. Referring to FIG. 13D, a surface 650a_s of the first circuit element 650a and / or a surface 650b_s of the second circuit element 650b may be exposed by the encapsulation material 625. The exposure of the surfaces 650a_s, 650b_s of the first and / or second circuit elements 650a, 650b may allow additional external connections to be applied to the first and / or second circuit elements 650a, 650b. For example, a separate electrical connection, such as a ground signal, may be connected to the first and / or second circuit elements 650a, 650b via the respective exposed surfaces 650a_s, 650b_s.

[0224] The RF transistor amplifier device of FIG. 13D may be formed, for example, by constructing an embodiment similar to that of FIG. 13A and then performing a planarization operation on a portion of the encapsulation material 625 to expose surfaces 650a_s, 650b_s of the first and / or second circuit elements 650a, 650b.

[0225] The RF transistor amplifier die 210 coupled to the circuit module 610 shown in FIGS. 13A-13D may be utilized in multiple packaging configurations. FIGS. 14A-14D illustrate the use of packaging similar to that described herein with respect to FIGS. 8A and 8B. For example, the circuit module 610 and the RF transistor amplifier die 210 may be disposed within open-cavity semiconductor packages 1400a_1 and 1400a_2 (FIGS. 14A and 14B) or OMP packages 1400b_1 and 1400b_2 (FIGS. 14C and 14D). Elements of semiconductor package 1400a_1 and semiconductor package 1400a_2 similar to those previously described with respect to FIG. 8A, etc., will not be further described for the sake of brevity. Elements of semiconductor package 1400b_1 and semiconductor package 1400b_2 similar to those previously described with respect to FIG. 8B, etc., will not be further described for the sake of brevity.

[0226] 14A and 14C, semiconductor packages 1400a_1 and 1400b_1 illustrate the use of a circuit module 610 coupled to an RF transistor amplifier die 210 in an open-cavity package and an OMP package. FIG. 14A illustrates the open-cavity semiconductor package 1400a_1, and FIG. 14C illustrates the OMP semiconductor package 1400b_1. The semiconductor packages 1400a_1 and 1400b_1 further include a spacer 425, a first auxiliary spacer 246a, and a second auxiliary spacer 246b as shown and described with respect to FIG. 13B. The circuit module 610 can expose a gate lead 682 and a drain lead 684 that can be connected to leads 415A and 415B, respectively. In some embodiments, the semiconductor packages 1400a_1 and 1400b_1 can include a first auxiliary spacer 246a, a second auxiliary spacer 246b, and a spacer 245 that are substantially coplanar. Depending on the electrical and thermal requirements of the first and second circuit elements 650a, 650b, additional terminal / joint / spacer structures may be utilized with at least one of the first and second circuit elements 650a, 650b to provide an electrical, thermal, and / or mechanical interface between one or more of the at least one of the first and second circuit elements 650a, 650b and the carrier substrate 410.

[0227] In some embodiments, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be composed of a different material than the spacer 425. For example, in some embodiments, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be electrically conductive so as to be electrically coupled to the carrier substrate 410. For example, the first auxiliary spacer 246a and the second auxiliary spacer 246b may provide an electrical connection (e.g., a ground signal) to the first and second circuit elements 650a, 650b. In some embodiments, the spacer 245 may be thermally conductive but electrically insulating. This may allow the spacer 245 to dissipate heat from the RF transistor amplifier die 210. In some embodiments, the first and second auxiliary spacers 246a, 246b may be electrically insulating or conductive, but may also thermally connect the first and second circuit elements 650a, 650b to the carrier substrate 410 to dissipate thermal energy (e.g., heat) from the first and second circuit elements 650a, 650b.

[0228] 14B and 14D illustrate exemplary semiconductor packages 1400a_2, 1400b_2 incorporating an integrated spacer layer 245 in an open-cavity package and an OMP package. FIG. 14B illustrates the open-cavity semiconductor package 1400a_2, and FIG. 14D illustrates the OMP semiconductor package 1400b_2. The semiconductor packages 1400a_2, 1400b_2 can utilize the integrated spacer layer 245′ as described herein with respect to FIG. 13C. The integrated spacer layer 245′ can be connected and / or directly contacted to the carrier substrate 410. The integrated spacer 245′ can be coupled to the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210. In some embodiments, the integrated spacer layer 245′ may be configured to have a non-planar surface (e.g., a top surface) for bonding to the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210. The present invention is not limited in this respect, and in some embodiments, the top surface of the integrated spacer layer 245′ may be flat. In some embodiments, different portions of the integrated spacer layer 245′ may be composed of different materials. In some embodiments, additional layers (e.g., additional spacer layers) may be disposed between the first and second circuit elements 650a, 650b and the integrated spacer layer 245′, or between the integrated spacer layer 245′ and the carrier substrate 410, respectively.

[0229] While in Figures 14A-14D the RF transistor amplifier die 210 is shown as being directly coupled to the circuit modules 610 in the semiconductor packages 1400a_1, 1400a_2, 1400b_1, and 1400b_2, it will be appreciated that the RF transistor amplifier die 210 may, mutatis mutandis, be coupled to the circuit modules via coupling elements 270 or utilizing on-die RDLs.

[0230] 15A-15D are schematic cross-sectional views of additional RF transistor amplifier embodiments including a circuit module 610B and incorporating features for coupling to first and second circuit elements 650a, 650b, according to some embodiments of the present invention. Portions of the RF transistor amplifier die 210 and circuit module 610B may be substantially similar to those in FIGS. 9A-9D and other previously described figures, and therefore redundant description will be omitted. The embodiments of FIGS. 15A-15D may, for example, incorporate a circuit module 610B that exposes gate lead 682B and / or drain lead pad 684B on the same side 601 (e.g., bottom surface) of the circuit module 610B to which the RF transistor amplifier die 210 is coupled. The RF transistor amplifier embodiments of FIGS. 15A-15D may include an embodiment similar to the embodiment of FIG. 9B, for example, with the addition of spacer 245, first auxiliary spacer 246a, and / or second auxiliary spacer 246b.

[0231] 15A shows RF transistor amplifier die 210 coupled to circuit module 610B, with spacer 245 disposed on bottom surface 210a of RF transistor amplifier die 210. Encapsulating material 625 may leave bottom surface 245a of spacer 245 exposed.

[0232] In some embodiments, the spacer 245 may be formed of an electrically conductive material, such as a metal, and / or a thermally conductive material. In some embodiments, the spacer 245 may be or include, but is not limited to, gold (Au) copper (Cu), a Cu alloy, gold tin (AuSn), and / or epoxy. In some embodiments, the spacer 245 may be or include, but is not limited to, an electrically insulating and / or dielectric material, such as, for example, silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof. In some embodiments, the spacer 245 may be thermally conductive. Thus, the spacer 245 may be configured to dissipate heat transferred from the RF transistor amplifier die 210. In some embodiments, the spacer 245 may perform a similar function as the thermal layer 240 described herein and / or be composed of a similar material. In some embodiments, the spacer 245 may be composed of multiple layers, but is not limited to this. FIG. 15A illustrates an embodiment in which the RF transistor amplifier die 210 is directly bonded to the circuit module 610, but is not limited to this. In some embodiments, the transistor amplifier die 210 may be coupled to the circuit module 610 via a coupling element 270 similar to that shown in Figure 6B. Similarly, in some embodiments, the RF transistor amplifier die 210 may incorporate an on-die RDL, such as the RF transistor amplifier die 210' of Figure 3C.

[0233] FIG. 15B illustrates an embodiment similar to FIG. 15A with the addition of a first auxiliary spacer 246a and a second auxiliary spacer 246b. In some embodiments, the first auxiliary spacer 246a may be formed on and / or in contact with the first circuit element 650a, and the second auxiliary spacer 246b may be formed on and / or in contact with the second circuit element 650b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be formed of an electrically and / or thermally conductive material, such as a metal. In some embodiments, surfaces of the first and / or second auxiliary spacers 246a, 246b may be exposed from the encapsulation material 625. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be or include gold (Au), copper (Cu), a Cu alloy, gold-tin (AuSn), and / or epoxy, although the present invention is not limited thereto. As described herein with respect to other embodiments, the first and / or second auxiliary spacers 246a, 246b may provide a mechanism by which a ground signal is provided to the first and / or second circuit elements 650a, 650b or by which thermal energy is dissipated from the first and / or second circuit elements 650a, 650b.

[0234] In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of a similar material to the spacer 245, although the invention is not limited thereto. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of a different material than the spacer 245. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be electrically disconnected (e.g., separated) from the spacer 245. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of multiple layers, although the invention is not limited thereto.

[0235] Although the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 are shown as separate, individual elements, the invention is not limited thereto. In some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be formed as an integral (e.g., interconnected) spacer layer 245′. Such an embodiment is shown in FIG. 15C , which depicts the RF transistor amplifier die 210 coupled to a circuit module 610B that includes the integral spacer layer 245′. The integral spacer layer 245′ may be similar to that described herein with respect to FIG. 13C . The integral spacer layer 245′ may extend to contact the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210. In some embodiments, the surface 245a of the integral spacer layer 245′ may be exposed from the encapsulation material 625. In some embodiments, the integrated spacer layer 245′ may be formed of the same or similar material as the first auxiliary spacer 246a, the second auxiliary spacer 246b, and / or the spacer 245. In some embodiments, the top surface 245b′ of the integrated spacer layer 245′ may be non-planar or planar. For example, in some embodiments, the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210 may have different heights, and the integrated spacer layer 245′ may be formed to have a top surface 245b′ having portions at the different heights of each of the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210.

[0236] 15D illustrates an embodiment of an RF transistor amplifier device in which the first auxiliary spacer 246a and the second auxiliary spacer 246b are omitted. The RF transistor amplifier die 210 may be coupled to a circuit module 610B similar to FIG. 15A, and therefore, a duplicated description will be omitted. Referring to FIGS. 15A and 15D, a top surface 650a_s of the first circuit element 650a and / or a top surface 650b_s of the second circuit element 650b may be exposed from the encapsulation material 625. The exposure of the surfaces 650a_s, 650b_s of the first and / or second circuit elements 650a, 650b may enable additional external connections to be applied to the first and / or second circuit elements 650a, 650b. For example, a separate electrical connection, such as a ground signal, may be connected to the first and / or second circuit elements 650a, 650b via the respective exposed surfaces 650a_s, 650b_s.

[0237] The RF transistor amplifier device of FIG. 15D may be formed, for example, by building the RF transistor amplifier device of FIG. 15A and then performing a planarization operation on portions of the encapsulation material 625 to expose surfaces 650a_s, 650b_s of the first and / or second circuit elements 650a, 650b.

[0238] The RF transistor amplifier device shown in Figures 15A-15D can be utilized in multiple packaging configurations. Figures 16A-16D illustrate the use of packaging similar to that described herein with respect to Figures 10A, 10B, and 14A-14D. For example, the circuit module 610B and RF transistor amplifier die 210 may be disposed within open-cavity semiconductor packages 1600a_1, 1600a_2 (Figures 16A, 16B) or OMP packages 1600b_1, 1600b_2 (Figures 16C, 16D). In some embodiments, the spacer layer 245 can be utilized with first and second auxiliary spacers 246a, 246b within the open-cavity semiconductor package 1600a_1 (Figure 16A) or OMP package 1600b_1 (Figure 16C). In some embodiments, the integrated spacer layer 245′ can be utilized with the open cavity semiconductor package 1600a_2 ( FIG. 16B ) or the OMP package 1600b_2 ( FIG. 16D ). Elements in FIGS. 16A-16D of the semiconductor packages 1600a_1, 1600a_2, 1600b_1, and 1600b_2 similar to those described above with respect to other figures, such as FIGS. 10A and 10B , will not be further described for brevity. In some embodiments, the semiconductor packages 1600a_1, 1600a_2, 1600b_1, and 1600b_2 can house RF transistor amplifier devices with gate lead pads 682B and drain lead pads 684B exposed on the underside of the circuit module 610B. While in Figures 16A-16D the RF transistor amplifier die 210 is shown as being directly coupled to the circuit modules 610B in the semiconductor packages 1600a_1, 1600a_2, 1600b_1, and 1600b_2, it will be appreciated that the RF transistor amplifier die 210 may, mutatis mutandis, be coupled to the circuit modules via coupling elements 270 or utilizing on-die RDLs.

[0239] 16A and 16C, the first and second auxiliary spacers 246a, 246b can be connected to and / or directly contact the carrier substrate 410. In this manner, the first and second auxiliary spacers 246a, 246b can be configured to dissipate heat from the first and second circuit elements 650a, 650b and / or provide electrical signals (e.g., ground signals). Depending on the electrical and thermal requirements of the first and second circuit elements 650a, 650b, additional terminal / junction / spacer structures can be utilized with at least one of the first and second circuit elements 650a, 650b to provide electrical, thermal, and / or mechanical interfaces between one or more of the at least one of the first and second circuit elements 650a, 650b and the substrate 410.

[0240] 16B and 16D , the first and second auxiliary spacers 246a, 246b can be replaced with an integral spacer layer 245′ coupled to the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210. The integral spacer layer 245′ can be connected to and / or directly contact the carrier substrate 410. The integral spacer layer 245′ can have a flat or non-flat upper surface. In some embodiments, an additional layer (e.g., an additional spacer layer) can be disposed between the first and second circuit elements 650a, 650b and the integral spacer layer 245′ or between the integral spacer layer 245′ and the carrier substrate 410, respectively.

[0241] The embodiments described herein provide improved RF transistor amplifiers and improved packaging incorporating such RF transistor amplifiers. By avoiding and / or reducing the use of backside vias, some embodiments of the present invention provide improved thermal management of power amplifiers. Furthermore, by locating the power amplifier contacts on the same side of the device, interconnects and circuit modules can be utilized, reducing the need for wire bonding. As a result, RF transistor amplifiers and associated packages can exhibit improved performance and thermal characteristics over conventional devices. Advantages of direct bonding provided by embodiments of the present invention include reduced form factor, lower electrical resistance, and improved communication speeds.

[0242] Various embodiments are described herein with reference to the accompanying drawings, in which exemplary embodiments are shown. However, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Various modifications to the exemplary embodiments and general principles and features described herein will be readily apparent. In the drawings, the sizes and relative sizes of layers and regions are not shown to scale and, in some cases, may be exaggerated for clarity.

[0243] Although terms such as "first," "second," etc. may be used herein to describe various elements, it will be understood that these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0244] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprise," "comprising," "include," and / or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0245] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this invention belongs. Terms used herein should be interpreted to have a meaning consistent with their meaning in the context of the present specification and related art, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0246] When an element, such as a layer, region, or substrate, is referred to as being "on," "attached to," or extending "over" another element, it is understood that the element can be directly on the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on," or "directly attached to," or extending "directly onto," another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it is also understood that the element can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, there are no intervening elements present.

[0247] Relative terms such as "below" or "above" or "top" or "lower" or "horizontal" or "lateral" or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0248] Embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Elements shown in dotted lines may be optional in the illustrated embodiment.

[0249] Like numbers refer to like elements throughout, and therefore, same or similar numbers may be described with reference to other drawings even if not otherwise mentioned or described in the corresponding drawing, and unnumbered elements may be described with reference to other drawings.

[0250] In the drawings and specification, exemplary embodiments of the invention are disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

[0251] The present invention may alternatively or additionally include the following features. [Item 1] 1. A transistor amplifier, comprising: a III-nitride based amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die; an interconnect structure on the first surface of the amplifier die electrically coupled to the gate terminal, the drain terminal, and the source terminal of the amplifier die and electrically coupled to the input path and the output path of the transistor amplifier; A transistor amplifier comprising: [Item 2] Item 1. The transistor amplifier of item 1, wherein the interconnect structure comprises a redistribution layer on the first surface of the amplifier die and a circuit module electrically coupled to gate, drain, and source connections on the redistribution layer. [Item 3] Item 3. The transistor amplifier of item 2, wherein the circuit module comprises a circuit including at least a portion of a harmonic termination circuit, a matching circuit, a dividing circuit, a combining circuit, and / or a bias circuit. [Item 4] an input connection; an output connection; a ground connection; a circuit module including a gate connection electrically joined to the input connection, a drain connection coupled to the output connection, and a source connection coupled to the ground connection; Item 1. The transistor amplifier of item 1, further comprising: [Item 5] the amplifier die further comprising a second surface opposite the first surface; the transistor amplifier further comprising a carrier substrate; the amplifier die is thermally coupled to the carrier substrate on a second surface of the amplifier die; Item 1 to 4: A transistor amplifier according to any one of items 1 to 4. [Item 6] Item 6. The transistor amplifier of item 5, wherein the carrier substrate comprises a metal. [Item 7] the interconnect structure comprises a circuit module including a first side adjacent to the first surface of the amplifier die and a second side opposite the first side; the input path includes an input metal lead, and the output path includes an output metal lead; the input metal lead and the output metal lead are electrically joined at the first side or the second side of the circuit module; Item 1. The transistor amplifier according to item 1. [Item 8] Item 8. The transistor amplifier of item 7, wherein the circuit element is on the second side and / or the first side of the circuit module. [Item 9] 9. The transistor amplifier of item 7 or 8, wherein the circuit elements are formed in a circuit module. [Item 10] 10. The transistor amplifier of any one of items 1 to 9, wherein the transistor amplifier is at least partially encapsulated. [Item 11] 11. The transistor amplifier according to any one of items 1 to 10, wherein the operating frequency of the transistor amplifier is 500 MHz to 75 GHz. [Item 12] a semiconductor layer structure including a first major surface; a plurality of unit cell transistors on the first major surface electrically connected in parallel, the unit cell transistors including respective gate fingers coupled to the gate manifold, respective drain fingers coupled to the drain manifold, and respective source fingers; bonding elements on the first major surface, the bonding elements including gate connection pads connected to the gate manifold, drain connection pads connected to the drain manifold, and source connection pads connected to respective source fingers; 1. A radio frequency ("RF") transistor amplifier comprising: [Item 13] a unit cell transistor extending in a first direction within the semiconductor layer structure; the gate connection pad, the drain connection pad, and the source connection pad of the coupling element extend in a second direction intersecting the first direction; Item 13. The RF transistor amplifier according to item 12. [Item 14] Item 14. The RF transistor amplifier of item 12 or 13, wherein the coupling element is further configured to be coupled to an input matching circuit and / or an output matching circuit. [Item 15] 15. The RF transistor amplifier of any one of items 12 to 14, wherein the coupling element comprises a fan-out via structure. [Item 16] the semiconductor layer structure further comprising a second major surface; the RF transistor amplifier further comprises a carrier substrate on the second major surface of the semiconductor layer structure; 16. An RF transistor amplifier according to any one of items 12 to 15. [Item 17] Item 17. The RF transistor amplifier of item 16, further comprising a thermally conductive layer on the second major surface of the semiconductor layer structure between the semiconductor layer structure and the carrier substrate. [Item 18] Item 13. The RF transistor amplifier of item 12, further comprising a circuit module on the coupling element, such that the coupling element is between the circuit module and the semiconductor layer structure. [Item 19] Item 19. The RF transistor amplifier of item 18, wherein the circuit module comprises an input matching circuit and / or an output matching circuit. [Item 20] 20. The RF transistor amplifier of claim 18 or 19, wherein the circuit module comprises a ground plane. [Item 21] 21. The RF transistor amplifier of any one of items 18 to 20, wherein the circuit module comprises a first side surface adjacent to a first main surface of the amplifier die and a second side surface opposite the first side surface. [Item 22] 22. The RF transistor amplifier of claim 21, wherein the circuit elements are on the second side and / or the first side of the circuit module. [Item 23] 23. The RF transistor amplifier of claim 21 or 22, wherein the circuit elements are formed in a circuit module. [Item 24] 24. The RF transistor amplifier according to any one of items 21 to 23, wherein the circuit module comprises an impedance matching circuit and / or a harmonic termination circuit. [Item 25] the semiconductor layer structure further comprising a second major surface; the semiconductor layer structure does not have vias on the second major surface; Item 13. The RF transistor amplifier according to item 12. [Item 26] 26. The RF transistor amplifier of any one of items 12 to 25, wherein the semiconductor layer structure further comprises a Group III nitride. [Item 27] 27. The RF transistor amplifier of any one of items 12 to 26, wherein the semiconductor layer structure further comprises a silicon and / or silicon carbide substrate. [Item 28] 28. The RF transistor amplifier of any one of items 12 to 27, wherein the semiconductor layer structure further comprises a high electron mobility transistor (HEMT) or a laterally diffused metal oxide semiconductor (LDMOS) transistor. [Item 29] 1. A radio frequency (“RF”) transistor amplifier, comprising: an RF transistor amplifier die having a first major surface, the RF transistor amplifier die including a gate terminal, a drain terminal, and a source terminal on the first major surface; a circuit module on a first major surface of the RF transistor amplifier die, the circuit module including a gate lead connection pad electrically coupled to the gate terminal and a drain lead connection pad electrically coupled to the drain terminal; an input lead extending from outside the RF transistor amplifier and electrically coupled to the gate lead connection pad; an output lead extending from outside the RF transistor amplifier and electrically coupled to the drain lead connection pad; 1. A radio frequency ("RF") transistor amplifier comprising: [Item 30] a circuit module having a first side adjacent to the first major surface of the RF transistor amplifier die and a second side opposite the first side; the circuit module comprises one or more circuit elements coupled between the gate terminal and the input lead and / or between the drain terminal and the output lead; Item 30. The RF transistor amplifier of item 29. [Item 31] Item 31. The RF transistor amplifier of item 30, wherein one or more circuit elements are mounted on the first side and / or the second side of the circuit module. [Item 32] 32. The RF transistor amplifier of claim 30 or 31, wherein the one or more circuit elements are formed in a circuit module. [Item 33] 33. The RF transistor amplifier of any one of items 30 to 32, wherein the input leads and / or output leads are coupled to a second side of the circuit module. [Item 34] 33. The RF transistor amplifier of any one of items 30 to 32, wherein the input leads and / or output leads are coupled to a first side of the circuit module. [Item 35] 35. The RF transistor amplifier of any one of items 29 to 34, further comprising a coupling element between the amplifier die and the circuit module. [Item 36] a coupling element between the RF transistor amplifier die and the circuit module, the coupling element having a bottom surface adjacent to the first major surface of the RF transistor amplifier die and a top surface opposite the bottom surface; 30. The RF transistor amplifier of claim 29, wherein the top surface of the coupling element comprises a gate connection pad configured to be connected to a first interconnect pad of the circuit module, a drain connection pad configured to be connected to a second interconnect pad of the circuit module, and a source connection pad configured to be connected to a third interconnect pad of the circuit module. [Item 37] 37. The RF transistor amplifier of claim 29, wherein the RF transistor amplifier die comprises a plurality of unit cell transistors on a first major surface electrically connected in parallel, each unit cell transistor extending in a first direction and comprising a gate finger coupled to the gate manifold, a drain finger coupled to the drain manifold, and a source finger on an opposite side of the gate finger from the drain finger. [Item 38] the RF transistor amplifier die further comprising a second major surface; the RF transistor amplifier further comprising a carrier substrate on a second major surface of the RF transistor amplifier die; Item 38. An RF transistor amplifier according to any one of Items 29 to 37. [Item 39] Item 39. The RF transistor amplifier of item 38, further comprising a thermally conductive layer on the second major surface of the RF transistor amplifier die between the RF transistor amplifier die and the carrier substrate. [Item 40] Further comprising a sidewall and a lid; the carrier substrate, the sidewalls, and the lid define an interior cavity; an RF transistor amplifier die located within the internal cavity; Item 39. An RF transistor amplifier according to any one of Items 29 to 39. [Item 41] 40. The RF transistor amplifier of any one of items 29 to 39, further comprising an overmolding material on the circuit module and the RF transistor amplifier die. [Item 42] 42. The RF transistor amplifier according to any one of items 29 to 41, wherein the circuit module comprises an input matching circuit and / or an output matching circuit. [Item 43] the RF transistor amplifier die is a first RF transistor amplifier die, the gate terminal is a first gate terminal, the drain terminal is a first drain terminal, and the source terminal is a first source terminal; the RF transistor amplifier further comprises a second RF transistor amplifier die including a second gate terminal, a second drain terminal, and a second source terminal; a circuit module electrically coupled to the second gate terminal, the second drain terminal, and the second source terminal; 43. The RF transistor amplifier according to any one of items 29 to 42. [Item 44] 44. The RF transistor amplifier of any one of items 29 to 43, wherein the RF transistor amplifier die is a III-nitride based RF transistor amplifier die. [Item 45] 45. The RF transistor amplifier of any one of items 29 to 44, wherein the RF transistor amplifier die comprises a high electron mobility transistor (HEMT) or a laterally diffused metal oxide semiconductor (LDMOS) transistor. [Item 46] 46. ​​The RF transistor amplifier according to any one of items 29 to 45, wherein the operating frequency of the RF transistor amplifier is in the R-band, the S-band, the X-band, the Ku-band, the K-band, the Ka-band, and / or the V-band. [Item 47] a semiconductor layer structure including first and second major surfaces; a plurality of unit cell transistors on the first major surface electrically connected in parallel, each unit cell transistor including a gate finger coupled to the gate manifold, a drain finger coupled to the drain manifold, and a source finger; wherein the semiconductor layer structure does not include vias to source fingers on the second major surface. Radio frequency ("RF") transistor amplifier. [Item 48] Item 48. The RF transistor amplifier of item 47, further comprising a coupling element on the first major surface, the coupling element comprising a gate connection pad configured to be connected to the gate manifold, a drain connection pad configured to be connected to the drain manifold, and a source connection pad configured to be connected to each of the source fingers. [Item 49] Item 49. The RF transistor amplifier of item 47 or item 48, further comprising a carrier substrate on the second major surface of the semiconductor layer structure. [Item 50] Item 50. The RF transistor amplifier of item 49, further comprising a thermally conductive layer on the second major surface of the semiconductor layer structure between the semiconductor layer structure and the carrier substrate. [Item 51] Item 49. The RF transistor amplifier of item 48, further comprising a circuit module on the semiconductor layer structure, the circuit module comprising a gate lead connection pad electrically coupled to the gate manifold and a drain lead connection pad electrically coupled to the drain manifold. [Item 52] an input lead electrically coupled to the gate lead connection pad, the input lead configured to extend externally from a package containing the RF transistor amplifier; an output lead electrically coupled to the drain lead connection pad, the output lead configured to extend externally from a package containing the RF transistor amplifier; Item 52. The RF transistor amplifier of item 51, further comprising: [Item 53] 53. The RF transistor amplifier of any one of items 47 to 52, wherein the semiconductor layer structure further comprises a high electron mobility transistor (HEMT) or a laterally diffused metal oxide semiconductor (LDMOS) transistor. [Item 54] 1. A transistor amplifier, comprising: a transistor amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the transistor amplifier die; an input lead extending from the exterior of the transistor amplifier and electrically coupled to the gate terminal; an output lead extending from the exterior of the transistor amplifier and electrically coupled to the drain terminal; Equipped with a first electrical path from the input lead to the gate terminal does not include a bond wire; the second electrical path from the output lead to the drain terminal does not include a bond wire; Transistor amplifier. [Item 55] a circuit module electrically coupled between the input lead and the gate terminal; a circuit module on the first surface of the transistor amplifier die; Item 55. A transistor amplifier according to item 54. [Item 56] Item 56. The transistor amplifier of item 55, further comprising a coupling element electrically coupled between the circuit module and the gate terminal. [Item 57] Item 57. The transistor amplifier of item 56, further comprising a bonding layer between the coupling element and the circuit module. [Item 58] Item 58. The transistor amplifier of item 57, wherein the bonding layer comprises solder. [Item 59] 57. The transistor amplifier of claim 55 or 56, further comprising a bonding layer between the input lead and the circuit module. [Item 60] 60. The transistor amplifier of any one of items 55 to 59, further comprising a circuit element electrically coupled to the circuit module. [Item 61] Item 61. The transistor amplifier of item 60, wherein the circuit elements are on a side of the circuit module opposite the transistor amplifier die. [Item 62] an RF transistor amplifier die comprising a plurality of unit cell transistors electrically connected in parallel, each unit cell transistor comprising a respective gate finger coupled to a gate manifold, a respective drain finger coupled to a drain manifold, and a respective source finger; a gate terminal electrically coupled to the gate manifold; a drain terminal electrically coupled to the gate manifold; Item 62. A transistor amplifier according to any one of Items 54 to 61. [Item 63] Item 63. The transistor amplifier of item 62, further comprising a plurality of conductive patterns between the gate manifold and the gate terminal. [Item 64] 64. The transistor amplifier of any one of items 54 to 63, further comprising a carrier substrate, the carrier substrate being on a second surface of the transistor amplifier die. [Item 65] 1. A transistor amplifier, comprising: a III-nitride based amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die; a circuit module on the first surface of the amplifier die and electrically coupled to the gate, drain, and source terminals of the amplifier die, the circuit module including one or more circuit elements coupled between the gate terminal and a first lead of the transistor amplifier and / or between the drain terminal and a second lead of the transistor amplifier; Equipped with a circuit module having a first surface and a second surface opposite the first surface of the circuit module, the first surface of the circuit module being adjacent to the first surface of the amplifier die; Transistor amplifier. [Item 66] Item 66. The transistor amplifier of item 65, wherein one or more circuit elements are mounted on the first surface and / or the second surface of the circuit module. [Item 67] Item 67. The transistor amplifier of item 65 or item 66, wherein one or more circuit elements are formed within a circuit module. [Item 68] Item 68. The transistor amplifier of any one of items 65 to 67, wherein the first lead and / or the second lead is coupled to the second surface of the circuit module. [Item 69] Item 68. The transistor amplifier of any one of items 65 to 67, wherein the first lead and / or the second lead is coupled to the first surface of the circuit module. [Item 70] a circuit module comprising first and second interconnect pads on a first surface of the circuit module; a first interconnect pad configured to be coupled to a gate terminal of the amplifier die; a second interconnect pad configured to be coupled to a drain terminal of the amplifier die; Item 69. A transistor amplifier according to any one of Items 65 to 69. [Item 71] Item 71. The transistor amplifier of item 70, wherein the circuit module comprises a third interconnect pad on a first surface of the circuit module configured to be coupled to a source terminal of the amplifier die. [Item 72] 72. The transistor amplifier of any one of items 65 to 71, further comprising a coupling element between the amplifier die and the circuit module. [Item 73] a semiconductor layer structure including first and second major surfaces; a plurality of unit cell transistors on the first major surface electrically connected in parallel, each unit cell transistor including a gate finger coupled to the gate manifold, a drain finger coupled to the drain manifold, and a source finger; wherein the semiconductor layer structure does not include vias to source fingers on the second major surface. Radio frequency ("RF") transistor amplifier. [Item 74] Item 74. The RF transistor amplifier of item 73, further comprising a coupling element on the first major surface, the coupling element comprising a gate connection pad configured to be connected to the gate manifold, a drain connection pad configured to be connected to the drain manifold, and a source connection pad configured to be connected to each of the source fingers. [Item 75] 75. The RF transistor amplifier of claim 73 or 74, further comprising a carrier substrate on the second major surface of the semiconductor layer structure. [Item 76] Item 76. The RF transistor amplifier of item 75, further comprising a thermally conductive layer and / or an electrically conductive layer on the second major surface of the semiconductor layer structure between the semiconductor layer structure and the carrier substrate. [Item 77] 75. The RF transistor amplifier of claim 73 or 74, further comprising a circuit module on the semiconductor layer structure, the circuit module comprising a gate lead connection pad electrically coupled to the gate manifold and a drain lead connection pad electrically coupled to the drain manifold. [Item 78] an input lead electrically coupled to the gate lead connection pad, the input lead configured to extend externally from a package containing the RF transistor amplifier; an output lead electrically coupled to the drain lead connection pad, the output lead configured to extend externally from a package containing the RF transistor amplifier; Item 78. The RF transistor amplifier of item 77, further comprising: [Item 79] Item 78. The RF transistor amplifier of item 77, further comprising one or more circuit elements attached to the first side and / or the second side of the circuit module. [Item 80] 80. The RF transistor amplifier of claim 79, further comprising a thermally and / or electrically conductive auxiliary spacer layer on one or more circuit elements. [Item 81] 81. The RF transistor amplifier of any one of items 73 to 80, wherein the semiconductor layer structure further comprises a high electron mobility transistor (HEMT) or a laterally diffused metal oxide semiconductor (LDMOS) transistor. [Item 82] 1. A transistor amplifier, comprising: a III-nitride based amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die; a circuit module located on the first surface of the amplifier die and electrically coupled to the gate, drain, and source terminals of the amplifier die on the first surface of the amplifier die; Equipped with a circuit module including one or more circuit elements coupled between a gate terminal and a first lead of the transistor amplifier and / or between a drain terminal and a second lead of the transistor amplifier; a circuit module having a first surface and a second surface opposite the first surface of the circuit module; a first surface of the circuit module adjacent to a first surface of the amplifier die; Transistor amplifier. [Item 83] Item 83. The transistor amplifier of item 82, wherein one or more circuit elements are mounted on the first surface and / or the second surface of the circuit module. [Item 84] Item 84. The transistor amplifier of item 82 or item 83, further comprising a thermally and / or electrically conductive auxiliary spacer layer on one or more circuit elements. [Item 85] 85. A transistor amplifier according to any one of items 82 to 84, wherein one or more circuit elements are formed within a circuit module. [Item 86] 86. A transistor amplifier according to any one of items 82 to 85, wherein the first lead and / or the second lead is coupled to the second surface of the circuit module. [Item 87] 86. A transistor amplifier according to any one of items 82 to 85, wherein the first lead and / or the second lead is coupled to the first surface of the circuit module. [Item 88] a circuit module comprising first and second interconnect pads on a first surface of the circuit module; a first interconnect pad configured to be coupled to a gate terminal of the amplifier die; a second interconnect pad configured to be coupled to a drain terminal of the amplifier die; 88. A transistor amplifier according to any one of items 82 to 87. [Item 89] Item 89. The transistor amplifier of item 88, wherein the circuit module comprises a third interconnect pad on a first surface of the circuit module configured to be coupled to a source terminal of the amplifier die. [Item 90] 90. The transistor amplifier of any one of items 82 to 89, further comprising a coupling element between the amplifier die and the circuit module. [Item 91] an RF transistor amplifier die having a first major surface and a second major surface, the RF transistor amplifier die including a gate terminal, a drain terminal, and a source terminal on the first major surface; a circuit module on a first major surface of the RF transistor amplifier die, the circuit module including a gate lead connection pad electrically coupled to the gate terminal and a drain lead connection pad electrically coupled to the drain terminal; a carrier substrate on a second major surface of the RF transistor amplifier die; a thermally and / or electrically conductive spacer layer between the RF transistor amplifier die and the carrier substrate; 1. A radio frequency ("RF") transistor amplifier comprising: [Item 92] a circuit module having a first side adjacent to the first major surface of the RF transistor amplifier die and a second side opposite the first side; the circuit module comprises one or more circuit elements coupled to the gate terminal and / or the drain terminal; Item 92. The RF transistor amplifier of item 91. [Item 93] Item 93. The RF transistor amplifier of item 92, wherein one or more circuit elements are mounted on the first side and / or the second side of the circuit module. [Item 94] Item 94. The RF transistor amplifier of item 92 or item 93, further comprising a thermally and / or electrically conductive auxiliary spacer layer on one or more circuit elements. [Item 95] Item 95. The RF transistor amplifier of item 94, wherein the spacer layer and the auxiliary spacer layer form an integral spacer layer. [Item 96] Item 96. The RF transistor amplifier of any one of items 91 to 95, further comprising an input lead and / or an output lead coupled to a second side of the circuit module. [Item 97] a coupling element between the RF transistor amplifier die and the circuit module, the coupling element having a bottom surface adjacent to the first major surface of the RF transistor amplifier die and a top surface opposite the bottom surface; 97. The RF transistor amplifier of any one of claims 91 to 96, wherein the top surface of the coupling element comprises a gate connection pad configured to be connected to a first interconnect pad of the circuit module, a drain connection pad configured to be connected to a second interconnect pad of the circuit module, and a source connection pad configured to be connected to a third interconnect pad of the circuit module. [Item 98] Further comprising a sidewall and a lid; the carrier substrate, the sidewalls, and the lid define an interior cavity; an RF transistor amplifier die located within the internal cavity; 98. An RF transistor amplifier according to any one of items 91 to 97. [Item 99] 98. The RF transistor amplifier of any one of items 91 to 97, further comprising an overmolding material over the circuit module and the RF transistor amplifier die. [Item 100] 99. The RF transistor amplifier of any one of claims 91 to 99, wherein the RF transistor amplifier die is a III-nitride based RF transistor amplifier die. [Item 101] 101. The RF transistor amplifier of any one of items 91 to 100, wherein the operating frequency of the RF transistor amplifier is in the R-band, the S-band, the X-band, the Ku-band, the K-band, the Ka-band, and / or the V-band.

Claims

1. 1. A transistor device comprising: a transistor die having a gate terminal, a drain terminal, and a source terminal; a circuit module disposed on the transistor die, the circuit module electrically coupled to the gate terminal, the drain terminal, and / or the source terminal via interconnect pads exposed on a first surface or a second surface of the circuit module; one or more passive electrical components disposed on the first surface of the circuit module; the one or more passive electrical components are electrically coupled between the gate terminal and a first lead of the transistor device and / or between the drain terminal and a second lead of the transistor device via connection pads exposed on the first surface of the circuit module; the circuit module includes a conductive pattern that electrically connects the connection pads exposed on the first surface to the interconnection pads and to each of the first and second leads exposed on the second surface of the circuit module.

2. The transistor device of claim 1 , wherein the transistor die is disposed on the first surface of the circuit module adjacent to the one or more passive electrical components.

3. The transistor device of claim 1 , wherein the transistor die is disposed on a second surface of the circuit module opposite the first surface.

4. The transistor device of claim 1 , wherein the one or more passive electrical components comprise surface-mounted and / or integrated passive devices.

5. The transistor device of claim 4 , wherein the one or more passive electrical components include a plurality of conductive pads, the plurality of conductive pads being aligned with and electrically coupled to the connection pads of the circuit module.

6. 10. The transistor device of claim 1, wherein the gate, drain, and source terminals comprise conductive pillar structures adjacent the first surface of the transistor die and facing the circuit module.

7. a coupling element disposed between the first surface of the transistor die and the circuit module; The transistor device of claim 6 , wherein the coupling element comprises a redistribution layer structure including a conductive coupling pattern electrically coupled to the gate terminal, the drain terminal, and the source terminal.

8. The transistor device of claim 6 , further comprising a thermally conductive flange disposed on a second surface of the transistor die facing the circuit module.

9. the transistor die is disposed on a second surface of the circuit module opposite the first surface; a mechanical support structure disposed on the second surface of the circuit module adjacent to the transistor die, the mechanical support structure being between the thermally conductive flange and the second surface of the circuit module; 9. The transistor device of claim 8, wherein an interface between the second surface of the transistor die and the thermally conductive flange provides a first thermal conduction path, and the mechanical support structure provides a second thermal conduction path between the thermally conductive flange and the second surface of the circuit module.

10. further comprising a sidewall and a lid; the thermally conductive flange, the sidewall, and the lid define an interior cavity; The transistor device of claim 8 , wherein the transistor die and the circuit module are within the internal cavity.

11. The transistor device of claim 8 , further comprising an overmold material over the circuit module, the transistor die, and the thermally conductive flange.

12. 2. The transistor device of claim 1, wherein the first lead and / or the second lead is coupled to one of the first surface of the circuit module and a second surface of the circuit module opposite the first surface.

13. 1. A transistor device comprising: a transistor die having a gate terminal, a drain terminal, and a source terminal; a passive component assembly electrically coupled to the gate terminal, the drain terminal, and / or the source terminal, the passive component assembly including one or more passive electrical components on a first surface of the passive component assembly, the one or more passive electrical components electrically coupled to connection pads exposed on the first surface; the transistor die is disposed on a second surface of the passive component assembly opposite the first surface, the gate terminal, the drain terminal, and the source terminal being electrically coupled to interconnect pads exposed on the second surface; the passive component assembly includes a conductive pattern electrically connecting the connection pads exposed on the first surface to the interconnect pads exposed on the second surface and to at least one lead of the transistor device exposed on the second surface.

14. 14. The transistor device of claim 13, wherein the one or more passive electrical components are electrically coupled between the gate terminal and a first lead of the transistor device and / or between the drain terminal and a second lead of the transistor device.

15. 14. The transistor device of claim 13, wherein the one or more passive electrical components comprise surface-mounted devices and / or integrated passive devices, and the interconnect pads exposed on the second surface of the passive component assembly are configured to allow the one or more passive electrical components to be replaceable.

16. 14. The transistor device of claim 13, wherein the passive component assembly has a multi-layer structure including conductive traces and / or vias electrically coupled to the one or more passive electrical components at the first surface of the passive component assembly and coupled to the gate terminal, the drain terminal, and / or the source terminal of the transistor die at the second surface of the passive component assembly.

17. 17. The transistor device of claim 16, wherein the gate terminal, the drain terminal, and the source terminal comprise conductive pillar structures adjacent a first surface of the transistor die and facing the second surface of the passive component assembly.

18. 20. The transistor device of claim 17, further comprising a bonding element disposed between the first surface of the transistor die and the second surface of the passive component assembly, the bonding element comprising a redistribution layer structure including a conductive bonding pattern electrically coupled to the conductive pillar structure.

19. 20. The transistor device of claim 17, further comprising a thermally conductive flange disposed on a second surface of the transistor die opposite the second surface of the passive component assembly.

20. 20. The transistor device of claim 19, further comprising a mechanical support structure adjacent the transistor die and extending between the thermally conductive flange and the second surface of the passive component assembly.

21. Further comprising a sidewall and a lid; The thermally conductive flange, the sidewall, and the lid define an interior cavity.

20. The transistor device of claim 19, wherein the transistor die and the passive component assembly are within the internal cavity.

22. A transistor device a transistor die having a gate terminal, a drain terminal, and a source terminal; a passive component assembly electrically coupled to the gate terminal, the drain terminal, and / or the source terminal, the passive component assembly including one or more passive electrical components on a first surface of the passive component assembly, the one or more passive electrical components electrically coupled to connection pads exposed on the first surface. the transistor die is disposed on a first surface of the passive component assembly adjacent to the one or more passive electrical components, and the gate terminal, the drain terminal, and / or the source terminal are electrically coupled to interconnect pads exposed on the first surface; The passive component assembly includes a conductive pattern electrically connecting the connection pad to the interconnect pad exposed on the first surface and to at least one lead of the transistor device exposed on the second surface.

23. 23. The transistor device of claim 22, wherein the one or more passive electrical components are electrically coupled between the gate terminal and a first lead of the transistor device and / or between the drain terminal and a second lead of the transistor device.

24. 23. The transistor device of claim 22, wherein the one or more passive electrical components comprise surface-mounted devices and / or integrated passive devices, and the interconnect pads exposed on the first surface of the passive component assembly are configured to allow the one or more passive electrical components to be replaceable.

25. 23. The transistor device of claim 22, wherein the passive component assembly has a multi-layer structure including conductive traces and / or vias that are electrically coupled to the one or more passive electrical components at the first surface of the passive component assembly and are coupled to the gate terminal, the drain terminal, and / or the source terminal of the transistor die at the first surface of the passive component assembly.

26. 26. The transistor device of claim 25, wherein the gate terminal, the drain terminal, and the source terminal comprise conductive pillar structures adjacent a first surface of the transistor die and facing the first surface of the passive component assembly.

27. 27. The transistor device of claim 26, further comprising a bonding element disposed between the first surface of the transistor die and the first surface of the passive component assembly, the bonding element comprising a redistribution layer structure including a conductive bonding pattern electrically coupled to the conductive pillar structure.

28. 27. The transistor device of claim 26, further comprising a thermally conductive flange disposed on a second surface of the transistor die opposite the first surface of the passive component assembly.

29. The transistor device of claim 1 , wherein the transistor die comprises a high electron mobility transistor (HEMT) or a laterally diffused metal oxide semiconductor (LDMOS) transistor.

30. The transistor device of claim 1 , wherein the transistor die is a Group III-nitride based RF transistor amplifier die.

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