Semiconductor Devices

Abstract

This semiconductor device includes: a semiconductor chip which has a main surface; a device region which is partitioned off on the main surface; a differential amplifier which is formed in the device region and which amplifies and then outputs a differential signal that has been input; an insulating layer which is provided on the main surface so as to cover the device region; and a shielding electrode which is incorporated in the insulating layer so as to cover the device region in a view from above and which is fixed to the ground potential.

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device to which a differential signal is input. [Background technology]

[0002] Patent Document 1 discloses a differential amplifier circuit having a cascode-type class AB control terminal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-94533 Summary of the Invention [Problem to be solved by the invention]

[0004] Semiconductor devices that receive differential signals are required to have excellent EMI (electromagnetic interference) resistance in order to suppress noise, malfunctions, etc. caused by external electromagnetic waves. Examples of external electromagnetic waves include electromagnetic interference signals such as RF (radio frequency) signals outside the operating frequency band.

[0005] An embodiment of the present invention provides a semiconductor device that can improve EMI resistance in a structure in which a differential signal is input. [Means for solving the problem]

[0006] One embodiment of the present invention provides a semiconductor device including a semiconductor chip having a main surface, a device region defined on the main surface, a differential amplifier formed in the device region and amplifying and outputting an input differential signal, and a shield electrode disposed on the main surface so as to conceal the device region in a plan view, the shield electrode being fixed to ground potential. This semiconductor device can improve EMI immunity.

[0007] One embodiment of the present invention provides a semiconductor device including a semiconductor chip having a main surface, a constant current region defined on the main surface, an input region defined on the main surface, a constant current circuit formed in the constant current region and generating a constant current, a differential circuit formed in the input region and electrically connected to the constant current circuit and converting an input differential signal into a differential current, and a shield electrode disposed on the main surface so as to conceal at least one of the input region and the constant current region in a plan view, the shield electrode being fixed to ground potential. This semiconductor device can improve EMI resistance.

[0008] The above and other objects, features and advantages of the present invention will become apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view showing a semiconductor package incorporating a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a diagram showing the electrical structure of the semiconductor package shown in FIG. 1 using circuit symbols. [Figure 3] FIG. 3 is a plan view showing the internal structure of the semiconductor package shown in FIG. [Figure 4] FIG. 4 is an electric circuit diagram showing the electrical structure of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a plan view showing, in block diagram form, the layout of the internal structure of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a plan view in which a shield electrode is added to the layout shown in FIG. [Figure 8A] 8A is an enlarged plan view of a main part of the shield electrode shown in FIG. [Figure 8B] 8B is an enlarged plan view of a main part of the shield electrode shown in FIG. [Figure 9]FIG. 9 is a plan view corresponding to FIG. 7, and is a plan view for explaining the structure of a semiconductor device according to a second embodiment of the present invention. [Figure 10] FIG. 10 is a perspective view showing a semiconductor package incorporating a semiconductor device according to the third embodiment of the present invention. [Figure 11] FIG. 11 is a diagram showing the electrical structure of the semiconductor package shown in FIG. 10 using circuit symbols. [Figure 12] FIG. 12 is a plan view showing the internal structure of the semiconductor package shown in FIG. [Figure 13] FIG. 13 is an electric circuit diagram showing the electrical structure of the semiconductor device shown in FIG. [Figure 14] FIG. 14 is a plan view showing, in block form, the layout of the internal structure of the semiconductor device shown in FIG. [Figure 15] FIG. 15 is a schematic cross-sectional view of the semiconductor device shown in FIG. [Figure 16] FIG. 16 is a plan view in which a shield electrode is added to the layout shown in FIG. [Figure 17] FIG. 17 is a plan view corresponding to FIG. 16 and is a plan view for explaining the structure of the semiconductor device according to the fourth embodiment of the present invention. [Figure 18] FIG. 18 is a cross-sectional view showing a modification of the semiconductor package shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Fig. 1 is a perspective view showing a semiconductor package 2 incorporating a semiconductor device 1 according to a first embodiment of the present invention. Fig. 2 is a diagram showing the semiconductor package 2 shown in Fig. 1 using circuit symbols. Fig. 3 is a plan view showing the internal structure of the semiconductor package 2 shown in Fig. 1.

[0011] 1 to 3, in this embodiment, the semiconductor package 2 is a five-terminal small outline package (SOP). The semiconductor package 2 is not limited to an SOP, and may be a quad for non-lead package (QFN), a dual flat package (DFP), a dual inline package (DIP), a quad flat package (QFP), a single inline package (SIP), a small outline J-leaded package (SOJ), or various similar packages.

[0012] The semiconductor package 2 includes a package body 3. The package body 3 is made of molded resin (e.g., epoxy resin) and is molded into a rectangular parallelepiped shape. The package body 3 has a mounting surface 4 on one side, a non-mounting surface 5 on the other side, and first to fourth side walls 6A to 6D connecting the mounting surface 4 and the non-mounting surface 5. The mounting surface 4 and the non-mounting surface 5 are formed in a quadrangular shape (specifically, a rectangular shape) in a plan view seen from their normal direction Z. The mounting surface 4 is a surface that faces a connection target when the semiconductor package 2 is mounted on the connection target. An example of the connection target is a circuit board such as a PCB (printed circuit board).

[0013] The first to fourth side walls 6A to 6D include a first side wall 6A, a second side wall 6B, a third side wall 6C, and a fourth side wall 6D. The first side wall 6A and the second side wall 6B extend along a first direction X and face a second direction Y perpendicular to the first direction X. The first side wall 6A and the second side wall 6B form long sides of the package body 3. The third side wall 6C and the fourth side wall 6D extend along the second direction Y and face the first direction X. The third side wall 6C and the fourth side wall 6D form short sides of the package body 3. The length of the long sides of the package body 3 may be 2 mm or more and 5 mm or less. The length of the short sides of the package body 3 may be 1 mm or more and 4 mm or less.

[0014] The semiconductor package 2 includes a plate-shaped die pad 7 disposed within the package body 3. The die pad 7 is disposed on the mounting surface 4 side within the package body 3. The die pad 7 may also serve as a shield plate that blocks external electromagnetic waves. The die pad 7 includes at least one of copper, a copper-based alloy, iron, and an iron-based alloy. The die pad 7 includes a pad body 8, a first lead portion 9, and a second lead portion 10.

[0015] The pad body 8 is formed in a quadrangular shape in a plan view. The first lead portion 9 is drawn out in a strip shape from a side of the pad body 8 that is along the fourth side wall 6D toward the fourth side wall 6D in a plan view. The second lead portion 10 is drawn out in a strip shape from a side of the pad body 8 that is along the third side wall 6C toward the third side wall 6C in a plan view. The die pad 7 may have any shape, and the first lead portion 9 and the second lead portion 10 do not necessarily have to be formed. A die pad 7 that does not have either or both of the first lead portion 9 and the second lead portion 10 may also be used.

[0016] The semiconductor package 2 includes a plurality of lead terminals 11 (five in this embodiment) extending from inside the package body 3 to the outside. The plurality of lead terminals 11 are bent toward the mounting surface 4 outside the package body 3. Each of the plurality of lead terminals 11 includes at least one of copper, a copper-based alloy, iron, and an iron-based alloy. Specifically, the plurality of lead terminals 11 include a high-potential lead terminal 12, a low-potential lead terminal 13, a non-inverting input lead terminal 14, an inverting input lead terminal 15, and an output lead terminal 16.

[0017] The high potential lead terminal 12 and the low potential lead terminal 13 are power supply lead terminals, with a reference potential being applied to the low potential lead terminal 13. Specifically, the low potential lead terminal 13 is a ground lead terminal that is fixed to the ground potential.

[0018] On the first side wall 6A side, the inverting input lead terminal 15, the low potential lead terminal 13, and the non-inverting input lead terminal 14 are arranged at intervals in this order from the third side wall 6C side toward the fourth side wall 6D side. On the second side wall 6B side, the output lead terminal 16 and the high potential lead terminal 12 are arranged at intervals in this order from the third side wall 6C side toward the fourth side wall 6D side. The output lead terminal 16 faces the inverting input lead terminal 15 across the package body 3. The high potential lead terminal 12 faces the non-inverting input lead terminal 14 across the package body 3.

[0019] Each of the multiple lead terminals 11 has an inner end 17, an outer end 18, and a lead portion 19. The inner end 17 is located inside the package body 3 and has a plate surface parallel to the mounting surface 4 (non-mounting surface 5). The inner end 17 of each of the multiple lead terminals 11 arranged at the four corners has a curved portion 20 that is recessed in a direction away from the die pad 7 in the portion facing the die pad 7. The inner end 17 of the low-potential lead terminal 13 is formed integrally with the die pad 7 and fixes the die pad 7 to the same potential.

[0020] The outer end 18 is located outside the package body 3 and has a plate surface parallel to the mounting surface 4 (non-mounting surface 5). The lead portion 19 is drawn out from the inner end 17 to the outside of the package body 3 and connected to the outer end 18. The lead portion 19 is bent outside the package body 3 toward the mounting surface 4 and is connected to the outer end 18 at a height position that crosses the mounting surface 4 in the normal direction Z.

[0021] The plurality of lead terminals 11 may have any shape. The high potential lead terminal 12, low potential lead terminal 13, non-inverting input lead terminal 14, inverting input lead terminal 15, and output lead terminal 16 may be arranged in any manner and are not limited to the arrangements shown in FIGS. 1 to 3.

[0022] The semiconductor package 2 includes a semiconductor device 1 arranged on a die pad 7 (specifically, a pad body 8) within a package body 3. The semiconductor device 1 is arranged on the non-mounting surface 5 side of the die pad 7 within the package body 3. The semiconductor device 1 includes a differential amplifier 21 that amplifies and outputs an input differential signal, and a plurality of terminals 22 electrically connected to the differential amplifier 21. The differential amplifier 21 is formed inside the semiconductor device 1. The plurality of terminals 22 are formed on one surface of the semiconductor device 1. The semiconductor device 1 is arranged on the plate surface on the non-mounting surface 5 side of the die pad 7 (specifically, the pad body 8) with the plurality of terminals 22 facing the non-mounting surface 5 of the package body 3.

[0023] In this embodiment, the semiconductor device 1 is a single-channel type including one differential amplifier 21. The multiple terminals 22 include a high potential terminal 23, a low potential terminal 24, a non-inverting input terminal 25, an inverting input terminal 26, and an output terminal 27. The high potential terminal 23 and the low potential terminal 24 are power supply terminals to which a reference potential is applied to the low potential terminal 24. Specifically, the low potential terminal 24 is a ground terminal fixed to ground potential.

[0024] The semiconductor package 2 includes a conductive bonding material 28 (see the hatched portion in FIG. 3 ) that is interposed between the die pad 7 and the semiconductor device 1 within the package body 3 and bonds the die pad 7 to the semiconductor device 1. The conductive bonding material 28 is made of an insulating adhesive, a metal adhesive, or solder.

[0025] The semiconductor package 2 includes a plurality of (five in this embodiment) conductive wires 29 that electrically connect the plurality of terminals 22 of the semiconductor device 1 to the corresponding lead terminals 11 within the package body 3. Each of the conductive wires 29 is made of a bonding wire. The conductive wires 29 include at least one of copper wire, gold wire, and aluminum wire.

[0026] The plurality of conductors 29 specifically include a high potential conductor 30, a low potential conductor 31, a non-inverting input conductor 32, an inverting input conductor 33, and an output conductor 34. The high potential conductor 30 is connected to the high potential lead terminal 12 and the high potential terminal 23. The low potential conductor 31 is connected to the die pad 7 (first lead portion 9) and the low potential terminal 24, and electrically connects the low potential lead terminal 13 and the low potential terminal 24 via the die pad 7. The non-inverting input conductor 32 is connected to the non-inverting input lead terminal 14 and the non-inverting input terminal 25. The inverting input conductor 33 is connected to the inverting input lead terminal 15 and the inverting input terminal 26. The output conductor 34 is connected to the output lead terminal 16 and the output terminal 27.

[0027] 4 is an electrical circuit diagram showing the electrical structure of the semiconductor device 1 shown in FIG. The semiconductor device 1 includes a differential amplifier 21. The differential amplifier 21 is connected to a high potential terminal 23, a low potential terminal 24, a non-inverting input terminal 25, an inverting input terminal 26, and an output terminal 27, and amplifies and outputs an input differential signal. In this embodiment, the differential amplifier 21 is a rail-to-rail output class AB amplifier that operates in such a manner that the potential difference between the non-inverting input terminal 25 and the inverting input terminal 26 is in the range of the potential difference between the high potential terminal 23 and the low potential terminal 24.

[0028] The differential amplifier 21 includes a plurality of (three in this embodiment) constant current circuits 41 to 43, an input circuit 44, an amplifier circuit 45, and an output circuit 46. The constant current circuits 41 to 43, the input circuit 44, the amplifier circuit 45, and the output circuit 46 may be referred to as a constant current stage, an input stage, an amplifier stage, and an output stage, respectively. Furthermore, the constant current circuits 41 to 43, the input circuit 44, and the amplifier circuit 45 may be collectively referred to as a differential amplifier circuit (differential amplifier stage).

[0029] The multiple constant current circuits 41 to 43 specifically include a first constant current circuit 41, a second constant current circuit 42, and a third constant current circuit 43. Since the multiple constant current circuits 41 to 43 have the same configuration, the multiple constant current circuits 41 to 43 are shown in a single circuit diagram on the right side of the page in FIG.

[0030] Each of the constant current circuits 41 to 43 is interposed between the high potential terminal 23 and the low potential terminal 24 and generates a constant current. In this embodiment, each of the constant current circuits 41 to 43 is configured by a self-biased cascode current mirror circuit. Specifically, each of the constant current circuits 41 to 43 integrally includes a first constant current generating circuit 47 that generates a first constant current on the high potential terminal 23 side, and a second constant current generating circuit 48 that generates a second constant current on the low potential terminal 24 side.

[0031] Specifically, the first constant current generating circuit 47 includes a first current mirror circuit 49, a second current mirror circuit 50, a first resistor 51, and a second resistor 52. The first constant current generating circuit 47 is configured such that the first current mirror circuit 49 and the second current mirror circuit 50 operate in two stages due to the first resistor 51.

[0032] The first current mirror circuit 49 includes a pair of first constant current transistors 53A and 53B. Each of the first constant current transistors 53A and 53B is formed of a p-type (first polarity type) field effect transistor or a p-type bipolar transistor (field effect transistor in FIG. 4). The field effect transistor may be formed of a part of a CMOS transistor.

[0033] The gates of the first constant current transistors 53A and 53B are connected to each other and form a first gate node GN1. The sources of the first constant current transistors 53A and 53B are connected to the high potential terminal 23.

[0034] The second current mirror circuit 50 includes a pair of second constant current transistors 54A and 54B, which are cascode-connected to the first current mirror circuit 49. The second constant current transistors 54A and 54B are each formed of a p-type field effect transistor or a p-type bipolar transistor (field effect transistor in FIG. 4). The field effect transistor may be formed of part of a CMOS transistor.

[0035] The gates of the second constant current transistors 54A and 54B are connected to each other and form a second gate node GN2. The source of the second constant current transistor 54A is connected to the drain of the first constant current transistor 53A. The source of the second constant current transistor 54B is connected to the drain of the first constant current transistor 53B.

[0036] The first resistor 51 is connected to the drain of the second constant current transistor 54A. Specifically, one end of the first resistor 51 is connected to the drain of the second constant current transistor 54A and the first gate node GN1 of the first current mirror circuit 49. The other end of the first resistor 51 is connected to the second gate node GN2 of the second current mirror circuit 50. The second resistor 52 is interposed between the high potential terminal 23 and the source of the first constant current transistor 53B.

[0037] Specifically, the second constant current generating circuit 48 includes a third current mirror circuit 55, a fourth current mirror circuit 56, and a third resistor 57. The second constant current generating circuit 48 is configured such that the third current mirror circuit 55 and the fourth current mirror circuit 56 operate in two stages due to the third resistor 57.

[0038] The third current mirror circuit 55 includes a pair of third constant current transistors 58A and 58B. The third constant current transistors 58A and 58B are each composed of an n-type (second polarity type) field effect transistor or an n-type bipolar transistor (field effect transistor in FIG. 4). The field effect transistor may be composed of part of a CMOS transistor.

[0039] The gates of the third constant current transistors 58A and 58B are connected to each other and form a third gate node GN3. The drain of the third constant current transistor 58A is connected to the other end of the first resistor 51 and to the drain of the second constant current transistor 54A via the first resistor 51. The drain of the third constant current transistor 58B is connected to the drain of the second constant current transistor 54B.

[0040] The fourth current mirror circuit 56 includes a pair of fourth constant current transistors 59A and 59B, which are cascode-connected to the third current mirror circuit 55. The fourth constant current transistors 59A and 59B are each formed of an n-type field effect transistor or an n-type bipolar transistor (field effect transistor in FIG. 4). The field effect transistor may be formed of part of a CMOS transistor.

[0041] The gates of the fourth constant current transistors 59A and 59B are connected to each other and form a fourth gate node GN4. The drain of the fourth constant current transistor 59A is connected to the source of the third constant current transistor 58A. The drain of the fourth constant current transistor 59B is connected to the source of the third constant current transistor 58B. The sources of the fourth constant current transistors 59A and 59B are each connected to the low potential terminal 24.

[0042] The third resistor 57 is interposed between the drain of the second constant current transistor 54B and the drain of the third constant current transistor 58B. Specifically, one end of the third resistor 57 is connected to the drain of the second constant current transistor 54B and the third gate node GN3 of the third current mirror circuit 55. The other end of the third resistor 57 is connected to the drain of the third constant current transistor 58B and the fourth gate node GN4 of the fourth current mirror circuit 56.

[0043] The input circuit 44 is connected to the non-inverting input terminal 25, the inverting input terminal 26, and the first constant current circuit 41. The input circuit 44 converts the differential signals input to the non-inverting input terminal 25 and the inverting input terminal 26 into differential currents. Specifically, the input circuit 44 includes a first differential circuit 61 and a second differential circuit 62.

[0044] The first differential circuit 61 operates in a first differential voltage range in which the second differential circuit 62 does not operate, and the second differential circuit 62 operates in a second differential voltage range in which the first differential circuit 61 does not operate. In this manner, the input circuit 44 is configured so that the differential voltage between the non-inverting input terminal 25 and the inverting input terminal 26 operates in the voltage range between the high potential terminal 23 and the low potential terminal 24.

[0045] Specifically, the first differential circuit 61 includes a pair of first differential transistors 63A and 63B that form a differential connection. Each of the first differential transistors 63A and 63B is formed by a p-type field effect transistor or a p-type bipolar transistor (field effect transistor in FIG. 4). The field effect transistor may be formed by a part of a CMOS transistor.

[0046] The gate of the first differential transistor 63A is connected to the inverting input terminal 26. The gate of the first differential transistor 63B is connected to the non-inverting input terminal 25. The sources of the first differential transistors 63A and 63B are connected to the first constant current generating circuit 47 of the first constant current circuit 41 serving as a constant current source. The drains of the first differential transistors 63A and 63B are connected to the amplifier circuit 45.

[0047] Specifically, the second differential circuit 62 includes a pair of second differential transistors 64A and 64B that form a differential connection. The second differential transistors 64A and 64B are each composed of an n-type field effect transistor or an n-type bipolar transistor (field effect transistor in FIG. 4). The field effect transistor may be composed of a part of a CMOS transistor.

[0048] The gate of the second differential transistor 64A is connected to the inverting input terminal 26. The gate of the second differential transistor 64B is connected to the non-inverting input terminal 25. The sources of the second differential transistors 64A and 64B are connected to the second constant current generating circuit 48 of the first constant current circuit 41, which serves as a constant current source. The drains of the second differential transistors 64A and 64B are connected to the amplifier circuit 45.

[0049] The amplifier circuit 45 is connected to the high potential terminal 23, the low potential terminal 24, the second constant current circuit 42, the third constant current circuit 43, and the input circuit 44. The amplifier circuit 45 amplifies the differential current generated by the input circuit 44 to generate an amplified current. Specifically, the amplifier circuit 45 includes a first current folding circuit 71, a second current folding circuit 72, and an AB class control circuit 73.

[0050] The first current folding circuit 71 forms a first folded cascode circuit with the first differential circuit 61, and amplifies the differential current in cooperation with the first differential circuit 61. The second current folding circuit 72 forms a second folded cascode circuit with the second differential circuit 62, and amplifies the differential current in cooperation with the second differential circuit 62.

[0051] The first current folding circuit 71 includes a pair of first bias transistors 74A and 74B that are cascode-connected with the first differential circuit 61. The first bias transistors 74A and 74B are each composed of an n-type field-effect transistor or an n-type bipolar transistor (field-effect transistor in FIG. 4). The field-effect transistor may be composed of part of a CMOS transistor.

[0052] The gates of the first bias transistors 74A and 74B are connected to each other and form a fifth gate node GN5. The source of the first bias transistor 74A is connected to the drain of the first differential transistor 63A and the second constant current generating circuit 48 of the second constant current circuit 42, which serves as a constant current source.

[0053] The source of the first bias transistor 74B is connected to the drain of the first differential transistor 63B and to the second constant current generating circuit 48 of the third constant current circuit 43, which serves as a constant current source. The first current folding circuit 71 is controlled by a first bias voltage source VB1 interposed between the low potential terminal 24 and the fifth gate node GN5.

[0054] The second current folding circuit 72 includes a pair of second bias transistors 75A and 75B that are cascode-connected with the second differential circuit 62. The second bias transistors 75A and 75B are each composed of a p-type field-effect transistor or a p-type bipolar transistor (field-effect transistor in FIG. 4). The field-effect transistor may be composed of part of a CMOS transistor.

[0055] The gates of the second bias transistors 75A and 75B are connected to each other to form a sixth gate node GN6. The source of the second bias transistor 75A is connected to the drain of the second differential transistor 64A and the first constant current generating circuit 47 of the second constant current circuit 42, which serves as a constant current source.

[0056] The source of the second bias transistor 75B is connected to the drain of the second differential transistor 64B and to the first constant current generating circuit 47 of the third constant current circuit 43, which serves as a constant current source. The second current folding circuit 72 is controlled by a second bias voltage source VB2 interposed between the high potential terminal 23 and the sixth gate node GN6.

[0057] The class AB control circuit 73 is connected to the drains of the first bias transistors 74A and 74B and the drains of the second bias transistors 75A and 75B. The class AB control circuit 73 generates and outputs a class AB control signal according to the amplified current generated by the first current folding circuit 71 and the amplified current generated by the second current folding circuit 72.

[0058] The output circuit 46 is connected to the high potential terminal 23, the low potential terminal 24, the output terminal 27, and the amplifier circuit 45. In response to the class AB control signal generated by the amplifier circuit 45 (class AB control circuit 73), the output circuit 46 generates an output current according to the amplified current and outputs it to the output terminal 27.

[0059] Specifically, the output circuit 46 includes a push-pull circuit 82 including a pair of output transistors 81A and 81B that form a push-pull connection. The output transistor 81A is made up of a p-type field effect transistor or a p-type bipolar transistor (field effect transistor in FIG. 4). The output transistor 81B is made up of an n-type field effect transistor or an n-type bipolar transistor (field effect transistor in FIG. 4). The field effect transistor may be made up of part of a CMOS transistor.

[0060] The gate of the output transistor 81A is connected to the class AB control circuit 73 and is controlled by a class AB control signal from the class AB control circuit 73. The source of the output transistor 81A is connected to the high potential terminal 23. The gate of the output transistor 81B is connected to the class AB control circuit 73 and is controlled by a class AB control signal from the class AB control circuit 73. The source of the output transistor 81B is connected to the low potential terminal 24. The drain of the output transistor 81B is connected to the drain of the output transistor 81A and forms an output node N. The output node N is connected to the output terminal 27.

[0061] In this embodiment, the differential amplifier 21 further includes a first low-pass filter circuit 83 and a second low-pass filter circuit 84. The first low-pass filter circuit 83 includes a fourth resistor 85 and is interposed between the non-inverting input terminal 25 and the first differential circuit 61. The second low-pass filter circuit 84 includes a fifth resistor 86 and is interposed between the inverting input terminal 26 and the second differential circuit 62.

[0062] Fig. 5 is a plan view showing in block form the layout of the internal structure of the semiconductor device 1 shown in Fig. 3. Fig. 6 is a schematic cross-sectional view of the semiconductor device 1 shown in Fig. 4. Fig. 7 is a plan view in which a shield electrode 130 is added to the layout shown in Fig. 5. Figs. 8A and 8B are enlarged plan views of a main part of the shield electrode 130 shown in Fig. 7. Fig. 6 shows a simplified cross-sectional structure of the semiconductor device 1 and does not show a cross section of a specific location.

[0063] 5 to 7, the semiconductor device 1 includes a rectangular parallelepiped semiconductor chip 100 made of silicon. The semiconductor chip 100 has a first main surface 101 on one side, a second main surface 102 on the other side, and first to fourth side surfaces 103A to 103D connecting the first main surface 101 and the second main surface 102. The first main surface 101 and the second main surface 102 are formed in a quadrangular shape in a plan view seen from a normal direction Z thereof (hereinafter simply referred to as a "plan view").

[0064] The first to fourth side surfaces 103A to 103D include a first side surface 103A, a second side surface 103B, a third side surface 103C, and a fourth side surface 103D. The first side surface 103A and the second side surface 103B extend in a first direction X along the first main surface 101 and face a second direction Y that intersects with (specifically, is perpendicular to) the first direction X. The third side surface 103C and the fourth side surface 103D extend in the second direction Y and face the first direction X.

[0065] The semiconductor device 1 includes a device region 104 defined on a first main surface 101 of a semiconductor chip 100. The device region 104 is defined in an inner portion of the first main surface 101 at intervals from the first to fourth side surfaces 103A to 103D. The device region 104 specifically includes a constant current region 105, an input region 106, an amplification region 107, and an output region 108 defined at intervals from one another. The constant current region 105, the input region 106, and the amplification region 107 form a single differential amplification region 109.

[0066] The constant current region 105 is defined in a region near a corner connecting the second side surface 103B and the fourth side surface 103D on the first main surface 101. The input region 106 is defined in a region near a corner connecting the first side surface 103A and the fourth side surface 103D on the first main surface 101. The amplification region 107 is defined in a region between the constant current region 105 and the input region 106 on the first main surface 101. In this embodiment, the amplification region 107 is defined in an L-shape facing the constant current region 105 from two directions, the first side surface 103A side and the third side surface 103C side, in a plan view.

[0067] The output region 108 is defined as an area on the third side surface 103C side of the first main surface 101, and faces the input region 106 and the amplification region 107. The output region 108 faces the constant current region 105, sandwiching a part of the amplification region 107 between them. The arrangement and planar shapes of the constant current region 105, the input region 106, the amplification region 107, and the output region 108 are arbitrary and are not limited to specific locations or shapes.

[0068] The semiconductor device 1 includes a differential amplifier 21 formed in a device region 104. Specifically, the differential amplifier 21 includes a plurality of constant current circuits 41 to 43 formed in a constant current region 105, an input circuit 44 formed in an input region 106, an amplifier circuit 45 formed in an amplifier region 107, and an output circuit 46 formed in an output region 108. The differential amplifier 21 includes a plurality of transistors fabricated on the first main surface 101. In FIG. 7, the structure of the differential amplifier 21 is shown in a simplified form using a semiconductor region 110 on the semiconductor chip 100 side and an electrode structure 111 (see hatched portion) on the upper side of the semiconductor chip 100.

[0069] The semiconductor device 1 includes an insulating layer 120 that is stacked on the first main surface 101 of the semiconductor chip 100 and collectively covers the device region 104 (constant current region 105, input region 106, amplification region 107, and output region 108). The insulating layer 120 is made of a multilayer wiring structure 123 having a stacked structure in which multiple interlayer insulating layers 121 and multiple wiring layers 122 are alternately stacked. The interlayer insulating layer 121 refers to the insulating layer 120 interposed between two wiring layers 122 adjacent to each other in the vertical direction. However, the lowest interlayer insulating layer 121 of the multiple interlayer insulating layers 121 refers to the insulating layer 120 interposed between the semiconductor chip 100 and the first wiring layer 122.

[0070] In this embodiment, the multilayer wiring structure 123 has a layered structure in which first to third interlayer insulating layers 121A to 121C and first to third wiring layers 122A to 123C are alternately stacked. The number of stacked interlayer insulating layers 121 and wiring layers 122 is arbitrary and is not limited to a specific number. Therefore, the multilayer wiring structure 123 may have a layered structure in which four or more interlayer insulating layers 121 and four or more wiring layers 122 are alternately stacked.

[0071] Each interlayer insulating layer 121 includes at least one of an SiO2 film and an SiN film. Each interlayer insulating layer 121 may have a single-layer structure made of an SiO2 film or an SiN film. Each interlayer insulating layer 121 may have a layered structure in which multiple SiO2 films or multiple SiN films are stacked. Each interlayer insulating layer 121 may have a layered structure in which one or more SiO2 films and one or more SiN films are stacked in any order.

[0072] The plurality of interlayer insulating layers 121 may each have a thickness of 1 μm or more and 5 μm or less. The plurality of interlayer insulating layers 121 do not necessarily have to have the same thickness, and may each have a different thickness.

[0073] A plurality of first wiring layers 122A are formed on the lowermost first interlayer insulating layer 121A. Each of the plurality of first wiring layers 122A forms a part of the wiring portion of the circuit diagram shown in FIG. 4. The plurality of first wiring layers 122A are selectively routed on the first interlayer insulating layer 121A. The plurality of first wiring layers 122A are electrically connected to corresponding circuits among the plurality of constant current circuits 41 to 43, the input circuit 44, the amplifier circuit 45, and the output circuit 46 via one or more first via electrodes 124 that penetrate the first interlayer insulating layer 121A. The first via electrodes 124 may be tungsten plug electrodes. The first wiring layer 122A may have a thickness of 0.1 μm or more and 1 μm or less.

[0074] A plurality of second wiring layers 122B are formed on the intermediate second interlayer insulating layer 121B. Each of the plurality of second wiring layers 122B forms a part of the wiring portion of the circuit diagram shown in FIG. 4. The plurality of second wiring layers 122B are selectively routed on the second interlayer insulating layer 121B. The plurality of second wiring layers 122B are electrically connected to the corresponding first wiring layers 122A via one or more second via electrodes 125 that penetrate the second interlayer insulating layer 121B. The second via electrodes 125 may be tungsten plug electrodes. The second wiring layer 122B may have a thickness of 0.1 μm or more and 1 μm or less.

[0075] A plurality of third wiring layers 122C are formed on the uppermost third interlayer insulating layer 121C. Each of the plurality of third wiring layers 122C forms a part of the wiring portion of the circuit diagram shown in FIG. 4. The plurality of third wiring layers 122C are selectively routed on the third interlayer insulating layer 121C. The plurality of third wiring layers 122C are electrically connected to the corresponding second wiring layers 122B via one or more third via electrodes 126 that penetrate the third interlayer insulating layer 121C. The third via electrodes 126 may be tungsten plug electrodes. The third wiring layer 122C is formed thicker than the first and second wiring layers 122A and 122B below it.

[0076] The first and second wiring layers 122A and 122B each include a first barrier film 127, a main wiring film 128, and a second barrier film 129, which are stacked in this order from the semiconductor chip 100 side. On the other hand, the uppermost third wiring layer 122C has an electrode structure different from the lower first and second wiring layers 122A and 122B. In this embodiment, the uppermost third wiring layer 122C includes the first barrier film 127 and the main wiring film 128, which are stacked in this order from the semiconductor chip 100 side, and does not have the second barrier film 129.

[0077] The first barrier film 127 and the second barrier film 129 are each made of a Ti-based metal film. The first barrier film 127 and the second barrier film 129 may each have a layered structure including a Ti film and a TiN film stacked in any order. The first barrier film 127 and the second barrier film 129 may each have a single-layer structure made of a Ti film or a TiN film. The thickness of the first barrier film 127 and the second barrier film 129 may each be 0.1 μm or more and 0.5 μm or less.

[0078] The main wiring film 128 is made of an Al-based metal film. The main wiring film 128 may include at least one of an Al film, an AlSiCu alloy film, an AlSi alloy film, and an AlCu alloy film. The main wiring film 128 has a thickness that exceeds the thickness of the first barrier film 127 and the thickness of the second barrier film 129. The thickness of the main wiring film 128 may be 1 μm or more and 5 μm or less.

[0079] 5 and 7, the high potential terminal 23, the low potential terminal 24, the non-inverting input terminal 25, the inverting input terminal 26, and the output terminal 27 are formed as part of the uppermost third wiring layer 122C, spaced apart from one another on the uppermost third interlayer insulating layer 121C. The high potential terminal 23, the low potential terminal 24, the non-inverting input terminal 25, the inverting input terminal 26, and the output terminal 27 are each formed in a quadrangular shape in a plan view.

[0080] The high potential terminal 23 is arranged adjacent to the constant current region 105 in a planar view. Specifically, the high potential terminal 23 is arranged in a region between the fourth side surface 103D and the constant current region 105 in a planar view. The low potential terminal 24 is arranged adjacent to the input region 106 in a planar view. Specifically, the low potential terminal 24 is arranged in a region between the fourth side surface 103D and the input region 106 in a planar view. The low potential terminal 24 faces the high potential terminal 23 in the second direction Y.

[0081] The non-inverting input terminal 25 is arranged adjacent to the input region 106 in a planar view. Specifically, the non-inverting input terminal 25 is arranged in a region between the first side surface 103A and the input region 106 in a planar view. The inverting input terminal 26 is arranged adjacent to the output region 108 in a planar view. Specifically, the inverting input terminal 26 is arranged in a region between the first side surface 103A and the output region 108 in a planar view. The inverting input terminal 26 faces the non-inverting input terminal 25 in the first direction X.

[0082] The output terminal 27 is arranged adjacent to the output region 108 in a planar view. Specifically, the output terminal 27 is arranged in a region between the third side surface 103C and the output region 108 in a planar view. Only the output terminal 27 is arranged in the region between the third side surface 103C and the output region 108. The output terminal 27 faces the high potential terminal 23 in the first direction X in a planar view, with the constant current region 105, the amplification region 107, and the output region 108 sandwiched between them.

[0083] 7, the semiconductor device 1 includes a shield electrode 130 disposed on the first main surface 101 so as to shield the device region 104 and fixed to a ground potential. Specifically, the shield electrode 130 is incorporated into the insulating layer 120 (multilayer wiring structure 123). The shield electrode 130 blocks external electromagnetic waves. An example of the external electromagnetic waves is an electromagnetic interference signal such as an RF (radio frequency) signal outside the operating frequency band of the differential amplifier 21.

[0084] The shield electrode 130 preferably has a shield frequency band in the range of 1 MHz to 5 GHz. This shield electrode 130 can adequately shield electromagnetic interference signals in the range of 1 MHz to 5 GHz. It is particularly preferable that the shield electrode 130 has a shield frequency band in the range of at least 1 MHz to 2 GHz.

[0085] The shield electrode 130 forms one of any of the first to third wiring layers 122A to 123C in the multilayer wiring structure 123, and is disposed on any of the interlayer insulating layers 121. In this embodiment, the shield electrode 130 forms one of the uppermost third wiring layers 122C in the multilayer wiring structure 123, and is disposed on the uppermost third interlayer insulating layer 121C.

[0086] In this embodiment, the shield electrode 130 conceals the constant current region 105, the input region 106, the amplification region 107, and the output region 108. Specifically, the shield electrode 130 integrally includes a first shield electrode 131 that conceals the constant current region 105, a second shield electrode 132 that conceals the input region 106, a third shield electrode 133 that conceals the amplification region 107, and a fourth shield electrode 134 that conceals the output region 108.

[0087] The first shield electrode 131 shields electromagnetic waves directed from the outside toward the constant current region 105, thereby suppressing noise and malfunction in the constant current region 105. It is preferable that the first shield electrode 131 shields the entire constant current region 105. The second shield electrode 132 shields electromagnetic waves directed from the outside toward the input region 106, thereby suppressing noise and malfunction in the input region 106. It is preferable that the second shield electrode 132 shields the entire input region 106.

[0088] The third shield electrode 133 shields electromagnetic waves directed from the outside toward the amplification region 107, thereby suppressing noise and malfunction in the amplification region 107. It is preferable that the third shield electrode 133 shields the entire amplification region 107. The fourth shield electrode 134 shields electromagnetic waves directed from the outside toward the output region 108, thereby suppressing noise and malfunction in the output region 108. It is preferable that the fourth shield electrode 134 shields the entire output region 108.

[0089] In this embodiment, the first shield electrode 131, the second shield electrode 132, and the third shield electrode 133 form a differential amplification shield electrode 135 that collectively shields the differential amplification region 109 including the constant current region 105, the input region 106, and the amplification region 107. On the other hand, the fourth shield electrode 134 forms an output shield electrode 136 that alone shields the output region 108.

[0090] The shield electrode 130 extends toward the low potential terminal 24 and includes a shield connection portion 137 electrically connected to the low potential terminal 24. The shield connection portion 137 may be routed in any manner as long as it is electrically connected to the low potential terminal 24. In this embodiment, the shield electrode 130 is formed integrally with the low potential terminal 24 and is fixed to the ground potential. In other words, the shield electrode 130 forms one uppermost third wiring layer 122C between itself and the low potential terminal 24.

[0091] The shield electrode 130 only needs to include at least one of the first to fourth shield electrodes 131 to 134, and does not necessarily need to include all of the first to fourth shield electrodes 131 to 134. Of the first to fourth shield electrodes 131 to 134, the shield electrode 130 preferably has at least one of the first shield electrode 131 that shields the constant current region 105 and the second shield electrode 132 that shields the input region 106.

[0092] In this case, it is particularly preferable that the shield electrode 130 includes both the first shield electrode 131 and the second shield electrode 132. It is most preferable that the shield electrode 130 includes all of the first to fourth shield electrodes 131 to 134. Furthermore, the first to fourth shield electrodes 131 to 134 only need to be fixed to the ground potential, and do not necessarily have to be formed integrally. At least one of the first to fourth shield electrodes 131 to 134 may be formed separately.

[0093] 8A and 8B, the shield electrode 130 includes a plurality of through holes 138. The plurality of through holes 138 relieves stress generated in the shield electrode 130. The plurality of through holes 138 penetrates the shield electrode 130 and exposes the underlying interlayer insulating layer 121. The plurality of through holes 138 may be arranged in a staggered pattern as shown in FIG. 8A, or may be arranged in a matrix pattern as shown in FIG. 8B. Of course, the plurality of through holes 138 may be arranged in a concentric pattern or an irregular pattern.

[0094] In this embodiment, the plurality of through holes 138 are each formed in a circular shape in a plan view. The planar shape of the plurality of through holes 138 is arbitrary and is not limited to a circular shape. The plurality of through holes 138 may be formed in a polygonal shape (e.g., a rectangular shape) or an elliptical shape in a plan view. It is preferable that the plurality of through holes 138 each have a size smaller than the wavelength of the electromagnetic wave to be shielded. In this case, it is possible to suppress the penetration of the electromagnetic wave through the plurality of through holes 138 while mitigating the stress generated in the shield electrode 130.

[0095] The size of each through hole 138 may be 1 μm or more and 10 μm or less. The size of each through hole 138 may be 1 μm or more and 2 μm or less, 2 μm or more and 4 μm or less, 4 μm or more and 6 μm or less, 6 μm or more and 8 μm or less, or 8 μm or more and 10 μm or less. The size of each through hole 138 is preferably 2 μm or more and 6 μm or less. The multiple through holes 138 do not necessarily have to have the same size, and may have different sizes from each other.

[0096] When the through-hole 138 is circular, the size of the through-hole 138 is defined by the diameter (when the through-hole 138 is elliptical, the size of the major axis). When the through-hole 138 is polygonal, the size of the through-hole 138 is defined by the length of the longest side or the length of the longest diagonal. The size of the multiple through-holes 138 is preferably less than the thickness of the shield electrode 130. The size of the multiple through-holes 138 may be equal to or greater than the thickness of the shield electrode 130.

[0097] 6 again, the semiconductor device 1 includes a protective layer 140 that covers the insulating layer 120 (multilayer wiring structure 123). The protective layer 140 covers the entire area of ​​the shield electrode 130 and has a plurality of pad openings 141 in an area outside the shield electrode 130. The protective layer 140 extends from above the shield electrode 130 into a plurality of through holes 138. The protective layer 140 contacts the insulating layer 120 (the uppermost third interlayer insulating layer 121C) within the plurality of through holes 138. The plurality of pad openings 141 expose, as pad portions, a portion of the high potential terminal 23, a portion of the low potential terminal 24, a portion of the non-inverting input terminal 25, a portion of the inverting input terminal 26, and a portion of the output terminal 27.

[0098] The protective layer 140 has a laminated structure including an inorganic insulating film 142 and an organic insulating film 143, which are laminated in this order from the insulating layer 120 side. In this embodiment, the inorganic insulating film 142 includes silicon nitride. The inorganic insulating film 142 may also be referred to as a passivation film. The inorganic insulating film 142 preferably fills the multiple through-holes 138 and covers the shield electrode 130. In other words, the inorganic insulating film 142 preferably contacts the insulating layer 120 (the uppermost third interlayer insulating layer 121C) within the multiple through-holes 138.

[0099] The organic insulating film 143 includes a negative or positive photosensitive resin. The organic insulating film 143 may include at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating film 143 includes polyimide. The organic insulating film 143 is preferably formed outside the plurality of through-holes 138 and covers the shield electrode 130 with the inorganic insulating film 142 sandwiched therebetween.

[0100] As described above, the semiconductor device 1 includes the semiconductor chip 100, the differential amplifier 21, the insulating layer 120, and the shield electrode 130. The differential amplifier 21 is formed in a device region 104 defined on the first main surface 101, and amplifies and outputs an input differential signal. The insulating layer 120 covers the device region 104 on the first main surface 101. The shield electrode 130 is disposed on the first main surface 101 so as to conceal the device region 104, and is fixed to a ground potential. Specifically, the shield electrode 130 is incorporated into the insulating layer 120. This allows the shield electrode 130 to block external electromagnetic waves, thereby improving EMI (electromagnetic interference) resistance.

[0101] It is preferable that the shield electrode 130 conceals either the constant current region 105 or the input region 106. That is, it is preferable that the shield electrode 130 has either a first shield electrode 131 that conceals the constant current region 105 or a second shield electrode 132 that conceals the input region 106. With this structure, noise caused by electromagnetic waves can be suppressed in the stage of converting a differential signal into a differential current. Therefore, a differential current with suppressed noise can be appropriately generated. It is more preferable that the shield electrode 130 has both the first shield electrode 131 and the second shield electrode 132. With this structure, it is possible to appropriately suppress noise caused by electromagnetic waves in the stage of converting a differential signal into a differential current.

[0102] More preferably, shield electrode 130 conceals constant current region 105, input region 106, amplification region 107, and output region 108. That is, more preferably, shield electrode 130 includes first shield electrode 131 concealing constant current region 105, second shield electrode 132 concealing input region 106, third shield electrode 133 concealing amplification region 107, and fourth shield electrode 134 concealing output region 108. With this structure, noise caused by electromagnetic waves can be appropriately suppressed in the constant current stage, input stage, amplification stage, and output stage.

[0103] Preferably, shield electrode 130 forms part of the uppermost third wiring layer 122C in multilayer wiring structure 123, and is disposed on the uppermost third interlayer insulating layer 121C. With this structure, shield electrode 130 can be appropriately formed without being restricted by the design rules of the lower first and second wiring layers 122A-122B. Conversely, first and second wiring layers 122A-122B can be appropriately formed without being restricted by the design rules of shield electrode 130.

[0104] The shield electrode 130 preferably includes a plurality of through holes 138. With this structure, the stress generated in the shield electrode 130 can be alleviated by the plurality of through holes 138, thereby suppressing warping of the insulating layer 120 due to the stress. Suppressing warping of the insulating layer 120 is effective in suppressing cracks in the insulating layer 120. The plurality of through holes 138 preferably each have a size smaller than the wavelength of the electromagnetic waves to be shielded. With this structure, it is possible to prevent electromagnetic waves having wavelengths larger than the size of the plurality of through holes 138 from passing through the through holes 138. Therefore, it is possible to suppress the penetration of electromagnetic waves through the plurality of through holes 138 while alleviating the stress generated in the shield electrode 130.

[0105] The semiconductor device 1 may be incorporated into a semiconductor package 2 (see FIGS. 1 to 3). In the semiconductor package 2, the die pad 7 and the shield electrode 130 are fixed to the ground potential. That is, the differential amplifier 21 built into the semiconductor chip 100 is sandwiched between the die pad 7 and the shield electrode 130. This provides an electromagnetic wave shielding effect from both the die pad 7 and the shield electrode 130. Therefore, when mounted in the semiconductor package 2, the EMI resistance of the semiconductor device 1 can be improved.

[0106] 9 is a plan view corresponding to FIG. 7, and is a plan view for explaining the structure of a semiconductor device 151 according to a second embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0107] 9, semiconductor device 151 includes a slit 152 in shield electrode 130 that borders differential amplifier shield electrode 135. Slit 152 externally defines differential amplifier region 109, which includes constant current region 105, input region 106, and amplifier region 107, in plan view. Slit 152 extends in a C-shape in plan view so as to leave the connection portion between differential amplifier shield electrode 135 and output shield electrode 136.

[0108] The semiconductor device 151 includes a guard electrode 153 that is formed along the periphery of the differential amplifier shield electrode 135 at a distance from the differential amplifier shield electrode 135 and is fixed to a ground potential. The guard electrode 153 forms one of the uppermost third wiring layers 122C in the multilayer wiring structure 123 and is disposed on the uppermost third interlayer insulating layer 121C. The guard electrode 153 is formed in a strip shape that extends along the differential amplifier shield electrode 135 so as to define the differential amplifier shield electrode 135 from the outside in a plan view. The guard electrode 153 extends in a C-shape in a plan view.

[0109] The guard electrode 153 is formed on the third interlayer insulating layer 121C independently (separately) from the low potential terminal 24 and the shield electrode 130. In this embodiment, the guard electrode 153 is electrically connected to the low potential terminal 24 via any of the first and second wiring layers 122A and 122B and any of the first to third via electrodes 124 to 126. Of course, the guard electrode 153 may include a connection portion electrically connected to the low potential terminal 24 on the third interlayer insulating layer 121C. In other words, the guard electrode 153 may be formed integrally with the low potential terminal 24 and the shield electrode 130.

[0110] As described above, the semiconductor device 151 can also achieve the same effects as those described for the semiconductor device 1. The semiconductor device 151 also includes a guard electrode 153 formed in a strip shape along the differential amplifier shield electrode 135. As a result, when an ESD surge voltage is applied to any of the high potential terminal 23, the low potential terminal 24, the non-inverting input terminal 25, the inverting input terminal 26, and the output terminal 27, the ESD surge voltage can be absorbed by the guard electrode 153. As a result, the electrostatic discharge resistance can be improved.

[0111] Fig. 10 is a perspective view showing a semiconductor package 202 incorporating a semiconductor device 201 according to a third embodiment of the present invention. Fig. 11 is a diagram showing the electrical structure of the semiconductor package 202 shown in Fig. 10 using circuit symbols. Fig. 12 is a plan view showing the internal structure of the semiconductor package 202 shown in Fig. 10.

[0112] 10 to 12, in this embodiment, semiconductor package 202 is an 8-terminal SOP. Semiconductor package 202 is not limited to an SOP, and may be a QFN, DFP, DIP, QFP, SIP, SOJ, or any of various other packages similar thereto.

[0113] The semiconductor package 202 includes a package body 3. The package body 3 is made of molded resin (e.g., epoxy resin) and is molded into a rectangular parallelepiped shape. The package body 3 has a mounting surface 4 on one side, a non-mounting surface 5 on the other side, and first to fourth side walls 6A to 6D connecting the mounting surface 4 and the non-mounting surface 5. The mounting surface 4 and the non-mounting surface 5 are formed in a quadrangular shape (specifically, a rectangular shape) in a plan view seen from their normal direction Z. The mounting surface 4 is a surface that faces a connection target when the semiconductor package 202 is mounted on the connection target. An example of the connection target is a circuit board such as a PCB.

[0114] The first to fourth side walls 6A to 6D include a first side wall 6A, a second side wall 6B, a third side wall 6C, and a fourth side wall 6D. The first side wall 6A and the second side wall 6B extend along a first direction X and face a second direction Y perpendicular to the first direction X. The first side wall 6A and the second side wall 6B form long sides of the package body 3. The third side wall 6C and the fourth side wall 6D extend along the second direction Y and face the first direction X. The third side wall 6C and the fourth side wall 6D form short sides of the package body 3. The length of the long sides of the package body 3 may be 4 mm or more and 8 mm or less. The length of the short sides of the package body 3 may be 3 mm or more and 7 mm or less.

[0115] The semiconductor package 202 includes a plate-shaped die pad 7 disposed within the package body 3. The die pad 7 is disposed on the mounting surface 4 side within the package body 3. The die pad 7 includes at least one of copper, a copper-based alloy, iron, and an iron-based alloy. In this embodiment, the die pad 7 includes only a pad body 8, and does not have a first exposed portion 9 or a second exposed portion 10. The die pad 7 (pad body 8) is formed in a quadrangular shape in a plan view.

[0116] The semiconductor package 202 includes a plurality of lead terminals 11 (eight in this embodiment) extending from the inside to the outside of the package body 3. Each of the plurality of lead terminals 11 includes at least one of copper, a copper-based alloy, iron, and an iron-based alloy. Specifically, the plurality of lead terminals 11 includes a single high-potential lead terminal 12, a single low-potential lead terminal 13, a plurality of non-inverting input lead terminals 14, a plurality of inverting input lead terminals 15, and a plurality of output lead terminals 16.

[0117] The plurality of non-inverting input lead terminals 14 include a first non-inverting input lead terminal 14A and a second non-inverting input lead terminal 14B. The plurality of inverting input lead terminals 15 include a first inverting input lead terminal 15A and a second inverting input lead terminal 15B. The plurality of output lead terminals 16 include a first output lead terminal 16A and a second output lead terminal 16B. The high potential lead terminal 12 and the low potential lead terminal 13 are power supply lead terminals, with a reference potential applied to the low potential lead terminal 13. Specifically, the low potential lead terminal 13 is a ground lead terminal fixed to ground potential.

[0118] On the first side wall 6A side, the first output lead terminal 16A, the first inverting input lead terminal 15A, the first non-inverting input lead terminal 14A, and the low potential lead terminal 13 are arranged at intervals in this order from the third side wall 6C side toward the fourth side wall 6D side. On the second side wall 6B side, the high potential lead terminal 12, the second output lead terminal 16B, the second inverting input lead terminal 15B, and the second non-inverting input lead terminal 14B are arranged at intervals in this order from the third side wall 6C side toward the fourth side wall 6D side.

[0119] The high potential lead terminal 12 faces the first output lead terminal 16A across the package body 3. The second output lead terminal 16B faces the first inverting input lead terminal 15A across the package body 3. The second inverting input lead terminal 15B faces the first non-inverting input lead terminal 14A across the package body 3. The second non-inverting input lead terminal 14B faces the low potential lead terminal 13 across the package body 3.

[0120] Each of the multiple lead terminals 11 has an inner end 17, an outer end 18, and a lead portion 19. The inner end 17 is located within the package body 3 and has a plate surface parallel to the mounting surface 4 (non-mounting surface 5). The inner end 17 of each of the multiple lead terminals 11 located at the four corners is formed in an L-shape so as to face two sides of the die pad 7 in a plan view. The outer end 18 is located outside the package body 3 and has a plate surface parallel to the mounting surface 4 (non-mounting surface 5). The lead portion 19 is drawn from the inner end 17 to the outside of the package body 3 and connected to the outer end 18. The lead portion 19 bends toward the mounting surface 4 outside the package body 3 and is connected to the outer end 18 at a height position crossing the mounting surface 4 in the normal direction Z.

[0121] The plurality of lead terminals 11 may have any shape. Furthermore, the high potential lead terminal 12, the low potential lead terminal 13, the first non-inverting input lead terminal 14A, the first inverting input lead terminal 15A, the first output lead terminal 16A, the second non-inverting input lead terminal 14B, the second inverting input lead terminal 15B, and the second output lead terminal 16B may be arranged in any manner and are not limited to the arrangements shown in FIGS. 10 to 13.

[0122] The semiconductor package 202 includes a semiconductor device 201 arranged on the die pad 7 within the package body 3. The semiconductor device 201 is arranged on the non-mounting surface 5 side of the die pad 7 within the package body 3. Similar to the semiconductor device 1 according to the first embodiment, the semiconductor device 201 includes a differential amplifier 21 that amplifies and outputs an input differential signal, and a plurality of terminals 22 electrically connected to the differential amplifier 21. The differential amplifier 21 is formed inside the semiconductor device 201. The plurality of terminals 22 are formed on one surface of the semiconductor device 201. The semiconductor device 201 is arranged on the plate surface on the non-mounting surface 5 side of the die pad 7, with the plurality of terminals 22 facing the non-mounting surface 5 of the package body 3.

[0123] The semiconductor device 201 differs from the semiconductor device 1 according to the first embodiment in that it is a multi-channel type that includes a plurality (two or more) of differential amplifiers 21. In this embodiment, the semiconductor device 201 is a dual-channel type that includes two differential amplifiers 21 as an example of a multi-channel type. The plurality of differential amplifiers 21 include a first differential amplifier 21A and a second differential amplifier 21B.

[0124] The multiple terminals 22 include a single high potential terminal 23, a single low potential terminal 24, multiple non-inverting input terminals 25, multiple inverting input terminals 26, and multiple output terminals 27. The high potential terminal 23 and the low potential terminal 24 are power supply terminals to which a reference potential is applied, and are connected as common terminals to the multiple differential amplifiers 21. Specifically, the low potential terminal 24 is a ground terminal fixed to ground potential.

[0125] The plurality of non-inverting input terminals 25 include a first non-inverting input terminal 25A electrically connected to the first differential amplifier 21A and a second non-inverting input terminal 25B electrically connected to the second differential amplifier 21B. The plurality of inverting input terminals 26 include a first inverting input terminal 26A electrically connected to the first differential amplifier 21A and a second inverting input terminal 26B electrically connected to the second differential amplifier 21B. The plurality of output terminals 27 include a first output terminal 27A electrically connected to the first differential amplifier 21A and a second output terminal 27B electrically connected to the second differential amplifier 21B.

[0126] The semiconductor package 202 includes a conductive bonding material 28 (see the hatched portion in FIG. 12 ) that is interposed between the die pad 7 and the semiconductor device 201 in the package body 3 and bonds the die pad 7 and the semiconductor device 201. The conductive bonding material 28 is made of an insulating adhesive, a metal adhesive, or solder.

[0127] The semiconductor package 202 includes a plurality of (eight in this embodiment) conductive wires 29 that electrically connect the plurality of terminals 22 of the semiconductor device 201 to the corresponding lead terminals 11 within the package body 3. Each of the conductive wires 29 is made of a bonding wire. The conductive wires 29 include at least one of copper wire, gold wire, and aluminum wire.

[0128] The plurality of conductors 29 specifically includes a single high potential conductor 30, a single low potential conductor 31, a plurality of non-inverting input conductors 32, a plurality of inverting input conductors 33, and a plurality of output conductors 34. The plurality of non-inverting input conductors 32 includes a first non-inverting input conductor 32A and a second non-inverting input conductor 32B. The plurality of inverting input conductors 33 includes a first inverting input conductor 33A and a second inverting input conductor 33B. The plurality of output conductors 34 includes a first output conductor 34A and a second output conductor 34B.

[0129] The high potential conductor 30 is connected to the high potential lead terminal 12 and the high potential terminal 23. The low potential conductor 31 is connected to the low potential lead terminal 13 and the low potential terminal 24. The first non-inverting input conductor 32A is connected to the first non-inverting input lead terminal 14A and the first non-inverting input terminal 25A. The second non-inverting input conductor 32B is connected to the second non-inverting input lead terminal 14B and the second non-inverting input terminal 25B.

[0130] The first inverting input conductor 33A is connected to the first inverting input lead terminal 15A and the first inverting input terminal 26A. The second inverting input conductor 33B is connected to the second inverting input lead terminal 15B and the second inverting input terminal 26B. The first output conductor 34A is connected to the first output lead terminal 16A and the first output terminal 27A. The second output conductor 34B is connected to the second output lead terminal 16B and the second output terminal 27B.

[0131] The semiconductor package 202 has a mark 35 indicating the arrangement of the multiple lead terminals 11. In this embodiment, the mark 35 is a recess 36 formed in the third side wall 6C. The recess 36 is recessed in an arc shape from the third side wall 6C toward the fourth side wall 6D in a plan view. This gives the third side wall 6C and the fourth side wall 6D an asymmetric shape, which determines the arrangement of the multiple lead terminals 11. Instead of or in addition to the recess 36, the mark 35 may be a recess formed in the non-mounting surface 5 and / or a mark colored in a different color from the semiconductor package 202. In this case, the mark 35 may be formed near any lead terminal 11 (for example, the first output lead terminal 16A) in a plan view.

[0132] 13 is an electrical circuit diagram showing the electrical structure of the semiconductor device 201 shown in FIG. The semiconductor device 201 includes a first differential amplifier 21A and a second differential amplifier 21B. The first differential amplifier 21A is connected to a high potential terminal 23, a low potential terminal 24, a first non-inverting input terminal 25A, a first inverting input terminal 26A, and a first output terminal 27A, and amplifies and outputs an input differential signal. The first differential amplifier 21A is a rail-to-rail output class AB amplifier that operates in a range in which the potential difference between the first non-inverting input terminal 25A and the first inverting input terminal 26A is the same as the potential difference between the high potential terminal 23 and the low potential terminal 24.

[0133] The second differential amplifier 21B is connected to the high potential terminal 23, the low potential terminal 24, the second non-inverting input terminal 25B, the second inverting input terminal 26B, and the second output terminal 27B, and amplifies and outputs the input differential signal. The second differential amplifier 21B is a Rail-to-Rail output class AB amplifier that operates in such a manner that the potential difference between the second non-inverting input terminal 25B and the second inverting input terminal 26B is in the range of the potential difference between the high potential terminal 23 and the low potential terminal 24.

[0134] Like the differential amplifier 21 according to the first embodiment, the first differential amplifier 21A and the second differential amplifier 21B each include a plurality of (three in this embodiment) constant current circuits 41 to 43, an input circuit 44, an amplifier circuit 45, and an output circuit 46. The configurations of the input circuit 44, amplifier circuit 45, and output circuit 46 of the second differential amplifier 21B are similar to the configurations of the input circuit 44, amplifier circuit 45, and output circuit 46 of the first differential amplifier 21A, so the second differential amplifier 21B is shown in a simplified block diagram, and a specific circuit diagram is not shown.

[0135] Furthermore, since the constant current circuits 41 to 43 of the first differential amplifier 21A and the constant current circuits 41 to 43 of the second differential amplifier 21B have the same configuration, the multiple constant current circuits 41 to 43 are shown in a single circuit diagram on the right side of the page of Fig. 13. The configurations of the multiple constant current circuits 41 to 43, the input circuit 44, the amplifier circuit 45, and the output circuit 46 are the same as those of the differential amplifier 21 according to the first embodiment, so the same reference numerals are used and their description will be omitted.

[0136] Fig. 14 is a plan view showing, in block diagram form, the layout of the internal structure of semiconductor device 201 shown in Fig. 12. Fig. 15 is a schematic cross-sectional view of semiconductor device 201 shown in Fig. 14. Fig. 16 is a plan view in which shield electrode 130 is added to the layout shown in Fig. 14. Fig. 15 shows a simplified cross-sectional structure of semiconductor device 201 and does not show a cross section of a specific location.

[0137] 14 to 16, similar to the semiconductor device 1 according to the first embodiment, the semiconductor device 201 includes a semiconductor chip 100 and a device region 104 defined on a first main surface 101 of the semiconductor chip 100. In this embodiment, the device region 104 includes a constant current region 105, a plurality of input regions 106, a plurality of amplification regions 107, and a plurality of output regions 108 defined at intervals from one another.

[0138] The multiple input regions 106 include a first input region 106A and a second input region 106B. The multiple amplification regions 107 include a first amplification region 107A and a second amplification region 107B. The multiple output regions 108 include a first output region 108A and a second output region 108B. The constant current region 105, the multiple input regions 106, and the multiple amplification regions 107 form a single differential amplification region 109.

[0139] The constant current region 105 is defined in the center of the first main surface 101. The constant current region 105 is defined in a quadrangular shape in plan view. In this embodiment, the constant current region 105 is defined in a rectangular shape extending along the first direction X in plan view.

[0140] The first input region 106A is defined in the first main surface 101 as a region between the first side surface 103A and the constant current region 105. The first input region 106A is defined in a region near a corner connecting the first side surface 103A and the fourth side surface 103D. The first input region 106A is defined in a quadrangular shape in plan view. In this embodiment, the first input region 106A is defined in a rectangular shape extending along the first direction X in plan view.

[0141] First amplification region 107A is defined as a region between constant current region 105 and first input region 106A on first main surface 101. In this embodiment, first amplification region 107A is defined in an L-shape facing first input region 106A from two directions, that is, from second side surface 103B side and third side surface 103C side, in plan view.

[0142] The first output region 108A is defined in a region between the third side surface 103C and the first amplification region 107A on the first main surface 101. The first output region 108A is defined in a region near a corner connecting the first side surface 103A and the third side surface 103C. The first output region 108A may face the constant current region 105 in the first direction X. The first output region 108A faces the first input region 106A across the first amplification region 107A.

[0143] The second input region 106B is defined as a region between the second side surface 103B and the constant current region 105. The second input region 106B is defined as a region near a corner of the first main surface 101 that connects the second side surface 103B and the fourth side surface 103D. The second input region 106B is defined as a quadrangle in plan view. In this embodiment, the second input region 106B is defined as a rectangle extending along the first direction X in plan view.

[0144] Second amplification region 107B is defined as a region between constant current region 105 and second input region 106B on first main surface 101. In this embodiment, second amplification region 107B is defined in an L-shape facing second input region 106B from two directions, that is, from first side surface 103A side and third side surface 103C side, in a plan view.

[0145] The second output region 108B is defined in a region between the third side surface 103C and the second amplification region 107B on the first main surface 101. The second output region 108B is defined in a region near a corner connecting the second side surface 103B and the third side surface 103C, and faces the first output region 108A in the second direction Y. The second output region 108B may face the constant current region 105 in the first direction X. The second output region 108B faces the second input region 106B across the second amplification region 107B.

[0146] The arrangement and planar shapes of the constant current region 105, first input region 106A, second input region 106B, first amplification region 107A, second amplification region 107B, first output region 108A, and second output region 108B are arbitrary and are not limited to specific locations or shapes.

[0147] The semiconductor device 201 includes a plurality of differential amplifiers 21 formed in the device region 104. The plurality of differential amplifiers 21 include a first differential amplifier 21A and a second differential amplifier 21B. The first differential amplifier 21A is fabricated in a region on the first side surface 103A side, and the second differential amplifier 21B is fabricated in a region on the second side surface 103B side of the first differential amplifier 21A.

[0148] The first differential amplifier 21A includes a plurality of constant current circuits 41 to 43 formed in the constant current region 105, an input circuit 44 formed in the first input region 106A, an amplifier circuit 45 formed in the first amplification region 107A, and an output circuit 46 formed in the first output region 108A.

[0149] The second differential amplifier 21B includes a plurality of constant current circuits 41 to 43 formed in the constant current region 105, an input circuit 44 formed in the second input region 106B, an amplifier circuit 45 formed in the second amplification region 107B, and an output circuit 46 formed in the second output region 108B. The plurality of constant current circuits 41 to 43 of the second differential amplifier 21B are integrated into one constant current region 105 together with the plurality of constant current circuits 41 to 43 of the first differential amplifier 21A.

[0150] Each of the differential amplifiers 21 includes a plurality of transistors fabricated on the first main surface 101. In Fig. 15, the structure of the differential amplifiers 21 is shown in a simplified manner using a semiconductor region 110 on the semiconductor chip 100 side and an electrode structure 111 (see hatched portion) on the upper side of the semiconductor chip 100.

[0151] 15, similarly to the semiconductor device 1 according to the first embodiment, the semiconductor device 201 includes an insulating layer 120 (multilayer wiring structure 123) stacked on the first main surface 101 and collectively covering the device region 104 (constant current region 105, multiple input regions 106, multiple amplification regions 107, and multiple output regions 108). In this embodiment, multiple first to third wiring layers 122A to 122C each form a part of the wiring section of the circuit diagram shown in FIG.

[0152] 14 and 16, the high potential terminal 23, the low potential terminal 24, the first non-inverting input terminal 25A, the first inverting input terminal 26A, the first output terminal 27A, the second non-inverting input terminal 25B, the second inverting input terminal 26B, and the second output terminal 27B are formed as the uppermost third wiring layer 122C on the uppermost third interlayer insulating layer 121C with intervals therebetween. The high potential terminal 23, the low potential terminal 24, the first non-inverting input terminal 25A, the first inverting input terminal 26A, the first output terminal 27A, the second non-inverting input terminal 25B, the second inverting input terminal 26B, and the second output terminal 27B are each formed in a quadrangular shape in a plan view.

[0153] The high potential terminal 23 is disposed adjacent to the second output region 108B in a planar view. Specifically, the high potential terminal 23 is disposed in the region between the third side surface 103C and the second output region 108B in a planar view. The low potential terminal 24 is disposed adjacent to the first input region 106A in a planar view. Specifically, the low potential terminal 24 is disposed in the region between the fourth side surface 103D and the first input region 106A in a planar view.

[0154] The first non-inverting input terminal 25A is disposed adjacent to the first input region 106A in a plan view. Specifically, the first non-inverting input terminal 25A is disposed in a region between the first side surface 103A and the first input region 106A in a plan view.

[0155] The first inverting input terminal 26A is disposed adjacent to the first input region 106A in a plan view. Specifically, the first inverting input terminal 26A is disposed in a region between the first side surface 103A and the first input region 106A in a plan view. The first inverting input terminal 26A is disposed at a distance from the first non-inverting input terminal 25A toward the third side surface 103C, and faces the first non-inverting input terminal 25A in the first direction X.

[0156] The first output terminal 27A is disposed adjacent to the first output region 108A in a plan view. Specifically, the first output terminal 27A is disposed in a region between the third side surface 103C and the first output region 108A in a plan view.

[0157] The second non-inverting input terminal 25B is disposed adjacent to the second input region 106B in plan view. Specifically, the second non-inverting input terminal 25B is disposed in a region between the fourth side surface 103D and the second input region 106B in plan view. The second non-inverting input terminal 25B is disposed at a distance from the low potential terminal 24 toward the second side surface 103B, and faces the low potential terminal 24 in the second direction Y.

[0158] The second inverting input terminal 26B is disposed adjacent to the second input region 106B in a plan view. Specifically, the second inverting input terminal 26B is disposed in a region between the second side surface 103B and the second input region 106B in a plan view.

[0159] The second output terminal 27B is arranged adjacent to the second output region 108B in a planar view. Specifically, the second output terminal 27B is arranged in a region between the second side surface 103B and the second output region 108B in a planar view. The second output terminal 27B may be arranged adjacent to the second amplification region 107B. That is, a part or all of the second output terminal 27B may be arranged in a region between the second side surface 103B and the second amplification region 107B in a planar view. The second output terminal 27B is arranged at a distance from the second inverting input terminal 26B toward the third side surface 103C, and faces the second inverting input terminal 26B in the first direction X.

[0160] 16, similar to the semiconductor device 1 according to the first embodiment, the semiconductor device 201 includes a shield electrode 130 disposed on the first main surface 101 so as to conceal the device region 104 and fixed to ground potential. Specifically, the shield electrode 130 is incorporated in the insulating layer 120 (multilayer wiring structure 123). The shield electrode 130 blocks external electromagnetic waves. An example of the external electromagnetic waves is an electromagnetic interference signal formed of an RF (radio frequency) signal or the like outside the operating frequency band of the differential amplifier 21 (first differential amplifier 21A and second differential amplifier 21B).

[0161] The shield electrode 130 has a shield frequency band in the range of 1 MHz to 5 GHz, inclusive. This shield electrode 130 can adequately shield electromagnetic interference signals in the range of 1 MHz to 5 GHz, inclusive. It is particularly preferable that the shield electrode 130 has a shield frequency band in the range of at least 1 MHz to 2 GHz, inclusive.

[0162] The shield electrode 130 forms one of any of the first to third wiring layers 122A to 123C in the multilayer wiring structure 123, and is disposed on any of the interlayer insulating layers 121. In this embodiment, the shield electrode 130 forms one of the uppermost third wiring layers 122C in the multilayer wiring structure 123, and is disposed on the uppermost third interlayer insulating layer 121C.

[0163] In this embodiment, the shield electrode 130 conceals the constant current region 105, the plurality of input regions 106, the plurality of amplification regions 107, and the plurality of output regions 108. Specifically, the shield electrode 130 integrally includes a first shield electrode 131 concealing the constant current region 105, a plurality of second shield electrodes 132 concealing the plurality of input regions 106, a plurality of third shield electrodes 133 concealing the plurality of amplification regions 107, and a plurality of fourth shield electrodes 134 concealing the plurality of output regions 108.

[0164] The first shield electrode 131 shields electromagnetic waves directed from the outside toward the constant current region 105, and suppresses noise and malfunction in the constant current region 105. It is preferable that the first shield electrode 131 shields the entire constant current region 105.

[0165] The plurality of second shield electrodes 132 includes a second shield electrode 132A that conceals the first input area 106A and a second shield electrode 132B that conceals the second input area 106B. The plurality of second shield electrodes 132 shield electromagnetic waves traveling from the outside toward the corresponding input area 106, and suppress noise and malfunctions in the corresponding input area 106. It is preferable that the plurality of second shield electrodes 132 each conceal the entire area of ​​the corresponding input area 106.

[0166] The plurality of third shield electrodes 133 includes a third shield electrode 133A that conceals the first amplification region 107A and a third shield electrode 133B that conceals the second amplification region 107B. The plurality of third shield electrodes 133 shields electromagnetic waves directed from the outside toward the corresponding amplification region 107, and suppresses noise and malfunctions in the corresponding amplification region 107. It is preferable that the plurality of third shield electrodes 133 each conceal the entire area of ​​the corresponding amplification region 107.

[0167] The plurality of fourth shield electrodes 134 includes a fourth shield electrode 134A that conceals the first output region 108A and a fourth shield electrode 134B that conceals the second output region 108B. The plurality of fourth shield electrodes 134 shield electromagnetic waves traveling from the outside toward the corresponding output region 108, and suppress noise and malfunctions in the corresponding output region 108. It is preferable that the plurality of fourth shield electrodes 134 each conceal the entire area of ​​the corresponding output region 108.

[0168] In this embodiment, the first shield electrode 131, the plurality of second shield electrodes 132, and the plurality of third shield electrodes 133 form a differential amplification shield electrode 135 that collectively shields the differential amplification region 109 including the constant current region 105, the plurality of input regions 106, and the plurality of amplification regions 107. Meanwhile, the plurality of fourth shield electrodes 134 form an output shield electrode 136 that shields the plurality of output regions 108.

[0169] The shield electrode 130 extends toward the low potential terminal 24 and includes a shield connection portion 137 electrically connected to the low potential terminal 24. The shield connection portion 137 may be routed in any manner as long as it is connected to the low potential terminal 24. In this embodiment, the shield electrode 130 is formed integrally with the low potential terminal 24 and is fixed to ground potential. In other words, the shield electrode 130 forms one uppermost third wiring layer 122C between itself and the low potential terminal 24.

[0170] In this way, first differential amplifier 21A is concealed by the integrated portion of first shield electrode 131, second shield electrode 132A, third shield electrode 133A, and fourth shield electrode 134A. Also, second differential amplifier 21B is concealed by the integrated portion of first shield electrode 131, second shield electrode 132B, third shield electrode 133B, and fourth shield electrode 134B.

[0171] The shield electrode 130 only needs to include at least one of the first to fourth shield electrodes 131 to 134, and does not necessarily need to include all of the first to fourth shield electrodes 131 to 134. It is preferable that the shield electrode 130 has at least one of the first shield electrode 131 that conceals the constant current region 105 and the plurality of second shield electrodes 132 that conceal the plurality of input regions 106 among the first to fourth shield electrodes 131 to 134.

[0172] In this case, it is particularly preferable that the shield electrode 130 has both the first shield electrode 131 and a plurality of second shield electrodes 132. It is most preferable that the shield electrode 130 includes all of the first to fourth shield electrodes 131 to 134. Furthermore, the first to fourth shield electrodes 131 to 134 only need to be fixed to the ground potential, and do not necessarily have to be formed integrally. At least one of the first to fourth shield electrodes 131 to 134 may be formed separately.

[0173] Although specific illustrations are omitted, the shield electrode 130 includes a plurality of through holes 138 that expose the underlying insulating layer 120, similar to the semiconductor device 1 according to the first embodiment (see also FIGS. 8A and 8B). The structure of the plurality of through holes 138 is similar to the plurality of through holes 138 according to the first embodiment, and therefore a description of the plurality of through holes 138 will be omitted.

[0174] 15 again, the semiconductor device 201 includes a protective layer 140 (an inorganic insulating film 142 and an organic insulating film 143) that covers the insulating layer 120 (a multilayer wiring structure 123) similar to the semiconductor device 1 according to the first embodiment. The protective layer 140 covers the entire shield electrode 130 and has a plurality of pad openings 141 in an area outside the shield electrode 130.

[0175] The plurality of pad openings 141 expose, as pad portions, a portion of the high potential terminal 23, a portion of the low potential terminal 24, a portion of the first non-inverting input terminal 25A, a portion of the second non-inverting input terminal 25B, a portion of the first inverting input terminal 26A, a portion of the second inverting input terminal 26B, a portion of the first output terminal 27A, and a portion of the second output terminal 27B. Description of other structures of the protective layer 140 will be omitted as they are the same as those of the protective layer 140 according to the first embodiment.

[0176] As described above, even in a structure including a plurality of differential amplifiers 21, such as the semiconductor device 201, it is possible to achieve the same effects as those described for the semiconductor device 1 according to the first embodiment.

[0177] Fig. 17 is a plan view corresponding to Fig. 16, and is a plan view for explaining the structure of a semiconductor device 211 according to a fourth embodiment of the present invention. In the following, structures corresponding to those described for the semiconductor device 201 are given the same reference numerals, and descriptions thereof will be omitted.

[0178] 17, semiconductor device 211 includes a slit 152 in shield electrode 130 that borders differential amplifier shield electrode 135. Slit 152 externally defines differential amplifier region 109, which includes constant current region 105, input region 106, and amplifier region 107, in plan view. Slit 152 extends in a C-shape in plan view so as to leave the connection portion between differential amplifier shield electrode 135 and output shield electrode 136.

[0179] The semiconductor device 211 includes a guard electrode 153 that is formed along the periphery of the differential amplifier shield electrode 135 at a distance from the differential amplifier shield electrode 135 and is fixed to ground potential. The guard electrode 153 forms one of the uppermost third wiring layers 122C in the multilayer wiring structure 123 and is disposed on the uppermost third interlayer insulating layer 121C. The guard electrode 153 is formed in a strip shape that extends along the differential amplifier shield electrode 135 so as to define the differential amplifier shield electrode 135 from the outside in a plan view. The guard electrode 153 extends in a C-shape in a plan view.

[0180] The guard electrode 153 is formed on the third interlayer insulating layer 121C independently (separately) from the low potential terminal 24 and the shield electrode 130. In this embodiment, the guard electrode 153 is electrically connected to the low potential terminal 24 via any of the first and second wiring layers 122A and 122B and any of the first to third via electrodes 124 to 126. Of course, the guard electrode 153 may include a connection portion electrically connected to the low potential terminal 24 on the third interlayer insulating layer 121C. In other words, the guard electrode 153 may be formed integrally with the low potential terminal 24 and the shield electrode 130.

[0181] As described above, the semiconductor device 211 can also achieve the same effects as those described for the semiconductor device 1. The semiconductor device 211 also includes a guard electrode 153 formed in a strip shape along the differential amplifier shield electrode 135. This allows the guard electrode 153 to absorb an ESD surge voltage when it is applied to any of the high potential terminal 23, the low potential terminal 24, the plurality of non-inverting input terminals 25, the plurality of inverting input terminals 26, and the plurality of output terminals 27. As a result, the electrostatic discharge resistance can be improved.

[0182] The present invention can be embodied in other forms.

[0183] In each of the above-described embodiments, the various transistors included in the differential amplifier 21 (constant current circuits 41 to 43, input circuit 44, amplifier circuit 45, and output circuit 46) may be formed using CMOS transistors. That is, the differential amplifier 21 may be a CMOS differential amplifier. CMOS differential amplifiers have the advantages of low power consumption and high input impedance, but have a structural problem in that noise is easily generated in CMOS transistors. In this regard, by concealing the CMOS differential amplifier with the shield electrode 130, noise components caused by external electromagnetic waves in the CMOS transistors can be reduced.

[0184] In each of the above-described embodiments, if there is no problem with the design rules for the first and second wiring layers 122A and 122B, the shield electrode 130 may be disposed on the interlayer insulating layer (first and second interlayer insulating layers 121A and 121B) located below the uppermost interlayer insulating layer (third interlayer insulating layer 121C).

[0185] In each of the above-described embodiments, the semiconductor chip 100 may include a p-type (first conductivity type) or n-type (second conductivity type) semiconductor substrate. The semiconductor chip 100 may also include a p-type or n-type epitaxial layer formed on the p-type or n-type semiconductor substrate.

[0186] In each of the above-described embodiments, the protective layer 140 made of either the inorganic insulating film 142 or the organic insulating film 143 may be employed.

[0187] In the first and second embodiments described above, an example was described in which three constant current circuits, the first to third constant current circuits 41 to 43, were formed. However, instead of the three constant current circuits 41 to 43, a system in which a constant current is diverted from one constant current circuit (the first constant current generating circuit 47 and the second constant current generating circuit 48) to various circuits may be employed.

[0188] In the first and second embodiments described above, an example was described in which the three first to third constant current circuits 41 to 43 were formed in one constant current region 105. However, the three first to third constant current circuits 41 to 43 may be formed in two or more constant current regions 105 that are partitioned into any regions with a gap between them. In this case, it is sufficient that the corresponding constant current regions 105 are each covered by two or more first shield electrodes 131.

[0189] In the third and fourth embodiments described above, examples have been described in which the high potential terminal 23 and the low potential terminal 24 are formed as common terminals for the first differential amplifier 21A and the second differential amplifier 21B, respectively. However, a plurality of high potential terminals 23 to which high potentials are applied individually to the first differential amplifier 21A and the second differential amplifier 21B may be formed. Also, a plurality of low potential terminals 24 to which low potentials are applied individually to the first differential amplifier 21A and the second differential amplifier 21B may be formed.

[0190] In the third and fourth embodiments described above, an example was described in which three first to third constant current circuits 41 to 43 were formed for the first differential amplifier 21A and three first to third constant current circuits 41 to 43 were formed for the second differential amplifier 21B. However, instead of the six constant current circuits 41 to 43, a system may be employed in which a constant current is diverted from one constant current circuit (first constant current generating circuit 47 and second constant current generating circuit 48) to various circuits of the first differential amplifier 21A and the second differential amplifier 21B.

[0191] In the third and fourth embodiments described above, an example was described in which three first to third constant current circuits 41 to 43 are formed for the first differential amplifier 21A and three first to third constant current circuits 41 to 43 are formed for the second differential amplifier 21B. However, the six first to third constant current circuits 41 to 43 may each be formed in two or more constant current regions 105 that are partitioned into any desired regions with a gap between them. For example, the constant current region 105 for the first differential amplifier 21A and the constant current region 105 for the second differential amplifier 21B may each be partitioned into any desired regions with a gap between them. In these cases, it is sufficient that two or more first shield electrodes 131 cover the corresponding constant current regions 105.

[0192] In the third and fourth embodiments described above, examples have been described in which the die pad 7 in the semiconductor package 202 is formed in an electrically floating state. However, the semiconductor package 202 may also adopt a configuration in which the die pad 7 is fixed to ground potential, as in the semiconductor packages 2 according to the first and second embodiments described above. For example, the inner end 17 of the low potential lead terminal 13 in the semiconductor package 202 may be formed integrally with the die pad 7, and the die pad 7 may be fixed to the same potential. In this case, the die pad 7 may also serve as a shield plate that blocks external electromagnetic waves.

[0193] In the first and second embodiments described above, a semiconductor package 2 shown in Fig. 18 may be employed. Fig. 18 is a cross-sectional view showing a modification of the semiconductor package 2 shown in Fig. 1.

[0194] 18, the die pad 7 is arranged on the non-mounting surface 5 side within the package body 3. The plurality of lead terminals 11 are bent towards the mounting surface 4 side outside the package body 3. The semiconductor device 1 is arranged on the mounting surface 4 side of the package body 3 with respect to the die pad 7 within the package body 3. The semiconductor device 1 is arranged on the plate surface on the mounting surface 4 side of the die pad 7 with the plurality of terminals 22 facing the mounting surface 4 of the package body 3.

[0195] The plurality of conductors 29 connect the corresponding lead terminals 11 to the corresponding terminals 22 in the same manner as in the semiconductor package 2 according to the first embodiment, thereby fixing the die pad 7 and the shield electrode 130 to the ground potential.

[0196] Such a semiconductor package 2 can also improve the EMI resistance of the semiconductor device 1 when mounted on the semiconductor package 2. If the semiconductor package 2 is mounted on a connection target and there is little influence of electromagnetic waves from the connection target, the shield electrode 130 may be removed from the semiconductor device 1. An example of a case where there is little influence of electromagnetic waves from the connection target is when the connection target is provided with an electromagnetic shield that blocks external electromagnetic waves. The structure of the semiconductor package 2 according to the modified example can also be applied to the semiconductor packages 202 according to the third and fourth embodiments.

[0197] This application corresponds to Japanese Patent Application No. 2019-223029 filed with the Japan Patent Office on December 10, 2019, the entire disclosure of which is incorporated herein by reference. Although the embodiments of the present invention have been described in detail, these are merely specific examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these specific examples, and the scope of the present invention is limited by the appended claims. [Explanation of symbols]

[0198] 1. Semiconductor device 21 Differential Amplifier 24 Low potential terminal (ground terminal) 41 1st constant current circuit 42 2nd constant current circuit 43 3rd constant current circuit 44 Input circuit 45 Amplification circuit 46 Output circuit 49 First current mirror circuit 50 Second current mirror circuit 55 Third current mirror circuit 56 4th current mirror circuit 61 1st differential circuit 62 Second differential circuit 63A First differential transistor 63B First differential transistor 64A Second Differential Transistor 64B Second differential transistor 71 First current folding circuit 72 Second current folding circuit 73 Class AB control circuit 74A First bias transistor 74B First bias transistor 75A Second Bias Transistor 75B Second bias transistor 81A output transistor 81B output transistor 82 Push-pull circuit 100 semiconductor chips 101 First main surface 104 Device Area 105 Constant current region 106 Input Area 107 Amplified Region 108 Output Area 120 insulating layer 121 Interlayer insulating layer 122 wiring layer 123 Multilayer wiring layer 130 Shield electrode 138 Through Hole 140 Protective layer 142 Inorganic insulating film 143 Organic insulating film 151 Semiconductor devices 201 Semiconductor devices 211 Semiconductor devices

Claims

1. a semiconductor chip having a main surface; a device region defined on the main surface; a differential amplifier formed in the device region, which amplifies and outputs an input differential signal; a shield electrode disposed on the main surface so as to conceal the device region in a plan view; an insulating layer that is formed on the main surface and covers the device region, the insulating layer being a multilayer wiring layer in which a plurality of interlayer insulating layers and a plurality of wiring layers are alternately stacked; a protective layer including an inorganic insulating film and covering the shield electrode; a ground terminal formed in the uppermost wiring layer and fixed to a ground potential; the shield electrode forms a part of the uppermost wiring layer on the uppermost interlayer insulating layer and includes a plurality of through holes; the inorganic insulating film covers the shield electrode, penetrates into the plurality of through holes, and contacts the uppermost interlayer insulating layer within the plurality of through holes; the device region includes an input region and a constant current region; the differential amplifier includes an input circuit formed in the input region, and a constant current circuit formed in the constant current region and generating a constant current; the input circuit includes a differential circuit electrically connected to the constant current circuit and converting the input differential signal into a differential current; the input region and the constant current region are defined on the main surface with a gap between them, the shield electrode integrally includes a first shield electrode that conceals the entire input region in a planar view and a second shield electrode that conceals the entire constant current region in a planar view, and is formed integrally with the ground terminal.

2. the device region further comprises an amplification region and an output region; 2. The semiconductor device according to claim 1, wherein the differential amplifier further includes: an amplifier circuit formed in the amplification region that amplifies the differential current to generate an amplified current; and an output circuit formed in the output region that generates an output current corresponding to the amplified current.

3. The input region, the constant current region, the amplification region, and the output region are partitioned on the main surface at intervals from one another, 3. The semiconductor device according to claim 2, wherein the shield electrode further integrally includes a third shield electrode that shields the entire amplification region in a plan view, and a fourth shield electrode that shields the entire output region in a plan view.

4. the differential circuit includes a pair of differential transistors forming a differential connection; the amplifier circuit includes a current folding circuit including a pair of bias transistors that are cascode-connected with the differential circuit and that form a folded cascode circuit between the differential circuit and the current folding circuit, 4. The semiconductor device according to claim 2, wherein said output circuit includes a push-pull circuit including a pair of output transistors forming a push-pull connection.

5. the amplifier circuit includes a class AB control circuit connected to the current folding circuit and generating a class AB control signal according to the amplified current generated by the current folding circuit; 5. The semiconductor device according to claim 4, wherein said push-pull circuit is connected to said class AB control circuit and generates said output current corresponding to said amplified current in response to said class AB control signal.

6. 6. The semiconductor device according to claim 1, wherein the constant current circuit includes a current mirror circuit.

7. 7. The semiconductor device according to claim 6, wherein said protective layer has a pad opening that exposes a portion of said ground terminal.

8. 8. The semiconductor device according to claim 1, wherein each of the plurality of through holes has a size smaller than the wavelength of the electromagnetic wave to be shielded.

9. 9. The semiconductor device according to claim 1, wherein the plurality of through holes are arranged in a staggered pattern, a matrix pattern, or a concentric pattern in a plan view.

10. 10. The semiconductor device according to claim 1, wherein the shield electrode includes an Al-based metal film.

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