Semiconductor device, package, and method of manufacturing the semiconductor device

Abstract

The semiconductor device according to the present disclosure comprises a structure having a cavity that opens upward, a semiconductor chip provided at the bottom of the cavity within the structure, and a molded resin that covers the structure, wherein the bottom of the cavity has a first portion formed of metal and a second portion that has a higher adhesion to the molded resin than the first portion and is provided outside the first portion and at the end of the bottom.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device, a package, and a method for manufacturing a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a wiring board having a plurality of insulating layers and a plurality of conductor layers. The wiring board has a cavity that opens on one side. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-146983 Summary of the Invention [Problem to be solved by the invention]

[0004] A package is sometimes formed by molding a substrate having a cavity structure such as that described in Patent Document 1. In such packages, the cavity bottom and wire bond pads are sometimes plated with gold. However, the adhesion between the gold plating and the mold resin is generally poor. For this reason, when reflow is performed after moisture absorption, there is a risk of peeling occurring at the interface between the cavity bottom and the mold resin, and at the interface between the wire bond pads and the mold resin.

[0005] An object of the present disclosure is to provide a semiconductor device, a package, and a method for manufacturing a semiconductor device that can suppress peeling of a molding resin. [Means for solving the problem]

[0006] A semiconductor device according to a first disclosure includes a structure in which a cavity that opens upward is formed, a semiconductor chip provided in the structure at the bottom of the cavity, and a molding resin that covers the structure, wherein the bottom of the cavity has a first portion formed of metal and a second portion that has higher adhesion to the molding resin than the first portion and is provided outside the first portion and at an end of the bottom. As the second portion, a solder resist is provided at a corner formed by the side surface and the bottom of the cavity, and a surface of the solder resist that comes into contact with the molding resin is a curved surface. do. The semiconductor device according to the second disclosure comprises a structure having a cavity formed therein that is open upward, a semiconductor chip provided at the bottom of the cavity within the structure, and a molded resin covering the structure, wherein the bottom of the cavity has a first portion formed of metal and a second portion that has higher adhesion to the molded resin than the first portion and is provided outside the first portion and at an end of the bottom, the bottom having a first metal layer and a second metal layer formed of a metal that has higher adhesion to the molded resin than the first metal layer and is provided below the first metal layer, the second portion being an exposed portion where the second metal layer is exposed from the first metal layer, and the surface of the second metal layer at the exposed portion is rougher than the surface of the first metal layer.

[0007] No. 3 The semiconductor device disclosed in the above item includes a structure having a cavity formed therein that is open upward, a protrusion provided on the bottom of the cavity of the structure, a semiconductor chip provided on the protrusion, and a molding resin that covers the structure, and the bottom has a portion on the outside of the protrusion: The convex portion is recessed relative to the protruding surface. A groove is formed.

[0009] No. 6 The method for manufacturing a semiconductor device according to the disclosure includes forming a first metal layer on a second metal layer that forms the bottom of a structure having a cavity that opens upward, removing at least a portion of the first metal layer that is provided at an end of the bottom to form an exposed portion where the second metal layer is exposed from the first metal layer, mounting a semiconductor chip on the bottom, covering the structure, the semiconductor chip, and the exposed portion with a molding resin, and forming the second metal layer to have higher adhesion to the molding resin than the first metal layer. The structure has a heat sink on which the semiconductor chip is mounted and a printed circuit board surrounding the semiconductor chip. . [Effects of the Invention]

[0010] In the semiconductor device according to the first disclosure, the second portion that has high adhesion to the molding resin is formed at the edge of the cavity where stress tends to concentrate and become the starting point for peeling, thereby preventing peeling of the molding resin. In the semiconductor device according to the second disclosure, even if peeling occurs at the edge of the cavity where stress is concentrated and peeling is likely to start, the grooves can suppress the progression of the peeling. Furthermore, even if the peeling progresses beyond the grooves, the protrusions can suppress the progression of the peeling. In the package according to the third disclosure, the second portion has a rougher surface than the first portion, which can prevent the molding resin from peeling off from the wire bond pad. In the semiconductor device manufacturing method according to the fourth disclosure, exposed portions of the second metal layer that have high adhesion to the molding resin are formed at the edges of the cavity where stress tends to concentrate and become the starting point for peeling, thereby preventing peeling of the molding resin. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a semiconductor device according to a first embodiment. [Figure 3A] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3B] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3C] 2A to 2C are diagrams illustrating a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] FIG. 10 is a cross-sectional view of a semiconductor device according to a comparative example. [Figure 5] FIG. 10 is a plan view of a semiconductor device according to a first modification of the first embodiment. [Figure 6] FIG. 10 is a plan view of a semiconductor device according to a second modification of the first embodiment. [Figure 7] 10 is a cross-sectional view taken along line AB of a semiconductor device according to a second modification of the first embodiment. FIG. [Figure 8] FIG. 10 is a plan view of a semiconductor device according to a third modification of the first embodiment. [Figure 9] FIG. 10 is a plan view of a semiconductor device according to a fourth modification of the first embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor device according to a fifth modification of the first embodiment. [Figure 11] FIG. 13 is a plan view of a semiconductor device according to a sixth modification of the first embodiment. [Figure 12] FIG. 13 is a plan view of a semiconductor device according to a seventh modification of the first embodiment. [Figure 13] FIG. 10 is a cross-sectional view of a semiconductor device according to a second embodiment. [Figure 14] FIG. 10 is a plan view of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a plan view of a semiconductor device according to a first modification of the second embodiment. [Figure 16] FIG. 10 is a cross-sectional view of a semiconductor device according to a second modification of the second embodiment. [Figure 17] FIG. 10 is a plan view of a semiconductor device according to a third modification of the second embodiment. [Figure 18] FIG. 10 is a plan view of a semiconductor device according to a fourth modification of the second embodiment. [Figure 19] FIG. 10 is a cross-sectional view of a semiconductor device according to a third embodiment. [Figure 20] FIG. 10 is a plan view of a semiconductor device according to a third embodiment. [Figure 21] 10 is a flowchart illustrating a method for manufacturing a semiconductor device according to a third embodiment. [Figure 22] FIG. 13 is a plan view of a semiconductor device according to a first modification of the third embodiment. [Figure 23] FIG. 13 is a plan view of a semiconductor device according to a second modification of the third embodiment. [Figure 24] FIG. 10 is a plan view showing a wire bond pad according to a fourth embodiment. [Figure 25] FIG. 10 is a cross-sectional view showing a wire bond pad according to a fourth embodiment. [Figure 26] FIG. 10 is a plan view showing a wire bond pad according to a fifth embodiment. [Figure 27] FIG. 10 is a cross-sectional view showing a wire bond pad according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] The semiconductor device, package, and method of manufacturing the semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components are designated by the same reference numerals, and repeated description may be omitted.

[0013] Embodiment 1 FIG. 1 is a cross-sectional view of a semiconductor device 100 according to a first embodiment. FIG. 2 is a plan view of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 includes a structure 10 in which a cavity 16 that opens upward is formed. A semiconductor chip 20 is provided at the bottom of the cavity 16 of the structure 10. The semiconductor chip 20 is joined to the bottom of the cavity 16 with solder 22 or the like. The structure 10 is covered with a molded resin 50.

[0014] Specifically, the structure 10 has a heat sink 13 on which a semiconductor chip 20 is mounted, and a printed circuit board 14 that surrounds the semiconductor chip 20. The heat sink 13 is made of metal. The printed circuit board 14 has multiple insulating layers and multiple conductor layers that are alternately stacked. The multiple conductor layers are connected to each other by via holes. The configuration of the structure 10 shown in FIG. 1 is one example, and any configuration that has a cavity 16 can be used for the structure 10. For example, a printed circuit board may be provided in place of the heat sink 13.

[0015] The bottom of the cavity 16 has a first portion 61 made of metal and a second portion 62 provided outside the first portion 61 and at the end of the bottom of the cavity 16. The second portion 62 has stronger adhesion to the molded resin 50 than the first portion 61. In this embodiment, the second portion 62 is provided as a solder resist 70 at a corner formed by the side surface and bottom of the cavity 16. The solder resist 70 is provided so as to surround the semiconductor chip 20 in a plan view, for example.

[0016] Chip components 42 and wire bond pads 30 are provided on the printed circuit board 14. The chip components 42 are capacitors, resistors, inductors, etc. The wire bond pads 30 are connected to the semiconductor chip 20 via wires 40.

[0017] 3A to 3C are diagrams illustrating a manufacturing method of the semiconductor device 100 according to the first embodiment. First, as shown in FIG. 3A, a printed circuit board 14 is mounted on a metal layer 12, which is a heat sink, to form a cavity 16. At this time, the metal layer 32 and the metal layer 12 on the printed circuit board 14 are formed of, for example, Cu. Next, as shown in FIG. 3B, a solder resist 70 is formed on the corners of the cavity 16. Next, as shown in FIG. 3C, a metal layer 11 is formed on the metal layer 12, and a metal layer 31 is formed on the metal layer 32. The metal layers 11 and 31 are formed by, for example, Au plating. This forms the heat sink 13 and the wire bond pad 30.

[0018] Cu forming metal layer 12 has higher adhesion to mold resin 50 than Au forming metal layer 11. In other words, the bottom of cavity 16 has metal layer 11 and metal layer 12 formed from a metal that has higher adhesion to mold resin 50 than metal layer 11 and provided below metal layer 11. Solder resist 70 is provided on the exposed portion where metal layer 12 is exposed from metal layer 11.

[0019] FIG. 4 is a cross-sectional view of a semiconductor device 800 according to a comparative example. In the semiconductor device 800, a cavity is formed in the structure 10, similar to the semiconductor device 100 of the present embodiment. Because Au plating is a poorly adhesive material, the adhesive strength between the molded resin 50 and the Au plating on the surface of the structure 10 is low. Therefore, in a structure such as that shown in FIG. 4, stress is concentrated at the corners of the cavity, which are likely to become the starting point for peeling of the molded resin 50. Peeling of the molded resin 50 is particularly likely to occur during reflow after moisture absorption. Specifically, peeling may occur in region A1 in FIG. 4.

[0020] In contrast, in this embodiment, solder resist 70 is provided at the corners of cavity 16. This can alleviate stress concentration and prevent peeling from occurring. Therefore, peeling at the interface between the bottom of cavity 16 and molded resin 50 can be prevented.

[0021] Furthermore, the solder resist 70 adheres not to the metal layer 11, which is Au plated, but to the underlying metal layer 12, which is made of Cu, Ni, or the like. This improves the adhesive strength of the solder resist 70. Note that the configuration in which the solder resist 70 is provided on the exposed portion where the metal layer 12 is exposed from the metal layer 11 is not essential to this embodiment.

[0022] In the semiconductor device 100, the solder resist 70 is provided around the entire periphery of the cavity 16. In contrast, the solder resist 70 may be provided on at least some of the corners of the cavity 16. For example, the solder resist 70 may be provided on only some of the four sides of the cavity 16.

[0023] 5 is a plan view of a semiconductor device 100a according to a first modification of the first embodiment. In the semiconductor device 100a, the width of the solder resist 70 is wider than that of the semiconductor device 100. This increases the bonding area between the solder resist 70 and the mold resin 50. This improves the adhesion between the mold resin 50 and the bottom of the cavity 16.

[0024] FIG. 6 is a plan view of a semiconductor device 100b according to a second modified example of the first embodiment. FIG. 7 is an AB cross-sectional view of the semiconductor device 100b according to the second modified example of the first embodiment. Note that the printed circuit board 14 is omitted from FIG. 7. The solder resist 70 of the semiconductor device 100b has notches formed therein. This allows the side surfaces of each portion of the divided solder resist 70 to be provided with an area that will adhere to the mold resin 50. This increases the adhesion area between the solder resist 70 and the mold resin 50. This improves the adhesion between the mold resin 50 and the bottom of the cavity 16.

[0025] 8 is a plan view of a semiconductor device 100c according to a third modification of embodiment 1. A plurality of semiconductor chips 20 may be mounted on the heat sink 13. In this case, solder resist 70 may be disposed between the plurality of semiconductor chips 20.

[0026] 9 is a plan view of a semiconductor device 100d according to a fourth modification of the first embodiment. Multiple layers of solder resist 70 may be provided to surround the semiconductor chip 20. In the example of FIG. 9, the semiconductor chip 20 is surrounded by five layers of solder resist 70. The solder resist 70 may surround the semiconductor chip 20 in two or more layers. This provides an area on the side of the solder resist 70 that is bonded to the mold resin 50, thereby increasing the bonding area between the solder resist 70 and the mold resin 50. This improves the adhesion between the mold resin 50 and the bottom of the cavity 16.

[0027] 10 is a plan view of a semiconductor device 100e according to a fifth modification of the first embodiment. The solder resist 70 may be provided in a lattice pattern. This increases the adhesion area between the solder resist 70 and the mold resin 50. This improves the adhesion between the mold resin 50 and the bottom of the cavity 16.

[0028] 11 is a plan view of a semiconductor device 100f according to a sixth modification of the first embodiment. Holes 71 may be formed in the solder resist 70. The shape, size, number, and arrangement of the holes 71 are arbitrary. The holes 71 may have a combination of multiple shapes, multiple sizes, and multiple arrangement patterns. In the semiconductor device 100f as well, the adhesion area between the solder resist 70 and the molded resin 50 can be increased. This improves the adhesion between the molded resin 50 and the bottom of the cavity 16.

[0029] FIG. 12 is a plan view of a semiconductor device according to a seventh modification of the first embodiment. In addition to the corners of the cavity 16, the solder resist 70 may be provided on the heat sink 13 in areas other than the corners. The shape, size, number, and arrangement of the solder resist 70 provided in areas other than the corners are arbitrary. The solder resist 70 provided in areas other than the corners may be combined in multiple shapes, multiple sizes, and multiple arrangement patterns. In the semiconductor device 100g, the adhesive area between the solder resist 70 and the molded resin 50 can also be increased. This improves the adhesion between the molded resin 50 and the bottom of the cavity 16.

[0030] Furthermore, the shape of the cavity 16 is not limited. The cavity 16 may be quadrilateral, such as a square or a rectangle, in a plan view, or may be any polygonal shape. Any type of semiconductor chip can be used as the semiconductor chip 20. The semiconductor chip 20 may be an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

[0031] In addition, in the present embodiment, an example has been described in which the metal layers 11 and 31 are formed by Au plating, and the metal layers 12 and 32 are formed by Cu or Ni. However, the present embodiment is not limited to this, and the outermost metal layers 11 and 31 may be formed of, for example, any of Au, Ag, Ni, Pd, and Pt. Furthermore, the underlying metal layers 12 and 32 may be formed of, for example, any of Au, Ag, Ni, Pd, Pt, and Cu. The metal layers 12 and 32 may be formed of a metal that has higher adhesion to the mold resin 50 than the metal layers 11 and 31. This can also be applied to other embodiments. Note that, in the present embodiment, such a structure in which multiple metal layers are stacked is not essential.

[0032] The above-described variations can be applied as appropriate to the semiconductor devices, packages, and semiconductor device manufacturing methods according to the following embodiments. Note that the semiconductor devices, packages, and semiconductor device manufacturing methods according to the following embodiments have many points in common with the first embodiment, so differences from the first embodiment will be mainly described.

[0033] Embodiment 2 FIG. 13 is a cross-sectional view of a semiconductor device 200 according to the second embodiment. FIG. 14 is a plan view of the semiconductor device 200 according to the second embodiment. In the semiconductor device 200, a protrusion 272 is provided at the bottom of the cavity 16 of the structure 10. The protrusion 272 is provided, for example, as a part of the heat sink 13. The semiconductor chip 20 is provided on the protrusion 272. Furthermore, a groove 274 is formed outside the protrusion 272 at the bottom of the cavity 16. As described above, this embodiment differs from the first embodiment in that the protrusion 272 and the groove 274 are formed instead of the solder resist 70. The other configurations are the same as those of the first embodiment.

[0034] As described above, the corners of the cavity are likely to be the starting point for peeling of the molding resin 50. If the bottom of the cavity is flat, peeling that occurs at the corners will progress toward the semiconductor chip 20. Here, the direction of the peeling progress is changed by 90 degrees at the groove 274. In other words, the peeling progresses downward along the groove 274. Therefore, the groove 274 can suppress the progress of the peeling. Furthermore, the molding resin 50 is caught in the groove 274, which further suppresses the progress of the peeling.

[0035] Furthermore, by forming a step by the convex portion 272 around the periphery of the semiconductor chip 20, even if the peeling progresses beyond the groove 274, the progress of the peeling can be stopped at the step.

[0036] The grooves 274 are formed, for example, on all four sides of the protrusion 272. The grooves 274 may be formed so as to surround the protrusion 272. FIG. 15 is a plan view of a semiconductor device 200a according to a first modification of the second embodiment. In the semiconductor device 200, one groove 274 is formed so as to surround the protrusion 272. This is not a limitation, and multiple grooves 274 may be formed so as to surround the protrusion 272. The multiple grooves 274 may have any shape, size, number, and arrangement. The multiple grooves 274 may have a combination of multiple shapes, multiple sizes, and multiple arrangement patterns.

[0037] 16 is a cross-sectional view of a semiconductor device 200b according to a second modification of the second embodiment. In the semiconductor device 200, the shape of the groove 274 in the cross section is rectangular. However, as shown in FIG. 16, the groove 274 may be V-shaped, U-shaped, or trapezoidal in the cross section.

[0038] 17 is a plan view of a semiconductor device 200c according to a third modification of the second embodiment. A plurality of semiconductor chips 20 may be mounted on the semiconductor device 200c. In this case, grooves 274 may be arranged between the semiconductor chips 20. Also, a plurality of protrusions 272 may be provided corresponding to the plurality of semiconductor chips 20.

[0039] 18 is a plan view of a semiconductor device 200d according to a fourth modification of embodiment 2. A plurality of grooves 274 may be provided surrounding the protrusion 272. In the example of FIG. 18, the semiconductor chip 20 is surrounded by three grooves 274. The grooves 274 may be surrounded by two or more grooves.

[0040] It is to be noted that this embodiment may be combined with the solder resist 70 of the first embodiment. Also, in this embodiment, a structure in which a plurality of metal layers such as Au and Cu are stacked is not essential.

[0041] Embodiment 3 Fig. 19 is a cross-sectional view of a semiconductor device 300 according to embodiment 3. Fig. 20 is a plan view of semiconductor device 300 according to embodiment 3. In this embodiment, similar to embodiment 1, the bottom of cavity 16 has metal layer 11 and metal layer 12 formed of a metal having higher adhesion to mold resin 50 than metal layer 11 and provided below metal layer 11. The metals that can be used for each metal layer are the same as those in embodiment 1.

[0042] In the present embodiment, an exposed portion 376 where the metal layer 12 is exposed from the metal layer 11 is provided as the second portion 62 that has higher adhesion to the mold resin 50 than the first portion 61. The surface of the metal layer 12 in the exposed portion 376 is rougher than the surface of the metal layer 11. The exposed portion 376 is provided so as to surround the semiconductor chip 20 in a plan view, for example. The other configurations are the same as those in the first embodiment.

[0043] 21 is a flowchart illustrating a manufacturing method of a semiconductor device 300 according to the third embodiment. First, in the structure 10, a metal layer 11 is formed on a metal layer 12 that forms the bottom of the cavity 16, thereby forming the metal layers 11 and 12 (Step 1). At this time, for example, a Cu underlayer is used for the metal layer 12, and Ni / Pd / Au plating is used for the metal layer 11.

[0044] Next, at least a portion of the metal layer 11 located at the edge of the bottom of the cavity 16 is removed to form an exposed portion 376 where the metal layer 12 is exposed from the metal layer 11 (step 2). The exposed portion 376 can be formed by removing the metal layer 11 using a physical method such as polishing, a chemical treatment such as etching, or a non-contact method such as a laser. Removing the metal layer 11 roughens the surface of the underlying metal layer 12. Therefore, the surface of the metal layer 12 in the exposed portion 376 can be made rougher than the surface of the metal layer 11.

[0045] The surface of metal layer 12 may be roughened by pressing a mold with an uneven surface against exposed portion 376. Furthermore, if the surface of metal layer 12 in exposed portion 376 can ultimately be made rougher than the surface of metal layer 11, exposed portion 376 may be formed without removing metal layer 11. For example, exposed portion 376 may be formed by forming metal layer 11 by selective plating. Partial plating is a technique in which areas that do not require plating are masked and not plated.

[0046] Next, the semiconductor chip 20 is mounted on the bottom of the cavity 16 (step 3). Next, the structure 10, the semiconductor chip 20 and the exposed portion 376 are covered with the molding resin 50 (step 4).

[0047] The adhesive strength of the base metal, such as Ni or Cu, to the mold resin 50 is stronger than that of Au plating. Furthermore, because the surface of the metal layer 12 is roughened by removing the plating and exposing the base metal, the anchor effect can further improve the adhesion between the exposed portion 376 and the mold resin 50. Also, as in the first embodiment, the exposed portion 376, which has high adhesiveness to the mold resin 50, is formed at the end of the cavity 16, where stress tends to concentrate and become a starting point for peeling. Therefore, peeling of the mold resin 50 can be suppressed.

[0048] In the semiconductor device 300, the exposed portion 376 is provided around the entire periphery of the cavity 16. In contrast, the exposed portion 376 may be provided on at least a portion of the edge of the cavity 16. For example, the exposed portion 376 may be provided on only some of the four sides of the cavity 16.

[0049] 22 is a plan view of a semiconductor device 300a according to a first modification of embodiment 3. A plurality of semiconductor chips 20 may also be mounted on the semiconductor device 300. In this case, an exposed portion 376 may be disposed between the plurality of semiconductor chips 20.

[0050] 23 is a plan view of a semiconductor device 300b according to a second modification of the third embodiment. A plurality of exposed portions 376 may be provided to surround the semiconductor chip 20. In the example of FIG. 23, the semiconductor chip 20 is surrounded by three exposed portions 376. The exposed portions 376 may be surrounded by two or more layers.

[0051] 19, the semiconductor chip 20 is bonded to the metal layer 11, avoiding the exposed portion 376. However, the present invention is not limited to this, and the semiconductor chip 20 may be provided on the exposed portion 376. Furthermore, the entire bottom surface of the cavity 16 may be the exposed portion 376. Furthermore, the present embodiment may be combined with the protrusion 272 or the groove 274 of the second embodiment.

[0052] Embodiment 4 FIG. 24 is a plan view showing wire bond pad 430 according to the fourth embodiment. FIG. 25 is a cross-sectional view showing wire bond pad 430 according to the fourth embodiment. Wire bond pad 430 is provided, for example, at the position of wire bond pad 30 in FIG. 1. Wire bond pad 430 is provided on a substrate in a package. The substrate is, for example, printed circuit board 14 shown in FIG. 1. Wire 40 is connected to wire bond pad 430. As shown in FIG. 1, wire bond pad 430 is covered with molding resin 50.

[0053] Wire bond pad 430 has a first portion 61 to which wire 40 is bonded, and a second portion 62 having a rougher surface than first portion 61. Wire bond pad 430 has a metal layer 31 and a metal layer 32 formed from a metal that has higher adhesion to mold resin 50 than metal layer 31 and provided below metal layer 31. First portion 61 is a portion covered with metal layer 31. Wire bond pad 430 has an exposed portion 476 formed as second portion 62, where metal layer 32 is exposed from metal layer 31.

[0054] The exposed portion 476 can be formed by a method similar to the method for forming the exposed portion 376 in the third embodiment. That is, the metal layer 31 is formed on the metal layer 32 by plating or the like, and a portion of the metal layer 31 is removed to form the exposed portion 476. This allows the surface of the second portion 62 to be rougher than the surface of the first portion 61.

[0055] As described in the first embodiment, peeling of mold resin 50 is likely to occur during reflow or the like after moisture absorption. Specifically, peeling is likely to occur at the interface between wire bond pads and mold resin 50 in region A2 shown in FIG. 4. In contrast, in the present embodiment, as in the third embodiment, the adhesion between exposed portion 476 and mold resin 50 can be improved. Therefore, peeling of wire bond pad 430 and mold resin 50 can be suppressed.

[0056] The combination of metal layers 31 and 32 can be the same as that of embodiment 1. Furthermore, wire bond pad 430 of this embodiment can be applied to any package, not just the package shown in Figure 1. Wire bond pad 430 of this embodiment may be applied to any of embodiments 1 to 3.

[0057] Embodiment 5 FIG. 26 is a plan view showing a wire bond pad 530 according to the fifth embodiment. FIG. 27 is a cross-sectional view showing the wire bond pad 530 according to the fifth embodiment. In this embodiment, too, the wire bond pad 530 has a first portion 61 to which the wire 40 is bonded, and a second portion 62 having a rougher surface than the first portion 61. This embodiment differs from the fourth embodiment in that, instead of the exposed portion 476, the second portion 62 is formed with a plurality of bump bonds 578 to which the wire 40 is not bonded. The other configurations are the same as those of the fourth embodiment.

[0058] Wire bond pad 530 can be formed by applying bump bonds 578 to the empty spaces where wire 40 is not connected. This allows the surface of second portion 62 to be rougher than the surface of first portion 61. Bump bonds 578 increase the bonding area, and molding resin 50 becomes embedded in bump bonds 578. This prevents wire bond pad 530 from peeling off molding resin 50.

[0059] The size, number and arrangement of bump bonds 578 are arbitrary. Furthermore, in this embodiment, the structure in which a plurality of metal layers such as Au and Cu are stacked as in the fourth embodiment is not essential.

[0060] The technical features described in each embodiment may be used in appropriate combination. [Explanation of symbols]

[0061] 10 structure, 11, 12 metal layer, 13 heat sink, 14 printed circuit board, 16 cavity, 20 semiconductor chip, 22 solder, 30 wire bond pad, 31, 32 metal layer, 40 wire, 42 chip component, 50 molding resin, 61 first portion, 62 second portion, 70 solder resist, 71 hole, 100, 100a-100g, 200, 200a-200d semiconductor device, 272 protrusion, 274 groove, 300, 300a, 300b semiconductor device, 376 exposed portion, 430 wire bond pad, 476 exposed portion, 530 wire bond pad, 578 bump bond

Claims

1. a structure in which a cavity opening upward is formed; a semiconductor chip provided at the bottom of the cavity of the structure; a molding resin that covers the structure; Equipped with The bottom of the cavity is a first portion formed of metal; a second portion that has higher adhesion to the molding resin than the first portion and is provided outside the first portion and at an end of the bottom portion; and As the second portion, a solder resist is provided at a corner formed by a side surface and the bottom of the cavity, The semiconductor device is characterized in that the surface of the solder resist that comes into contact with the molding resin is a curved surface.

2. the bottom portion has a first metal layer and a second metal layer formed of a metal having higher adhesion to the molding resin than the first metal layer and provided below the first metal layer; 2. The semiconductor device according to claim 1, wherein the solder resist is provided on an exposed portion of the first metal layer where the second metal layer is exposed.

3. a structure in which a cavity opening upward is formed; a semiconductor chip provided at the bottom of the cavity of the structure; a molding resin that covers the structure; Equipped with The bottom of the cavity is a first portion formed of metal; a second portion that has higher adhesion to the molding resin than the first portion and is provided outside the first portion and at an end of the bottom portion; and the bottom portion has a first metal layer and a second metal layer formed of a metal having higher adhesion to the molding resin than the first metal layer and provided below the first metal layer; the second portion is an exposed portion where the second metal layer is exposed from the first metal layer, The semiconductor device is characterized in that the surface of the second metal layer in the exposed portion is rougher than the surface of the first metal layer.

4. 4. The semiconductor device according to claim 1, wherein the second portion is provided so as to surround the semiconductor chip in a plan view.

5. 4. The semiconductor device according to claim 1, wherein the structure includes a heat sink on which the semiconductor chip is mounted, and a printed circuit board surrounding the semiconductor chip.

6. a structure in which a cavity opening upward is formed; a protrusion provided on the bottom of the cavity of the structure; a semiconductor chip provided on the protruding portion; a molding resin that covers the structure; Equipped with The semiconductor device is characterized in that a groove recessed relative to the surface from which the convex portion protrudes is formed on the bottom portion outside the convex portion.

7. 7. The semiconductor device according to claim 6, wherein the groove is formed on all four sides of the protrusion.

8. 8. The semiconductor device according to claim 6, wherein the groove is formed so as to surround the protrusion.

9. 8. The semiconductor device according to claim 6, wherein the structure comprises a heat sink on which the semiconductor chip is mounted, and a printed circuit board surrounding the semiconductor chip.

10. In a structure having a cavity that opens upward, a first metal layer is formed on a second metal layer that forms a bottom of the cavity; removing at least a portion of the first metal layer provided at an end of the bottom portion to form an exposed portion in which the second metal layer is exposed from the first metal layer; a semiconductor chip mounted on the bottom; covering the structure, the semiconductor chip, and the exposed portion with a molding resin; the second metal layer has higher adhesion to the molding resin than the first metal layer; The method for manufacturing a semiconductor device is characterized in that the structure has a heat sink on which the semiconductor chip is mounted and a printed circuit board surrounding the semiconductor chip.

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the surface of the second metal layer in the exposed portion is rougher than the surface of the first metal layer.

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