Selecting the Error Correction Code Type for a Memory Device

Abstract

Selecting an error correction code type for the memory device includes selecting, by the memory device, one of a plurality of error correction code types according to predetermined selection criteria, and executing a memory access request using the selected error correction code type.

Description

[Background technology]

[0001] Memory devices are implemented in computing systems in a variety of ways. Some memory devices are directly attached, while others are connected to a host computing system through one or more fabrics. In some computing systems, various different connection types may represent or implement different layers of the memory hierarchy. Two memory device connections through the same fabric may even have different access characteristics due to the "distance" (e.g., number of hops) from the host system to the memory device itself. Furthermore, memory devices coupled to a system with the same connection type may be implemented in the memory hierarchy. Some connection types, such as non-volatile random access memory (NVRAM) fabrics, may be less reliable in terms of data corruption over time than other fabrics. [Brief explanation of the drawings]

[0002] [Figure 1] FIG. 1 is a functional block diagram of an exemplary system for selecting an error correction code type for a memory device, according to an embodiment of the present disclosure. [Figure 2] 1 is a flowchart illustrating an exemplary method for selecting an error correction code type for a memory device, according to an embodiment of the present disclosure. [Figure 3] 10 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device, according to an embodiment of the present disclosure. [Figure 4] 10 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device initiated by the memory device, according to an embodiment of the present disclosure. [Figure 5] 10 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device, where the selection process is initiated by a host device. [Figure 6]10 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device, where the selection process is initiated by the memory device, according to an embodiment of the present disclosure. [Figure 7] 10 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device, according to an embodiment of the present disclosure. [Figure 8] 10 is a flowchart illustrating an exemplary method for selecting an error correction code type, in which a host of a system performs the selection process, according to an embodiment of the present disclosure. [Figure 9] 10 is a flowchart illustrating another exemplary method for selecting an error correction code type in which a host of a system performs the selection process, according to an embodiment of the present disclosure. [Figure 10] 10 is a flowchart illustrating another exemplary method for selecting an error correction code type in which a host of a system performs the selection process, according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0003] Disclosed herein are exemplary methods, apparatus, and articles of manufacture for selecting an error correction code type for a memory device. Various embodiments for selecting an error correction code type for a memory device are described in more detail with respect to the following figures. Such selection of an error correction code type for a memory device, in some embodiments, includes selecting one of a plurality of error correction code (ECC) types by the memory device according to predetermined selection criteria. The memory device stores ECC types within the device itself such that, regardless of the system in which the memory device is implemented, the memory device selects one of the different ECC types based on the criteria. Each ECC type is a different code rate from other ECC types stored in the memory device. Each different code rate represents a trade-off between code calculation latency, the number of detectable faults, the number of correctable faults, and the size of the redundant data.

[0004] The memory device selects the ECC type based on predetermined selection criteria, including the type of connection between the memory device and the system's host, the level of the memory hierarchy in which the memory device is implemented, the communication distance between the memory device and the host system, the access pattern of data stored in the memory device, such as a frequently accessed pattern ("hot" data) or an infrequently accessed pattern ("cold" data), and any other criteria or combination thereof.

[0005] In some embodiments, the memory device selects the error correction code type during initialization of the memory device, such as during enumeration of the device by the host. In some embodiments, the memory device queries a host of a system for location information of the memory device. Such location information specifies one or a combination of the layer of a memory hierarchy in which the memory device is implemented, the type of connection between memory hierarchies, the communication distance between the memory device and the host, etc. In some implementations, rather than the memory device querying the host, the host notifies the memory device of the location information of the memory device without a request from the memory device.

[0006] After the error correction code type is selected, the memory device performs memory access requests, such as read and write operations, using the selected error correction code type.

[0007] In some embodiments, the memory device is removed from its current implementation in the system and replaced in another location. In some embodiments, the memory device is reconnected to the same host, regardless of connection type, but with a different connection type, at a different communication distance, or at a different level in the memory hierarchy. In other embodiments, the memory device is connected to a different host. In either case, the memory device reselects one of multiple error correction code types in response to detecting a change in connection to the host (whether the same host or a different host).

[0008] The above-described embodiments illustrate embodiments in which a memory device stores or is otherwise programmed with a variety of different ECC types and the memory device selects and implements one of the ECC types. In other embodiments, the host selects the ECC type and communicates the selection to the memory device. A memory device that is programmed with multiple different ECC types implements the ECC type selected by the host. The host selects the ECC type based on one or more criteria, including the type of connection between the memory module and the host, the level of hierarchy in which the memory module operates, the communication distance between the memory module and the host, and the access pattern of data on the memory module.

[0009] For further explanation, Figure 1 illustrates a functional block diagram of an exemplary system for selecting an error correction code type for a memory device, according to an embodiment of the present disclosure. The system of Figure 1 includes a host (102) in the form of a computing system (e.g., a server). The host (102) in turn includes a computer processor (104) including one or more central processing unit (CPU) cores (106) and a memory controller (108). The memory controller is coupled to memory devices (114, 116) of a memory subsystem (126).

[0010] The memory subsystem (126) includes two memory devices. The reader will recognize that systems often include any number of memory devices. Each of the memory devices (114, 116) in the exemplary system of FIG. 1 is coupled to the host system via a different connection type. One memory device (114) is coupled to the memory controller (108) via a direct attached memory bus (110). The other memory device (116) is coupled to the memory controller (108) via a memory fabric (112). Examples of direct attached memory include dual in-line memory module (DIMM) slots, direct attached nonvolatile RAM (NVRAM), etc. Examples of memory fabrics include NVMe over fabrics (nonvolatile memory), fabric attached NVRAM, etc.

[0011] Each connection type has different characteristics. For example, performance, capacity, and reliability differ between the two types of connections. Therefore, each connection type is often utilized in a memory subsystem to store different types of data. In some embodiments, the memory subsystem is a memory hierarchy in which more frequently accessed data is stored at higher levels in the hierarchy and less frequently accessed data is stored at lower levels in the hierarchy. The higher levels of the memory hierarchy share high performance characteristics, and the lower levels share greater capacity and reliability. In other systems, no hierarchy exists. However, in such systems, the different characteristics of the connection types continue to exist.

[0012] The example memory device (114, 116) of FIG. 1 includes several different ECC types (118, 120). Each of the different ECC types (118, 120) has a different code rate. Here, the term "code rate" generally refers to the strength of the ECC relative to its computational complexity. The strength of an ECC is defined by the number of errors that the scheme can detect and correct. In other words, the "code rate" is the percentage of non-redundant data relative to the total amount of data when encoded. Thus, if there are 2 bits of redundant data in a 10-bit string, the code rate is 8 / 10, or 80%. The greater the percentage of non-redundant data, the lower the computational complexity for encoding or decoding data using the ECC scheme. Furthermore, the greater the percentage of non-redundant data, the lower the strength of the ECC scheme compared to an ECC scheme with a lower percentage of non-redundant data. Thus, an ECC scheme with a high code rate computes faster than an ECC scheme with a low code rate, but has lower strength than an ECC scheme with a lower code rate.

[0013] To that end, each memory device (114, 116) selects one of a plurality of error correction code types and executes memory access requests using the selected error correction code type to store and access ECC-encoded data (122, 124). The memory devices in the example memory subsystem (126) of FIG. 1 select one of the ECC types to implement based on predetermined selection criteria. Such predetermined selection criteria include one or more of the connection type (e.g., direct-attached or fabric), the memory subsystem's (126) level in the memory hierarchy, the communication distance between the memory devices (114, 116) and the host (102), and the memory device's data access pattern. In the case of a memory fabric with low reliability, the memory module selects an ECC type with a lower code rate, i.e., an ECC scheme that provides better detection and correction at the expense of computational performance (and therefore latency). In the case of a faster (higher throughput, bandwidth, or both) direct-attached memory bus, the memory device (114) selects an ECC type with a higher code rate. In such an example, the memory device 114 is expected to be accessed frequently, resulting in a shorter amount of time that data resides on the device. Therefore, a higher code rate ECC type allows the memory device 114 to more quickly encode or decode data being written to or read from the memory device, reducing the likelihood of data errors occurring due to the shorter amount of time that data is expected to reside, and therefore reducing the need for a stronger ECC. These are just a few examples among many possible examples of selecting an ECC type based on a trade-off between latency, which is affected by the computational complexity of the ECC scheme, and the strength of the ECC type. Another parameter included in the selection process in some examples is the amount of redundant data required. Stronger ECC types tend to require more redundant data along with the original data.Thus, memory devices take into account, in some cases, the capacity of the memory device, the strength of the ECC type, and the latency of the ECC type.

[0014] For further explanation, several figures are shown below, each of which includes a flowchart illustrating a method. In various embodiments, each method is performed in a system similar to that of Figure 1, which includes a memory device and a host, and the memory device includes multiple different ECC types.

[0015] 2 is a flowchart of an exemplary method for selecting an error correction code type for a memory device according to an embodiment of the present disclosure. The method of FIG. 2 includes selecting (202) one of a plurality of error correction code types (208) by a memory device (114) in response to predetermined (predefined) selection criteria (206). The predetermined selection criteria (206) may be any one or combination of the following: the type of connection between the memory device and a host in a system, the level of the memory hierarchy in which the memory device is implemented, the communication distance between the memory device and the host system, the access pattern of data stored in the memory device, such as a frequently accessed pattern ("hot" data) or an infrequently accessed pattern ("cold" data), and / or any other criteria.

[0016] In some embodiments, the memory device (114) selects an ECC type (210) by setting a flag in one or more predetermined locations in a register of the memory device's controller designated for such purpose. In various embodiments, the flag is implemented as a bit in a bit string, with each bit representing a different ECC type, as a particular value stored in one of multiple registers, with each different register representing a different ECC type, or in any other manner as would occur to one skilled in the art.

[0017] 2 also includes performing 204 the memory access request using the selected error correction code type. The memory device 114 performs 204 the memory access request by encoding data received from the host in a write command 212 in accordance with the selected ECC type, writing the encoded data 214 to a location in memory 216, loading the encoded data from a location in memory 216 in response to a read command from the host, and decoding the data in accordance with the selected ECC type before transmitting the data to the host.

[0018] For further explanation, Figure 3 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device, according to an embodiment of the present disclosure. The method of Figure 3 is similar to the method of Figure 2 in that it also includes selecting (202) one of a plurality of ECC types (208) (210) by a memory device (114) in response to predetermined selection criteria (206), and executing (204) a memory access request (212) using the selected ECC type (210).

[0019] However, Figure 3 differs from the method of Figure 2 in that in the method of Figure 3, selecting (202) one of a plurality of ECC types (208) by the memory device (114) in response to predetermined selection criteria (206) may be performed in one or more different ways. Although generally shown and described herein as alternative ways of performing the ECC type selection process, the reader will recognize that any of the methods described below with respect to Figure 3 may be performed in various combinations to achieve the ECC type selection process of Figure 3. That is, nothing in this disclosure precludes multiple different selection criteria being employed in selecting an ECC type (202).

[0020] In some embodiments of the method of FIG. 3 , selecting (202) one of a plurality of ECC types (208) by the memory device (114) in response to predetermined selection criteria (206) includes selecting (302) one of a plurality of ECC types in response to a type of connection coupling between the memory device and the host. In such embodiments, each ECC type is associated with a particular connection type, such as direct connect or fabric. The memory device (114) selects the ECC type associated with the type of connection that exists between the memory device (114) and the host. In one example, directly connected NVRAM is associated with an ECC type with a higher code rate than an ECC type associated with NVRAM coupled via a fabric.

[0021] In some embodiments of the method of FIG. 3 , selecting (202) one of a plurality of ECC types (208) by the memory device (114) in response to predetermined selection criteria (206) includes selecting (304) one of a plurality of ECC types in response to a level at which the memory device is assigned in the memory hierarchy. In such embodiments, each ECC type is associated with a different level or range of levels in the memory hierarchy. The “higher” the level in the hierarchy, the more frequently data is accessed and the more likely the data is to change. Thus, ECC types associated with higher levels of the memory hierarchy, introduced due to the computational complexity of the encoding and decoding processes, have lower latencies than ECC types associated with lower levels of the memory hierarchy. Furthermore, because data stored at higher levels of the memory hierarchy is more likely to change (have a shorter “lifetime” in memory), it is less likely to experience memory errors than memories at lower levels of the memory hierarchy. Thus, ECC types associated with higher levels of the memory hierarchy have lower redundancy or strength than ECC types associated with lower levels of the memory hierarchy, where data is stored and not modified for longer periods and therefore is more likely to experience memory errors.

[0022] In some embodiments of the method of FIG. 3 , selecting (202) one of a plurality of ECC types (208) by the memory device (114) in response to predetermined selection criteria (206) includes selecting (306) one of a plurality of ECC types in response to an access pattern of data stored in the memory device. The access pattern of data stored in the memory device indicates whether the data is accessed more frequently or less frequently. This data may be referred to as “hot” data (high access frequency) or “cold” data (low access frequency). In such embodiments, each ECC type is associated with a hot data access pattern or a cold data access pattern. In some embodiments, the memory device monitors the access pattern over time and reselects the ECC type based on changes in the access pattern. Such dynamic changes, in some embodiments, include dividing the memory into ECC-type-specific partitions or migrating data to another memory device of the first ECC type before performing the ECC type reselection.

[0023] In some embodiments of the method of FIG. 3 , selecting (202) one of a plurality of ECC types (208) by the memory device (114) in response to predetermined selection criteria (206) includes selecting (306) one of a plurality of ECC types in response to an access pattern of data stored on the memory device. The access pattern is defined by the frequency of access of data at one or more memory locations or memory devices. Data accessed frequently is referred to as “hot” data, and data accessed less frequently is referred to as “cold” data. In some embodiments, each ECC type is designated as either a hot ECC type or a cold ECC type. ECC types that enable lower latency (lower computational complexity for encoding and decoding data) are associated with hot data access patterns and higher latency data access patterns, while greater redundancy is associated with cold data access patterns.

[0024] In some embodiments of the method of FIG. 3 , selecting (202) one of a plurality of ECC types (210) by the memory device (114) in response to predetermined selection criteria (206) includes selecting (308) one of a plurality of ECC types in response to a communication distance between the memory device and the host. The term “communication distance” refers to the length of a physical data communication link, a logical data communication link, or a combination of physical and logical data communication links coupling the memory device to the host. Communication distance may include any combination of the number of hops, switches, controllers, cables, cable lengths, trace lengths, etc., as will be appreciated by those skilled in the art. For example, in a system in which multiple memory devices are coupled to a host via a memory fabric, the coupling of each memory device in some embodiments results in a different communication distance. In such embodiments, an ECC type with a lower code rate is selected when the communication distance is short, and an ECC type with a higher code rate is selected when the communication distance is long.

[0025] 4 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device initiated by a memory device (114) according to an embodiment of the present disclosure. The method of FIG. 4 is similar to the method of FIG. 2 in that it also includes selecting (202) one of a plurality of ECC types (208) (210) by the memory device (114) in response to predetermined selection criteria (206) and executing (204) a memory access request (212) using the selected ECC type (210).

[0026] 4 differs from the method of FIG. 2 in that selecting (202) one of a plurality of ECC types (208) by the memory device (114) in response to predetermined selection criteria (206) is performed by selecting (402) one of a plurality of ECC types during initialization of the memory device. That is, when the memory device is initialized, the memory device performs the ECC type selection process. In some embodiments, initialization occurs during enumeration of the memory subsystem by the host system. In some embodiments, such initialization occurs after hot installation of the memory device within the system. In some embodiments, initialization of the memory device occurs after the boot process of the operating system of the host system.

[0027] In some embodiments, the selection process described above is initiated by the memory device, and in other embodiments, by the host. Accordingly, for further explanation, Figure 5 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device, in which the selection process is initiated by the host device. The method of Figure 5 is similar to the method of Figure 2 in that it also includes selecting (202) one of a plurality of ECC types (208) (210) by the memory device (114) in response to predetermined selection criteria (206), and executing (204) a memory access request (212) using the selected ECC type (210).

[0028] However, Figure 5 differs from the method of Figure 2 in that the method of Figure 5 includes receiving (502) from a host (102) of the system, without a request from the memory device, location information (506) of the memory device within the system. The location information (506) may refer to any one or more of the following: the level at which the memory device is in the memory hierarchy; the type of connection coupling the memory device to the host; the communication distance of the connection between the host and the memory device; the access pattern intended for use with the memory device; etc. To that end, in the method of Figure 5, selecting (202) one of a plurality of ECC types (208) by the memory device (114) in response to predetermined selection criteria (206) includes selecting (504) one of a plurality of ECC types in response to the received location information (506).

[0029] 6 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device, in which the selection process is initiated by the memory device, according to an embodiment of the present disclosure. The method of FIG. 6 is similar to the method of FIG. 2 in that it also includes selecting (202) one of a plurality of ECC types (208) by the memory device (114) in response to predetermined selection criteria (206) and executing (204) a memory access request (212) using the selected ECC type (210).

[0030] 6 differs from the method of FIG. 2 in that the method of FIG. 6 includes querying (602) a system host (102) for location information (506) of the memory device by the memory device and receiving (604) the location information (506) from the host. In some embodiments, the memory device queries the host by sending an enumeration request to the host. The host returns enumeration information, such as the device's location within the memory hierarchy, connection type, etc. To that end, in the method of FIG. 6, selecting (202) one of a plurality of ECC types (208) by the memory device (114) in response to predetermined selection criteria (206) includes selecting (606) one of a plurality of ECC types in response to the received location information.

[0031] For further explanation, Figure 7 is a flowchart illustrating another exemplary method for selecting an error correction code type for a memory device, according to an embodiment of the present disclosure. The method of Figure 7 is similar to the method of Figure 2 in that it also includes selecting (202) one of a plurality of ECC types (208) (210) by a memory device (114) in response to predetermined selection criteria (206), and executing (204) a memory access request (212) using the selected ECC type (210).

[0032] However, the method of FIG. 7 also differs from FIG. 2 in that it includes detecting a different connection to the host (702) and reselecting one of a plurality of error correction code types (704). In the example of FIG. 7, the memory device detects a different connection to the same host. However, the reader will recognize that in some embodiments, the memory device detects a different connection to a different host. For example, assume that the memory device is removed from a direct-attached connection to the host and installed in the memory fabric of the same host. In such an example, the memory device reselects the ECC type (704) according to the same predetermined selection criteria (206). As another example, assume that the memory device is removed from the memory fabric of a first host and installed in the memory fabric of a second host. Even if the connection type is the same, removing the device from one system and installing it in another system will trigger an ECC type reselection. As described above, the predetermined selection criteria in some embodiments identify multiple different criteria types, e.g., connection type, communication distance, memory access pattern, memory hierarchy level, etc., such that the ECC type selected by the memory module when moved from a first host to a second host differs. With memory devices programmed with multiple ECC types, the memory device can be moved (within the memory subsystem of the same system or to a different system entirely) and the ECC type selected for the memory device reselected.

[0033] Various embodiments described above with respect to FIGS. 2-7 include memory devices that perform ECC type selection. In some embodiments, rather than the memory device performing such ECC type selection, the host device performs the process. To that end, FIG. 8 is a flowchart illustrating an exemplary method for selecting an error correction code type in which the host of a system performs the selection process, according to an embodiment of the present disclosure. The method of FIG. 8 includes determining (802), by the host of the system, a type of connection (810) coupling the memory device to the host. Determining (802) the type of connection coupling the memory device to the host is performed by enumeration.

[0034] 8 also includes the host (102) selecting (804) one of a plurality of error correction code types (812) based on the connection type, and the host notifying (806) the memory device of the selected error correction code type. The selection process (804) performed by the host (102) is performed similarly to the memory device method described above. The host includes several ECC types, each associated with a particular connection type. The ECC type associated with the connection type of the memory device (114) is selected.

[0035] The host (102) communicates (806) the selected ECC type (812) to the memory device in any of several ways. In some embodiments, for example, the host (102) writes a specific data pattern or "flag" to a memory location in the memory device designated for such purpose. In other embodiments, the memory device is configured to receive such information as part of an enumeration of devices in the system. The memory device, in some embodiments, includes several different ECC types (814), which the memory device communicates to the host (102).

[0036] Upon receiving the ECC type selected by the host (102), the method of Figure 8 continues by the memory device executing (808) the memory (818) access request utilizing the selected error correction code, i.e., the memory device (114) encodes and stores data (816) in memory (818) upon a write command, and loads, decodes, and transmits data to the host upon a read command.

[0037] For further explanation, Figure 9 is a flowchart illustrating another exemplary method for selecting an error correction code type in which a system host performs the selection process, according to an embodiment of the present disclosure. The method of Figure 9 includes determining, by the system host, the tier of the memory device within the system's memory hierarchy (902). Determining, by the system host, the tier of the memory device within the system's memory hierarchy (902), in some embodiments, is performed by inquiring about the memory system configuration. In some embodiments, particular slots or data communication ports are associated with different tiers of the hierarchy. In such embodiments, the host determines the tier of the memory device's hierarchy by identifying the slot or port in which the memory device is installed.

[0038] 9 also includes the host (102) selecting (904) one of a plurality of ECC types based on the memory device's tier (position, location) (910) within the system's memory hierarchy, and the host notifying (906) the memory device of the selected ECC type (912). The selection process (904) performed by the host (102) is performed similarly to the memory device method described above. The host includes several ECC types, each associated with a particular tier of the memory hierarchy. The ECC type associated with the tier of the memory device's (114) hierarchy is selected.

[0039] The host (102) notifies (906) the memory device of the selected ECC type (912) in any of several ways. In some embodiments, for example, the host (102) writes a specific data pattern or "flag" to a memory location in the memory device designated for such purpose. In other embodiments, the memory device is configured to receive such information as part of an enumeration of devices in the system.

[0040] Upon receiving the ECC type selected by the host (102), the method of Figure 9 continues by the memory device executing (908) the memory (918) access request utilizing the selected error correction code, i.e., the memory device (914) encodes and stores data (916) in memory (918) upon a write command, and loads, decodes, and transmits data to the host upon a read command.

[0041] For further explanation, Figure 10 is a flowchart illustrating another exemplary method for selecting an error correction code type in which a host of a system performs the selection process, according to an embodiment of the present disclosure. The method of Figure 10 includes determining 1002, by the host of the system, the communication distance of the coupling of the memory device to the host. Determining 1002, the communication distance of the coupling of the memory device to the host, in some embodiments, is performed by enumerating the fabric or other data communication channel coupling the memory device to the host.

[0042] The method of Figure 10 also includes selecting (1004), by the host (102), one of a plurality of ECC types based on the communication distance (1010) of the memory device's coupling to the host, and notifying (1006) the memory device of the selected ECC type (1012). The selection process (1004) performed by the host (102) is performed similarly to the memory device method described above. The host includes several ECC types, each associated with a particular layer of the memory hierarchy. The ECC type associated with the layer of the hierarchy of the memory device (114) is selected.

[0043] The host (102) notifies (1006) the memory device of the selected ECC type (1012) in any of several ways. In some embodiments, for example, the host (102) writes a particular data pattern or "flag" to a memory location in the memory device designated for such purpose. In other embodiments, the memory device is configured to receive such information as part of an enumeration of devices in the system.

[0044] Upon receiving the ECC type selected by the host (102), the method of Figure 10 continues by the memory device executing (1008) the memory (1018) access request utilizing the selected error correction code, i.e., the memory device (1014) encodes and stores data (1016) in memory (1018) upon a write command, and loads, decodes, and transmits data to the host upon a read command.

[0045] The exemplary embodiments are described primarily in terms of fully functional computer systems. However, readers skilled in the art will recognize that the present disclosure may be embodied in a computer program product disposed on a computer-readable storage medium for use with any suitable data processing system. Such computer-readable storage media include any storage medium for machine-readable information, including magnetic, optical, or other suitable media. Examples of such media include magnetic disks in hard drives or diskettes, compact discs for optical drives, magnetic tape, and others as will occur to those skilled in the art. Those skilled in the art will readily recognize that any computer system with appropriate programming means is capable of performing the method steps embodied in a computer program product. Those skilled in the art will also recognize that while some of the exemplary embodiments described herein are directed to software installed and executed on computer hardware, alternative embodiments implemented as firmware or hardware are nevertheless well within the scope of the present disclosure.

[0046] Embodiments may include systems, methods, and / or computer program products including computer-readable storage medium(s) having computer-readable program instructions for causing a processor to perform aspects of the present disclosure.

[0047] A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media may be, for example, but not limited to, electronic, magnetic, optical, electromagnetic, or semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves having instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as being ephemeral signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over electrical wires.

[0048] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). In some embodiments, the network includes copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within each computing / processing device.

[0049] In some embodiments, the computer-readable program instructions for carrying out the operations of the present disclosure are implemented as source or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine language instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or object code written in one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. In some embodiments, the computer-readable program instructions execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer in some embodiments is connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or is connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to personalize the electronic circuitry to perform aspects of the present disclosure.

[0050] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to some embodiments of the present disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0051] These computer-readable program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus to produce a machine, whereby the instructions, executed by the processor of the computer or other programmable data processing apparatus, produce means for implementing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, and / or other device to function in a particular manner, such that a computer-readable storage medium having instructions stored therein is an article of manufacture containing instructions that implement aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0052] Furthermore, the computer-readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device and cause the computer, other programmable apparatus, or other device to perform a series of operational steps to generate a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0053] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially concurrently. Or, the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, can be implemented by a special-purpose hardware-based system performing the specified function or operation, or by executing a combination of special-purpose hardware and computer instructions.

Claims

1. 1. A memory device for selecting an error correction code type, comprising: Multiple error correction code types; error correction selection logic; The error correction selection logic: selecting one of a plurality of error correction code types according to predetermined selection criteria, the predetermined selection criteria including location information of the memory device, the location information including at least one of a connection type coupling the memory device to a host, a level of a memory hierarchy in which the memory device is implemented, a communication distance between the memory device and the host, or an access pattern of the memory device; performing the memory access request utilizing the selected error correction code type; configured to: Memory device.

2. the error correction selection logic is configured to select one of the plurality of error correction code types in response to a predetermined selection criterion by selecting one of the plurality of error correction code types in response to a type of connection coupling between the memory device and a host. The memory device of claim 1.

3. the error correction selection logic is configured to select one of the plurality of error correction code types by selecting one of the plurality of error correction code types according to an assigned level of the memory device within a memory hierarchy. The memory device of claim 1.

4. the error correction selection logic is configured to select one of the plurality of error correction code types in accordance with a predetermined selection criterion by selecting one of the plurality of error correction code types in accordance with an access pattern of data stored in the memory device. The memory device of claim 1.

5. the error correction selection logic is configured to select one of the plurality of error correction code types in accordance with a predetermined selection criterion by selecting one of the plurality of error correction code types in accordance with a communication distance between the memory device and a host; the communication distance refers to the length of a data communication link coupling the memory device and the host; The memory device of claim 1.

6. the error correction selection logic is configured to select one of the plurality of error correction code types according to predetermined selection criteria by selecting one of the plurality of error correction code types during initialization of the memory device. The memory device of claim 1.

7. The error correction selection logic: configured to receive, from a host of a system, location information of the memory device within the system without a request from the memory device; selecting one of the plurality of error correction code types includes selecting one of the plurality of error correction code types in accordance with received location information; The memory device of claim 1.

8. The error correction selection logic: querying a system host for location information of said memory device; receiving the location information from the host; and selecting one of the plurality of error correction code types includes selecting one of the plurality of error correction code types in accordance with received location information; The memory device of claim 1.

9. the error correction selection logic is configured to reselect one of the plurality of error correction code types in response to detecting a different connection to a host. The memory device of claim 1.

10. each of the plurality of error correction code types includes a different code rate; The memory device of claim 1.

11. 1. A method for selecting an error correction code type, comprising: determining, by a host of the system, location information for a memory device coupled to the host, the location information including at least one of a connection type coupling the memory device to the host, a level of a memory hierarchy in which the memory device is implemented, a communication distance between the memory device and the host, or an access pattern of the memory device; selecting, by the host, one of a plurality of error correction code types based on the location information; notifying the memory device by the host of a selected error correction code type; method.

12. the memory device is configured to include a plurality of error correction code types, and upon receiving a selected error correction code type from the host, to execute a memory access request using the selected error correction code. The method of claim 11.

13. the location information is transmitted by the host to the memory device without a request from the memory device; The method of claim 11.

14. the location information is transmitted by the host to the memory device in response to the host receiving a query requesting the location information from the memory device; The method of claim 11.

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