Semiconductor device manufacturing method

Abstract

To provide a semiconductor device capable of realizing a high threshold voltage.SOLUTION: A semiconductor device according to an embodiment includes: a silicon carbide layer having a first face and a second face; a trench disposed in the silicon carbide layer and extending in a first direction; a gate electrode disposed in the trench; a gate insulating layer; an n-type first silicon carbide region; a p-type second silicon carbide region disposed between the first silicon carbide region and the first face, and having a smaller depth than a depth of the trench; an n-type third silicon carbide region disposed between the second silicon carbide region and the first face, and including a first region in contact with a first side surface of the trench and a second region in contact with a second side surface of the trench; an n-type fourth silicon carbide region disposed between the third silicon carbide region and the first face, and including a third region in contact with the first side surface and the first region and a fourth region in contact with the second side surface and the second region, a width of the fourth silicon carbide region in a second direction perpendicular to the first direction being smaller than a width of the third silicon carbide region; and a first electrode in contact with the fourth silicon carbide region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device, a method for manufacturing a semiconductor device, an inverter circuit, a drive device, a vehicle, and an elevator. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a material for next-generation semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. Utilizing these physical properties will enable the realization of semiconductor devices that are low-loss and capable of operating at high temperatures.

[0003] In vertical metal oxide semiconductor field effect transistors (MOSFETs) using silicon carbide, a trench gate structure in which a gate electrode is provided inside a trench is used to achieve low on-resistance. By using the trench gate structure, the channel area per unit area increases, reducing on-resistance. A high threshold voltage is desired for MOSFETs with a trench gate structure. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 5800162 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a semiconductor device that can achieve a high threshold voltage. [Means for solving the problem]

[0006] Semiconductor device of an embodiment The manufacturing method includes ion-implanting p-type impurities into an n-type first silicon carbide layer to form a p-type first region, forming a first mask material on the first silicon carbide layer, the first mask material having a first opening that exposes the first region, using the first mask material as a mask to ion-implant n-type impurities into the first region through the first opening to form an n-type second region shallower than the first region, peeling off the first mask material, forming a p-type second silicon carbide layer on the first silicon carbide layer by epitaxial growth, forming a second mask material on the second silicon carbide layer, the second mask material having a second opening that exposes the second silicon carbide layer above the second region, and removing the second mask material. and forming a gate insulating layer in the second opening; forming a gate electrode on the gate insulating layer in the trench, the gate electrode having an upper surface located in the trench; the gate insulating layer being formed on the gate insulating layer in the trench; the trench extending in a first direction parallel to a surface of the second silicon carbide layer; and forming a gate electrode in the second opening in a second direction perpendicular to the first direction and parallel to the surface, the gate insulating layer being formed on the gate insulating layer in the trench; the gate electrode having an upper surface located in the trench; the trench extending in a first direction parallel to a surface of the second silicon carbide layer; and forming a gate electrode in the second direction ... insulating layer being formed on the gate insulating layer in the trench; the gate insulating layer being formed on the gate insulating layer in the trench; the gate insulating layer being formed on the gate insulating layer; the gate electrode having an upper surface located in the trench; the gate insulating layer being . [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. [Figure 3] FIG. 2 is an enlarged schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] FIG. 3 is a graph showing the profile of the n-type impurity concentration of the semiconductor device according to the first embodiment. [Figure 5] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 6] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 7] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 8] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 9] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 10] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 11] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 12] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 13] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 14] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 15] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 16] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 17] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 18]3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 19] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 20] 3A to 3C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 21] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a modified example of the first embodiment. [Figure 22] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 23] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 24] FIG. 6 is an enlarged schematic cross-sectional view of a semiconductor device according to a second embodiment. [Figure 25] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 26] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 27] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 28] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 29] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 30] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 31] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 32] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 33] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 34] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 35] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 36]5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 37] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 38] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 39] 5A to 5C are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the second embodiment. [Figure 40] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to a modified example of the second embodiment. [Figure 41] FIG. 10 is a schematic diagram of a drive device according to a third embodiment. [Figure 42] FIG. 10 is a schematic diagram of a vehicle according to a fourth embodiment. [Figure 43] FIG. 10 is a schematic diagram of a vehicle according to a fifth embodiment. [Figure 44] FIG. 10 is a schematic diagram of an elevator according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0009] In the following description, n + , n, n - and p + , p, p - When the notation is used, these notations represent the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n - The type is simply n-type, p + type, p - The type is sometimes simply referred to as p-type.

[0010] The impurity concentration can be measured by, for example, Secondary Ion Mass Spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration determined by, for example, Scanning Capacitance Microscopy (SCM). The distances, such as the width and depth, of the impurity region can be determined by, for example, SIMS. The distances, such as the width and depth, of the impurity region can also be determined from, for example, an SCM image.

[0011] The trench width, trench spacing, trench depth, insulating layer thickness, etc. can be measured, for example, on an image taken with a Transmission Electron Microscope (TEM).

[0012] In this specification, unless otherwise defined, the impurity concentration of a specific region is represented by the impurity concentration at the center of the region.

[0013] (First embodiment) A semiconductor device according to a first embodiment includes a silicon carbide layer having a first surface parallel to a first direction and a second direction perpendicular to the first direction, and a second surface parallel to the first surface; a first trench present in the silicon carbide layer, located on the first surface side of the silicon carbide layer, extending in the first direction, and having a first side surface and a second side surface; a first gate electrode located in the first trench; a first gate insulating layer located between the first gate electrode and the silicon carbide layer; an n-type first silicon carbide region located in the silicon carbide layer; a p-type second silicon carbide region located in the silicon carbide layer, located between the first silicon carbide region and the first surface, and having a depth from the first surface shallower than a depth from the first surface of the first trench; an n-type third silicon carbide region located between the second silicon carbide region and the first surface, including a first region in contact with the first side surface and a second region in contact with the second side surface, and having a first width in the second direction; an n-type fourth silicon carbide region located in the silicon carbide layer, between the third silicon carbide region and the first surface, including a third region in contact with the first side surface and the first region and a fourth region in contact with the second side surface and the second region, and having a second width in the second direction that is smaller than the first width; a first electrode located on the first surface side of the silicon carbide layer and in contact with the fourth silicon carbide region; a second electrode located on the second surface side of the silicon carbide layer; and an interlayer insulating layer provided between the first gate electrode and the first electrode.

[0014] The semiconductor device of the first embodiment also includes a second trench present in the silicon carbide layer, located on the first surface side of the silicon carbide layer, extending in a first direction, located in a second direction relative to the first trench, and having a third side surface facing the second side surface and a fourth side surface; a second gate electrode located in the second trench; a second gate insulating layer located between the second gate electrode and the silicon carbide layer; and a second gate insulating layer located in the silicon carbide layer and intersecting the second silicon carbide region with the first surface. and an n-type fifth silicon carbide region located between the first surface and the second surface, the n-type sixth silicon carbide region including a fifth region in contact with the third side surface and a sixth region in contact with the fourth side surface, and a seventh region in contact with the third side surface and the fifth region and an eighth region in contact with the fourth side surface and the sixth region, the n-type sixth silicon carbide region being located in the silicon carbide layer and being between the fifth silicon carbide region and the first surface, the n-type sixth silicon carbide region being a fourth width smaller than the third width. The second silicon carbide region is located between the third silicon carbide region and the fifth silicon carbide region.

[0015] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is a trench-gate vertical MOSFET 100 made of silicon carbide. The MOSFET 100 is an n-channel MOSFET that uses electrons as carriers.

[0016] Fig. 2 is a schematic cross-sectional view of the semiconductor device of the first embodiment. Fig. 2 is a cross-sectional view taken along the Fx plane in Fig. 1. Fig. 1 is a cross-sectional view taken along the line AA' in Fig. 2.

[0017] 3 is an enlarged schematic cross-sectional view of the semiconductor device of the first embodiment, and is an enlarged view of a part of FIG.

[0018] The MOSFET 100 includes a silicon carbide layer 10, a first trench 11, a first gate electrode 12, a first gate insulating layer 13, a second trench 21, a second gate electrode 22, a second gate insulating layer 23, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), and an interlayer insulating layer 43.

[0019] Hereinafter, the first trench 11 and the second trench 21 may be collectively referred to as trenches. The first gate electrode 12 and the second gate electrode 22 may be collectively referred to as gate electrodes. The first gate insulating layer 13 and the second gate insulating layer 23 may be collectively referred to as gate insulating layers.

[0020] In the silicon carbide layer 10, n + n-type drain region 50 - a p-type drift region 51 (first silicon carbide region), a p-type body region 52 (second silicon carbide region), + a first lower source region 53a (third silicon carbide region) of type n + a second lower source region 53b (fifth silicon carbide region) of type n + a first upper source region 54a (fourth silicon carbide region) of type n + a second upper source region 54b (sixth silicon carbide region) of type p + type contact region 55 (seventh silicon carbide region), and p + A field relief region 56 is provided.

[0021] Hereinafter, the first lower source region 53a and the second lower source region 53b may be collectively referred to as the lower source region 53. Furthermore, the first upper source region 54a and the second upper source region 54b may be collectively referred to as the upper source region 54.

[0022] The silicon carbide layer 10 is made of single-crystal SiC, for example, 4H—SiC.

[0023] Silicon carbide layer 10 has a first surface ("F1" in FIG. 1) and a second surface ("F2" in FIG. 1). First surface F1 and second surface F2 face each other. First surface F1 and second surface F2 are parallel to each other. Hereinafter, first surface F1 will also be referred to as the front surface, and second surface F2 will also be referred to as the back surface. Note that, hereinafter, "depth" refers to the depth in the direction toward second surface F2, with first surface F1 as the reference.

[0024] 1 to 3, the first direction and the second direction are parallel to the first plane F1, and the second direction is perpendicular to the first direction.

[0025] 1 to 3, the third direction is a direction perpendicular to the first direction and the second direction. The third direction is a direction from the first surface F1 toward the second surface F2. Hereinafter, the third direction may be referred to as the depth direction.

[0026] The first plane F1 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (0001) plane. That is, the normal is a plane inclined at an angle of 0 to 8 degrees with respect to the c-axis in the

[0001] direction. In other words, the off-angle with respect to the (0001) plane is 0 to 8 degrees. The second plane F2 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (000-1) plane.

[0027] The (0001) plane is called the silicon plane. The (000-1) plane is called the carbon plane. The tilt direction of the first plane F1 and the second plane F2 is, for example, the [11-20] direction. The [11-20] direction is the a-axis direction. In FIG. 1, for example, the second direction shown in the figure is the a-axis direction.

[0028] The first trench 11 and the second trench 21 are present in the silicon carbide layer 10. The first trench 11 and the second trench 21 are located on the surface side of the silicon carbide layer 10. The first trench 11 and the second trench 21 extend in a first direction as shown in FIG.

[0029] The widths of the first trench 11 and the second trench 21 in the second direction are, for example, smaller than the distance between the first trench 11 and the second trench 21.

[0030] The width of the first trench 11 and the second trench 21 in the second direction is, for example, not less than 0.3 μm and not more than 1 μm. The distance between the first trench 11 and the second trench 21 is, for example, not less than 0.5 μm and not more than 2 μm. The depth of the first trench 11 and the second trench 21 is, for example, not less than 1 μm and not more than 3 μm.

[0031] A plurality of trenches including the first trench 11 and the second trench 21 are repeatedly arranged in the second direction. The repeat pitch of the plurality of trenches in the second direction is, for example, not less than 1 μm and not more than 5 μm.

[0032] The first trench 11 has a first side surface 11a, a second side surface 11b, and a first bottom surface 11c. The first bottom surface 11c is provided between the first side surface 11a and the second side surface 11b.

[0033] The first gate electrode 12 is provided in the first trench 11. The first gate electrode 12 is provided between the source electrode 41 and the drain electrode 42. The first gate electrode 12 extends in a first direction.

[0034] The first gate insulating layer 13 is provided between the first gate electrode 12 and the silicon carbide layer 10. The first gate insulating layer 13 is provided between the first gate electrode 12 and each of the first lower source region 53 a, the body region 52, the drift region 51, and the electric field reduction region 56.

[0035] The second trench 21 has a third side surface 21a, a fourth side surface 21b, and a second bottom surface 21c. The second bottom surface 21c is provided between the third side surface 21a and the fourth side surface 21b. The third side surface 21a faces the second side surface 11b.

[0036] The second gate electrode 22 is provided in the second trench 21. The second gate electrode 22 is provided between the source electrode 41 and the drain electrode 42. The second gate electrode 22 extends in the first direction.

[0037] The second gate insulating layer 23 is provided between the second gate electrode 22 and the silicon carbide layer 10. The second gate insulating layer 23 is provided between the second gate electrode 22 and each of the second lower source region 53b, the body region 52, the drift region 51, and the electric field reduction region 56.

[0038] The first gate electrode 12 and the second gate electrode 22 are conductive layers, and are made of, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0039] The first gate insulating layer 13 and the second gate insulating layer 23 are, for example, silicon oxide films. For example, a high-k insulating film (a high-dielectric-constant insulating film such as HfSiON, ZrSiON, or AlON) can be used for the first gate insulating layer 13 and the second gate insulating layer 23. Furthermore, for example, a stacked film of a silicon oxide film (SiO2) and a high-k insulating film can also be used for the first gate insulating layer 13 and the second gate insulating layer 23.

[0040] The interlayer insulating layer 43 is provided on the first gate electrode 12 and on the second gate electrode 22. The interlayer insulating layer 43 is provided between the first gate electrode 12 and the source electrode 41, and between the second gate electrode 22 and the source electrode 41.

[0041] At least a portion of the interface between the interlayer insulating layer 43 and the source electrode 41 is located within the first trench 11. At least a portion of the interface between the interlayer insulating layer 43 and the source electrode 41 is located within the second trench 21.

[0042] The interlayer insulating layer 43 is, for example, a silicon oxide film.

[0043] The source electrode 41 is provided on the surface side of the silicon carbide layer 10. The source electrode 41 is provided on the surface of the silicon carbide layer 10. The source electrode 41 is electrically connected to the body region 52, the upper source region 54, the lower source region 53, and the contact region 55. The source electrode 41 is in contact with the upper source region 54 and the contact region 55.

[0044] The source electrode 41 contacts the first side surface 11a and the second side surface 11b of the first trench 11. The source electrode 41 contacts the third region 54ax of the first upper source region 54a at the first side surface 11a. The source electrode 41 contacts the fourth region 54ay of the first upper source region 54a at the second side surface 11b.

[0045] The source electrode 41 contacts the third side surface 21a and the fourth side surface 21b of the second trench 21. The source electrode 41 contacts the seventh region 54bx of the second upper source region 54b at the third side surface 21a. The source electrode 41 contacts the eighth region 54by of the second upper source region 54b at the fourth side surface 21b.

[0046] The source electrode 41 includes a metal. The metal forming the source electrode 41 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). The source electrode 41 may include a metal silicide or a metal carbide in contact with the silicon carbide layer 10.

[0047] The drain electrode 42 is provided on the back surface side of the silicon carbide layer 10. The drain electrode 42 is provided on the back surface of the silicon carbide layer 10. The drain electrode 42 is in contact with the drain region 50.

[0048] The drain electrode 42 is, for example, a metal or a metal-semiconductor compound, and includes, for example, a material selected from the group consisting of nickel silicide (NiSi), titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0049] n + The n-type drain region 50 is provided on the back surface side of the silicon carbide layer 10. The drain region 50 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 50 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The following is the result.

[0050] n -A type drift region 51 is provided on the drain region 50. The drift region 51 is provided between the drain region 50 and the surface of the silicon carbide layer 10.

[0051] The drift region 51 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 51 is, for example, 4×10 14 cm -3 More than 1×10 18 cm -3 The thickness of the drift region 51 in the third direction is, for example, not less than 4 μm and not more than 150 μm.

[0052] The p-type body region 52 is provided between the drift region 51 and the surface of the silicon carbide layer 10. The body region 52 is provided between the first trench 11 and the second trench 21. The body region 52 contacts the first side surface 11a, the second side surface 11b, the third side surface 21a, and the fourth side surface 21b.

[0053] The body region 52 functions as a channel region of the MOSFET 100. For example, when the MOSFET 100 is in an on-state, a channel through which electrons flow is formed in the region of the body region 52 that is in contact with the gate insulating layer.

[0054] The depth of body region 52 is deeper than the depth of first trench 11 from the surface of silicon carbide layer 10. First trench 11 penetrates body region 52. The depth of body region 52 is deeper than the depth of second trench 21 from the surface of silicon carbide layer 10. Second trench 21 penetrates body region 52. The depth of body region 52 is, for example, not less than 0.8 μm and not more than 2.0 μm.

[0055] The body region 52 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 52 is, for example, 5×10 16 cm -3 5x10 or more 18 cm -3 The following is the result.

[0056] n +A first lower source region 53a of the type is provided between the body region 52 and the surface of the silicon carbide layer 10. The first lower source region 53a extends in a first direction.

[0057] The first lower source region 53a includes a first region 53ax and a second region 53ay. The first trench 11 is located between the first region 53ax and the second region 53ay. The second region 53ay is located in a second direction from the first region 53ax.

[0058] The first region 53ax contacts the first side surface 11a of the first trench 11. The second region 53ay contacts the second side surface 11b of the first trench 11.

[0059] The first lower source region 53a contains nitrogen (N) or phosphorus (P) as an n-type impurity. The n-type impurity concentration of the first lower source region 53a is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0060] The depth of the first lower source region 53a is shallower than the depth of the body region 52. The depth of the first lower source region 53a is, for example, not less than 0.4 μm and not more than 1.0 μm. The distance between the drift region 51 and the first lower source region 53a is, for example, not less than 0.1 μm and not more than 0.9 μm.

[0061] n + The second lower source region 53b is provided between the body region 52 and the surface of the silicon carbide layer 10. The second lower source region 53b extends in the first direction.

[0062] The second lower source region 53b is provided in the second direction of the first lower source region 53a. The body region 52 is located between the first lower source region 53a and the second lower source region 53b.

[0063] The second lower source region 53b includes a fifth region 53bx and a sixth region 53by. The second trench 21 is located between the fifth region 53bx and the sixth region 53by. The sixth region 53by is located in the second direction of the fifth region 53bx.

[0064] The fifth region 53bx contacts the third side surface 21a of the second trench 21. The sixth region 53by contacts the fourth side surface 21b of the second trench 21.

[0065] The second lower source region 53b contains nitrogen (N) or phosphorus (P) as an n-type impurity. The n-type impurity concentration of the second lower source region 53b is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0066] The depth of the second lower source region 53b is shallower than the depth of the body region 52. The depth of the second lower source region 53b is, for example, not less than 0.1 μm and not more than 0.3 μm. The distance between the drift region 51 and the second lower source region 53b is, for example, not less than 0.1 μm and not more than 0.9 μm.

[0067] n + The first upper source region 54a of the N-type is provided between the first lower source region 53a and the surface of the silicon carbide layer 10. The first upper source region 54a extends in a first direction.

[0068] The first upper source region 54a includes a third region 54ax and a fourth region 54ay. The first trench 11 is located between the third region 54ax and the fourth region 54ay. The fourth region 54ay is located in the second direction from the third region 54ax.

[0069] The third region 54ax contacts the first side surface 11a of the first trench 11. The third region 54ax contacts the first region 53ax. The fourth region 54ay contacts the second side surface 11b of the first trench 11. The fourth region 54ay contacts the second region 53ay.

[0070] The first upper source region 54a is in contact with the source electrode 41. The first upper source region 54a is in contact with the source electrode 41 on the side surface of the first trench 11.

[0071] The third region 54ax contacts the source electrode 41 on the first side surface 11a of the first trench 11. The fourth region 54ay contacts the source electrode 41 on the second side surface 11b of the first trench 11.

[0072] The first upper source region 54a contains nitrogen (N) or phosphorus (P) as an n-type impurity. The n-type impurity concentration of the first upper source region 54a is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0073] n + The second upper source region 54b of the N-type is provided between the second lower source region 53b and the surface of the silicon carbide layer 10. The second upper source region 54b extends in the first direction.

[0074] The second upper source region 54b includes a seventh region 54bx and an eighth region 54by. The second trench 21 is located between the seventh region 54bx and the eighth region 54by. The eighth region 54by is located in a second direction from the seventh region 54bx.

[0075] The seventh region 54bx contacts the third side surface 21a of the second trench 21. The seventh region 54bx contacts the fifth region 53bx. The eighth region 54by contacts the fourth side surface 21b of the second trench 21. The eighth region 54by contacts the sixth region 53by.

[0076] The second upper source region 54b contacts the source electrode 41. The second upper source region 54b contacts the source electrode 41 on the side surface of the second trench 21.

[0077] The seventh region 54bx contacts the source electrode 41 on the third side surface 21a of the second trench 21. The eighth region 54by contacts the source electrode 41 on the fourth side surface 21b of the second trench 21.

[0078] The second upper source region 54b contains nitrogen (N) or phosphorus (P) as an n-type impurity. The n-type impurity concentration of the second upper source region 54b is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0079] The second upper source region 54b is provided in a second direction from the first upper source region 54a. The body region 52 is located between the first upper source region 54a and the second upper source region 54b.

[0080] The second width (w2 in FIG. 3) of the first upper source region 54a in the second direction is smaller than the first width (w1 in FIG. 3) of the first lower source region 53a in the second direction. In other words, the first width (w1 in FIG. 3) of the first lower source region 53a in the second direction is larger than the second width (w2 in FIG. 3) of the first upper source region 54a in the second direction. The difference between the first width (w1 in FIG. 3) of the first lower source region 53a in the second direction and the second width (w2 in FIG. 3) of the first upper source region 54a in the second direction is, for example, 0.1 μm or more.

[0081] The width of the third region 54ax in the second direction (w4 in FIG. 3) is, for example, smaller than the width of the first region 53ax in the second direction (w3 in FIG. 3). In other words, the width of the first region 53ax in the second direction (w3 in FIG. 3) is, for example, larger than the width of the third region 54ax in the second direction (w4 in FIG. 3).

[0082] Furthermore, the width of the fourth region 54ay in the second direction (w6 in FIG. 3) is smaller than, for example, the width of the second region 53ay in the second direction (w5 in FIG. 3). In other words, the width of the second region 53ay in the second direction (w5 in FIG. 3) is larger than, for example, the width of the fourth region 54ay in the second direction (w6 in FIG. 3).

[0083] The fourth width in the second direction of the second upper source region 54b is smaller than the third width in the second direction of the second lower source region 53b. In other words, the third width in the second direction of the second lower source region 53b is larger than the fourth width in the second direction of the second upper source region 54b. The difference between the third width in the second direction of the second lower source region 53b and the fourth width in the second direction of the second upper source region 54b is, for example, 0.1 μm or more.

[0084] The width of the seventh region 54bx in the second direction is, for example, smaller than the width of the fifth region 53bx in the second direction, and the width of the eighth region 54by in the second direction is smaller than the width of the sixth region 53by in the second direction.

[0085] 4 is a diagram showing the profile of the n-type impurity concentration of the semiconductor device of the first embodiment. Fig. 4 shows the n-type impurity profile in the direction from the first face F1 to the second face F2 of a portion including the upper source region 54, the lower source region 53, and the body region 52 of the silicon carbide layer 10. Specifically, it is the n-type impurity profile of the portion indicated by the dotted arrow in Fig. 3.

[0086] 4, in the MOSFET 100, the standard deviation (ΔRp) of the profile at the base of the body region 52 in the n-type impurity profile is 0.08 μm or less. The standard deviation (ΔRp) of the profile at the base of the body region 52 can be calculated by fitting the profile to a Pearson distribution.

[0087] p +The contact region 55 is provided between the body region 52 and the surface of the silicon carbide layer 10. The contact region 55 is in contact with the source electrode 41.

[0088] The contact region 55 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the contact region 55 is higher than the p-type impurity concentration of the body region 52, for example.

[0089] The p-type impurity concentration of the contact region 55 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The p-type impurity concentration of the contact region 55 in the contact area with the source electrode 41 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0090] p + A type electric field relaxation region 56 is provided between the drift region 51 and the first trench 11. The electric field relaxation region 56 is provided between the drift region 51 and the first bottom surface 11c. The electric field relaxation region 56 is in contact with the first bottom surface 11c.

[0091] The electric field relaxation region 56 is provided between the drift region 51 and the second trench 21. The electric field relaxation region 56 is provided between the drift region 51 and the second bottom surface 21c. The electric field relaxation region 56 is in contact with the second bottom surface 21c.

[0092] The electric field buffer region 56 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the electric field buffer region 56 is higher than the p-type impurity concentration of the body region 52. The p-type impurity concentration of the electric field buffer region 56 is, for example, 1×10 17 cm -3 More than 1×10 20 cm -3 The following is the result.

[0093] The potential of the electric field relaxation region 56 is fixed, for example, to the potential of the source electrode 41. The potential of the electric field relaxation region 56 is fixed, for example, to the source potential. The electric field relaxation region 56 has the function of relaxing the electric field applied to the gate insulating layer at the bottom of the trench.

[0094] A method for manufacturing a semiconductor device according to a first embodiment includes ion-implanting p-type impurities into an n-type first silicon carbide layer to form a p-type first region, forming a first mask material on the first silicon carbide layer, the first mask material having a first opening that exposes the first region, using the first mask material as a mask to ion-implant n-type impurities into the first region through the first opening to form an n-type second region shallower than the first region, peeling off the first mask material, forming a p-type second silicon carbide layer on the first silicon carbide layer by epitaxial growth, and forming a p-type second silicon carbide layer on the second silicon carbide layer. a second mask material having a second opening exposing the second silicon carbide layer on top of the second region; using the second mask material as a mask, n-type impurities are ion-implanted into the second silicon carbide layer through the second opening to form an n-type third region in contact with the second region; a sidewall is formed at the second opening; using the second mask material and the sidewall as a mask, a trench is formed that penetrates the third region, the second region, and the first region; a gate insulating layer is formed in the trench; and a gate electrode having an upper surface located within the trench is formed on the gate insulating layer in the trench.

[0095] An example of a method for manufacturing the semiconductor device of the first embodiment will be described below.

[0096] Figures 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device of the first embodiment. Figures 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 are cross-sectional views corresponding to Figure 1.

[0097] First, n + A drain region 50 of the type and an n-type semiconductor layer formed on the drain region 50 by epitaxial growth.- A silicon carbide layer 10 having a first epitaxial layer 60 of a type is prepared (FIG. 5). The first epitaxial layer 60 is an example of a first silicon carbide layer. A portion of the first epitaxial layer 60 will eventually become the drift region 51.

[0098] Next, p-type impurities are ion-implanted into the first epitaxial layer 60 to form a p-type body region 52 (FIG. 6). The body region 52 is an example of a first region. The p-type impurity is, for example, aluminum (Al). The body region 52 can also be formed using an epitaxial growth method.

[0099] Next, a first mask material 61 is formed on the first epitaxial layer 60 (FIG. 7). The first mask material 61 has a first opening 61a. The body region 52 is exposed in the first opening 61a.

[0100] The first mask material 61 is formed by, for example, depositing a film by a chemical vapor deposition (CVD) method, and patterning the film by a lithography method and a reactive ion etching (RIE) method. The first mask material 61 is, for example, a silicon oxide film.

[0101] Next, using the first mask material 61 as a mask, n-type impurities are ion-implanted into the body region 52 through the first opening 61a. + An n-type lower source region 53 is formed (FIG. 8). The lower source region 53 is an example of a second region. The lower source region 53 is shallower than the body region 52. The n-type impurity is, for example, phosphorus (P) or nitrogen (N).

[0102] When forming the lower source region 53, if the n-type impurity to be ion-implanted is phosphorus (P), the ion implantation is performed with an acceleration energy of, for example, 100 keV to 350 keV. If the n-type impurity to be ion-implanted is nitrogen (N), the ion implantation is performed with an acceleration energy of, for example, 100 keV to 450 keV.

[0103] Next, the first mask material 61 is removed by, for example, wet etching.

[0104] Next, a p-type second epitaxial layer 70 is formed on the first epitaxial layer 60 using an epitaxial growth method (FIG. 9). The second epitaxial layer 70 is an example of a second silicon carbide layer. Note that, for example, it is also possible to form a p-type second epitaxial layer by forming an n-type epitaxial layer using an epitaxial growth method and then ion-implanting p-type impurities.

[0105] Next, p-type impurities are ion-implanted into the second epitaxial layer 70 to form p + A p-type contact region 55 is formed (FIG. 10). The contact region 55 is an example of the fourth region. The p-type impurity is, for example, aluminum (Al).

[0106] Next, a second mask material 62 is formed on the second epitaxial layer 70 (FIG. 11). The second mask material 62 has a second opening 62a. The second epitaxial layer 70 above the lower source region 53 is exposed in the second opening 62a. The width of the second opening 62a in the second direction is smaller than the width of the lower source region 53 in the second direction.

[0107] The second mask material 62 is formed by, for example, depositing a film by a CVD method, and patterning the film by a lithography method and an RIE method. The second mask material 62 is, for example, a silicon oxide film.

[0108] Next, using the second mask material 62 as a mask, a recess 71 is formed that penetrates the contact region 55 (FIG. 12). The recess 71 is formed by, for example, the RIE method.

[0109] Next, using the second mask material 62 as a mask, n-type impurities are ion-implanted into the second epitaxial layer 70 through the second opening 62a, thereby forming n +An n-type upper source region 54 is formed (FIG. 13). The upper source region 54 is an example of a third region. The upper source region 54 contacts the lower source region 53. The upper source region 54 is shallower than the lower source region 53. The n-type impurity is, for example, phosphorus (P) or nitrogen (N).

[0110] Next, a sidewall 63 is formed in the second opening 62a of the second mask material 62 (FIG. 14). The sidewall 63 is, for example, a silicon oxide film.

[0111] Next, using the second mask material 62 and the sidewall 63 as a mask, a trench 72 is formed (FIG. 15). The trench 72 penetrates the upper source region 54, the lower source region 53, and the body region 52. The trench 72 is formed by, for example, the RIE method.

[0112] The upper source region 54 and the lower source region 53 are divided into left and right halves by a trench 72. The upper source region 54 and the lower source region 53 are divided into two regions sandwiching the trench.

[0113] Next, using the second mask material 62 and the sidewall 63 as a mask, p-type impurity ions are implanted. + A p-type electric field relaxation region 56 is formed (FIG. 16). The electric field relaxation region 56 is formed at the bottom of the trench 72. The p-type impurity is, for example, aluminum (Al).

[0114] Next, the second mask material 62 and the sidewall 63 are removed. The second mask material 62 and the sidewall 63 are removed by, for example, wet etching.

[0115] Next, a gate insulating layer 73 is formed in the trench 72. Next, a gate electrode 74 is formed on the gate insulating layer 73 in the trench 72 (FIG. 17). The upper surface of the gate electrode 74 is located in the trench 72.

[0116] The gate insulating layer 73 is, for example, a silicon oxide film. The gate electrode 74 is, for example, polycrystalline silicon containing p-type impurities or n-type impurities. The gate insulating layer 73 and the gate electrode 74 are formed by, for example, a CVD method.

[0117] Next, the trench 72 is filled with a buried insulating layer 75 (FIG. 18). The buried insulating layer 75 is an example of an insulating layer. The buried insulating layer 75 is, for example, a silicon oxide film. The buried insulating layer 75 is formed by, for example, a CVD method.

[0118] Next, the buried insulating layer 75 is etched so as to expose at least a part of the side surface of the trench 72 (FIG. 19). For example, the upper source region 54 is exposed on the side surface of the trench 72.

[0119] Next, the source electrode 41 is formed. The source electrode 41 is formed in the trench 72 and on the upper surface of the second epitaxial layer 70. The source electrode 41 is formed, for example, on the side surface of the trench 72 so as to contact the upper source region 54. The source electrode 41 is formed, for example, by depositing a metal film by a CVD method.

[0120] Thereafter, a drain electrode 42 is formed on the back surface of the silicon carbide layer 10 using a known process technique (FIG. 20).

[0121] By the above manufacturing method, the MOSFET 100 shown in FIGS. 1 to 3 is manufactured.

[0122] Next, the operation and effects of the semiconductor device of the first embodiment will be described.

[0123] The MOSFET 100 of the first embodiment can achieve a reduced on-resistance and a high threshold voltage, as will be described in detail below.

[0124] A trench gate structure in which a gate electrode is provided in a trench is applied to the MOSFET 100. By applying the trench gate structure, the channel area per unit area increases, and the on-resistance of the MOSFET 100 is reduced.

[0125] In the MOSFET 100, the source electrode 41 contacts the upper source region 54 on the side surface of the first trench 11 and the side surface of the second trench 21. By realizing the contact of the source electrode 41 with the source region on the side surface of the trench, the distance between the trenches can be reduced. This allows the MOSFET 100 to be miniaturized, further reducing the on-resistance of the MOSFET 100.

[0126] When the contact of the source electrode with the source region is provided on the side of the trench, the depth of the source region must be made deeper. The source region is formed by ion implantation of n-type impurities. To make the source region deeper, the acceleration energy of the ion implantation of n-type impurities must be increased. As the acceleration energy of the ion implantation increases, the tail of the n-type impurity profile in the depth direction becomes larger.

[0127] In a trench-gate MOSFET, if the depth of the n-type impurity profile in the source region extends too far, the short-channel effect of the MOSFET may increase, resulting in a lower threshold voltage and a larger variation in threshold voltage.

[0128] The source region of the MOSFET 100 has a two-layer structure consisting of a lower source region 53 and an upper source region 54. By providing the source region with a two-layer structure, the acceleration energy of the ion implantation of n-type impurities can be reduced compared to, for example, a case where the source region is made of a single layer. Therefore, the base extension of the n-type impurity profile in the lower source region 53 in the depth direction can be reduced.

[0129] Therefore, the short channel effect is suppressed and a high threshold voltage can be achieved with the MOSFET 100. Furthermore, the short channel effect is suppressed and variations in threshold voltage are suppressed.

[0130] From the viewpoint of realizing a high threshold voltage, it is preferable that the standard deviation (ΔRp) of the profile of the n-type impurity in the depth direction of the portion of silicon carbide layer 10 including lower source region 53 and body region 52 is 0.08 μm or less at the base of the profile on the body region 52 side.

[0131] When the n-type impurity to be ion-implanted in forming the lower source region 53 of the MOSFET 100 is phosphorus (P), the ion implantation is preferably performed with an acceleration energy of 350 keV or less. When the n-type impurity to be ion-implanted is nitrogen (N), the ion implantation is preferably performed with an acceleration energy of 450 keV or less.

[0132] By limiting the acceleration energy to the above range, the standard deviation (ΔRp) of the profile at the base on the body region 52 side in the depth direction of the n-type impurity profile of the portion including the lower source region 53 and the body region 52 of the silicon carbide layer 10 can be made 0.08 μm or less.

[0133] The second width (w2 in FIG. 3) of the first upper source region 54a in the second direction is smaller than the first width (w1 in FIG. 3) of the first lower source region 53a in the second direction. In other words, the first width (w1 in FIG. 3) of the first lower source region 53a in the second direction is larger than the second width (w2 in FIG. 3) of the first upper source region 54a in the second direction.

[0134] The fourth width in the second direction of the second upper source region 54b is smaller than the third width in the second direction of the second lower source region 53b. In other words, the third width in the second direction of the second lower source region 53b is larger than the fourth width in the second direction of the second upper source region 54b.

[0135] When forming the second mask material 62 (see FIG. 11) in manufacturing the MOSFET 100, the second mask material 62 may be misaligned in the second direction relative to the lower source region 53 due to misalignment in the lithography process. If the second mask material 62 is misaligned in the second direction relative to the lower source region 53, one of the widths in the second direction (wx in FIG. 15) of the two regions of the lower source region 53 divided into left and right parts by the trench 72 may become smaller (see FIG. 15).

[0136] When the width in the second direction of the lower source region 53 divided into left and right halves by the trench 72 becomes smaller, the parasitic resistance of the MOSFET 100 increases. Therefore, the on-resistance of the MOSFET 100 increases. In particular, when the width in the second direction of the lower source region 53 divided into left and right halves by the trench 72 (wx in FIG. 15) becomes smaller than the width in the second direction of the upper source region 54 divided into left and right halves by the trench 72 (wy in FIG. 15), the parasitic resistance of the MOSFET 100 increases, and the on-resistance of the MOSFET 100 increases.

[0137] When the width in the second direction of lower source region 53 divided into left and right halves by trench 72 becomes smaller, the parasitic resistance of MOSFET 100 varies, and the variation in the on-resistance of MOSFET 100 also increases.

[0138] In the MOSFET 100, the width of the lower source region 53 in the second direction is larger than the width of the upper source region in the second direction. Therefore, even if the second mask material 62 is shifted in the second direction relative to the lower source region 53 due to misalignment in the lithography process, the width in the second direction (wx in FIG. 15 ) of the lower source region 53 divided into left and right halves by the trench 72 is prevented from becoming smaller. This reduces the on-resistance of the MOSFET 100. Furthermore, variations in the on-resistance of the MOSFET 100 are also reduced.

[0139] From the viewpoint of reducing the on-resistance of MOSFET 100, the difference between the first width in the second direction (w1 in FIG. 3) of first lower source region 53a and the second width in the second direction (w2 in FIG. 3) of first upper source region 54a is preferably 0.1 μm or more. Also, the difference between the third width in the second direction of second lower source region 53b and the fourth width in the second direction of second upper source region 54b is preferably 0.1 μm or more.

[0140] The width in the second direction of the third region 54ax (w4 in FIG. 3) is preferably smaller than the width in the second direction of the first region 53ax (w3 in FIG. 3) from the viewpoint of reducing the on-resistance of the MOSFET 100. In other words, the width in the second direction of the first region 53ax (w3 in FIG. 3) is preferably larger than the width in the second direction of the third region 54ax (w4 in FIG. 3).

[0141] Furthermore, the width of the fourth region 54ay in the second direction (w6 in FIG. 3) is preferably smaller than the width of the second region 53ay in the second direction (w5 in FIG. 3). In other words, the width of the second region 53ay in the second direction (w5 in FIG. 3) is preferably larger than the width of the fourth region 54ay in the second direction (w6 in FIG. 3).

[0142] (Variation) Fig. 21 is a schematic cross-sectional view of a semiconductor device according to a modification of the first embodiment, and corresponds to Fig. 1 of the first embodiment.

[0143] MOSFET 101 of the modification differs from MOSFET 100 of the first embodiment in that a part of interlayer insulating layer 43 exists above first face F1 of silicon carbide layer 10.

[0144] As described above, the MOSFETs of the first embodiment and the modifications thereof can achieve a reduced on-resistance and a high threshold voltage.

[0145] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that a seventh silicon carbide region is provided between the third silicon carbide region and the fifth silicon carbide region. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0146] 22 is a schematic cross-sectional view of a semiconductor device according to the second embodiment. The semiconductor device according to the second embodiment is a trench-gate vertical MOSFET 200 made of silicon carbide. The MOSFET 200 is an n-channel MOSFET that uses electrons as carriers.

[0147] Fig. 23 is a schematic cross-sectional view of the semiconductor device of the second embodiment. Fig. 23 is a cross-sectional view taken along the Fx plane in Fig. 22. Fig. 22 is a cross-sectional view taken along the line AA' in Fig. 23.

[0148] 24 is an enlarged schematic cross-sectional view of the semiconductor device of the second embodiment, and is an enlarged view of a part of FIG.

[0149] The MOSFET 200 includes a silicon carbide layer 10, a first trench 11, a first gate electrode 12, a first gate insulating layer 13, a second trench 21, a second gate electrode 22, a second gate insulating layer 23, a source electrode 41 (first electrode), a drain electrode 42 (second electrode), and an interlayer insulating layer 43.

[0150] Hereinafter, the first trench 11 and the second trench 21 may be collectively referred to as trenches. The first gate electrode 12 and the second gate electrode 22 may be collectively referred to as gate electrodes. The first gate insulating layer 13 and the second gate insulating layer 23 may be collectively referred to as gate insulating layers.

[0151] In the silicon carbide layer 10, n + n-type drain region 50 - a p-type drift region 51 (first silicon carbide region), a p-type body region 52 (second silicon carbide region), + a first lower source region 53a (third silicon carbide region) of type n +a second lower source region 53b (fifth silicon carbide region) of type n + a first upper source region 54a (fourth silicon carbide region) of type n + a second upper source region 54b (sixth silicon carbide region) of type p + type contact region 55 (seventh silicon carbide region), and p + A field relief region 56 is provided.

[0152] Hereinafter, the first lower source region 53a and the second lower source region 53b may be collectively referred to as the lower source region 53. Furthermore, the first upper source region 54a and the second upper source region 54b may be collectively referred to as the upper source region 54.

[0153] p + The contact region 55 is provided between the body region 52 and the surface of the silicon carbide layer 10. The contact region 55 is in contact with the source electrode 41.

[0154] The contact region 55 is provided between the first upper source region 54a and the second upper source region 54b. The contact region 55 contacts the first upper source region 54a. The contact region 55 contacts the second upper source region 54b.

[0155] The contact region 55 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the contact region 55 is higher than the p-type impurity concentration of the body region 52, for example.

[0156] The p-type impurity concentration of the contact region 55 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The p-type impurity concentration of the contact region 55 in the contact area with the source electrode 41 is, for example, 1×10 19 cm -3 More than 1×10 21 cm -3 The following is the result.

[0157] The method for manufacturing a semiconductor device according to the second embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that a p-type fourth region is formed after forming a trench. Hereinafter, some of the content that overlaps with the method for manufacturing a semiconductor device according to the first embodiment may be omitted.

[0158] An example of a method for manufacturing the semiconductor device according to the second embodiment will be described below.

[0159] Figures 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, and 39 are schematic cross-sectional views showing an example of a method for manufacturing the semiconductor device of the second embodiment. Figures 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, and 39 are cross-sectional views corresponding to Figure 22.

[0160] First, n + A drain region 50 of the type and an n-type semiconductor layer formed on the drain region 50 by epitaxial growth. - A silicon carbide layer 10 having a first epitaxial layer 60 of a type is prepared (FIG. 25). The first epitaxial layer 60 is an example of a first silicon carbide layer. A portion of the first epitaxial layer 60 will eventually become the drift region 51.

[0161] Next, p-type impurities are ion-implanted into the first epitaxial layer 60 to form a p-type body region 52 (FIG. 26). The body region 52 is an example of a first region. The p-type impurity is, for example, aluminum (Al). The body region 52 can also be formed by epitaxial growth.

[0162] Next, a first mask material 61 is formed on the first epitaxial layer 60 (FIG. 27). The first mask material 61 has a first opening 61a. The body region 52 is exposed in the first opening 61a.

[0163] The first mask material 61 is formed by, for example, depositing a film by a CVD method, and patterning the film by a lithography method and an RIE method. The first mask material 61 is, for example, a silicon oxide film.

[0164] Next, using the first mask material 61 as a mask, n-type impurities are ion-implanted into the body region 52 through the first opening 61a. + An n-type lower source region 53 is formed (FIG. 28). The lower source region 53 is an example of a second region. The lower source region 53 is shallower than the body region 52. The n-type impurity is, for example, phosphorus (P) or nitrogen (N).

[0165] When forming the lower source region 53, if the n-type impurity to be ion-implanted is phosphorus (P), the ion implantation is performed with an acceleration energy of, for example, 100 keV to 350 keV. If the n-type impurity to be ion-implanted is nitrogen (N), the ion implantation is performed with an acceleration energy of, for example, 100 keV to 450 keV.

[0166] Next, the first mask material 61 is removed by, for example, wet etching.

[0167] Next, a p-type second epitaxial layer 70 is formed on the first epitaxial layer 60 using an epitaxial growth method (FIG. 29). The second epitaxial layer 70 is an example of a second silicon carbide layer. Note that, for example, it is also possible to form a p-type second epitaxial layer by forming an n-type epitaxial layer using an epitaxial growth method and then ion-implanting p-type impurities.

[0168] Next, a second mask material 62 is formed on the second epitaxial layer 70 (FIG. 30). The second mask material 62 has a second opening 62a. The second epitaxial layer 70 above the lower source region 53 is exposed in the second opening 62a. The width of the second opening 62a in the second direction is smaller than the width of the lower source region 53 in the second direction.

[0169] The second mask material 62 is formed by, for example, depositing a film by a CVD method, and patterning the film by a lithography method and an RIE method. The second mask material 62 is, for example, a silicon oxide film.

[0170] Next, using the second mask material 62 as a mask, n-type impurities are ion-implanted into the second epitaxial layer 70 through the second opening 62a, thereby forming n + An n-type upper source region 54 is formed (FIG. 31). The upper source region 54 is an example of a third region. The upper source region 54 contacts the lower source region 53. The upper source region 54 is shallower than the lower source region 53. The n-type impurity is, for example, phosphorus (P) or nitrogen (N).

[0171] Next, a sidewall 63 is formed in the second opening 62a of the second mask material 62 (FIG. 32). The sidewall 63 is, for example, a silicon oxide film.

[0172] Next, using the second mask material 62 and the sidewall 63 as a mask, a trench 72 is formed (FIG. 33). The trench 72 penetrates the upper source region 54, the lower source region 53, and the body region 52. The trench 72 is formed by, for example, the RIE method.

[0173] The upper source region 54 and the lower source region 53 are divided into left and right halves by a trench 72. The upper source region 54 and the lower source region 53 are divided into two regions sandwiching the trench.

[0174] Next, using the second mask material 62 and the sidewall 63 as a mask, p-type impurity ions are implanted. + A p-type electric field relaxation region 56 is formed (FIG. 34). The electric field relaxation region 56 is formed at the bottom of the trench 72. The p-type impurity is, for example, aluminum (Al).

[0175] Next, the second mask material 62 and the sidewall 63 are removed. The second mask material 62 and the sidewall 63 are removed by, for example, wet etching (FIG. 35).

[0176] Next, a third mask material 77 is formed in the trenches 72 and on the second epitaxial layer 70 .

[0177] The third mask material 77 is formed by depositing a film by, for example, a CVD method, and patterning the film by, for example, a lithography method and an RIE method. The third mask material 77 is, for example, a silicon oxide film.

[0178] Next, using the third mask material 77 as a mask, p-type impurities are ion-implanted into the second epitaxial layer 70, + A p-type contact region 55 is formed (FIG. 36). The contact region 55 is an example of the fourth region. The p-type impurity is, for example, aluminum (Al).

[0179] Next, the third mask material 77 is removed by, for example, wet etching.

[0180] Next, a gate insulating layer 73 is formed in the trench 72. Next, a gate electrode 74 is formed on the gate insulating layer 73 in the trench 72. The upper surface of the gate electrode 74 is located in the trench 72.

[0181] The gate insulating layer 73 is, for example, a silicon oxide film. The gate electrode 74 is, for example, polycrystalline silicon containing p-type impurities or n-type impurities. The gate insulating layer 73 and the gate electrode 74 are formed by, for example, a CVD method.

[0182] Next, the trench 72 is filled with a buried insulating layer 75 (FIG. 37). The buried insulating layer 75 is an example of an insulating layer. The buried insulating layer 75 is, for example, a silicon oxide film. The buried insulating layer 75 is formed by, for example, a CVD method.

[0183] Next, the buried insulating layer 75 is etched so as to expose at least a part of the side surface of the trench 72 (FIG. 38). The upper source region 54 is exposed on the side surface of the trench 72.

[0184] Next, the source electrode 41 is formed. The source electrode 41 is an example of an electrode. The source electrode 41 is formed in the trench 72 and on the upper surface of the second epitaxial layer 70. The source electrode 41 is formed, for example, on the side surface of the trench 72 so as to contact the upper source region 54. The source electrode 41 is formed, for example, by depositing a metal film by a CVD method.

[0185] Thereafter, a drain electrode 42 is formed on the back surface of the silicon carbide layer 10 using a known process technique (FIG. 39).

[0186] By the above manufacturing method, the MOSFET 200 shown in FIGS. 22 to 24 is manufactured.

[0187] The MOSFET 200 of the second embodiment has the same functions and effects as the MOSFET 100 of the first embodiment. That is, the MOSFET 200 can be miniaturized, and the on-resistance of the MOSFET 200 is reduced. In addition, the short channel effect is suppressed, and a high threshold voltage can be achieved. In addition, the short channel effect is suppressed, and variations in threshold voltage are suppressed.

[0188] (Variation) Fig. 40 is a schematic cross-sectional view of a semiconductor device according to a modification of the second embodiment, which corresponds to Fig. 22 of the first embodiment.

[0189] The MOSFET 201 of the modification differs from the MOSFET 200 of the second embodiment in that a part of the interlayer insulating layer 43 is located above the first face F1 of the silicon carbide layer 10.

[0190] As described above, the MOSFETs of the second embodiment and the modified examples can achieve a reduced on-resistance and a high threshold voltage.

[0191] (Third embodiment) The inverter circuit and the drive device of the third embodiment are drive devices that include the semiconductor device of the first embodiment.

[0192] 41 is a schematic diagram of a driving device of the third embodiment. The driving device 1000 includes a motor 140 and an inverter circuit 150.

[0193] The inverter circuit 150 is composed of three semiconductor modules 150a, 150b, and 150c, each of which uses the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140.

[0194] According to the third embodiment, the inverter circuit 150 and the driving device 1000 are provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the inverter circuit 150 and the driving device 1000.

[0195] (Fourth embodiment) The vehicle of the fourth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0196] 42 is a schematic diagram of a vehicle according to the fourth embodiment. The vehicle 1100 according to the fourth embodiment is a railway vehicle. The vehicle 1100 includes a motor 140 and an inverter circuit 150.

[0197] The inverter circuit 150 is composed of three semiconductor modules that use the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The wheels 90 of the vehicle 1100 are rotated by the motor 140.

[0198] According to the fourth embodiment, the vehicle 1100 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 1100.

[0199] (Fifth embodiment) The vehicle of the fifth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0200] 43 is a schematic diagram of a vehicle according to the fifth embodiment. The vehicle 1200 according to the fifth embodiment is an automobile. The vehicle 1200 includes a motor 140 and an inverter circuit 150.

[0201] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0202] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the wheels 90 of the vehicle 1200.

[0203] According to the fifth embodiment, the vehicle 1200 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the vehicle 1200.

[0204] (Sixth embodiment) The elevator of the sixth embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0205] 44 is a schematic diagram of an elevator according to the sixth embodiment. The elevator 1300 according to the sixth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoist 616, a motor 140, and an inverter circuit 150.

[0206] The inverter circuit 150 is composed of three semiconductor modules using the MOSFET 100 of the first embodiment as a switching element. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 having three AC voltage output terminals U, V, and W is realized.

[0207] The motor 140 is driven by the AC voltage output from the inverter circuit 150. The motor 140 rotates the hoisting machine 616, causing the car 610 to rise and fall.

[0208] According to the sixth embodiment, the elevator 1300 is provided with the MOSFET 100 having improved characteristics, thereby improving the characteristics of the elevator 1300.

[0209] In the above, the first and second embodiments have been described using an example in which the silicon carbide has a crystal structure of 4H—SiC, but the present invention can also be applied to silicon carbide with other crystal structures, such as 6H—SiC and 3C—SiC.

[0210] In the first and second embodiments, a MOSFET is used as an example of a semiconductor device, but the present invention can also be applied to an Insulated Gate Bipolar Transistor (IGBT). For example, an IGBT can be realized by replacing the region corresponding to the drain region 50 of the MOSFET 100 from n-type to p-type.

[0211] Furthermore, in the third to sixth embodiments, the semiconductor device of the first embodiment is used as an example, but the semiconductor device of the second embodiment can also be applied.

[0212] Furthermore, in the third to sixth embodiments, the semiconductor device of the present invention has been described as being applied to vehicles and elevators, but the semiconductor device of the present invention can also be applied to, for example, a power conditioner of a solar power generation system.

[0213] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0214] 10 Silicon carbide layer 11 First Trench 11a First Aspect 11b The second aspect 11c First bottom 12 First gate electrode 13 First gate insulating layer 21 Second Trench 21a The Third Aspect 21b The Fourth Aspect 21c Second bottom 22 second gate electrode 23 Second gate insulating layer 41 source electrode (first electrode, electrode) 42 drain electrode (second electrode) 43 Interlayer insulating layer 51 drift region (first silicon carbide region) 52 body region (second silicon carbide region, first region) 53 Lower source region (second region) 53a: first lower source region (third silicon carbide region) 53ax First Area 53ay Second Area 53b second lower source region (fifth silicon carbide region) 53bx The Fifth Realm 53 by The Sixth Realm 54 Upper source region (third region) 54a: First upper source region (fourth silicon carbide region) 54ax The Third Realm 54ay The Fourth Realm 54b Second upper source region (sixth silicon carbide region) 54bx The Seventh Realm 54 by The 8th Realm 55 contact region (seventh silicon carbide region, fourth region) 60 First epitaxial layer (first silicon carbide layer) 61 First mask material 61a First opening 62 Second mask material 62a Second opening 63 Side wall 70 Second epitaxial layer (second silicon carbide layer) 71 Recess 72 Trench 73 Gate insulating layer 74 gate electrode 75 Buried insulating layer (insulating layer) 100 MOSFET (semiconductor device) 150 Inverter circuit 200 MOSFET (semiconductor device) 1000 Drive Unit 1100 vehicles 1200 vehicles 1300 elevator w1 First width w2 Second width F1 First Side F2 Second side

Claims

1. forming a p-type first region by ion-implanting p-type impurities into the n-type first silicon carbide layer; forming a first mask material on the first silicon carbide layer, the first mask material having a first opening exposing the first region; using the first mask material as a mask, ion-implanting n-type impurities into the first region through the first opening to form an n-type second region shallower in depth than the first region; The first mask material is peeled off; forming a p-type second silicon carbide layer on the first silicon carbide layer by epitaxial growth; forming a second mask material on the second silicon carbide layer, the second mask material having a second opening that exposes the second silicon carbide layer in an upper portion of the second region; using the second mask material as a mask, ion-implanting an n-type impurity into the second silicon carbide layer through the second opening to form an n-type third region in contact with the second region; forming a sidewall at the second opening; forming a trench that penetrates the third region, the second region, and the first region using the second mask material and the sidewall as a mask; forming a gate insulating layer in the trench; forming a gate electrode on the gate insulating layer in the trench, the gate electrode having an upper surface located in the trench; the trench extends in a first direction parallel to a surface of the second silicon carbide layer; a width of the second opening in a second direction perpendicular to the first direction and parallel to the surface, the width of the second opening being smaller than a width of the second region in the second direction.

2. After forming the gate electrode, an insulating layer is filled into the trench above the gate electrode; etching the insulating layer so as to expose at least a portion of the sidewall of the trench; 2. The method for manufacturing a semiconductor device according to claim 1, further comprising forming an electrode on a side surface of the trench so as to contact the third region.

3. After forming the second silicon carbide layer and before forming the second mask material, ion-implanting a p-type impurity into the second silicon carbide layer to form a p-type fourth region; before forming the third region, forming a recess that penetrates the fourth region using the second mask material as a mask; 3. The method for manufacturing a semiconductor device according to claim 1, wherein the third region is formed after the recess is formed.

4. 4. The method for manufacturing a semiconductor device according to claim 1, wherein when forming the second region, if the n-type impurity to be ion-implanted is phosphorus (P), the ion implantation is performed with an acceleration energy of 350 keV or less, and if the n-type impurity to be ion-implanted is nitrogen (N), the ion implantation is performed with an acceleration energy of 450 keV or less.

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