Stack structure and manufacturing method thereof, capacitor using the same, transistor using the same, dye-sensitized solar cell using the same, and architectural film for window glass coating using the same

Abstract

To provide a manufacturing method of a stack structure which improves interface characteristics between a channel layer and a dielectric layer, a stack structure and a transistor.SOLUTION: A manufacturing method of a stack structure includes the steps of: preparing a substrate; forming a two-dimensional semiconductor material on the substrate; and oxidizing the two-dimensional semiconductor material using oxygen plasma to form a dielectric layer including a high dielectric (high-k) material containing any one of Bi2SeO5, a hafnium oxide (HfOx, x>0) and a zirconium oxide (ZrOx, x>0). The stack structure may be easily applied to a MOS capacitor, a field effect transistor (FET), an impact ionization super-tilt switching device, a dye-sensitized solar cell, an architectural film (particularly, a film used for window coating), and the like.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a stack structure and a manufacturing method thereof, and more particularly to a stack structure having a structure in which a plurality of thin films are stacked, and a manufacturing method thereof.

[0002] The stack structure and its manufacturing method according to the present invention are applicable to MOS capacitors, ultra-low power switching devices, dye-sensitized solar cells, and architectural films for coating window glass. [Background technology]

[0003] Since the development of the field-effect transistor (FET), the semiconductor-dielectric gate stack structure has served as a fundamental building block for controlling the overall current flow along the surface of the conductive channel for efficient information processing and computing applications. However, as the geometric scaling of silicon (Si)-based semiconductor devices continues, the controllability of the gate stack is lost, resulting in an overall degradation of electrical performance.

[0004] Two-dimensional (2D) van der Waals (vdW) semiconductor materials have inherently low dielectric constants, thin structures, and high charge transport mobilities, which can effectively mitigate the inherent problems of silicon (Si)-based semiconductor devices. They are therefore attracting attention as promising candidates to replace silicon (Si). In particular, integrating high-k dielectrics into 2D van der Waals semiconductor materials can improve gate stack controllability through efficient capacitive coupling with a thin equivalent oxide thickness. Therefore, the development of high-quality high-k gate stacks based on 2D van der Waals semiconductor materials is one of the key challenges for the super-connected society of the Fourth Industrial Revolution. Accordingly, extensive research into high-k gate stacks based on 2D semiconductor materials has been conducted for several years.

[0005] The most commonly used approach to fabricating gate stacks with 2D semiconductor / dielectric structures is atomic layer deposition (ALD), which deposits a dielectric directly on a 2D semiconductor layer. However, unlike existing silicon (Si)-based technologies, ALD can lead to uneven nucleation and island formation in 2D semiconductors, which can easily cause current leakage when the equivalent oxide thickness (EOT) is low (Kim, HG & Lee, HBR, "Atomic layer deposition on 2D materials," April 25, 2017, Chem. Mater. 29, 3809-3826).

[0006] To overcome these problems with atomic layer deposition, the introduction of a buffer layer such as perylene tetracarboxylic dianhydride has been proposed (Zhang, X. et al., "Van der Waals-Interface-Dominated All-2D Electronics", November 10, 2022, Adv. Mater. 2207966), but the problem is that the buffer layer does not achieve effective EOT scaling.

[0007] Therefore, in order to manufacture electronic devices that have higher electrical characteristics and reliability and can be driven with low power, an approach different from the above-mentioned methods is required. [Prior art documents] [Non-patent literature]

[0008] [Non-Patent Document 1] Kim, HG & Lee, HBR, “Atomic layer deposition on 2D materials”, April 25, 2017, Chem. Mater., 29, 3809-3826 [Non-patent document 2] Zhang, X. et al., “Van der Waals‐Interface‐Dominated All‐2D Electronics”, November 10, 2022, Adv. Mater., 2207966 Summary of the Invention [Problem to be solved by the invention]

[0009] An object of the present invention is to provide a stack structure in which a channel layer including a two-dimensional semiconductor material and a dielectric layer including a ferroelectric (high-k) material are stacked, and a method for manufacturing the same.

[0010] Another object of the present invention is to provide a stack structure having improved interfacial properties between a channel layer and a dielectric layer, and a method for manufacturing the same.

[0011] It is yet another object of the present invention to provide a stack structure having a subthreshold swing (SS) value close to the Boltzmann limit at room temperature, and a method for manufacturing the same.

[0012] It is yet another object of the present invention to provide a stack structure and a manufacturing method thereof that facilitates the realization of a low-power device.

[0013] It is still another object of the present invention to provide a capacitor to which the stack structure is applied.

[0014] It is still another object of the present invention to provide a transistor to which the stack structure is applied.

[0015] It is still another object of the present invention to provide a solar cell to which the stack structure is applied.

[0016] It is still another object of the present invention to provide an architectural film to which the stack structure is applied.

[0017] The object of the present invention is not limited to the above. [Means for solving the problem]

[0018] To achieve the above object, the present invention provides a method for manufacturing a stack structure.

[0019] The method for manufacturing the stack structure includes the steps of preparing a substrate, forming a two-dimensional (2D) semiconductor material layer including Bi2O2Se on the substrate, and oxidizing the 2D semiconductor material layer to form a high-k material layer including Bi2SeO5.

[0020] The crystal structure of Bi2SeO5 contained in the high dielectric material layer is controlled by the oxidation method of the two-dimensional semiconductor material layer.

[0021] The two-dimensional semiconductor material layer is oxidized by oxygen plasma (O2 plasma) to form the high dielectric material layer including amorphous Bi2SeO5.

[0022] The two-dimensional semiconductor material layer is natively oxidized to form the high-k material layer including crystalline Bi2SeO5.

[0023] The two-dimensional semiconductor material layer is oxidized by an oxidation method using ultraviolet (UV) light to form the high-dielectric material layer including single crystalline β-Bi2SeO5.

[0024] The method for manufacturing the stack structure includes the steps of: preparing a substrate; forming a channel layer including a two-dimensional (2D) semiconductor material on the substrate; and oxidizing the channel layer to form a dielectric layer including a high-k material.

[0025] By oxidizing the channel layer, one region of the channel layer is converted into the dielectric layer including the high-k material, and another region of the channel layer remains as the channel layer including the two-dimensional semiconductor material.

[0026] The high dielectric material is formed by oxidizing the two-dimensional semiconductor material.

[0027] The dielectric layer is formed by oxidizing the channel layer with oxygen plasma.

[0028] The thickness of the dielectric layer is controlled by the time the channel layer is exposed to the oxygen plasma.

[0029] To achieve the above object, the present invention provides a stack structure.

[0030] The stack structure includes a channel layer including a two-dimensional (2D) semiconductor material and a dielectric layer disposed on the channel layer, the dielectric layer including a high-k material obtained by oxidizing the 2D semiconductor material.

[0031] The two-dimensional semiconductor material includes any one of Bi2O2Se, hafnium diselenide (HfSe2), hafnium disulfide (HfS2), and zirconium diselenide (ZrSe2).

[0032] The high dielectric material is Bi2SeO5, hafnium oxide (HfO x , x>0), and zirconium oxide (ZrO x , x>0).

[0033] An interface is formed between the channel layer and the dielectric layer.

[0034] To achieve the above object, the present invention provides a transistor.

[0035] The transistor includes a source electrode and a drain electrode spaced apart from each other, a channel layer including a two-dimensional (2D) semiconductor material and disposed on the source electrode and the drain electrode such that one side of the channel layer contacts the source electrode and the other side of the channel layer contacts the drain electrode, a dielectric layer including a high-k material formed by oxidizing the 2D semiconductor material and disposed on the dielectric layer, and a gate electrode disposed on the dielectric layer.

[0036] The dielectric layer is formed by oxidizing a portion of the channel layer with oxygen plasma, and the electrical characteristics of the dielectric layer are controlled by the power of the oxygen plasma provided to the channel layer. [Effects of the Invention]

[0037] A method for manufacturing a stack structure according to the present invention includes the steps of preparing a substrate, forming a channel layer including a two-dimensional semiconductor material on the substrate, and oxidizing the channel layer with oxygen plasma to form a dielectric layer including a high-k material, thereby improving interface characteristics between the channel layer and the dielectric layer.

[0038] As a result, an electronic device (e.g., a field effect transistor) using the stack structure can have a subthreshold swing (SS) value close to the Boltzmann limit at room temperature, facilitating low-power operation. [Brief explanation of the drawings]

[0039] [Figure 1] FIG. 1 is a flowchart illustrating a method for manufacturing a stack structure according to an embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram for explaining a manufacturing process of the stack structure according to the embodiment of the present invention. [Figure 3] FIG. 3 is a schematic diagram for explaining a manufacturing process of the stack structure according to the embodiment of the present invention. [Figure 4] FIG. 4 is a schematic diagram for explaining the manufacturing process of the HfO2 / HfSe2 stack structure. [Figure 5] FIG. 5 is a schematic diagram for explaining the manufacturing process of the HfO2 / HfSe2 stack structure. [Figure 6] FIG. 6 is a schematic diagram for explaining the manufacturing process of the HfO2 / HfSe2 stack structure. [Figure 7] FIG. 7 is a schematic diagram for more specifically explaining the manufacturing mechanism of the HfO2 / HfSe2 stack structure. [Figure 8] FIG. 8 is a schematic diagram for explaining the oxidation process of HfSe2 at an appropriate oxygen concentration. [Figure 9] FIG. 9 is a schematic diagram for explaining the oxidation process of HfSe2 at an excessive oxygen concentration. [Figure 10] FIG. 10 is a flowchart illustrating a method for manufacturing a capacitor to which the HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied. [Figure 11] FIG. 11 is a schematic diagram for explaining a capacitor to which a HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied. [Figure 12] FIG. 12 is a flowchart illustrating a method for manufacturing a field effect transistor to which the HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied. [Figure 13] FIG. 13 is a schematic diagram for explaining a field effect transistor to which a HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied. [Figure 14] FIG. 14 is a flowchart illustrating a method for manufacturing an impact ionization super gradient switching device using a HfO2 / HfSe2 stack structure according to an embodiment of the present invention. [Figure 15] FIG. 15 is a schematic diagram for explaining an impact ionization super gradient switching device to which a HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied. [Figure 16] FIG. 16 is a schematic diagram illustrating an architectural film to which a HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied. [Figure 17] FIG. 17 is a schematic diagram for explaining a solar cell to which a HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied. [Figure 18] FIG. 18 is a schematic diagram for explaining a first modified example of the HfO2 / HfSe2 stack structure according to an embodiment of the present invention. [Figure 19] FIG. 19 is a schematic diagram for explaining a second modified example of the HfO2 / HfSe2 stack structure according to an embodiment of the present invention. [Figure 20] FIG. 20 is a schematic diagram for explaining a second modified example of the HfO2 / HfSe2 stack structure according to an embodiment of the present invention. [Figure 21] FIG. 21 is a schematic diagram for explaining a third modified example of the HfO2 / HfSe2 stack structure according to an embodiment of the present invention. [Figure 22] FIG. 22 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 7 W. [Figure 23] FIG. 23 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 8 W. [Figure 24] FIG. 24 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 10 W. [Figure 25] FIG. 25 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 20 W. [Figure 26] FIG. 26 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 30 W. [Figure 27]FIG. 27 is a diagram illustrating an OM image and thickness change profile of HfSe2 in a state before being oxidized with oxygen plasma. [Figure 28] FIG. 28 is a diagram illustrating an OM image and thickness change profile for HfSe2 after oxidization with oxygen plasma for 3 minutes. [Figure 29] FIG. 29 is a diagram illustrating an OM image and thickness change profile for HfSe2 after oxidization with oxygen plasma for 5 minutes. [Figure 30] FIG. 30 is a diagram for explaining the results of Raman analysis of the plasma oxidation process of HfSe2. [Figure 31] FIG. 31 is a diagram for explaining the change in thickness due to plasma oxidation of HfSe2 and the change in thickness of HfO2 converted from HfSe2. [Figure 32] FIG. 32 is a diagram for explaining the conversion rate of HfSe2 to HfO2 by plasma oxidation. [Figure 33] FIG. 33 is a schematic diagram for the definition of various parameters required for the thickness calculation of HfO2 converted from HfSe2. [Figure 34] FIG. 34 is a diagram for explaining the results of XPS analysis of the HfO2 / HfSe2 stack structure. [Figure 35] FIG. 35 shows a STEM image and FFT pattern for the HfO2 / HfSe2 stack structure. [Figure 36] FIG. 36 shows STEM images and EDS mapping results for the HfO2 / HfSe2 stack structure. [Figure 37] FIG. 37 shows a high-resolution STEM image of the HfO2 / HfSe2 stack structure. [Figure 38] FIG. 38 is a diagram for explaining the results of XPS analysis of HfO2 and HfSe2 in the HfO2 / HfSe2 stack structure. [Figure 39] FIG. 39 is a diagram showing the capacitance-voltage characteristics of the MOS capacitor according to Experimental Example 2 and a schematic diagram thereof. [Figure 40] FIG. 40 is a diagram showing the conductance-voltage characteristics of the MOS capacitor according to Experimental Example 2. In FIG. [Figure 41] FIG. 41 is a diagram for explaining the results of extracting the interface trap density of the MOS capacitor according to Experimental Example 2 using the conductance measured in FIG. [Figure 42] FIG. 42 is a diagram illustrating the equivalent oxide thickness and dielectric constant of the MOS capacitor according to Experimental Example 2. In FIG. [Figure 43] FIG. 43 is a schematic diagram of a field effect transistor according to Experimental Example 3. As shown in FIG. [Figure 44] FIG. 44 is a diagram showing ID-VG curves of the field effect transistor according to Experimental Example 3. In FIG. [Figure 45] FIG. 45 is a diagram showing ID-VG curves obtained by sweeping the gate voltage of the field effect transistor according to Experimental Example 3. In FIG. [Figure 46] FIG. 46 is a diagram showing ID-VG curves as a function of temperature of the field effect transistor according to Experimental Example 3. In FIG. [Figure 47] FIG. 47 is a diagram showing changes in the subthreshold swing value with temperature of the field-effect transistor according to Experimental Example 3. In FIG. [Figure 48] FIG. 48 is a diagram for explaining the simulation results of the RC delay characteristics depending on the interface charge trap concentration of the field-effect transistor according to Experimental Example 3. In FIG. [Figure 49] FIG. 49 is a diagram showing the electrical characteristics of a field effect transistor according to Experimental Example 3 having a thickness ratio of HfO2:HfSe2 of 1:1. [Figure 50] FIG. 50 is a diagram showing the electrical characteristics of a field effect transistor according to Experimental Example 3 having a thickness ratio of HfO2:HfSe2 of 1:2. [Figure 51] FIG. 51 is a diagram showing the electrical characteristics of a field-effect transistor according to Experimental Example 3 having a thickness ratio of HfO2:HfSe2 of 1:3. [Figure 52]FIG. 52 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 10 W is used. [Figure 53] FIG. 53 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 15 W is used. [Figure 54] FIG. 54 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 20 W is used. [Figure 55] FIG. 55 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 25 W is used. [Figure 56] FIG. 56 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 30 W is used. [Figure 57] FIG. 57 is a diagram illustrating the results of measuring the leakage current value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasmas having different powers is applied. [Figure 58] FIG. 58 is a schematic diagram of an impact ionization super-gradient switching element according to Experimental Example 4. [Figure 59] FIG. 59 is a diagram showing ID-VG curves of the impact ionization super gradient switching device according to Experimental Example 4. In FIG. [Figure 60] FIG. 60 is a diagram showing ID-VD curves of the impact ionization super-gradient switching device according to Experimental Example 4. In FIG. [Figure 61]FIG. 61 is a diagram showing electron-hole pairs generated in the gate non-overlapping region of the impact ionization super-gradient switching device according to Experimental Example 4. In FIG. [Figure 62] FIG. 62 is a diagram showing the critical voltage depending on the change in HfO2 thickness and the length of the gate non-overlapping region of the impact ionization super-gradient switching device according to Experimental Example 4. [Figure 63] FIG. 63 is a diagram showing the channel current at various drain and gate voltages of the impact ionization super-gradient switching device according to Experimental Example 4. [Figure 64] FIG. 64 is a diagram for explaining the change in electrical characteristics due to the change in length of the gate non-overlapping region of the impact ionization super-gradient switching element according to Experimental Example 4. [Figure 65] FIG. 65 is a schematic diagram for explaining the manufacturing process of the transistor according to Experimental Example 5. [Figure 66] FIG. 66 is a diagram illustrating the MoS2 semiconductor characteristics of the transistor according to Experimental Example 5. [Figure 67] FIG. 67 is a diagram for explaining the subthreshold swing value of the transistor according to Experimental Example 5. In FIG. [Figure 68] FIG. 68 is a diagram for explaining the WSe2 semiconductor characteristics of the transistor according to Experimental Example 6. [Figure 69] FIG. 69 is a diagram for explaining the subthreshold swing value of the transistor according to Experimental Example 6. In FIG. DETAILED DESCRIPTION OF THE INVENTION

[0040] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. The embodiments described herein are provided so that the disclosure will be thorough and complete, and so that the concept of the present invention will be fully conveyed to those skilled in the art.

[0041] In this specification, when a component is described as being on another component, it means that it can be directly formed on the other component, or a third component can be sandwiched between them. Also, in the drawings, shapes and sizes are exaggerated for the purpose of effectively explaining the technical content.

[0042] Furthermore, in various embodiments of this specification, terms such as "first," "second," and "third" are used to describe various components, but these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Thus, what is referred to as a "first" component in one embodiment may also be referred to as a "second" component in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean that at least one of the components listed before and after it is included.

[0043] In this specification, the singular expression includes the plural expression unless the context clearly dictates otherwise. Furthermore, the terms "comprise" or "have" are intended to specify the presence of a feature, number, step, component, or combination thereof described in the specification, and should not be understood to exclude the presence or possibility of addition of one or more other features, number, step, component, or combination thereof. Furthermore, in this specification, the term "coupled" is used to mean both indirectly and directly coupling multiple components.

[0044] Furthermore, when describing the present invention, if it is determined that a detailed description of related publicly known functions or configurations would unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0045] (Stack structure and manufacturing method thereof) FIG. 1 is a flowchart illustrating a method for manufacturing a stack structure according to an embodiment of the present invention, and FIGS. 2 and 3 are schematic diagrams illustrating the manufacturing process of a stack structure according to an embodiment of the present invention.

[0046] As shown in FIGS. 1 to 3, a substrate (SB) is prepared (S110). In one embodiment, the substrate (SB) is a silicon semiconductor substrate. In another embodiment, the substrate (SB) is a compound semiconductor substrate. In another embodiment, the substrate (SB) is a glass substrate. In still another embodiment, the substrate (SB) is a plastic substrate. The type of the substrate (SB) is not limited.

[0047] A channel layer 100 including a two-dimensional semiconductor material is formed on the substrate (SB) (S120). In one embodiment, the two-dimensional semiconductor material includes one of Bi2O2Se, hafnium diselenide (HfSe2), hafnium disulfide (HfS2), and zirconium diselenide (ZrSe2). In one embodiment, the channel layer 100 is formed using various growth methods, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), using a precursor. In another embodiment, the channel layer 100 may be formed by transferring a two-dimensional semiconductor material exfoliated from a bulk onto the substrate (SB). The method for forming the channel layer 100 is not limited.

[0048] The channel layer 100 is oxidized to form a dielectric layer 200 including a high-k material (130). According to one embodiment, as the channel layer 100 is oxidized, one region of the channel layer 100 is converted into the dielectric layer 200 including the high-k material, and another region of the channel layer 100 remains as the channel layer 100 including the 2D semiconductor material. That is, when the channel layer 100 is oxidized, the oxidized region of the channel layer 100 is converted into the high-k material resulting from the oxidization of the 2D semiconductor material, and the unoxidized region remains as the 2D semiconductor material. Thus, the high-k material can be defined as the oxidized 2D semiconductor material.

[0049] According to one embodiment, the high dielectric material is Bi2SeO5, hafnium oxide (HfO x , x>0), and zirconium oxide (ZrO x , x>0). More specifically, when the two-dimensional semiconductor material includes Bi2O2Se, Bi2O2Se is converted into Bi2SeO5 high-dielectric material as the two-dimensional semiconductor material oxidizes. In contrast, when the two-dimensional semiconductor material includes hafnium diselenide (HfSe2) or hafnium disulfide (HfS2), hafnium diselenide (HfSe2) or hafnium disulfide (HfS2) is converted into hafnium oxide (HfO x , x>0) is converted into a high dielectric material. In contrast, when the two-dimensional semiconductor material includes zirconium diselenide (ZrSe2), as the two-dimensional semiconductor material oxidizes, zirconium diselenide (ZrSe2) is converted into zirconium oxide (ZrO x , x>0) is converted into a high dielectric material.

[0050] According to an embodiment, the channel layer 100 is oxidized by one of plasma oxidation, native oxidation, and ultraviolet (UV) oxidation. Also, the channel layer 100 may be oxidized by different oxidation methods depending on the type of the two-dimensional semiconductor material.

[0051] Specifically, when the two-dimensional semiconductor material includes Bi2O2Se, the channel layer 100 is oxidized using one of plasma oxidation, natural oxidation, and ultraviolet (UV) oxidation. When the two-dimensional semiconductor material includes Bi2O2Se, the crystalline structure of the Bi2SeO5 high-k material formed by oxidation of Bi2O2Se is controlled by the oxidation method of the channel layer 100. For example, when the channel layer 100 including Bi2O2Se is oxidized using oxygen plasma, an amorphous Bi2SeO5 high-k material is formed. Alternatively, when the channel layer 100 including Bi2O2Se is oxidized using natural oxidation, a crystalline Bi2SeO5 high-k material is formed. Alternatively, when the channel layer 100 including Bi2O2Se is oxidized using ultraviolet (e.g., UV-assisted intercalative oxidation), a single crystalline β-Bi2SeO5 high-k material is formed.

[0052] When the two-dimensional semiconductor material includes zirconium diselenide (ZrSe2), the channel layer 100 is oxidized by natural oxidation to form zirconium oxide (ZrO x , x>0) to form a high dielectric material.

[0053] When the two-dimensional semiconductor material includes hafnium diselenide (HfSe2) or hafnium disulfide (HfS2), the channel layer 100 can be oxidized by natural oxidation or oxygen plasma (O2 plasma) to form hafnium oxide (HfO x , x>0).

[0054] As described above, the high dielectric material can be formed by applying various oxidation methods depending on the type of the 2D semiconductor material. However, except for the case where hafnium diselenide (HfSe2) is oxidized with oxygen plasma to form hafnium oxide (HfO2), there is a problem that the interface characteristics between the channel layer 100 and the dielectric layer 200 are poor, and the subthreshold swing (SS) value increases, making it difficult to implement a low-power device.

[0055] That is, Bi2SeO5 / Bi2O2Se stack structure formed by plasma oxidation, natural oxidation, and oxidation using ultraviolet light, ZrO formed by oxidation using natural oxidation x / ZrSe2 stack structure, HfO formed by oxidation method using natural oxidation x / HfSe2 stack structure, HfO formed by oxidation method using natural oxidation and plasma oxidation x The / HfS2 stack structure has a problem in that the interface characteristics between the channel layer 100 and the dielectric layer 200 are poor, which increases the threshold swing (SS) value, making it difficult to implement a low-power device.

[0056] In contrast, the HfO2 / HfSe2 stack structure formed by plasma oxidation (e.g., O2 plasma oxidation) has high interfacial characteristics between the channel layer 100 and the dielectric layer 200, and can have a subthreshold swing (SS) value close to the Boltzmann limit at room temperature, facilitating the realization of low-power devices. Hereinafter, the HfO2 / HfSe2 stack structure formed by plasma oxidation (e.g., O2 plasma oxidation) will be described in more detail.

[0057] 4 to 6 are schematic diagrams for explaining the manufacturing process of the HfO2 / HfSe2 stack structure, FIG. 7 is a schematic diagram for explaining more specifically the manufacturing mechanism of the HfO2 / HfSe2 stack structure, FIG. 8 is a schematic diagram for explaining the HfSe2 oxidation process at an appropriate oxygen concentration, and FIG. 9 is a schematic diagram for explaining the HfSe2 oxidation process at an excessive oxygen concentration.

[0058] As shown in FIGS. 4 to 7, when the channel layer 100 including hafnium diselenide (HfSe) is subjected to an oxygen plasma oxidation process, layer-by-layer oxidation is performed.

[0059] More specifically, when the channel layer 100 is subjected to an oxidation process using oxygen plasma, oxygen atoms (O) penetrate into the channel layer 100. One of the oxygen atoms (O) can replace a selenium atom (Se) in the hafnium diselenide (HfSe) without any additional substitution energy barrier. Furthermore, the oxygen atom (O) that replaced the selenium atom (Se) can form covalent bonds with three hafnium atoms (Hf). As a result, hafnium diselenide (HfSe) is oxidized to form hafnium oxide (HfO). That is, a region of the channel layer 100 containing hafnium diselenide (HfSe) is converted into a dielectric layer 200 containing hafnium oxide (HfO). Subsequently, as shown in FIGS. 5 and 7(a), the area of ​​the dielectric layer 200 gradually increases due to the continuously penetrated oxygen atoms (O). That is, due to the continuous penetration of oxygen atoms (O), the thickness of the dielectric layer 200 gradually increases, and the thickness of the channel layer 100 gradually decreases.

[0060] Meanwhile, as shown in FIGS. 5 and 7(b), the infiltrated oxygen atoms (O) replace the selenium atoms (Se) of hafnium diselenide (HfSe). The replaced selenium atoms (Se) diffuse into oxygen vacancies (Vo) in the dielectric layer 200 and are then discharged to the outside of the dielectric layer 200 through the oxygen vacancies. The replaced selenium atoms (Se) form an interface between the channel layer 100 and the dielectric layer 200 before diffusing into the oxygen vacancies in the dielectric layer 200. Therefore, the channel layer 100 and the dielectric layer 200 are prevented from merging by the interface formed by the replaced selenium atoms (Se). This facilitates continuous layer-by-layer oxidation by the infiltrated oxygen atoms (O).

[0061] However, the formation of the interface by the substitutional selenium atoms (Se) is achieved under appropriate oxygen concentration conditions, as shown in Figure 8. That is, when hafnium diselenide (HfSe2) is oxidized using oxygen plasma, layer-by-layer oxidation is easily achieved by maintaining appropriate oxygen concentration conditions, and a HfO2 / HfSe2 stack structure in which hafnium diselenide (HfSe2) and hafnium oxide (HfO2) are clearly separated can be fabricated. In contrast, when hafnium diselenide (HfSe2) is oxidized under excessive oxygen concentration conditions, the formation of the interface by the substitutional selenium atoms (Se) does not occur, as shown in Figure 9, resulting in the problem of the channel layer 100 and the dielectric layer 200 merging. In other words, when hafnium diselenide (HfSe2) is oxidized under excessive oxygen concentration conditions, hafnium diselenide (HfSe2) and hafnium oxide (HfO2) are not clearly distinguished, and the problem of hafnium diselenide (HfSe2) and hafnium oxide (HfO2) mixing occurs.

[0062] According to one embodiment, the oxygen concentration condition is controlled by the power of oxygen plasma provided to hafnium diselenide (HfSe2). More specifically, the power of oxygen plasma provided to hafnium diselenide (HfSe2) is controlled to be greater than 7 W and less than 20 W. If the oxygen plasma power is controlled to 20 W or more, the excessive oxygen concentration can prevent hafnium diselenide (HfSe2) and hafnium oxide (HfO2) from being clearly distinguished, resulting in a problem of mixing of hafnium diselenide (HfSe2) and hafnium oxide (HfO2). Furthermore, if the oxygen plasma power is controlled to 7 W or less, the minimum amount of oxygen atoms (O) required for forming hafnium oxide (HfO2) is not penetrated, resulting in a problem of not oxidizing hafnium diselenide (HfSe2) and not forming hafnium oxide (HfO2).

[0063] As a result, the HfO2 / HfSe2 stack structure according to the embodiment of the present invention is fabricated by oxidizing hafnium diselenide (HfSe2) with oxygen plasma, and an interface is formed between the channel layer 100 (HfSe2) and the dielectric layer 200 (HfO2) due to the substitutional selenium atoms (Se) during the oxidation process, thereby improving the interface characteristics between the channel layer 100 (HfSe2) and the dielectric layer 200 (HfO2). As a result, an electronic device using the HfO2 / HfSe2 stack structure according to the embodiment can have a subthreshold swing value close to the Boltzmann limit at room temperature, facilitating the realization of a low-power device.

[0064] The stack structure and the manufacturing method thereof according to the embodiment of the present invention have been described above. Various application examples of the stack structure according to the embodiment of the present invention will now be described.

[0065] (Capacitor using HfO2 / HfSe2 stack structure) FIG. 10 is a flowchart illustrating a method for manufacturing a capacitor using an HfO2 / HfSe2 stack structure according to an embodiment of the present invention, and FIG. 11 is a schematic diagram illustrating a capacitor using an HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0066] 10 and 11, after a substrate (SB) is prepared (S210), a bottom electrode (BE) is formed on the substrate (SB) (S220). According to one embodiment, the substrate (SB) is a silicon semiconductor substrate. According to another embodiment, the substrate (SB) is a compound semiconductor substrate. According to yet another embodiment, the substrate (SB) is a glass substrate. According to yet another embodiment, the substrate (SB) is a plastic substrate. The type of the substrate (SB) is not limited.

[0067] A channel layer 100 including a two-dimensional semiconductor material is formed on the bottom electrode (BE) (S230). The two-dimensional semiconductor material includes hafnium diselenide (HfSe2). According to one embodiment, the channel layer 100 is formed by a dry transfer method using PDMS (polydimethylsiloxane) to transfer hafnium diselenide (HfSe2) flakes mechanically exfoliated from a bulk crystal.

[0068] The channel layer 100 is oxidized to form a dielectric layer 200 including a high-k material (S240). More specifically, the channel layer 100 including hafnium diselenide (HfSe2) is oxidized with oxygen plasma to convert a portion of the channel layer 100 into hafnium oxide (HfO2). That is, the region where hafnium diselenide (HfSe2) is oxidized and converted into hafnium oxide (HfO2) is defined as the dielectric layer 200.

[0069] Finally, a top electrode (TE) is formed (S250) on the dielectric layer 200. This allows a MOS capacitor to be manufactured using a HfO2 / HfSe2 stack structure.

[0070] In the MOS capacitor according to the embodiment, the hafnium diselenide (HfSe2) contained in the channel layer 100 exhibits n-type semiconductor characteristics, exhibits largely unchanged behavior in the depletion region and accumulation region over a wide frequency range (1 kHz to 1 MHz), and has a low level of interface traps (interface traps between the channel layer and the dielectric layer). Furthermore, the MOS capacitor according to the embodiment has a constant dielectric constant (k) of 23 over a wide frequency range (1 kHz to 1 MHz). That is, the MOS capacitor according to the embodiment has stable, high-dielectric-constant dielectric characteristics, making it easily applicable to low-power and high-frequency electronic devices.

[0071] (Field-effect transistor using HfO2 / HfSe2 stack structure) FIG. 12 is a flowchart illustrating a method for manufacturing a field effect transistor using a HfO2 / HfSe2 stack structure according to an embodiment of the present invention, and FIG. 13 is a schematic diagram illustrating a field effect transistor using a HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0072] 12 and 13, a source electrode (S) and a drain electrode (D) spaced apart from each other are prepared (S310). Then, a channel layer 100 including a two-dimensional semiconductor material is formed on the source electrode (S) and the drain electrode (D) (S320). More specifically, the channel layer 100 is formed so that one side contacts the source electrode (S) and the other side contacts the drain electrode (D). The two-dimensional semiconductor material includes hafnium diselenide (HfSe2). According to one embodiment, the channel layer 100 is formed by dry-transferring hafnium diselenide (HfSe2) flakes mechanically peeled from a bulk crystal using PDMS.

[0073] The channel layer 100 is oxidized to form a dielectric layer 200 including a high-k material (S330). More specifically, the channel layer 100 including hafnium diselenide (HfSe2) is oxidized with oxygen plasma to convert a portion of the channel layer 100 into hafnium oxide (HfO2). That is, the region where hafnium diselenide (HfSe2) is oxidized and converted into hafnium oxide (HfO2) is defined as the dielectric layer 200.

[0074] Finally, a gate electrode (GE) is formed on the dielectric layer 200 (S250) to cover the entire upper surface of the dielectric layer 200. This allows a field effect transistor (FET) to be manufactured using the HfO2 / HfSe2 stack structure.

[0075] The field effect transistor according to the embodiment has excellent electrical characteristics due to the excellent interface characteristics of the HfO2 / HfSe2 stack structure. More specifically, the field effect transistor according to the embodiment has an ideal subthreshold swing value of 61 mV / dec, which is close to the Boltzmann limit at room temperature, and a subthreshold swing value of about 10 8 High on-off ratio and 10 -6 A / cm 2 It has a low gate leakage current value of .

[0076] (Impact ionization super-gradient switching device using HfO2 / HfSe2 stack structure) FIG. 14 is a flowchart illustrating a method for manufacturing an impact ionization super gradient switching device using a HfO2 / HfSe2 stack structure according to an embodiment of the present invention, and FIG. 15 is a schematic diagram illustrating an impact ionization super gradient switching device using a HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0077] 14 and 15, a source electrode (S) and a drain electrode (D) spaced apart from each other are prepared (S410). Then, a channel layer 100 including a two-dimensional semiconductor material is formed on the source electrode (S) and the drain electrode (D) (S420). More specifically, the channel layer 100 is formed so that one side contacts the source electrode (S) and the other side contacts the drain electrode (D). The two-dimensional semiconductor material includes hafnium diselenide (HfSe2). According to one embodiment, the channel layer 100 is formed by a dry transfer method using PDMS to transfer hafnium diselenide (HfSe2) flakes that are mechanically peeled from a bulk crystal.

[0078] The channel layer 100 is oxidized to form a dielectric layer 200 including a high-k material (S430). More specifically, the channel layer 100 including hafnium diselenide (HfSe2) is oxidized using oxygen plasma to convert a portion of the channel layer 100 into hafnium oxide (HfO2). That is, the region where hafnium diselenide (HfSe2) is oxidized and converted into hafnium oxide (HfO2) is defined as the dielectric layer 200.

[0079] Finally, a gate electrode (GE) is formed on the dielectric layer 200 so as to cover one region of the dielectric layer 200 and expose the other region (S440). This allows for the fabrication of an impact ionization super gradient switching device using a HfO2 / HfSe2 stack structure. The impact ionization super gradient switching device has n-type characteristics due to the application of the HfO2 / HfSe2 stack structure.

[0080] According to one embodiment, the gate electrode (GE) is formed to cover an upper region of the dielectric layer 200 and is disposed adjacent to the source electrode (S) of the source electrode (S) and the drain electrode (D). That is, the upper surface of the dielectric layer 200 is divided into a first region (A1) overlapped by the gate electrode (GE) and a second region (A2) where the gate electrode (GE) does not overlap and the upper surface of the dielectric layer 200 is exposed to the outside.

[0081] According to one embodiment, a voltage is applied to the drain electrode (D) to generate an electric field greater than the minimum electric field strength (hereinafter defined as the "critical electric field") for avalanche multiplication to occur in the second region (A2).

[0082] In addition, a voltage is applied to the drain electrode (D) and the gate electrode (GE) simultaneously, and the voltage is gradually increased. As a result, an avalanche carrier amplification phenomenon occurs in the second region (A2). That is, while a strong electric field greater than the critical electric field is applied to the first region (A1) through the voltage of the drain electrode (D), the gate voltage is gradually increased to generate an avalanche carrier amplification phenomenon, thereby realizing a super-gradient switching phenomenon at room temperature.

[0083] When an electric field is applied to the first region (A1), charge carriers are accelerated in the second region (A2). Generally, the charge carrier velocity does not increase indefinitely but saturates at a certain velocity due to collisions with the lattice. However, when a sufficiently high electric field, i.e., an electric field greater than the critical electric field, is applied, the charge carriers accelerated sufficiently by the electric field collide with the lattice, elevating electrons in the valence band to the conduction band and generating new electron-hole pairs. These secondary electron-hole pairs again gain high energy and continuously generate additional electron-hole pairs, thereby greatly increasing the carrier density. The aforementioned avalanche amplification refers to the amplification of carriers due to impact ionization, and the critical electric field refers to the minimum electric field strength at which avalanche amplification occurs.

[0084] The impact ionization supergradient switching device according to the embodiment has excellent electrical characteristics due to the excellent interface characteristics of the HfO2 / HfSe2 stack structure. More specifically, the impact ionization supergradient switching device according to the embodiment can have a very low threshold swing (SS) value of 3.43 mV / dec, overcoming the thermionic limit (60 mV / dec) of CMOS devices. This allows the supply voltage to be reduced while maintaining a high on-off ratio, thereby easily improving power consumption and device reliability.

[0085] Furthermore, in the case of the impact ionization super gradient switching device according to the embodiment, the gate electrode (GE) overlaps only a portion of the channel layer 100 and the dielectric layer 200 having impact ionization characteristics, so that the gate region can be adjusted and a strong electric field equal to or greater than the critical electric field can be applied to the channel layer 100 while gradually increasing the gate voltage, thereby increasing the probability of occurrence of the avalanche carrier amplification phenomenon. This significantly increases the number of charge carriers generated in the channel layer 100, and as a result, a super gradient switching device having a very low SS (Subthreshold Swing) value even at room temperature can be realized.

[0086] Furthermore, according to the present invention, an inverter device having a high inverter gain and an ideal noise margin based on the super-gradient switching phenomenon can be realized by simply configuring a series connection circuit of the super-gradient switching device and a transistor capable of operating complementarily therewith.

[0087] According to the present invention, the upper surface of the dielectric layer 200 includes a first region A1 overlapping the gate electrode GE and a second region A2 not overlapping the gate electrode GE, and the first region A1 and the second region A2 have a length ratio of 1:0.1 to 0.4. This increases the probability of avalanche carrier amplification occurring in the first region A1, significantly increasing the number of charge carriers generated in the channel layer 100. As a result, a super-gradient switching device with an optimized On / Off ratio and a very low SS value (less than 5 mV / dec) even at room temperature can be realized. In contrast, when the length ratio of the second region A2 to the length of the first region A1 is less than 0.1, the Off current increases while the On / Off ratio decreases, which increases the SS value and reduces the probability of impact ionization. On the other hand, if the ratio of the length of the second region (A2) to the length of the first region (A1) exceeds 0.4, a problem occurs in that the steep-switching phenomenon does not occur.

[0088] (Architectural film using HfO2 / HfSe2 stack structure) FIG. 16 is a schematic diagram illustrating an architectural film to which a HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied.

[0089] Passive cooling is a building design approach that focuses on controlling heat gain and dissipation in buildings to improve indoor thermal comfort with little or no energy consumption. It is a technology that regulates the temperature inside a building by adjusting only the direction of convection without any special temperature control devices. Among the technologies related to this passive cooling technology, architectural films (especially those used for window coatings) have traditionally used films in which silicon carbide (SiC) and hafnium oxide (HfO2) are alternately and repeatedly layered (HfO2 / SiC), as shown in the upper part of Figure 16.

[0090] However, hafnium diselenide (HfSe2) can also be used instead of silicon carbide (SiC). When hafnium diselenide (HfSe2) is used, a HfO2 / HfSe2 stacked structure can be manufactured by a simple method of oxidizing hafnium diselenide (HfSe2) as described in the present invention. This not only improves process convenience compared to conventional methods, but also makes it easier to manufacture large areas.

[0091] (Solar cells using HfO2 / HfSe2 stack structure) FIG. 17 is a schematic diagram for explaining a solar cell to which a HfO2 / HfSe2 stack structure according to an embodiment of the present invention is applied.

[0092] As shown in FIG. 17, the HfO2 / HfSe2 stack structure according to the embodiment is used as a blocking layer to prevent electron recombination (back reaction) between a transparent conductive oxide (TCO) and an electrolyte in a dye-sensitized solar cell (DSSC). When electron recombination occurs between the TCO and the electrolyte, the efficiency of the DSSC decreases significantly. Therefore, titanium oxide (TiO2) has been used as a blocking layer in the past. However, using hafnium oxide (HfO2), which has a larger energy band gap than titanium dioxide (TiO2), can more efficiently prevent electron recombination between the TCO and the electrolyte, thereby more easily resolving the problem of decreased efficiency of the DSSC.

[0093] Various application examples of the HfO2 / HfSe2 stack structure according to the embodiments of the present invention have been described above. Below, various modified examples of the HfO2 / HfSe2 stack structure according to the embodiments of the present invention will be described.

[0094] (First variant: crystallization of HfO2) FIG. 18 is a schematic diagram for explaining a first modified example of the HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0095] 18, after forming a stack structure, i.e., a HfO2 / HfSe2 stack structure, in which the channel layer 100 and the dielectric layer 200 are stacked on a substrate (SB), the dielectric layer 200 is post-treated to change the hafnium oxide (HfO2) from an amorphous state to a crystalline state. That is, in the case of hafnium oxide (HfO2) formed by oxidizing hafnium diselenide (HfSe2), since it has an amorphous state, it can be post-treated to change it to a crystalline state. According to one embodiment, the amorphous hafnium oxide (HfO2) can be changed to a crystalline state by performing post-treatment processes such as thermal annealing, laser exposure, and electron beam exposure.

[0096] Crystalline hafnium oxide (HfO2) has relatively improved insulating properties compared to amorphous hafnium oxide (HfO2), so it can be easily applied to areas where high insulating properties are required using the method described above.

[0097] According to one embodiment, amorphous hafnium oxide (HfO2) is converted to crystalline hafnium oxide (HfO2), with one region being converted to crystalline hafnium oxide (HfO2) and the remaining region remaining as amorphous hafnium oxide (HfO2). For example, by post-treating only the top surface of the amorphous hafnium oxide (HfO2), the upper region of the dielectric layer 200 is converted to crystalline hafnium oxide (HfO2), while the lower region, i.e., the region where the dielectric layer 200 is adjacent to the channel layer 100, remains as amorphous hafnium oxide (HfO2). In this case, the excellent interface characteristics between the channel layer 100 and the dielectric layer 200 can be maintained while also exhibiting the reduced gate leakage current characteristic of crystalline hafnium oxide (HfO2), making it easily applicable to various fields.

[0098] (Second variant: HfZrO2 formation by Zr doping) 19 and 20 are schematic diagrams for explaining a second modified example of the HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0099] As shown in Figure 19, after hafnium diselenide (HfSe2) and zirconium diselenide (ZrSe2) are sequentially deposited on a substrate, oxygen plasma (O2 plasma) is applied to the zirconium diselenide (ZrSe2). In this case, the zirconium diselenide (ZrSe2) decomposes to generate zirconium atoms (Zr atoms). At this time, the generated zirconium atoms (Zr atoms) can be used to form HfZrO2. More specifically, when oxygen plasma is continuously applied to the zirconium diselenide (ZrSe2), the zirconium atoms (Zr atoms) decomposed from the zirconium diselenide (ZrSe2) bond with oxygen atoms (O atoms), and the zirconium-oxygen bond (Zr-O) penetrates the hafnium diselenide (HfSe2). The infiltrated zirconium-oxygen (Zr-O) bonds then replace the selenium atoms (Se) of hafnium diselenide (HfSe2), forming HfZrO2. Furthermore, the formed HfZrO2 can be crystallized by thermal annealing.

[0100] As shown in Figure 20, after hafnium diselenide (HfSe2) and zirconium diselenide (ZrSe2) are sequentially deposited on a substrate, oxygen plasma is continuously applied to the zirconium diselenide (ZrSe2). In this case, zirconium atoms (Zr atoms) decomposed from the zirconium diselenide (ZrSe2) bond with oxygen atoms (O atoms), and zirconium-oxygen bonds (Zr-O) are infiltrated into the hafnium diselenide (HfSe2). Thereafter, the infiltrated zirconium-oxygen bonds (Zr-O) replace the selenium atoms (Se) of the hafnium diselenide (HfSe2), and all of the hafnium diselenide (HfSe2) is converted to HfZrO2. Furthermore, by heat-treating the formed HfZrO2, it can be crystallized, and various transition metal dichalcogenides (TMDCs) are inserted between the HfZrO2 and the substrate.

[0101] (Third variant: Oxidize all HfSe2 and convert to HfO2) FIG. 21 is a schematic diagram for explaining a third modified example of the HfO2 / HfSe2 stack structure according to an embodiment of the present invention.

[0102] 21, after forming the channel layer 100 on the substrate (SB), continuous oxygen plasma is applied to convert the entire channel layer 100 into the dielectric layer 200. That is, all hafnium diselenide (HfSe2) is converted into hafnium oxide (HfO2).

[0103] According to one embodiment, the third modification described above is used as a method for integrating gate dielectrics on various two-dimensional semiconductors. For example, hafnium diselenide (HfSe) is deposited on molybdenum disulfide (MoS), and then the hafnium diselenide (HfSe) is continuously exposed to oxygen plasma to convert both the HfSe and HfO. This results in a structure in which a gate dielectric (HfO) is integrated on the two-dimensional semiconductor (MoS). More specifically, the method described above utilizes the van der Waals gap (vdW) formed between the two-dimensional semiconductor (MoS) and the hafnium diselenide (HfSe) by depositing the HfSe on the two-dimensional semiconductor (MoS) as a defect-free van der Waals interface.

[0104] Various modified examples of the stack structure according to the embodiment of the present invention have been described above. Hereinafter, specific experimental examples and characteristic evaluation results of the HfO2 / HfSe2 stack structure according to the embodiment of the present invention will be described.

[0105] (Experimental Example 1: Characterization of HfO2 / HfSe2 stack structure) After forming hafnium diselenide (HfSe2) on the substrate, the hafnium diselenide (HfSe2) was plasma oxidized to convert a region of the hafnium diselenide (HfSe2) to hafnium oxide (HfO2). A 5 nm thick protection layer was also formed on the hafnium oxide (HfO2). More specifically, the plasma oxidation of the hafnium diselenide (HfSe2) was performed by providing oxygen plasma at a flow rate of 5 sccm and a pressure of 470 mTorr.

[0106] FIG. 22 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 7 W.

[0107] Figure 22 shows a TEM (Transmission Electron Microscopy) image of HfSe2 oxidized with oxygen plasma having a power of 7 W. From Figure 22, it can be confirmed that the low plasma power does not cause oxidation of HfSe2.

[0108] FIG. 23 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 8 W.

[0109] Figure 23 shows a TEM image of HfSe2 oxidized with oxygen plasma having a power of 8 W. From Figure 23, it can be seen that a region of HfSe2 was converted to HfO2.

[0110] FIG. 24 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 10 W.

[0111] Figure 24 shows a TEM image of HfSe2 oxidized with oxygen plasma at a power of 10 W. It can be seen from Figure 24 that a region of HfSe2 was converted to HfO2, and that HfSe2 and HfO2 were clearly separated at the interface.

[0112] FIG. 25 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 20 W.

[0113] Figure 25 shows a TEM image of HfSe2 oxidized with oxygen plasma having a power of 20 W. From Figure 25, it can be seen that a region of HfSe2 was converted to HfO2, but the interface collapsed.

[0114] FIG. 26 is a TEM image of HfSe2 oxidized with oxygen plasma having a power of 30 W.

[0115] Figure 26 shows a TEM image of HfSe2 oxidized with oxygen plasma having a power of 30 W. From Figure 26, it can be seen that a region of HfSe2 has been converted to HfO2, but the collapse of the interface has also clearly occurred.

[0116] 22 to 26, it can be seen that when fabricating a HfO2 / HfSe2 stack structure, the power of oxygen plasma must be controlled during the plasma oxidation process of HfSe2. Specifically, a minimum plasma power of more than 7 W is required to convert HfSe2 to HfO2, and a maximum plasma power of less than 20 W is required to prevent interface breakdown between HfSe2 and HfO2.

[0117] [Table 1]

[0118] FIG. 27 is a diagram illustrating an OM image and a thickness change profile of HfSe2 before being oxidized with oxygen plasma.

[0119] An optical microscopy (OM) image and thickness change profile of HfSe2 before oxidation with oxygen plasma (0 min oxidation) are shown in Figure 27. From Figure 27, it can be seen that only HfSe2 is visible before oxidation with oxygen plasma.

[0120] FIG. 28 is a diagram illustrating an OM image and thickness change profile for HfSe2 after oxidization with oxygen plasma for 3 minutes.

[0121] Fig. 28 shows an optical microscopy (OM) image and thickness change profile of HfSe2 after 3 minutes of oxidation with oxygen plasma (3-minute oxidation). Fig. 28 confirms that HfSe2 was partially converted to HfO2.

[0122] FIG. 29 is a diagram illustrating an OM image and thickness change profile for HfSe2 after oxidization with oxygen plasma for 5 minutes.

[0123] Fig. 29 shows an optical microscopy (OM) image and thickness change profile of HfSe2 after 5 minutes of oxidation with oxygen plasma (5-minute oxidation). Fig. 29 confirms that all HfSe2 was fully converted to HfO2.

[0124] 27 to 29, the molecular mass (336.41 / 210.5) and density (6.54 / 9.68 g / cm) of HfO2 / HfSe2 were 3 ), the volume of HfO2 converted to HfSe2 can be estimated to be 1:2.3.

[0125] FIG. 30 is a diagram for explaining the results of Raman analysis of the plasma oxidation process of HfSe2.

[0126] Figure 30 shows the Raman spectra of HfO2 and HfO2 / HfSe2 formed by plasma oxidation of HfSe2, and the remaining HfSe2. From Figure 30, it is clear that the decreased A was observed even after 3 minutes of plasma treatment. 1g The Raman peak (red curve) indicates that after plasma treatment, there is a layer of unconverted single-crystalline HfSe2 beneath the converted HfO2, but after 5 minutes of plasma treatment, the peak disappears. 1g The Raman peaks show that HfSe2 has been converted to completely amorphous HfO2 (blue curve).

[0127] FIG. 31 is a diagram for explaining the change in thickness due to plasma oxidation of HfSe2 and the change in thickness of HfO2 converted from HfSe2.

[0128] Figure 31 shows the change in thickness (total thickness) of HfSe2 as a function of plasma oxidation time, and the change in thickness of HfO2 converted from HfSe2 (converted HfO2 thickness). Figure 31 confirms that as the plasma oxidation time increases, the thickness of HfSe2 decreases, and the thickness of HfO2 converted from HfSe2 increases.

[0129] FIG. 32 is a diagram for explaining the conversion rate of HfSe2 to HfO2 by plasma oxidation.

[0130] Figure 32 shows the change in HfO2 thickness (HfO2 thickness, nm) as a function of HfSe2 plasma oxidation time (Plasma time, min), from which the conversion rate of HfO2, i.e., the oxidation rate, was derived. More specifically, HfSe2 was oxidized using oxygen plasma under conditions of 10 W power, 5 sccm flow rate, and 470 MTorr pressure. From Figure 32, it can be seen that the conversion rate of HfO2, i.e., the oxidation rate, was derived to be approximately 2.1 nm / min.

[0131] FIG. 33 is a schematic diagram for the definition of various parameters required for the thickness calculation of HfO2 converted from HfSe2.

[0132] 27 to 31 include both the thickness of unconverted HfSe2 and the thickness of converted HfO2, so the thickness of HfO2 cannot be directly determined using an AFM (Atomic Force Microscope). Therefore, an indirect approach was applied to determine the thickness of converted HfO2, and the relevant elements were defined as follows, as indicated by the black arrows in Figure 33:

[0133] [Table 2]

[0134] The quantitative relationship between the above-mentioned parameters is shown below: The difference between the initial HfSe2 thickness (t0) and the total thickness of the HfO2 / HfSe2 stack structure (t3) is the same as the difference between the thickness of HfSe2 converted to HfO2 (t2) and the thickness of HfO2 converted from HfSe2 (t1), which can be summarized as follows:

[0135]

number

[0136] As described above, the thickness (t2) of HfSe2 converted to HfO2 is 2.3 times thicker than the thickness (t1) of HfO2 converted from HfSe2, and this can be summarized as the following equation 2.

[0137]

number

[0138] Considering the above-mentioned Equations 1 and 2, the following Equation 3 is derived. Since the initial HfSe2 thickness (t0) and the total thickness of the HfO2 / HfSe2 stack structure (t3) can be confirmed using AFM, the thickness of HfO2 converted from HfSe2 (t1) can be calculated using Equation 3. Furthermore, as shown in Figure 32, an oxidation rate of 2.1 nm / min was derived from the thickness of HfO2 converted from HfSe2 (t1), and a constant oxidation rate was also confirmed from various HfSe2 flakes. This confirms the high controllability of the plasma oxidation process.

[0139]

number

[0140] FIG. 34 is a diagram for explaining the results of XPS analysis of the HfO2 / HfSe2 stack structure.

[0141] Figure 34 shows the XPS (X-ray Photoelectron Spectroscopy) depth profile of the HfO2 / HfSe2 stack structure, which was fabricated and then analyzed by sputtering at a rate of 0.5 nm / min, reducing the thickness by 2.5 nm. Figure 34 shows that when the thickness is reduced by 10 nm, the Se 3d peak becomes clear and the O 1s peak (Hf-O) disappears. This confirms the accuracy of the oxidation rate as the thickness is reduced through the aforementioned thickness control conditions.

[0142] FIG. 35 shows a STEM image and FFT pattern for the HfO2 / HfSe2 stack structure.

[0143] In FIG. 35, a STEM (Scanning Transmission Electron Microscopy) image of the HfO2 / HfSe2 stack structure is shown on the right, and FFT (Fast Fourier Transform) patterns of HfO2 and HfSe2 in the HfO2 / HfSe2 stack structure are shown on the left.

[0144] The STEM image in Figure 35 shows a clean interface with no noticeable defects visible even over a wide area. The FFT pattern in Figure 35 also confirms the amorphous structure of HfO2 and the crystalline structure of HfSe2. More specifically, the interplanar distance of unconverted HfSe2 on (001) is estimated to be approximately 0.614 nm, which indicates that unconverted HfSe2 maintains its original crystalline structure.

[0145] FIG. 36 shows STEM images and EDS mapping results for the HfO2 / HfSe2 stack structure.

[0146] In Figure 36, a STEM (Scanning Transmission Electron Microscopy) image of the HfO2 / HfSe2 stack structure is shown on the left, and EDS mapping (Energy Dispersive Spectrometer mapping) results are shown on the right. From the EDS mapping results in Figure 36, it can be seen that hafnium (Hf) is confirmed in HfO2 and HfSe2, selenium (Se) is confirmed only in HfSe2, and oxygen (O) is confirmed only in HfO2 and the substrate.

[0147] FIG. 37 shows a high-resolution STEM image of the HfO2 / HfSe2 stack structure.

[0148] From Figure 37, we can again see the atomically clean interface between HfO2 and HfSe2, which indicates that the formation of HfO2 is limited by the merging of unconverted HfSe2 and HfO2 converted from HfSe2, and that the HfO2 formation process is carried out by layer-by-layer oxidation.

[0149] FIG. 38 is a diagram for explaining the results of XPS analysis of HfO2 and HfSe2 in the HfO2 / HfSe2 stack structure.

[0150] Figure 38 shows the XPS (X-ray Photoelectron Spectroscopy) analysis results for HfO2 and HfSe2, respectively, of the HfO2 / HfSe2 stack structure confirmed in Figure 37. Figure 38 confirms that the Hf 4f peak observed at 16.01 eV and the O 1s peak at 532.4 eV show the same results as for a general HfO2 dielectric.

[0151] (Experimental Example 2: Confirmation of MOS capacitor characteristics using HfO2 / HfSe2 stack structure) After forming a 10-nm-thick bottom electrode on the substrate, hafnium diselenide (HfSe2) mechanically peeled from the bulk crystal was dry-transferred using PDMS. The HfSe2 was then plasma-oxidized to convert a region of the HfSe2 to hafnium oxide (HfO2). A 30-nm-thick top electrode was then formed on the HfO2 to fabricate a MOS capacitor employing a HfO2 / HfSe2 stack structure. Specifically, the HfSe2 was formed to a thickness of 15 nm, and the HfO2 was formed to a thickness of 10 nm.

[0152] FIG. 39 is a diagram showing the capacitance-voltage characteristics of the MOS capacitor according to Experimental Example 2 and a schematic diagram thereof.

[0153] FIG. 39 shows the gate voltage (V G , V) by capacitance (nF / cm 2 ) was measured and shown. From Figure 39, it can be seen that HfSe2 is a typical n-type semiconductor through the capacitance that accumulates as the gate voltage increases. It can also be seen that there is a low level of interface traps through the largely unchanged behavior in both the depletion and accumulation regions depending on the frequency (1 kHz to 1 MHz).

[0154] FIG. 40 is a diagram showing the conductance-voltage characteristics of the MOS capacitor according to Experimental Example 2. In FIG.

[0155] FIG. 40 shows the gate voltage (V G , V) due to the conductance (G P / w, nF / cm 2 ) was measured and shown in Fig. 40. It can be seen from Fig. 40 that the change is substantially constant at various frequencies (1 kHz to 1 MHz).

[0156] FIG. 41 is a diagram for explaining the results of extracting the interface trap density of the MOS capacitor according to Experimental Example 2 using the conductance measured in FIG.

[0157] Figure 41 shows the interface charge trap density (D) that determines the performance of the stack structure based on HfO2 / HfSe2. it ) was evaluated using the conduction method using the conductivity of Figure 40, and from Figure 41, a very low interface charge trap density (D it ) ~ 5.7 × 10 10 cm -2 eV -1 More specifically, the interface charge trap density (D it ) is derived from the following equation 4, and Samples 1 to 3 (Sample #1, Sample #2, Sample #3) in FIG. 41 each represent a MOS capacitor manufactured in the same process.

[0158]

number

[0159] FIG. 42 is a diagram illustrating the equivalent oxide thickness and dielectric constant of the MOS capacitor according to Experimental Example 2. In FIG.

[0160] Figure 42 shows the equivalent oxide thickness (EOT) and dielectric constant (k) as a function of frequency calculated from the conductance-voltage curve of the MOS capacitor. From Figure 42, the MOS capacitor exhibits a constant k of 23 across the entire frequency range, confirming that HfO2 chemically converted through an oxidation process is a stable, high-k dielectric for low-power and high-frequency electronic devices. The equivalent oxide thickness (EOT ~ 1.6 nm) was also derived from the k value.

[0161] (Experimental Example 3: Confirmation of field effect transistor characteristics using HfO2 / HfSe2 stack structure) Hafnium diselenide (HfSe2), mechanically peeled from the bulk crystal, was dry-transferred onto the source and drain electrodes using PDMS. The HfSe2 was then plasma-oxidized to convert a region of the HfSe2 into hafnium oxide (HfO2). A 50-nm-thick gate electrode was then formed on the HfO2 to fabricate a field-effect transistor (FET) with a HfO2 / HfSe2 stack structure. Specifically, the gate electrode was formed to cover the entire top surface of the HfO2.

[0162] FIG. 43 is a schematic diagram of a field effect transistor according to Experimental Example 3. As shown in FIG.

[0163] Figure 43 shows a field effect transistor using a HfO2 / HfSe2 stack structure according to Experimental Example 3. From Figure 43, it can be seen that HfSe2 is formed so that one side is in contact with the source electrode and the other side is in contact with the drain electrode, and the gate electrode is formed to cover the entire top surface of the HfO2.

[0164] FIG. 44 is a diagram showing ID-VG curves of the field effect transistor according to Experimental Example 3. In FIG.

[0165] FIG. 44 shows the V GS (V) by I DS 44 shows that the field-effect transistor has an ideal subthreshold swing value of 61 mV / dec, which is close to the Boltzmann limit at room temperature, and a subthreshold swing value of ∼10 8 High on-off ratio (Ion / off) and 10 -6 A / cm 2 It can be seen that the HfO2 / HfSe2 stack structure of the field effect transistor has excellent interface characteristics.

[0166] FIG. 45 is a diagram showing ID-VG curves obtained by sweeping the gate voltage of the field effect transistor according to Experimental Example 3. In FIG.

[0167] Figure 45 shows the hysteresis observed during the gate voltage sweep (forward / reverse sweep). From Figure 45, it can be seen that the field-effect transistor exhibits a small hysteresis of ~11 mV during the gate voltage sweep. This indicates that the HfO2 / HfSe2 stack structure of the field-effect transistor contains a small trap concentration at the interface and inside the HfO2.

[0168] FIG. 46 is a diagram showing ID-VG curves as a function of temperature of the field effect transistor according to Experimental Example 3. In FIG.

[0169] Fig. 46 shows the change in the subthreshold swing (SS) value with temperature (100K to 300K) of the field effect transistor according to Experimental Example 3. It can be seen from Fig. 46 that the subthreshold swing (SS) value also decreases from 61mV / dec to 26mV / dec as the temperature decreases from 300K to 100K.

[0170] FIG. 47 is a diagram showing changes in the subthreshold swing value with temperature of the field-effect transistor according to Experimental Example 3. In FIG.

[0171] Figure 47 shows the change in the subthreshold swing value (SS, mV / dec) of the field-effect transistor as the temperature changes from 50 K to 300 K. It can be seen from Figure 47 that the subthreshold swing value increases as the temperature increases, which is in substantial agreement with the experimental data.

[0172] FIG. 48 is a diagram for explaining the simulation results of the RC delay characteristics depending on the interface charge trap concentration of the field-effect transistor according to Experimental Example 3. In FIG.

[0173] FIG. 48 shows the charge trap concentration (D it ) is shown in Figure 48. The interface charge trap concentration (D it ) increase, the RC delay that appears in the circuit is evaluated by simulation, and a low interface charge trap concentration (D it ) is important.

[0174] FIG. 49 is a diagram showing the electrical characteristics of a field effect transistor according to Experimental Example 3 having a thickness ratio of HfO2:HfSe2 of 1:1.

[0175] 49 shows the measured subthreshold swing (SS), operating current (On current), and threshold voltage (VTH) of the field effect transistor according to Experimental Example 3, which has a thickness ratio of HfO2:HfSe2 of 1:1. More specifically, the thickness of HfO2 and the thickness of HfSe2 are each 10 nm.

[0176] From Figure 49, the subthreshold swing value (SS) is measured to be ~61.5mV / dec, and the operating current value (On current) is ~10 -5 A and the threshold voltage (V TH) was measured to be ~-0.75V.

[0177] FIG. 50 is a diagram showing the electrical characteristics of a field effect transistor according to Experimental Example 3 having a thickness ratio of HfO2:HfSe2 of 1:2.

[0178] 50 shows the measured subthreshold swing (SS), operating current (On current), and threshold voltage (VTH) of the field effect transistor according to Experimental Example 3, which has a thickness ratio of HfO2:HfSe2 of 1:2. More specifically, the thicknesses of HfO2 and HfSe2 are 10 nm and 20 nm, respectively.

[0179] From Figure 50, the subthreshold swing value (SS) is measured to be ~80.7mV / dec, and the operating current value (On current) is ~10 -7 A and the threshold voltage (V TH ) was measured to be ~-1.1V.

[0180] FIG. 51 is a diagram showing the electrical characteristics of a field-effect transistor according to Experimental Example 3 having a thickness ratio of HfO2:HfSe2 of 1:3.

[0181] 51 shows the measured subthreshold swing (SS), operating current (On current), and threshold voltage (VTH) of the field effect transistor according to Experimental Example 3, which has a thickness ratio of HfO2:HfSe2 of 1:3. More specifically, the thicknesses of HfO2 and HfSe2 are 10 nm and 30 nm, respectively.

[0182] From Figure 51, the subthreshold swing value (SS) is measured to be ~103.2mV / dec, and the operating current value (On current) is ~10 -8 A and the threshold voltage (V TH ) was measured to be ~-1.6V.

[0183] [Table 3]

[0184] As a result, from FIGS. 49 to 51, when the HfSe2 thickness increases relative to the HfO2 thickness, the subthreshold swing (SS) increases, and the operating current (On current) and threshold voltage (V TH ) decreases, the electrical characteristics deteriorate. We also measured the electrical characteristics when the ratio of HfSe2 thickness to HfO2 thickness decreases, and found that when the ratio of HfSe2 thickness to HfO2 thickness decreases to less than 1, there is no substantial change compared to when the ratio of HfSe2 thickness to HfO2 thickness is 1. This shows that when manufacturing field-effect transistors using the HfO2 / HfSe2 stack structure, the ratio of HfSe2 thickness to HfO2 thickness must be controlled to 1 or less.

[0185] FIG. 52 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 10 W is used.

[0186] FIG. 52 shows the V GS (V) by I DS The subthreshold swing (SS) was derived by measuring (A). Figure 52 shows that when a power of 10 W is applied, the subthreshold swing (SS) is ~65 mV / dec.

[0187] FIG. 53 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 15 W is used.

[0188] FIG. 53 shows the V GS (V) by I DS The subthreshold swing (SS) was derived by measuring (A). Figure 53 shows that when a power of 15 W is applied, the subthreshold swing (SS) is about 98 mV / dec.

[0189] FIG. 54 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 20 W is used.

[0190] FIG. 54 shows the V GS (V) by I DS The subthreshold swing (SS) was derived by measuring (A). Figure 54 shows that when a power of 20 W is applied, the subthreshold swing (SS) is about 130 mV / dec.

[0191] FIG. 55 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 25 W is used.

[0192] In FIG. 55, the V GS (V) by I DS The subthreshold swing (SS) was derived by measuring (A). Figure 55 shows that when a power of 25 W is applied, the subthreshold swing (SS) is ~192 mV / dec.

[0193] FIG. 56 is a diagram illustrating the results of measuring the subthreshold swing value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasma having a power of 30 W is used.

[0194] FIG. 56 shows the V GS (V) by I DS The subthreshold swing (SS) was derived by measuring (A). Figure 56 shows that when a power of 30 W is applied, the subthreshold swing (SS) is about 250 mV / dec.

[0195] [Table 4]

[0196] 52 to 56, it was confirmed that the subthreshold swing value increased from about 65 mV / dec to about 250 mV / dec as the oxygen plasma power increased from 10 W to 30 W. Furthermore, based on the measurement results in FIGS. 52 to 56, an equation for calculating the subthreshold swing value (SS) according to the oxygen plasma power (W) was derived, and the derived equation can be summarized as Equation 5 below.

[0197]

number

[0198] As mentioned above, the field effect transistor using the HfO2 / HfSe2 stack structure can derive the subthreshold swing value only through oxygen plasma power for the oxidation of HfSe2, and therefore the prediction of the subthreshold swing value can be easily applied to various fields.

[0199] FIG. 57 is a diagram illustrating the results of measuring the leakage current value of a field effect transistor according to Experimental Example 3, in which a HfO2 / HfSe2 stack structure oxidized by oxygen plasmas having different powers is applied.

[0200] FIG. 57 shows the V for the field effect transistor according to Experimental Example 3, which employs a HfO2 / HfSe2 stack structure oxidized by oxygen plasma with different powers (10 W, 15 W, 20 W, 25 W, and 30 W). GS (V) leakage current value (Gate leakage current density, A / cm 2 ) was measured and shown in Figure 57. It can be seen from Figure 57 that as the oxygen plasma power increases from 10 W to 30 W, the leakage current value also increases.

[0201] (Experimental Example 4: Characterization of impact ionization super-gradient switching device using HfO2 / HfSe2 stack structure) Hafnium diselenide (HfSe2), mechanically peeled from the bulk crystal, was dry-transferred onto the source and drain electrodes using PDMS. The HfSe2 was then plasma-oxidized to convert a region of the HfSe2 into hafnium oxide (HfO2). A 50-nm-thick gate electrode was then formed on the HfO2 to fabricate a field-effect transistor (FET) with a HfO2 / HfSe2 stack structure. Specifically, the gate electrode was formed so that it covered a portion of the top surface of the HfO2 and exposed the remainder.

[0202] FIG. 58 is a schematic diagram of an impact ionization super-gradient switching element according to Experimental Example 4.

[0203] Figure 58 shows an impact ionization super gradient switching device according to Experimental Example 4, in which a HfO2 / HfSe2 stack structure is applied. Also shown is a diagram showing the band structure and impact ionization phenomenon depending on the gate voltage and drain voltage.

[0204] From FIG. 58, it can be seen that HfSe2 is formed so that one side is in contact with the source electrode (Source) and the other side is in contact with the drain electrode (Drain), and the gate electrode overlaps with HfO2 in the region (L gated ), and the region where the gate electrode does not overlap with HfO2 and the top surface of HfO2 is exposed to the outside (L ungated ) can be confirmed.

[0205] Also, a sufficiently high drain voltage (V BR ) and the gate voltage is applied, the area where the gate electrode does not overlap with HfO2 (L ungated ) it can be confirmed that impact ionization occurs.

[0206] FIG. 59 is a diagram showing ID-VG curves of the impact ionization super gradient switching device according to Experimental Example 4. In FIG.

[0207] Figure 59 shows the transmission characteristics indicating the sudden increase in current due to the impact ionization phenomenon that occurs in the impact ionization supergradient switching device of Experimental Example 4. The inserted portion in Figure 59 shows an enlarged view of the area where supergradient switching occurs. Figure 59 confirms that the impact ionization supergradient switching device of Experimental Example 4 has an extremely low threshold swing (SS) value of 3.43 mV / dec, overcoming the thermionic limit (60 mV / dec) of CMOS devices.

[0208] FIG. 60 is a diagram showing ID-VD curves of the impact ionization super-gradient switching device according to Experimental Example 4. In FIG.

[0209] From FIG. 60, it can be seen that the output characteristics show a rapid increase in current due to the impact ionization phenomenon that occurs in the impact ionization super-gradient switching element according to Experimental Example 4.

[0210] FIG. 61 is a diagram showing electron-hole pairs generated in the gate non-overlapping region of the impact ionization super-gradient switching device according to Experimental Example 4. In FIG.

[0211] Figure 61 shows the simulation results for the impact ionization rate and the density of electron-holes generated in the ungated region where the gate electrode and HfO2 do not overlap in the supergradient switching device according to Experimental Example 4. Figure 61 confirms that a sufficient number of electron-hole pairs are generated by impact ionization in the ungated region where the gate electrode and HfO2 do not overlap.

[0212] FIG. 62 is a diagram showing the critical voltage depending on the change in HfO 2 thickness and gate non-overlapping region length of the impact ionization super-gradient switching device according to Experimental Example 4.

[0213] FIG. 62 shows the HfO2 thickness (HfO2 thickness, nm) of the impact ionization super gradient switching element according to Experimental Example 4, and the length of the region where the gate electrode and HfO2 do not overlap (L ungated , nm) by adjusting the critical voltage (V BR , V). From FIG. 62, it can be seen that super-gradient switching is realized at even lower driving voltages.

[0214] FIG. 63 shows the drain voltage (V DS ) and gate voltage (V GS ) channel current (I DS ) is shown.

[0215] From FIG. 63, the interrelated prerequisites of gate voltage and drain voltage for supergradient switching in the impact ionization supergradient switching device according to Experimental Example 4 can be confirmed.

[0216] FIG. 64 is a diagram for explaining the change in electrical characteristics due to the change in length of the gate non-overlapping region of the impact ionization super-gradient switching element according to Experimental Example 4.

[0217] FIG. 64 shows the length (L ungated , nm) change in threshold voltage (V TH ), critical voltage (V BR ), and on-off ratio (On-off ratio).

[0218] From Figure 64, the length of the region where the gate electrode and HfO2 do not overlap (L ungated , nm), the threshold voltage (V TH ) and critical voltage (V BR ) can be further reduced. This allows the supply voltage to be reduced while maintaining a high on-off ratio, thereby improving power consumption and device reliability.

[0219] (Experimental Example 5: Characterization of a transistor with a gate dielectric integrated on a two-dimensional semiconductor, MoS2) FIG. 65 is a schematic diagram for explaining the manufacturing process of the transistor according to Experimental Example 5.

[0220] In Figure 65, MoS2 was formed as a two-dimensional semiconductor on a substrate, and a source electrode (S) and a drain electrode (D) were formed on one side and the other side of the MoS2, respectively. Then, HfSe2 was formed on the MoS2, and oxygen plasma was continuously applied to the HfSe2 to convert all of the HfSe2 to HfO2. Finally, a gate electrode was formed on the HfO2, thereby fabricating a transistor according to Experimental Example 5.

[0221] FIG. 66 is a diagram illustrating the MoS2 semiconductor characteristics of the transistor according to Experimental Example 5.

[0222] From FIG. 66, the V BG / TG (V) by I DSThe semiconductor properties of MoS2 were confirmed by measuring (A). From Figure 66, it can be confirmed that MoS2 has n-type semiconductor properties. It can also be confirmed that the transistor according to Experimental Example 5 exhibits small hysteresis.

[0223] FIG. 67 is a diagram for explaining the subthreshold swing value of the transistor according to Experimental Example 5. In FIG.

[0224] FIG. 67 shows the V TG (V) by I DS The subthreshold swing (SS) was derived by measuring (A). It can be seen from Fig. 67 that the transistor according to Experimental Example 5 has a low subthreshold swing of about 60.5 mV / dec.

[0225] That is, from FIGS. 66 and 67, it can be seen that the transistor according to Experimental Example 5 has a very low subthreshold swing value and small hysteresis, and therefore has excellent interface characteristics between MoS2 and HfO2, which can be predicted to be manifested by a high-quality van der Waals interface (vdW interface).

[0226] (Experimental Example 6: Characterization of a transistor with a gate dielectric integrated on a two-dimensional semiconductor WSe2) WSe2 was formed as a two-dimensional semiconductor on a substrate, and a source electrode (S) and a drain electrode (D) were formed on one side and the other side of the WSe2, respectively. HfSe2 was then formed on the WSe2, and oxygen plasma was continuously applied to the HfSe2 to convert all of the HfSe2 to HfO2. Finally, a gate electrode was formed on the HfO2, thereby fabricating a transistor according to Experimental Example 6.

[0227] FIG. 68 is a diagram for explaining the WSe2 semiconductor characteristics of the transistor according to Experimental Example 6.

[0228] From FIG. 68, the V BG / TG(V) by I DS The semiconductor properties of WSe2 were confirmed by measuring (A). From Figure 68, it can be confirmed that WSe2 has p-type semiconductor properties. It can also be confirmed that the transistor according to Experimental Example 6 exhibits small hysteresis.

[0229] FIG. 69 is a diagram for explaining the subthreshold swing value of the transistor according to Experimental Example 6. In FIG.

[0230] As shown in FIG. 69, the V TG (V) by I DS The subthreshold swing (SS) was derived by measuring (A). It can be seen from Fig. 69 that the transistor according to Experimental Example 6 has a low subthreshold swing of about 61.3 mV / dec.

[0231] That is, from FIGS. 68 and 69, it can be seen that the transistor according to Experimental Example 6 has excellent interface characteristics between WSe and HfO, as seen from its very low subthreshold swing value and small hysteresis, which can be predicted to be manifested by a high-quality van der Waals interface (vdW interface).

[0232] Although the present invention has been described in detail using preferred embodiments, the scope of the present invention should not be limited to the specific embodiments, but should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the present invention. [Explanation of symbols]

[0233] 100 channel layer 200 dielectric layer SB board GT stack structure BE bottom electrode TE upper electrode S, D Source electrode, drain electrode GE gate electrode

Claims

1. providing a substrate; forming a channel layer on the substrate, the channel layer comprising a two-dimensional (2D) semiconductor material comprising hafnium diselenide; and oxidizing the channel layer with oxygen plasma to form a dielectric layer including a high-k material including hafnium oxide (HfOx, x>0); The method for manufacturing a stack structure is characterized in that the power of the oxygen plasma is controlled to be greater than 7 W and less than 20 W.

2. The channel layer is oxidized to convert a region of the channel layer into the dielectric layer including the high-dielectric material; The method of claim 1 , wherein the other region of the channel layer remains as the channel layer including the two-dimensional semiconductor material.

3. The method of claim 1 , wherein the high-dielectric material is formed by oxidizing the two-dimensional semiconductor material.

4. 2. The method for manufacturing a stack structure according to claim 1, wherein the thickness of the dielectric layer is controlled by the time during which the channel layer is exposed to the oxygen plasma.

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