Semiconductor device and semiconductor module

Abstract

This semiconductor device comprises: a semiconductor chip having a major surface; a first electrically conductive layer formed on the major surface of the semiconductor chip and connected to a first potential; a second electrically conductive layer opposing the first electrically conductive layer in a direction normal to the major surface and connected to a second potential higher than the first potential; an insulating layer formed between the first electrically conductive layer and the second electrically conductive layer; and a first pad which, in a first direction in a plan view of the semiconductor chip when viewed from the normal direction, is formed in a region spaced apart from a region opposing the second electrically conductive layer, and is electrically connected to the first electrically conductive layer.

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a semiconductor module including the semiconductor device. [Background technology]

[0002] For example, Patent Document 1 discloses an integrated circuit comprising: a power supply; a constant current source powered by the power supply and having an output terminal connected to the anode of a temperature-sensitive diode; a PWM comparator having a non-inverting input terminal and an inverting input terminal, with the voltage of the anode of the temperature-sensitive diode applied to the non-inverting input terminal and a carrier signal (triangular wave signal) output by a carrier generation circuit applied to the inverting input terminal; and a photocoupler connected to the output terminal of the PWM comparator as an isolation means for transmitting signals from one high-voltage system to the other while isolating the high-voltage system from the low-voltage system. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-7580 Summary of the Invention [Means for solving the problem]

[0004] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor chip having a main surface, a first conductive layer formed on the main surface of the semiconductor chip and connected to a first potential, a second conductive layer facing the first conductive layer in a normal direction to the main surface and connected to a second potential higher than the first potential, an insulating layer formed between the first conductive layer and the second conductive layer, and a first pad formed in a region away from a region facing the second conductive layer in a first direction in a planar view when the semiconductor chip is viewed from the normal direction and electrically connected to the first conductive layer. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 is a plan view showing a semiconductor module according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram for explaining the operation of the semiconductor module of FIG. [Figure 3] FIG. 3 is a voltage waveform diagram used to explain FIG. [Figure 4] FIG. 4 is a schematic plan view of a semiconductor device according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a plan view showing a layer in which a low potential coil is formed in the semiconductor device of FIG. [Figure 6] FIG. 6 is a plan view showing a layer in which a high-potential coil is formed in the semiconductor device of FIG. [Figure 7] FIG. 7 is an enlarged view of a main part of the high-potential coil of FIG. [Figure 8] FIG. 8 is an enlarged view of a main part of the high-potential coil of FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view of the semiconductor device of FIG. [Figure 10] FIG. 10 is a diagram for explaining the effect of the semiconductor device of FIG. [Figure 11] FIG. 11 is a schematic plan view of a semiconductor device according to another embodiment of the present disclosure. [Figure 12] FIG. 12 is a schematic plan view of a semiconductor device according to another embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic plan view of a semiconductor device according to another embodiment of the present disclosure. [Figure 14] FIG. 14 is a schematic plan view of a semiconductor device according to another embodiment of the present disclosure. [Figure 15] FIG. 15 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. [Figure 17] FIG. 17 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. [Figure 18] FIG. 18 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. [Figure 19] FIG. 19 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0006] <Embodiments of the present disclosure> First, embodiments of the present disclosure will be listed and described.

[0007] A semiconductor device according to one embodiment of the present disclosure includes a semiconductor chip having a main surface, a first conductive layer formed on the main surface of the semiconductor chip and connected to a first potential, a second conductive layer facing the first conductive layer in a normal direction to the main surface and connected to a second potential higher than the first potential, an insulating layer formed between the first conductive layer and the second conductive layer, and a first pad formed in a region away from a region facing the second conductive layer in a first direction in a planar view when the semiconductor chip is viewed from the normal direction and electrically connected to the first conductive layer.

[0008] According to this configuration, the first pad, which is connected to a relatively low potential (first potential), is located away from the opposing region of the second conductive layer, which is connected to a relatively high potential (second potential), in the first direction in a plan view. This increases the creepage distance between the second conductive layer and the first pad compared to when the first pad is formed in the opposing region. As a result, creepage discharge can be suppressed in the region between the second conductive layer and the first pad, thereby suppressing breakdown or deterioration of the insulating layer between the second conductive layer and the first pad.

[0009] A semiconductor device according to one embodiment of the present disclosure may include a second pad that is aligned with the second conductive layer in a second direction that intersects the first direction in the planar view, has a width smaller than the width of the second conductive layer in the first direction, and is electrically connected to the second conductive layer.

[0010] In a semiconductor device according to one embodiment of the present disclosure, the semiconductor chip may be formed in a rectangular shape having a first corner and a second corner diagonally related to each other and a third corner and a fourth corner diagonally related to each other when viewed in a plane, and the second conductive layer may be provided one-to-one in a biased position toward the first corner, and the first pad may be provided one-to-one in a biased position toward the second corner.

[0011] In a semiconductor device according to one embodiment of the present disclosure, the semiconductor chip is formed in a rectangular shape in plan view having a first side and a second side opposite each other and a third side and a fourth side opposite each other, the second conductive layers are provided one on each of the first side and the second side, and the first pad may be provided in a region between a pair of opposing second conductive layers, biased toward at least one of the third side and the fourth side.

[0012] In the semiconductor device according to the embodiment of the present disclosure, the first conductive layer may include a first coil, and the second conductive layer may include a second coil.

[0013] In the semiconductor device according to the embodiment of the present disclosure, the second coil may have a thickness greater than that of the first coil.

[0014] In the semiconductor device according to the embodiment of the present disclosure, the second coil may have a thickness greater than a pitch of the second coil.

[0015] In a semiconductor device according to one embodiment of the present disclosure, the second coil may include a first portion that forms the outermost periphery of the second coil and has a first width, and a second portion that forms a coil portion more inward than the first portion and has a second width smaller than the first width.

[0016] In the semiconductor device according to the embodiment of the present disclosure, a distance between the first portion and an outermost portion of the second portion may be larger than a pitch of the second portion.

[0017] In the semiconductor device according to the embodiment of the present disclosure, the first coil may be made of AlCu, and the second coil may be made of Cu.

[0018] A semiconductor device according to one embodiment of the present disclosure may include a first conductive member connected to an inner end of the first coil, extending across the first coil below the first coil, and electrically connected to the first pad.

[0019] In the semiconductor device according to the embodiment of the present disclosure, the insulating layer may include an organic insulating layer.

[0020] In the semiconductor device according to the embodiment of the present disclosure, the organic insulating layer may include at least one of a polyimide film, a phenolic resin film, and an epoxy resin film.

[0021] In the semiconductor device according to the embodiment of the present disclosure, the insulating layer may include a stacked structure of a first inorganic insulating layer and a second inorganic insulating layer stacked on the first inorganic insulating layer.

[0022] In the semiconductor device according to the embodiment of the present disclosure, the first inorganic insulating layer may include a silicon nitride film, and the second inorganic insulating layer may include a silicon oxide film.

[0023] A semiconductor module according to one embodiment of the present disclosure includes a die pad, the semiconductor device mounted on the die pad, a package body that seals the die pad and the semiconductor device, and lead terminals that are electrically connected to the semiconductor device and exposed from the package body.

[0024] A semiconductor module according to one embodiment of the present disclosure may further include a second semiconductor device electrically connected to an insulating element for signal transmission that transmits signals in an insulated state between the first coil and the second coil, when the semiconductor device includes an insulating element for signal transmission between the first coil and the second coil.

[0025] In a semiconductor module according to one embodiment of the present disclosure, the second semiconductor device may include a control element electrically connected to one of the first coil and the second coil, and a drive element electrically connected to the other of the first coil and the second coil. Detailed Description of Embodiments of the Present Disclosure Next, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. [First embodiment] 1 is a plan view of a semiconductor module 1 according to an embodiment of the present disclosure, in which the central portion of a package body 2 is shown in a see-through manner to clarify the internal structure.

[0026] 1, in this embodiment, the semiconductor module 1 is made up of an SOP (Small Outline Package). The semiconductor module 1 is not limited to an SOP, but may be made up of a QFN (Quad For Non-Lead Package), a DFP (Dual Flat Package), a DIP (Dual Inline Package), a QFP (Quad Flat Package), a SIP (Single Inline Package), or an SOJ (Small Outline J-leaded Package), or various similar packages.

[0027] In this embodiment, the semiconductor module 1 is a composite module including multiple devices. The semiconductor module 1 includes a package body 2, multiple die pads 3, multiple lead terminals 4, a semiconductor device 5 as an example of an insulating element of the present disclosure, a controller IC 6 as an example of a control element of the present disclosure, a driver IC 7 as an example of a drive element of the present disclosure, and multiple conductors 17-20.

[0028] The semiconductor device 5 is a transformer chip that boosts and outputs an input electrical signal. The controller IC 6 is an IC chip that drives and controls the semiconductor device 5. The driver IC 7 is an IC chip that generates an electrical signal according to the electrical signal from the semiconductor device 5 and drives and controls a load (such as a switching device). The controller IC 6 is a low-potential device relative to the semiconductor device 5. The driver IC 7 is a high-potential device relative to the semiconductor device 5.

[0029] The package body 2 contains a mold resin. The mold resin may contain an epoxy resin. The package body 2 is formed in a rectangular parallelepiped shape. The package body 2 has a non-mounting surface 8 on one side, a mounting surface 9 on the other side, and side walls 10A to 10D connecting the non-mounting surface 8 and the mounting surface 9. The non-mounting surface 8 and the mounting surface 9 are formed in a quadrangular shape in a plan view seen from their normal direction Z. The mounting surface 9 is a surface that faces a connection target when the semiconductor module 1 is mounted on the connection target. An example of the connection target is a circuit board such as a PCB (printed circuit board).

[0030] The side walls 10A to 10D include a first side wall 10A, a second side wall 10B, a third side wall 10C, and a fourth side wall 10D. The first side wall 10A and the second side wall 10B extend along a first direction X and face a second direction Y that is perpendicular to the first direction X. The third side wall 10C and the fourth side wall 10D extend in the second direction Y and face the first direction X.

[0031] A plurality of die pads 3 are arranged in the package body 2. In this embodiment, each of the plurality of die pads 3 is formed in a rectangular parallelepiped shape. The plurality of die pads 3 includes a first die pad 3A and a second die pad 3B. The first die pad 3A is arranged on the fourth side wall 10D side. The second die pad 3B is arranged on the third side wall 10C side at a distance from the first die pad 3A.

[0032] The plurality of lead terminals 4 are provided on the third side wall 10C side and the fourth side wall 10D side of the package body 2. Each lead terminal 4 has one end located inside the package body 2 and the other end located outside the package body 2. The other end of each lead terminal 4 is formed as an external connection part to be connected to a connection target.

[0033] The semiconductor device 5 is disposed on the first die pad 3A in the package body 2. In this embodiment, the semiconductor device 5 is formed in a rectangular shape in a plan view. The semiconductor device 5 is disposed on the first die pad 3A with its long side facing the third side wall 10C (fourth side wall 10D).

[0034] The semiconductor device 5 includes a plurality of low potential terminals 11 and a plurality of high potential terminals 12. The plurality of low potential terminals 11 are arranged at intervals along the long side of the semiconductor device 5 on the side of the fourth side wall 10D. The plurality of high potential terminals 12 are arranged at intervals in approximately the center of the semiconductor device 5 along the long sides on the side of the third side wall 10C and the side of the fourth side wall 10D.

[0035] The controller IC 6 is disposed on the first die pad 3A in the package body 2. Specifically, the controller IC 6 is disposed on the first die pad 3A at a distance from the semiconductor device 5 toward the fourth sidewall 10D. In this embodiment, the controller IC 6 is formed in a rectangular shape in a plan view. The controller IC 6 is disposed on the first die pad 3A with its long side facing the third sidewall 10C (fourth sidewall 10D).

[0036] The controller IC 6 includes a plurality of first input pads 13 and a plurality of first output pads 14. The plurality of first input pads 13 are arranged at intervals along the long side of the controller IC 6 on the fourth side wall 10D side. The plurality of first output pads 14 are arranged at intervals along the long side of the controller IC 6 on the third side wall 10C side.

[0037] The driver IC 7 is disposed on the second die pad 3B in the package body 2. In this embodiment, the driver IC 7 is formed in a rectangular shape in a plan view. The driver IC 7 is disposed on the second die pad 3B with its long side facing the third side wall 10C (fourth side wall 10D).

[0038] The driver IC 7 includes a plurality of second input pads 15 and a plurality of second output pads 16. The plurality of second input pads 15 are arranged at intervals along the long side of the driver IC 7 on the fourth sidewall 10D side. The plurality of second output pads 16 are arranged at intervals along the long side of the driver IC 7 on the third sidewall 10C side.

[0039] The plurality of conductors 17 to 20 selectively connect the plurality of lead terminals 4, the semiconductor device 5, the controller IC 6, and the driver IC 7 within the package body 2. The plurality of conductors 17 to 20 are each made of a bonding wire. The plurality of conductors 17 to 20 include at least one of a copper wire, a gold wire, and an aluminum wire.

[0040] The multiple conductive wires 17-20 include a first conductive wire 17, a second conductive wire 18, a third conductive wire 19, and a fourth conductive wire 20. The first conductive wire 17 is connected to the lead terminal 4 on the fourth side wall 10D side and a first input pad 13 of the controller IC 6. The second conductive wire 18 is connected to the low potential terminal 11 of the semiconductor device 5 and a first output pad 14 of the controller IC 6. The third conductive wire 19 is connected to the high potential terminal 12 of the semiconductor device 5 and a second input pad 15 of the driver IC 7. The fourth conductive wire 20 is connected to the second output pad 16 of the driver IC 7 and the lead terminal 4 on the third side wall 10C side.

[0041] Fig. 2 is a diagram for explaining the operation of the semiconductor module 1 shown in Fig. 1. Fig. 3 is a voltage waveform diagram used to explain Fig. 2.

[0042] 2, the semiconductor device 5 includes a transformer 21. The transformer 21 includes a low-potential coil 22 (low-potential conductor pattern) as an example of a first conductive layer of the present disclosure on the primary side, and a high-potential coil 23 (high-potential conductor pattern) as an example of a second conductive layer of the present disclosure on the secondary side, which are opposed to each other in the vertical direction. The high-potential coil 23 is disposed above the low-potential coil 22 and faces the low-potential coil 22.

[0043] The high-potential coil 23 is AC-connected to the low-potential coil 22 by magnetic coupling, and at the same time is DC-insulated from the low-potential coil 22. In other words, the driver IC 7 is AC-connected to the controller IC 6 via the semiconductor device 5, and at the same time is DC-insulated from the controller IC 6 by the semiconductor device 5.

[0044] The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 wound helically between the first inner end 24 and the first outer end 25. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second helical portion 29 wound helically between the second inner end 27 and the second outer end 28.

[0045] The semiconductor device 5 includes a first low potential wiring 31, a second low potential wiring 32, a first high potential wiring 33, and a second high potential wiring 34. The first low potential wiring 31 connects the first inner end 24 of the low potential coil 22 to the corresponding low potential terminal 11. The second low potential wiring 32 connects the first outer end 25 of the low potential coil 22 to the corresponding low potential terminal 11. The first high potential wiring 33 connects the second inner end 27 of the high potential coil 23 to the corresponding high potential terminal 12. The second high potential wiring 34 connects the second outer end 28 of the high potential coil 23 to the corresponding high potential terminal 12.

[0046] The controller IC6 includes a first wiring 35 and a second wiring 36. The first wiring 35 is connected to the corresponding first input pad 13 and first output pad 14. The second wiring 36 is connected to the corresponding first input pad 13 and first output pad 14. The controller IC6 further includes a first switching device Sw1 and a second switching device Sw2. The first switching device Sw1 and the second switching device Sw2 are each formed of a transistor.

[0047] The first switching device Sw1 is disposed on the first wiring 35. The first switching device Sw1 controls the conduction and interruption of electrical signals transmitted to the first wiring 35. The second switching device Sw2 is disposed on the second wiring 36. The second switching device Sw2 controls the conduction and interruption of electrical signals transmitted to the second wiring 36.

[0048] The first input pad 13 on the first wiring 35 side is connected to the ground potential via a first conducting wire 17. The first output pad 14 on the first wiring 35 side is electrically connected to the low potential terminal 11 on the first inner end 24 side via a second conducting wire 18. The first input pad 13 on the second wiring 36 side is electrically connected to a power supply 37 via the first conducting wire 17. The power supply 37 applies a voltage of, for example, 5 V to the controller IC 6. The first output pad 14 on the second wiring 36 side is electrically connected to the low potential terminal 11 on the first outer end 25 side via the second conducting wire 18.

[0049] The driver IC 7 is electrically connected to the semiconductor device 5 via a plurality of third conducting wires 19. Specifically, the second input pad 15 of the driver IC 7 is electrically connected to the high potential terminal 12 on the second inner end 27 side via the third conducting wires 19. The second input pad 15 of the driver IC 7 is also electrically connected to the high potential terminal 12 on the second outer end 28 side via the third conducting wires 19.

[0050] The driver IC 7 is connected to a reference voltage power supply 38, a power supply 39, and a SiC-MISFET (Metal Insulator Semiconductor Field Effect Transistor) as an example of a load.

[0051] Here, semiconductor device 5 is an insulating element for transmitting PWM control signals and other electrical signals in an insulated state. Because driver IC 7 requires a higher voltage than controller IC 6, a significant potential difference occurs between controller IC 6 and driver IC 7, which is why semiconductor device 5 is necessary. Specifically, in an inverter device for an electric vehicle or hybrid vehicle, for example, the power supply voltage supplied to controller IC 6 is 5 V or 3.3 V with respect to the ground potential.

[0052] In contrast, a voltage of, for example, 600 V or more is transiently applied to the driver IC 7 compared to the ground potential of the controller IC 6. More specifically, a motor driver circuit in an inverter device for a hybrid vehicle or the like generally uses a half-bridge circuit in which a low-side switching element and a high-side switching element are connected in a totem pole configuration.

[0053] In an isolated gate driver, only one switch, either the low-side switching element or the high-side switching element, is turned on at any given time. In a high-voltage system, the source of the low-side switching element and the reference potential of the isolated gate driver that drives that switching element are connected to ground potential, so the gate-source voltage operates with respect to ground potential. On the other hand, the source of the high-side switching element and the reference potential of the isolated gate driver that drives that switching element are connected to the output node of the half-bridge circuit. Depending on whether the low-side switching element or the high-side switching element is on, the potential of the output node of the half-bridge circuit changes, so the reference potential of the isolated gate driver that drives the high-side switching element changes. When the high-side switching element is on, the reference potential becomes a voltage equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600 V or higher).

[0054] When the semiconductor module 1 is used as an isolated gate driver that drives a high-side switching element, the ground potentials of the driver IC 7 and the controller IC 6 are separated to ensure insulation, and therefore a voltage of 600 V or more is transiently applied to the driver IC 7 compared to the ground potential of the controller IC 6. Therefore, particularly in an isolated gate driver that drives a high-side switching element, a voltage of 600 V or more is transiently applied to the driver IC 7 compared to the ground potential of the controller IC 6.

[0055] 3, the controller IC6 controls the on / off of the first switching device Sw1 and the second switching device Sw2 in a predetermined switching pattern to generate a pulse signal PS. In this example, the predetermined switching pattern includes a first application state (Sw1: on, Sw2: off) and a second application state (Sw1: off, Sw2: on). FIG. 3 shows an example in which a 5V pulse signal PS is generated with 0V (ground potential) as the reference.

[0056] The pulse signal PS generated by the controller IC 6 is input to the semiconductor device 5. The semiconductor device 5 transmits the pulse signal PS from the low potential coil 22 to the high potential coil 23. As a result, the pulse signal PS is boosted by an amount corresponding to the winding ratio (transformation ratio) of the low potential coil 22 and the high potential coil 23.

[0057] The boosted pulse signal PS is input to the driver IC7. The driver IC7 generates an electrical signal corresponding to the boosted pulse signal PS and drives and controls the SiC-MISFET. For example, FIG. 3 shows a gate potential waveform when the semiconductor module 1 is used as an insulated gate driver that drives the high-side switching element described above. In FIG. 3, a waveform with a pulse width of 0V to 5V indicates the gate output waveform of the controller IC6, and a waveform with a pulse width of 0V to 615V indicates the gate output waveform of the insulated gate driver (driver IC7) that drives the high-side switching element.

[0058] A pulse signal of 15 V is applied to the high-side switching element with the source of the high-side switching element as the reference. Therefore, a signal of 0 V to 615 V is applied to the high-side switching element with the ground potential of the secondary side as the reference. Note that the values ​​shown in FIGS. 2 and 3 are merely examples. For example, the reference voltage of the secondary side (high potential side) may be 500 V or more and 4000 V or less.

[0059] FIG. 4 is a schematic plan view of a semiconductor device 5 according to an embodiment of the present disclosure. FIG. 5 is a plan view showing a layer in which the low-potential coil 22 is formed in the semiconductor device 5 of FIG. 4. FIG. 6 is a plan view showing a layer in which the high-potential coil 23 is formed in the semiconductor device 5 of FIG. 4. FIG. 7 is an enlarged view of a main portion of the high-potential coil 23 of FIG. 6. FIG. 8 is an enlarged view of a main portion of the high-potential coil 23 of FIG. 6. FIG. 9 is a schematic cross-sectional view of the semiconductor device 5 of FIG. 4. FIG. 10 is a diagram for explaining the effect of the semiconductor device 5 of FIG. 4. Note that although FIG. 9 is a cross-sectional view of the semiconductor device 5, it does not show a cross section of the semiconductor device 5 cut in a specific direction.

[0060] 4 to 6 and 9, semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 40. Semiconductor chip 40 includes at least one of silicon, a wide bandgap semiconductor, and a compound semiconductor.

[0061] The wide bandgap semiconductor is a semiconductor with a bandgap greater than that of silicon (approximately 1.12 eV). The bandgap of the wide bandgap semiconductor is preferably 2.0 eV or greater. The wide bandgap semiconductor may be silicon carbide (SiC). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may include at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0062] In this embodiment, the semiconductor chip 40 includes a silicon semiconductor substrate. The semiconductor chip 40 may also be an epitaxial substrate having a layered structure including a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0063] The semiconductor chip 40 has a first main surface 41 on one side, a second main surface 42 on the other side, and chip sidewalls 43A to 43D connecting the first main surface 41 and the second main surface 42. The first main surface 41 and the second main surface 42 are formed in a quadrangular shape (a square shape in this embodiment) in a plan view (hereinafter simply referred to as "plan view") seen from the normal direction Z thereof.

[0064] The chip sidewalls 43A to 43D include a first chip sidewall 43A as an example of a first side of the present disclosure, a second chip sidewall 43B as an example of a second side of the present disclosure, a third chip sidewall 43C as an example of a third side of the present disclosure, and a fourth chip sidewall 43D as an example of a fourth side of the present disclosure. The first chip sidewall 43A and the second chip sidewall 43B extend along the first direction X and face each other in the second direction Y. The third chip sidewall 43C and the fourth chip sidewall 43D extend in the second direction Y and face each other in the first direction X. The chip sidewalls 43A to 43D may be ground surfaces.

[0065] Semiconductor chip 40 has a rectangular shape in a plan view and includes a first corner 44A and a second corner 44B that are diagonally spaced from each other, and a third corner 44C and a fourth corner 44D that are diagonally spaced from each other. First corner 44A and third corner 44C are formed at both ends of first chip sidewall 43A. Second corner 44B and fourth corner 44D are formed at both ends of second chip sidewall 43B.

[0066] The semiconductor device 5 includes a first insulating portion 45, a second insulating portion 46, and a protective layer 47, which are formed in this order on a first main surface 41 of a semiconductor chip .

[0067] The first insulating portion 45 has an insulating main surface 48 and insulating sidewalls 49A-49D. The insulating main surface 48 is formed in a quadrangular shape (rectangular in this embodiment) that matches the first main surface 41 in a plan view. The insulating main surface 48 extends parallel to the first main surface 41. The insulating sidewalls 49A-49D include a first insulating sidewall 49A, a second insulating sidewall 49B, a third insulating sidewall 49C, and a fourth insulating sidewall 49D. The insulating sidewalls 49A-49D extend from the periphery of the insulating main surface 48 toward the semiconductor chip 40 and are continuous with the chip sidewalls 43A-43D. Specifically, the insulating sidewalls 49A-49D are formed flush with the chip sidewalls 43A-43D. The insulating sidewalls 49A-49D form ground surfaces that are flush with the chip sidewalls 43A-43D.

[0068] The second insulating portion 46 is formed on the insulating principal surface 48 and has an insulating principal surface 50 and insulating side walls 51A-51D. The insulating principal surface 50 extends parallel to the first principal surface 41. The insulating side walls 51A-51D include a first insulating side wall 51A, a second insulating side wall 51B, a third insulating side wall 51C, and a fourth insulating side wall 51D. The insulating side walls 51A-51D extend from the periphery of the insulating principal surface 50 toward the semiconductor chip 40. Specifically, the insulating side walls 51A-51D are formed inward relative to the insulating side walls 49A-49D. As a result, a step 52 is formed between the insulating side walls 49A-49D and the insulating side walls 51A-51D.

[0069] Furthermore, in this embodiment, the second insulating portion 46 has a recess 53 recessed inward in plan view. The recess 53 is formed by removing a portion of the second insulating portion 46 from the insulating principal surface 50 down to the insulating principal surface 48 of the first insulating portion 45. As a result, a portion of the first insulating portion 45 is exposed in the recess 53 of the second insulating portion 46. In this embodiment, the recess 53 is formed by forming a step in the third insulating sidewall 51C so that the second insulating portion 46 is selectively recessed at the second corner portion 44B of the semiconductor chip 40 in plan view. As a result, the second insulating portion 46 may be formed in an L-shape in plan view. The portion of the first insulating portion 45 exposed from the recess 53 forms a pad region 54 in which multiple low-potential terminals 67, 68 are arranged.

[0070] The protective layer 47 is formed on the insulating principal surface 50 of the second insulating portion 46 and has a protective principal surface 55 and protective sidewalls 56A to 56D. The protective principal surface 55 is formed in an L-shape in plan view similar to the insulating principal surface 50 of the second insulating portion 46. The protective principal surface 55 extends parallel to the first principal surface 41. The protective sidewalls 56A to 56D include a first protective sidewall 56A, a second protective sidewall 56B, a third protective sidewall 56C, and a fourth protective sidewall 56D. The protective sidewalls 56A to 56D extend from the periphery of the protective principal surface 55 toward the semiconductor chip 40. Specifically, the protective sidewalls 56A to 56D are formed inwardly of the insulating sidewalls 51A to 51D. As a result, a step 57 is formed between the protective sidewalls 56A to 56D and the insulating sidewalls 51A to 51D.

[0071] 9, the first insulating section 45 has a multilayer insulating laminate structure including a bottom insulating layer 58, a top insulating layer 59, and a plurality of (three in this embodiment) interlayer insulating layers 60. The bottom insulating layer 58 is an insulating layer that directly covers the first main surface 41 of the semiconductor chip 40. The top insulating layer 59 is an insulating layer that forms the insulating main surface 48 of the first insulating section 45. The plurality of interlayer insulating layers 60 are insulating layers interposed between the bottom insulating layer 58 and the top insulating layer 59. In this embodiment, the bottom insulating layer 58 has a single-layer structure containing silicon oxide. In this embodiment, the top insulating layer 59 has a single-layer structure containing silicon nitride. The thickness of the bottom insulating layer 58 and the top insulating layer 59 may each be 0.5 μm or more and 5 μm or less (for example, approximately 2 μm).

[0072] The multiple interlayer insulating layers 60 may have a stacked structure including a first insulating layer 61 on the side of the bottom insulating layer 58 and a second insulating layer 62 on the side of the top insulating layer 59. In this case, the first insulating layer 61 may be made of an inorganic insulating layer and may contain, for example, silicon nitride. The first insulating layer 61 is formed as an etching stopper layer for the second insulating layer 62. The thickness of the first insulating layer 61 may be 0.1 μm or more and 2 μm or less (for example, about 0.3 μm).

[0073] The second insulating layer 62 is formed on the first insulating layer 61. It contains a different insulating material from the first insulating layer 61. The second insulating layer 62 is made of an inorganic insulating layer different from the first insulating layer 61, and may contain, for example, silicon oxide. The thickness of the second insulating layer 62 may be 0.5 μm or more and 5 μm or less (for example, approximately 2 μm). The thickness of the second insulating layer 62 preferably exceeds the thickness of the first insulating layer 61.

[0074] Furthermore, the first insulating layer 61 may be a compressive stress film, and the second insulating layer 62 may be a tensile stress film. That is, the interlayer insulating layer 60 may have a structure in which compressive stress films and tensile stress films are repeatedly stacked. This allows the first insulating layer 61 to be formed while canceling stress at the stacking interface of the interlayer insulating layer 60. As a result, during the manufacturing process of the semiconductor device 5, it is possible to prevent significant warpage deformation from occurring in the semiconductor wafer that serves as the base of the semiconductor chip 40. The compressive stress film may be, for example, a silicon oxide film, and the tensile stress film may be, for example, a silicon nitride film.

[0075] Furthermore, the interlayer insulating layer 60 may include, for example, a layer consisting of a single layer of the second insulating layer 62. In this embodiment, the interlayer insulating layer 60 in contact with the uppermost insulating layer 59 is a layer consisting of a single layer of the second insulating layer 62.

[0076] The total thickness T1 of the first insulating portion 45 may be 2 μm or more and 30 μm or less. The total thickness T1 of the first insulating portion 45 and the number of stacked interlayer insulating layers 60 are arbitrary and are adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved. Furthermore, the insulating materials of the bottom insulating layer 58, the top insulating layer 59, and the interlayer insulating layer 60 are arbitrary and are not limited to a specific insulating material.

[0077] The second insulating portion 46 is made of an insulating material having a dielectric constant different from that of the first insulating layer 61 and the second insulating layer 62, and has a layered structure including, for example, an organic insulating layer 63. In this embodiment, the second insulating portion 46 is made of a single organic insulating layer 63, but may have a laminated structure of multiple organic insulating layers 63. Examples of the organic insulating layer 63 include a polyimide film, a phenolic resin film, and an epoxy resin film. The total thickness T2 of the second insulating portion 46 may be 5 μm or more and 100 μm or less. The total thickness T2 of the second insulating portion 46 is arbitrary and is adjusted according to the desired dielectric strength (dielectric breakdown resistance).

[0078] The protective layer 47 protects the second insulating portion 46, the first insulating portion 45, and the semiconductor chip 40 from above the insulating main surface 50. The protective layer 47 may be made of an organic insulating layer or may contain a photosensitive resin. The protective layer 47 may contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the protective layer 47 contains polyimide.

[0079] The semiconductor device 5 includes a first functional device 64 formed on a semiconductor chip 40. The first functional device 64 includes one or more (one in this embodiment) transformers 21. The transformer 21 is formed in an inner portion of a laminated structure of a first insulating section 45 and a second insulating section 46. Referring to FIG. 4, in this embodiment, the transformer 21 is provided biased toward a first corner 44A of the semiconductor chip 40 in a planar view. Here, "the transformer 21 being provided biased toward the first corner 44A" may mean, for example, that the transformer 21 is disposed closer to the first corner 44A with respect to a configuration (the second corner 44B in this embodiment) that is paired with the first corner 44A.

[0080] 5, 6, and 9, the transformer 21 includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed in a first insulating portion 45. The high-potential coil 23 is formed on a second insulating portion 46 so as to face the low-potential coil 22 in the normal direction Z.

[0081] 9, in this embodiment, the low-potential coil 22 is formed in a region sandwiched between the lowermost insulating layer 58 and the uppermost insulating layer 59 (i.e., multiple interlayer insulating layers 60). Referring to FIG. 9, the high-potential coil 23 is formed on the main insulating surface 50 of the second insulating portion 46. That is, the high-potential coil 23 faces the semiconductor chip 40 with the low-potential coil 22 sandwiched between them. The low-potential coil 22 and the high-potential coil 23 may be disposed at any position in the normal direction Z. Furthermore, it is sufficient that the high-potential coil 23 faces the low-potential coil 22 with the second insulating portion 46 sandwiched between them.

[0082] The distance D1 between the low-potential coil 22 and the high-potential coil 23 (i.e., the thicknesses of the uppermost insulating layer 59 and the second insulating portion 46) is adjusted as appropriate depending on the dielectric strength and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed on the uppermost interlayer insulating layer 60 counting from the lowermost insulating layer 58. More specifically, the low-potential coil 22 is formed on the interlayer insulating layer 60 having a laminated structure of a first insulating layer 61 and a second insulating layer 62, and may be further covered by the interlayer insulating layer 60 and the uppermost insulating layer 59, which are each made up of a single layer of the second insulating layer 62. On the other hand, the high-potential coil 23 is formed on the main insulating surface 50 of the second insulating portion 46. Therefore, the uppermost insulating layer 59 and the second insulating portion 46 are interposed between the low-potential coil 22 and the high-potential coil 23.

[0083] 5, the low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first spiral portion 26 wound in a spiral shape between the first inner end 24 and the first outer end 25. The first spiral portion 26 is wound in a spiral shape that extends in a circular shape in a plan view. The portion forming the innermost periphery of the first spiral portion 26 defines a first inner region 65 that is circular in a plan view.

[0084] The number of turns of the first helical portion 26 may be 5 or more and 30 or less. The width of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in a direction perpendicular to the helical direction. The first winding pitch of the first helical portion 26 may be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions of the first helical portion 26 in a direction perpendicular to the helical direction.

[0085] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 65 are arbitrary and are not limited to the form shown in Fig. 5 etc. The first spiral portion 26 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or an elliptical shape in a planar view. The first inner region 65 may be partitioned into a polygonal shape such as a triangular shape or a rectangular shape, or an elliptical shape in a planar view, depending on the winding shape of the first spiral portion 26.

[0086] The low-potential coil 22 may contain at least one of titanium (Ti), titanium nitride (TiN), copper (Cu), aluminum (Al), and tungsten (W). In this embodiment, the low-potential coil 22 is made of an aluminum-copper alloy (AlCu). The aluminum-copper alloy is an alloy material containing mainly Al and Cu, and may contain small amounts of alloying elements other than Al and Cu. For example, it may contain Si, Mg, etc. In this embodiment, the aluminum-copper alloy may be expressed as Al-Si-Cu, Al-Si-Mg, Al-Si-Cu-Mg, etc.

[0087] 9, the high-potential coil 23 is formed to stand on the opposite side of the first insulating part 45 from the main insulating surface 50 of the second insulating part 46. The top side of the high-potential coil 23 is covered with a protective layer 47. The high-potential coil 23 may also have a thickness greater than that of the low-potential coil 22.

[0088] 6, the high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. The second spiral portion 29 is wound in a spiral shape that extends in a circular shape in a plan view. The portion forming the innermost periphery of the second spiral portion 29 defines a second inner region 66 that is circular in a plan view. The second inner region 66 of the second spiral portion 29 faces the first inner region 65 of the first spiral portion 26 in the normal direction Z.

[0089] The number of turns of the second helical portion 29 may be 5 or more and 30 or less. The number of turns of the second helical portion 29 relative to the number of turns of the first helical portion 26 is adjusted according to the voltage value to be boosted. The number of turns of the second helical portion 29 preferably exceeds the number of turns of the first helical portion 26. Of course, the number of turns of the second helical portion 29 may be less than the number of turns of the first helical portion 26 or may be equal to the number of turns of the first helical portion 26.

[0090] The width of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The width of the second helical portion 29 is preferably 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in a direction perpendicular to the helical direction. The width of the second helical portion 29 is preferably equal to the width of the first helical portion 26.

[0091] The second winding pitch of the second helical portion 29 may be 0.1 μm or more and 5 μm or less. The second winding pitch is preferably 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction perpendicular to the helical direction. The second winding pitch is preferably equal to the first winding pitch of the first helical portion 26.

[0092] The winding shape of the second spiral portion 29 and the planar shape of the second inner region 66 are arbitrary and are not limited to the form shown in FIG. 6 etc. The second spiral portion 29 may be wound in a polygonal shape such as a triangular shape or a rectangular shape, or an elliptical shape in a planar view. The second inner region 66 may be defined in a polygonal shape such as a triangular shape or a rectangular shape, or an elliptical shape in a planar view, depending on the winding shape of the second spiral portion 29. Furthermore, a portion of the protective layer 47 fills the gaps in the second spiral portion 29.

[0093] The high-potential coil 23 may contain at least one of titanium (Ti), titanium nitride (TiN), copper (Cu), aluminum (Al), and tungsten (W). In this embodiment, the high-potential coil 23 is made of Cu. The high-potential coil 23 made of Cu may be formed, for example, by plating growth of Cu.

[0094] 4 to 6 and 9, the semiconductor device 5 includes, as a structure related to the low potential coil 22, a first low potential terminal 67, a second low potential terminal 68, a first low potential wiring 31, and a second low potential wiring 32. The first low potential terminal 67 and the second low potential terminal 68 are the above-mentioned low potential terminal 11. Note that, for clarity, part of the second low potential wiring 32 is omitted in FIGS. 4 and 6.

[0095] The first low potential terminal 67 and the second low potential terminal 68 are each formed in an island shape, and are formed in a second region 70 that is separated from a first region 69 that faces the high potential coil 23 in the first direction X in a plan view. As shown in FIGS. 4 to 6, the first region 69 is a region (hatched region in FIGS. 4 to 6) that overlaps with the high potential coil 23 when the high potential coil 23 is projected in the first direction X, and the second region 70 is a region (non-hatched region in FIGS. 4 to 6) that does not overlap with the high potential coil 23. Therefore, the width W1 of the first region 69 is 1 / 2 the width W of the high potential coil 23 in the second direction Y. C2More specifically, the first low potential terminal 67 and the second low potential terminal 68 are formed in the pad region 54 (the second corner portion 44B of the semiconductor chip 40) exposed from the second insulating portion 46. In the pad region 54, the first low potential terminal 67 and the second low potential terminal 68 are arranged at intervals in the second direction Y.

[0096] In this embodiment, the high-potential coil 23 (transformer 21) is formed at a distance from each of the first chip sidewall 43A and the second chip sidewall 43B of the semiconductor chip 40 in a plan view. Therefore, a pair of second regions 70 are formed sandwiching the first region 69 in the second direction Y. The pair of second regions 70 may include the second region 70A on the first chip sidewall 43A side and the second region 70B on the second chip sidewall 43B side. In this embodiment, the pad region 54 is formed to selectively expose the second region 70B.

[0097] Referring to FIG. 9 , the first low potential terminal 67 and the second low potential terminal 68 are each formed in the same interlayer insulating layer 60 as the low potential coil 22. The first low potential terminal 67 and the second low potential terminal 68 are covered by the uppermost insulating layer 59. Note that FIG. 9 only shows the first low potential terminal 67, and omits the second low potential terminal 68. A portion of the first low potential terminal 67 and the second low potential terminal 68 is exposed as a first low potential pad 73 and a second low potential pad 74 from a first pad opening 71 and a second pad opening 72 formed in the uppermost insulating layer 59, respectively. At least one of the first low potential pad 73 and the second low potential pad 74 may be an example of the first pad of the present disclosure. A second conducting wire 18 (bonding wire) is connected to the first low potential pad 73 and the second low potential pad 74, respectively.

[0098] The first low potential wiring 31 electrically connects the first low potential terminal 67 and the low potential coil 22. The first low potential wiring 31 may include a first low potential connecting portion 75, a first wiring 76 as an example of a first current-carrying member of the present disclosure, a second low potential connecting portion 77, a second wiring 78, a first connecting plug electrode 79, a second connecting plug electrode 80, and a substrate plug electrode 81.

[0099] The first low potential connecting portion 75, the first wiring 76, the second low potential connecting portion 77, the second wiring 78, the first connecting plug electrode 79, the second connecting plug electrode 80, and the substrate plug electrode 81 may contain at least one of titanium (Ti), titanium nitride (TiN), copper (Cu), aluminum (Al), and tungsten (W). The first low potential connecting portion 75 and the like may have a layered structure including a barrier layer and a main body layer. The barrier layer defines a recess space in the interlayer insulating layer 60. The main body layer is embedded in the recess space defined by the barrier layer. The barrier layer may include at least one of titanium and titanium nitride. The main body layer may include at least one of copper, aluminum, and tungsten.

[0100] The first low potential connection portion 75 is formed in the first inner region 65 of the transformer 21 (low potential coil 22) in the same interlayer insulating layer 60 as the low potential coil 22. The first low potential connection portion 75 is formed in an island shape and faces the high potential terminal (first high potential terminal 84) in the normal direction Z. The first low potential connection portion 75 is electrically connected to the first inner end 24 of the low potential coil 22.

[0101] The first wiring 76 is formed in the interlayer insulating layer 60. In this embodiment, the first wiring 76 is formed in the first interlayer insulating layer 60 counting from the bottom insulating layer 58, and extends below the low-potential coil 22 across the low-potential coil 22. The first wiring 76 includes a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of the first wiring 76 is located in the region between the semiconductor chip 40 and the first low-potential connecting portion 75. The second end of the first wiring 76 is located in the region between the semiconductor chip 40 and the second low-potential connecting portion 77. The wiring portion extends along the first direction X and in a strip shape (straight line) in the region between the first end and the second end.

[0102] The second low potential connection portion 77 is a portion that relays the first wiring 76 and the second wiring 78. The second low potential connection portion 77 is formed in the same interlayer insulating layer 60 as the low potential coil 22. The second low potential connection portion 77 is formed in an island shape and faces the first low potential connection portion 75 in the first direction X, with part of the first spiral portion 26 of the low potential coil 22 in between. As shown in FIG. 5 , the first low potential connection portion 75 and the second low potential connection portion 77 are connected over a relatively short distance by a linear first wiring 76 that extends across the lower part of the low potential coil 22. This reduces the wiring resistance of the first low potential wiring 31.

[0103] The second wiring 78 extends between the second low potential connecting portion 77 and the first low potential terminal 67 in the same interlayer insulating layer 60 as the low potential coil 22, and connects the second low potential connecting portion 77 and the first low potential terminal 67. Note that in FIG. 9, for the sake of convenience, the second low potential connecting portion 77 and the first low potential terminal 67 are shown as the same component. Furthermore, as shown in FIGS. 4 and 6, the second wiring 78 is formed across the inside and outside of the pad region 54. Therefore, a portion of the second wiring 78 is formed in the pad region 54, and the remaining portion of the second wiring 78 is formed outside the pad region 54 and is covered with the second insulating portion 46.

[0104] The first connection plug electrode 79 is formed in the interlayer insulating layer 60 in a region between the first low potential connecting portion 75 and the first wiring 76, and is electrically connected to the first low potential connecting portion 75 and a first end portion of the first wiring 76. The second connection plug electrode 80 is formed in the interlayer insulating layer 60 in a region between the second low potential connecting portion 77 and the first wiring 76, and is electrically connected to the second low potential connecting portion 77 and a second end portion of the first wiring 76.

[0105] In this embodiment, the substrate plug electrode 81 is formed in a region between the semiconductor chip 40 and the second end of the first wiring 76, and is electrically connected to the semiconductor chip 40 and the second end of the first wiring 76. The substrate plug electrode 81 may fix the first low potential wiring 31 to the ground potential.

[0106] The second low potential wiring 32 electrically connects the second low potential terminal 68 and the low potential coil 22. The second low potential wiring 32 may include a third low potential connection portion 82 and a third wiring 83. The third low potential connection portion 82 and the third wiring 83 are preferably formed from the same conductive material as the first low potential connection portion 75, etc. In other words, the third low potential connection portion 82 and the third wiring 83 preferably include a barrier layer and a main body layer, similar to the first low potential connection portion 75, etc.

[0107] The third low potential connection portion 82 is formed in the same interlayer insulating layer 60 as the low potential coil 22. The third low potential connection portion 82 is formed in an island shape and faces the first low potential connection portion 75 in the second direction Y, with part of the first spiral portion 26 of the low potential coil 22 in between. The third low potential connection portion 82 is electrically connected to the first outer end 25 of the low potential coil 22.

[0108] The third wiring 83 extends between the third low potential connecting portion 82 and the second low potential terminal 68 in the same interlayer insulating layer 60 as the low potential coil 22, and connects the third low potential connecting portion 82 and the second low potential terminal 68. Furthermore, as shown in FIGS. 4 and 6, the third wiring 83 is formed across the inside and outside of the pad region 54. Therefore, a portion of the third wiring 83 is formed in the pad region 54, and the remaining portion of the third wiring 83 is formed outside the pad region 54 and is covered with the second insulating portion 46.

[0109] 4, 6, and 9, the semiconductor device 5 includes, as a structure related to the high-potential coil 23, a first high-potential terminal 84, a second high-potential terminal 85, a first high-potential wiring 33, and a second high-potential wiring 34. The first high-potential terminal 84 and the second high-potential terminal 85 are the above-mentioned high-potential terminals 12. The first high-potential terminal 84, the second high-potential terminal 85, the first high-potential wiring 33, and the second high-potential wiring 34 are preferably formed on the insulating main surface 50 of the second insulating portion 46 from the same conductive material as that of the high-potential coil 23. That is, the first high-potential terminal 84, the second high-potential terminal 85, the first high-potential wiring 33, and the second high-potential wiring 34 may be made of Cu formed by plating growth of Cu.

[0110] The first high potential terminal 84 is formed in an island shape and is located in the second inner region 66 of the transformer 21 (high potential coil 23) in a planar view. The second high potential terminal 85 is formed in an island shape and is located outside the second inner region 66 in a planar view. In this embodiment, the second high potential terminal 85 faces the first high potential terminal 84 in the second direction Y across a part of the second spiral portion 29 of the high potential coil 23. Therefore, the second high potential terminal 85 is located in the second region 70. The second high potential terminal 85 may face a plurality of low potential terminals 67, 68 in the first direction X. In addition, the second high potential terminal 85 is located within the width W of the high potential coil 23 in the first direction X. C1 Width W smaller than T1 It has the following characteristics.

[0111] The first high potential terminal 84 and the second high potential terminal 85 are covered with the protective layer 47. A portion of each of the first high potential terminal 84 and the second high potential terminal 85 is exposed as a first high potential pad 88 and a second high potential pad 89 from a first pad opening 86 and a second pad opening 87 formed in the protective layer 47. The second high potential pad 89 may be an example of a second pad of the present disclosure. A third conducting wire 19 (bonding wire) is connected to each of the first high potential pad 88 and the second high potential pad 89.

[0112] The first high-potential wiring 33 connects the first high-potential terminal 84 and the second inner end 27 of the high-potential coil 23. The second high-potential wiring 34 connects the second high-potential terminal 85 and the second outer end 28 of the high-potential coil 23. Here, the structure of the high-potential coil 23 will be described in more detail with reference to Figs. 7 to 9.

[0113] The second spiral portion 29 of the high-potential coil 23 may include a first portion 90 that forms the outermost periphery of the second spiral portion 29 and a second portion 91 that forms the second spiral portion 29 on the inner side of the first portion 90. As shown in FIG. 9 , the first portion 90 has a first width W A and the second portion 91 has a first width W A The second width W is smaller than B Furthermore, the distance D between the first portion 90 and the outermost portion of the second portion 91 (i.e., the second turn from the outermost portion of the high-potential coil 23) may be greater than the pitch P of the second portion 91. Furthermore, the second portion 91 of the high-potential coil 23 may have a thickness greater than the pitch P of the second portion 91.

[0114] 7, the second high potential terminal 85 may be connected to both the first portion 90 and the second portion 91 of the high potential coil 23. In this case, the high potential coil 23 has a double helical structure extending from the second high potential terminal 85, with a first helical structure 92 continuing to the first portion 90 and a second helical structure 93 continuing to the second portion 91, but the first helical structure 92 and the second helical structure 93 may be shared by a connecting portion 94 extending in a direction transverse to the helical structures.

[0115] 8, the second high-potential terminal 85 may be selectively connected to the second portion 91 of the high-potential coil 23. In this case, the first portion 90 of the high-potential coil 23 is electrically isolated from the second portion 91. Therefore, only the second portion 91 of the high-potential coil 23 may be referred to as the high-potential coil 23 that contributes to the function of the transformer 21, and the first portion 90 of the high-potential coil 23 may be referred to as a dummy pattern 95 that does not contribute to the function of the transformer 21. For example, the dummy pattern 95 may be formed in a substantially annular shape with an open portion 96 in a portion thereof, and the second high-potential terminal 85 and the high-potential coil 23 (second portion 91) may be connected by a connection portion 97 that passes through the open portion 96. The dummy pattern 95 may be connected to ground potential or may be electrically floating (not shown). 9, the semiconductor device 5 includes a second functional device 98 formed on the first main surface 41 of the semiconductor chip 40 in a device region 100 (described below). The second functional device 98 is formed using a surface layer portion of the first main surface 41 of the semiconductor chip 40 and / or a region above the first main surface 41 of the semiconductor chip 40, and is covered with a first insulating section 45 (lowest insulating layer 58). In FIG. 9, the second functional device 98 is simply shown by a dashed line drawn on the surface layer portion of the first main surface 41. The second functional device 98 is electrically connected to low-potential terminals 67, 68 via low-potential wiring, and is electrically connected to a high-potential terminal via high-potential wiring.

[0116] The second functional device 98 may include at least one of a passive device, a semiconductor rectifying device, and a semiconductor switching device. The second functional device 98 may include circuitry in which any two or more of the passive devices, the semiconductor rectifying device, and the semiconductor switching device are selectively combined. The circuitry may form part or all of an integrated circuit.

[0117] The passive device may include a semiconductor passive device. The passive device may include either or both of a resistor and a capacitor. The semiconductor rectifying device may include at least one of a pn junction diode, a PIN diode, a Zener diode, a Schottky barrier diode, and a fast recovery diode. The semiconductor switching device may include at least one of a BJT (Bipolar Junction Transistor), a MISFET (Metal Insulator Field Effect Transistor), an IGBT (Insulated Gate Bipolar Junction Transistor), and a JFET (Junction Field Effect Transistor).

[0118] 4 to 6 and 9, the semiconductor device 5 further includes a seal conductor 99 embedded in the first insulating portion 45. The seal conductor 99 is embedded in the first insulating portion 45 in a wall shape at a distance from the insulating side walls 49A to 49D in a plan view, and divides the first insulating portion 45 into a device region 100 and an outer region 101. The seal conductor 99 prevents moisture and cracks from entering from the outer region 101 to the device region 100.

[0119] The device region 100 is a region including the first functional device 64 (transformer 21), the second functional device 98, a plurality of low potential terminals 67, 68, a plurality of high potential terminals 84, 85, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, and the second high potential wiring 34. The outer region 101 is a region outside the device region 100.

[0120] The seal conductor 99 is electrically isolated from the device region 100. Specifically, the seal conductor 99 is electrically isolated from the first functional device 64 (transformer 21), the second functional device 98, the plurality of low potential terminals 67, 68, the plurality of high potential terminals 84, 85, the first low potential wiring 31, the second low potential wiring 32, the first high potential wiring 33, and the second high potential wiring 34. More specifically, the seal conductor 99 is fixed in an electrically floating state. The seal conductor 99 does not form a current path leading to the device region 100.

[0121] The seal conductor 99 is formed in a strip shape along the insulating side walls 49A to 49D in plan view. In this embodiment, the seal conductor 99 is formed in a quadrangular ring shape (specifically, a square ring shape) in plan view. As a result, the seal conductor 99 defines a quadrangular (specifically, square) device region 100 in plan view. The seal conductor 99 also defines a quadrangular ring (specifically, a square ring) outer region 101 that surrounds the device region 100 in plan view.

[0122] Specifically, the seal conductor 99 has an upper end on the insulating principal surface 48 side, a lower end on the semiconductor chip 40 side, and a wall extending in a wall shape between the upper and lower ends. In this embodiment, the upper end of the seal conductor 99 is formed at a distance from the insulating principal surface 48 toward the semiconductor chip 40 and is located within the first insulating portion 45. In this embodiment, the upper end of the seal conductor 99 is covered by the top insulating layer 59. The upper end of the seal conductor 99 may be covered by one or more interlayer insulating layers 60. The upper end of the seal conductor 99 may be exposed from the top insulating layer 59. The lower end of the seal conductor 99 is formed at a distance from the semiconductor chip 40 toward the upper end.

[0123] Thus, in this embodiment, the seal conductor 99 is embedded in the first insulating section 45 so as to be located on the semiconductor chip 40 side with respect to the plurality of low potential terminals 67, 68 and the plurality of high potential terminals 84, 85. Furthermore, the seal conductor 99 faces the first functional device 64 (transformer 21), the first low potential wiring 31, and the second low potential wiring 32 in the first insulating section 45 in a direction parallel to the insulating principal surface 48. The seal conductor 99 may face a part of the second functional device 98 in the direction parallel to the insulating principal surface 48 in the first insulating section 45.

[0124] The seal conductor 99 includes a plurality of seal plug conductors 102 and one or more (in this embodiment, a plurality) seal via conductors 103. The number of seal via conductors 103 is arbitrary. The uppermost seal plug conductor 102 among the plurality of seal plug conductors 102 forms the upper end portion of the seal conductor 99. The plurality of seal via conductors 103 each form the lower end portion of the seal conductor 99. The seal plug conductor 102 and the seal via conductor 103 are preferably formed from the same conductive material as the low potential coil 22.

[0125] The multiple seal plug conductors 102 are embedded in the multiple interlayer insulating layers 60, respectively, and are each formed in a quadrangular ring shape (specifically, a square ring shape) surrounding the device region 100 in plan view. The multiple seal plug conductors 102 are stacked from the bottom insulating layer 58 to the top insulating layer 59 so as to be connected to each other. The number of stacked multiple seal plug conductors 102 matches the number of stacked multiple interlayer insulating layers 60. Of course, one or more seal plug conductors 102 may be formed penetrating the multiple interlayer insulating layers 60.

[0126] As long as a single annular seal conductor 99 is formed by an assembly of a plurality of seal plug conductors 102, it is not necessary for all of the plurality of seal plug conductors 102 to be formed in an annular shape. For example, at least one of the plurality of seal plug conductors 102 may be formed in an end-shaped form. Also, at least one of the plurality of seal plug conductors 102 may be divided into a plurality of strip-shaped portions with ends. However, in consideration of the risk of moisture or cracks penetrating into the device region 100, it is preferable that the plurality of seal plug conductors 102 be formed in an endless (annular) form.

[0127] The plurality of seal via conductors 103 are respectively formed in the region between the semiconductor chip 40 and the seal plug conductor 102 in the lowermost insulating layer 58. The plurality of seal via conductors 103 are connected to the semiconductor chip 40 and to the seal plug conductor 102. As a result, the seal conductor 99 may be fixed to the ground potential via the seal via conductor 103. The plurality of seal via conductors 103 have a planar area smaller than the planar area of ​​the seal plug conductor 102. When a single seal via conductor 103 is formed, the single seal via conductor 103 may have a planar area equal to or larger than the planar area of ​​the seal plug conductor 102.

[0128] The width of the shield conductor 99 may be 0.1 μm or more and 20 μm or less. The width of the shield conductor 99 is preferably 1 μm or more and 10 μm or less. The width of the shield conductor 99 is defined by the width in a direction perpendicular to the direction in which the shield conductor 99 extends.

[0129] 9, the protective layer 47 is formed on the insulating main surface 50 of the second insulating portion 46 so as to cover the high-potential coil 23 and the plurality of high-potential terminals 84, 85. The protective layer 47 may also be referred to as a passivation layer. The protective layer 47 protects the second insulating portion 46, the first insulating portion 45, and the semiconductor chip 40 from above the insulating main surface 50. In this embodiment, the protective layer 47 includes polyimide. The thickness of the protective layer 47 may be 1 μm or more and 100 μm or less.

[0130] The thickness of the protective layer 47 is preferably equal to or greater than the distance D1 between the low potential coil 22 and the high potential coil 23. In this case, the thickness of the protective layer 47 is preferably equal to or greater than 5 μm and equal to or less than 100 μm. These structures can prevent the protective layer 47 from becoming too thick, and at the same time, the protective layer 47 can appropriately increase the dielectric strength voltage on the high potential coil 23.

[0131] As described above, according to the semiconductor device 5, the first low-potential pad 73 and the second low-potential pad 74 are spaced apart from the first region 69 relative to the high-potential coil 23 in the first direction X in a plan view. This allows the creepage distance between the high-potential coil 23 and the first low-potential pad 73 and the second low-potential pad 74 to be increased compared to when the first low-potential pad 73' and the second low-potential pad 74' (reference) are formed in the first region 69. For example, as shown in FIG. 10 , the distance D on a straight line extending from the center of the high-potential coil 23 to each of the low-potential pads 73, 74, 73', 74' is P1 , D P2 , D P3 and D P4 is defined as the creepage distance. In this case, the distance D between the first low potential pad 73 and the second low potential pad 74 formed in the second region 70 and the high potential coil 23 is P1 ,D P2 is the distance D between the first low potential pad 73′ and the second low potential pad 74′ formed in the first region 69. P3 ,D P4 can be longer than

[0132] This makes it possible to suppress the occurrence of creeping discharge in the region between the high-potential coil 23 and the first and second low-potential pads 73 and 74. As a result, it is possible to suppress breakdown and deterioration of the first insulating portion 45, the second insulating portion 46, and the protective layer 47 between the high-potential coil 23 and the first and second low-potential pads 73 and 74. Therefore, it is possible to provide a highly reliable semiconductor device 5. [Second embodiment] 11 is a schematic plan view of a semiconductor device 5 according to another embodiment of the present disclosure. In the following, structures corresponding to structures already described will be given the same reference numerals and descriptions thereof will be omitted.

[0133] 4, the pad region 54 is selectively formed in the second corner portion 44B of the semiconductor chip 40. However, as shown in FIG. 11, the pad region 54 may be formed in a strip shape along the chip sidewall 43D of the semiconductor chip 40. As a result, the pad region 54 includes a pair of second regions 70A, 70B sandwiching the first region 69 along the chip sidewall 43D. One second region 70A is formed in the third corner portion 44C of the semiconductor chip 40, and the other second region 70B is formed in the second corner portion 44B of the semiconductor chip 40. The first low potential terminal 67 (first low potential pad 73) and the second low potential terminal 68 (second low potential pad 74) may be formed in one second region 70A and the other second region 70B, respectively. [Third embodiment] 12 is a schematic plan view of a semiconductor device 5 according to another embodiment of the present disclosure. In the following, structures corresponding to structures already described will be given the same reference numerals and descriptions thereof will be omitted.

[0134] Although one transformer 21 is formed in the semiconductor device 5 in FIG. 4, multiple transformers 21 may be formed in the semiconductor device 5. For example, as shown in FIG. 12, a pair of transformers 21A and 21B may be formed on a common semiconductor chip 40. In this case, the transformers 21A and 21B may be arranged in a point-symmetric relationship with respect to the center of gravity of the semiconductor chip 40, which is rectangular in plan view, as the center of symmetry C. Therefore, the pad region 54A corresponding to the transformer 21A and the pad region 54B corresponding to the transformer 21B may be formed in corners diagonally opposite each other. In FIG. 12, the pad region 54A is formed in the first corner 44A, and the pad region 54B is formed in the second corner 44B. That is, the first low potential terminals 67A, 67B (first low potential pads 73A, 73B) and the second low potential terminals 68A, 68B (second low potential pads 74A, 74B) corresponding to the transformer 21A and the transformer 21B, respectively, are formed in pad regions 54A, 54B that are separated from each other. [Fourth embodiment] 13 is a schematic plan view of a semiconductor device 5 according to another embodiment of the present disclosure. In the following, structures corresponding to structures already described will be given the same reference numerals and descriptions thereof will be omitted.

[0135] The structures of the pair of transformers 21A, 21B may be arranged in a point-symmetric relationship as shown in FIG. 12, or may be arranged in an axis-symmetric relationship with respect to a line segment that bisects the long side of the semiconductor chip 40, which is rectangular in plan view (in this embodiment, the third chip side wall 43C and the fourth chip side wall 43D), as the axis of symmetry A, as shown in FIG.

[0136] In this case, the transformer 21A may be formed biased toward the first chip sidewall 43A of the semiconductor chip 40, and the transformer 21B may be formed biased toward the second chip sidewall 43B of the semiconductor chip 40. Here, "the transformer 21A is provided biased toward the first chip sidewall 43A" may mean, for example, that the transformer 21A is disposed closer to the first chip sidewall 43A with respect to the configuration that forms a pair with the first chip sidewall 43A (in this embodiment, the second chip sidewall 43B). The same applies to "the transformer 21B is provided biased toward the second chip sidewall 43B." As a result, a relatively large second region 70 is secured between the transformer 21A and the transformer 21B in the second direction Y.

[0137] Therefore, the pad region 54A corresponding to the transformer 21A and the pad region 54B corresponding to the transformer 21B may be integrally formed, and the first low potential terminals 67A, 67B (first low potential pads 73A, 73B) and second low potential terminals 68A, 68B (second low potential pads 74A, 74B) corresponding to the transformers 21A and 21B, respectively, may be collected in the common pad region 54. The pad region 54 is formed biased toward at least one of the third chip sidewall 43C and the fourth chip sidewall 43D of the semiconductor chip 40 (the fourth chip sidewall 43D in this embodiment). [Fifth embodiment] 14 is a schematic plan view of a semiconductor device 5 according to another embodiment of the present disclosure. In the following, structures corresponding to structures already described will be given the same reference numerals and descriptions thereof will be omitted.

[0138] When the semiconductor device 5 has a structure including a pair of transformers 21A and 21B, the first low potential terminal 67 (first low potential pad 73) and the second low potential terminal 68 (second low potential pad 74) corresponding to each of the transformers 21A and 21B can be common, as shown in FIG. 14 . That is, the first low potential terminal 67 (first low potential pad 73) and the second low potential terminal 68 (second low potential pad 74) may be connected to both of the pair of transformers 21A and 21B. By commonalizing the pads, the area of ​​the pad region 54 can be reduced, thereby enabling the semiconductor device 5 to be made into a smaller chip. [Sixth embodiment] 15 is a schematic plan view of a semiconductor device 5 according to another embodiment of the present disclosure. In the following, structures corresponding to structures already described will be given the same reference numerals and descriptions thereof will be omitted.

[0139] In the above description, the first low potential wiring 31 and the seal conductor 99 are connected to the semiconductor chip 40 via the substrate plug electrode 81 and the seal via conductor 103, respectively, and are fixed to the ground potential. On the other hand, as shown in Fig. 15, by omitting the substrate plug electrode 81 and the seal via conductor 103, the first low potential wiring 31 and the seal conductor 99 do not need to be fixed to the ground potential. [Seventh embodiment] 16 is a schematic plan view of a semiconductor device 5 according to another embodiment of the present disclosure. In the following, structures corresponding to structures already described will be given the same reference numerals and descriptions thereof will be omitted.

[0140] In the above description, the low-potential coil 22 of the transformer 21 is formed in one interlayer insulating layer 60, but as shown in Fig. 16, the low-potential coil 22 may be low-potential coils 104 formed in multiple layers in the normal direction Z of the semiconductor chip 40. For example, the low-potential coil 104 may include a first low-potential coil 105 formed on the semiconductor chip 40 side and a second low-potential coil 106 formed on the second insulating part 46 side with respect to the first low-potential coil 105.

[0141] The first low potential coil 105 and the second low potential coil 106 may be formed in different interlayer insulating layers 60. For example, of a pair of interlayer insulating layers 60 that are in contact with each other in the normal direction Z, the first low potential coil 105 may be formed in the lower interlayer insulating layer 60 closer to the semiconductor chip 40, and the second low potential coil 106 may be formed in the upper interlayer insulating layer 60 closer to the second insulating portion 46.

[0142] The first low-potential coil 105 and the second low-potential coil 106 may be formed offset from each other. For example, the first low-potential coil 105 may be offset from the second low-potential coil 106 so that the first low-potential coil 105 faces the gap 107 (the region between adjacent spiral portions) of the second low-potential coil 106. [Eighth embodiment] 17 is a schematic plan view of a semiconductor device 5 according to another embodiment of the present disclosure. In the following, structures corresponding to structures already described will be given the same reference numerals and descriptions thereof will be omitted.

[0143] In the above description, the second insulating section 46 made of the organic insulating layer 63 is interposed between the low-potential coil 22 and the high-potential coil 23, but the second insulating section 46 may be omitted. In this case, the number of stacked interlayer insulating layers 60 of the first insulating section 45 may be adjusted according to the dielectric strength voltage (dielectric breakdown resistance) to be achieved.

[0144] The low potential terminals 67, 68 may be formed in the same layer (in this embodiment, the insulating main surface 48 of the first insulating portion 45) as the high potential terminals 84, 85. The low potential terminals 67, 68 and the first low potential wiring 31 may be connected by a through wiring 108 that penetrates the interlayer insulating layer 60 of the first insulating portion 45 in the thickness direction. [Ninth embodiment] 18 is a schematic plan view of a semiconductor device 5 according to another embodiment of the present disclosure. In the following, structures corresponding to structures already described will be given the same reference numerals and descriptions thereof will be omitted.

[0145] In the above description, the protective layer 47 is formed of an organic insulating layer. However, as shown in FIG. 18, this may be replaced with a protective layer 109 made of an inorganic insulating layer. The protective layer 109 has a laminated structure including a first inorganic insulating layer 110 and a second inorganic insulating layer 111. The first inorganic insulating layer 110 may contain silicon oxide. The first inorganic insulating layer 110 preferably contains USG (undoped silicate glass), which is silicon oxide without added impurities. The second inorganic insulating layer 111 may contain silicon nitride. When the first inorganic insulating layer 110 is made of USG and the second inorganic insulating layer 111 is made of silicon nitride, the breakdown voltage (V / cm) of USG exceeds the breakdown voltage (V / cm) of silicon nitride. Therefore, when the protective layer 109 is thickened, it is preferable to form the first inorganic insulating layer 110 thicker than the second inorganic insulating layer 111.

[0146] 17, the high-potential coil 23 may be formed in the first insulating part 45. For example, the high-potential coil 23 may be embedded in an interlayer insulating layer 60 that contacts the top insulating layer 59. In this case, the first high-potential connecting part 115 that connects the high-potential coil 23 and the first high-potential terminal 84 may be embedded in the same interlayer insulating layer 60 as the high-potential coil 23.

[0147] In addition, Figure 18 shows a structure in which the semiconductor device 5 of Figure 17 has a protective layer 109, but the protective layer 47 can also be replaced with the protective layer 109 in semiconductor devices 5 of embodiments other than the ninth embodiment. [Tenth embodiment] 19 is a schematic plan view of a semiconductor device 5 according to another embodiment of the present disclosure. In the following, structures corresponding to structures already described will be given the same reference numerals and descriptions thereof will be omitted.

[0148] In the above description, the semiconductor device 5 is equipped with a transformer 21 as an example of the first functional device 64. However, as shown in FIG. 19 , a capacitor 112 may be equipped instead of the transformer 21. The capacitor 112 may include, for example, a lower electrode 113 formed in the first insulating section 45 and an upper electrode 114 formed on the second insulating section 46. The lower electrode 113 and the upper electrode 114 may face each other with the first insulating section 45 and the second insulating section 46 interposed therebetween.

[0149] Although the embodiments of the present disclosure have been described above, the present disclosure can be embodied in other forms.

[0150] For example, the above features understood from the disclosure of each of the above embodiments can be combined with each other in different embodiments.

[0151] In addition, various design modifications can be made within the scope of the claims.

[0152] This application corresponds to Patent Application No. 2020-165411 filed with the Japan Patent Office on September 30, 2020, the entire disclosure of which is incorporated herein by reference. [Explanation of symbols]

[0153] 1: Semiconductor module 2: Package body 3: Die pad 3A: First die pad 3B: Second die pad 4: Lead terminal 5: Semiconductor device 6: Controller IC 7: Driver IC 8: Non-mounting surface 9: Mounting surface 10A: 1st side wall 10B: 2nd side wall 10C: 3rd side wall 10D: 4th side wall 11: Low potential terminal 12: High potential terminal 13: First input pad 14: 1st output pad 15: Second input pad 16: 2nd output pad 17:1st conductor 18:Second conductor 19:Third conductor 20: 4th conductor 21: Trance 21A: Transformer 21B: Transformer 22: Low potential coil 23: High potential coil 24: 1st medial end 25 :First outer end 26:1st spiral part 27 :Second medial end 28 :Second outer end 29:Second spiral part 31: 1st low potential wiring 32: 2nd low potential wiring 33: 1st high potential wiring 34: 2nd high potential wiring 35: 1st wiring 36: 2nd wiring 37: Power supply 38: Reference voltage power supply 39:Power supply 40: Semiconductor chip 41: First main surface 42: Second main surface 43A: First chip side wall 43B: Second chip side wall 43C: Third chip sidewall 43D: 4th chip sidewall 44A: First corner 44B: Second corner 44C: 3rd corner 44D: 4th corner 45: First insulating part 46: Second insulating part 47 :Protective layer 48: (First insulating part) Main insulating surface 49A: (First insulating part) First insulating side wall 49B: (First insulating part) Second insulating side wall 49C: (First insulating part) Third insulating side wall 49D: (First insulating part) Fourth insulating side wall 50: (Second insulating part) Main insulating surface 51A: (Second insulating part) First insulating side wall 51B: (Second insulating part) Second insulating side wall 51C: (Second insulating part) Third insulating side wall 51D: (Second insulating part) Fourth insulating side wall 52: Step 53: Recess 54: Pad area 54A: Pad area 54B: Pad area 55: Main protective surface 56A: 1st protection side wall 56B: 2nd protection side wall 56C: 3rd protection side wall 56D: Fourth protective side wall 57: Step 58: Bottom insulating layer 59: Top insulating layer 60: Interlayer insulating layer 61: First insulating layer 62: Second insulating layer 63: Organic insulating layer 64: First functional device 65: 1st inner area 66:Second inner area 67: 1st low potential terminal 67A: 1st low potential terminal 67B: 1st low potential terminal 68: 2nd low potential terminal 68A: Second low potential terminal 68B: 2nd low potential terminal 69: 1st area 70:Second area 70A: 2nd area 70B:Second area 71: First pad opening 72: Second pad opening 73: First low potential pad 73A: First low potential pad 73B: First low potential pad 74: Second low potential pad 74A: Second low potential pad 74B: Second low potential pad 75: First low potential connection 76: 1st wiring 77: Second low potential connection 78: 2nd wiring 79: First connecting plug electrode 80: Second connecting plug electrode 81: PCB plug electrode 82: Third low potential connection 83: 3rd wiring 84: First high potential terminal 85: Second high potential terminal 86: First pad opening 87: Second pad opening 88: First high potential pad 89: Second high potential pad 90: (High potential coil) 1st part 91: (High potential coil) 2nd part 92:First helical structure 93:Second helical structure 94: Connection 95: Dummy pattern 96:Open part 97: Connection 98: Second function device 99: Sealed conductor 100: Device area 101 :Outer area 102: Seal plug conductor 103: Seal via conductor 104: Low potential coil 105: First low potential coil 106: Second low potential coil 107: Gap 108: Through wiring 109 :Protective layer 110: First inorganic insulating layer 111: Second inorganic insulating layer 112: Capacitor 113: Lower electrode 114: Upper electrode 115: First high potential connection

Claims

1. a semiconductor chip having a main surface; an insulating portion formed on the main surface of the semiconductor chip; a first conductive layer formed within the insulating portion and connected to a first potential; a second conductive layer facing the first conductive layer in a normal direction of the main surface and connected to a second potential higher than the first potential; an insulating layer formed between the first conductive layer and the second conductive layer; a first pad electrically connected to the first conductive layer; a second pad that is aligned with the second conductive layer in a plan view when the semiconductor chip is viewed from the normal direction and is electrically connected to the second conductive layer, the second conductive layer and the second pad are located on the insulating layer; the semiconductor chip has one side and another side that intersect with each other in the plan view, The semiconductor device, wherein the first pad is formed in the insulating portion so as to be exposed from the insulating layer in a region away from the second pad in a third direction that intersects a first direction parallel to one side of the semiconductor chip and a second direction parallel to the other side of the semiconductor chip when viewed in the plane.

2. The insulating layer is located on the insulating portion, 2. The semiconductor device according to claim 1, wherein a distance between said second conductive layer and said first pad in said normal direction is greater than a thickness of said insulating layer in said normal direction.

3. the semiconductor chip is formed in a quadrangular shape having a first corner and a second corner diagonally disposed relative to each other, and a third corner and a fourth corner diagonally disposed relative to each other, in the plan view; the second conductive layer is provided one at a time in the first corner portion, 3. The semiconductor device according to claim 1, wherein the first pad is provided biased toward the second corner portion.

4. the semiconductor chip is formed in a quadrilateral shape having a first side and a second side opposite each other and a third side and a fourth side opposite each other in the plan view, the second conductive layers are provided one on each of the first side and the second side, 3. The semiconductor device according to claim 1, wherein said first pad is provided in a region between a pair of said second conductive layers facing each other, biased toward at least one of said third side and said fourth side.

5. the first conductive layer includes a first coil; 5. The semiconductor device according to claim 1, wherein the second conductive layer includes a second coil.

6. The semiconductor device according to claim 5 , wherein said second coil has a thickness greater than that of said first coil.

7. 7. The semiconductor device according to claim 5, wherein the second coil has a thickness greater than a pitch of the first coil.

8. The semiconductor device according to any one of claims 5 to 7, wherein the second coil includes a first portion that forms the outermost periphery of the second coil and has a first width, and a second portion that forms a coil portion that is more inward than the first portion and has a second width that is smaller than the first width.

9. 9. The semiconductor device according to claim 8, wherein a distance between said first portion and an outermost portion of said second portion is greater than a pitch of said second portion.

10. the first coil is made of AlCu, 10. The semiconductor device according to claim 5, wherein the second coil is made of Cu.

11. 11. The semiconductor device according to claim 5, further comprising a first current-carrying member connected to an inner end of the first coil, extending across the first coil below the first coil, and electrically connected to the first pad.

12. 12. The semiconductor device according to claim 1, wherein the insulating layer includes an organic insulating layer.

13. 13. The semiconductor device according to claim 12, wherein the organic insulating layer includes at least one of a polyimide film, a phenolic resin film, and an epoxy resin film.

14. 12. The semiconductor device according to claim 1, wherein the insulating layer includes a laminated structure of a first inorganic insulating layer and a second inorganic insulating layer laminated on the first inorganic insulating layer.

15. the first inorganic insulating layer includes a silicon nitride film, The semiconductor device according to claim 14 , wherein the second inorganic insulating layer includes a silicon oxide film.

16. One side and the other side of the semiconductor chip are perpendicular to each other, 16. The semiconductor device according to claim 1, wherein the third direction intersects with the first direction and the second direction which are orthogonal to each other.

17. A die pad; a semiconductor device according to any one of claims 5 to 11 mounted on the die pad; a package body that encapsulates the die pad and the semiconductor device; a lead terminal electrically connected to the semiconductor device and exposed from the package body.

18. the semiconductor device includes an insulating element for signal transmission that transmits a signal in an insulated state between the first coil and the second coil, The semiconductor module according to claim 17 , further comprising a second semiconductor device electrically connected to the isolation element.

19. 19. The semiconductor module according to claim 18, wherein the second semiconductor device includes a control element electrically connected to one of the first coil and the second coil, and a drive element electrically connected to the other of the first coil and the second coil.

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