Stiffener-equipped wiring board

Abstract

This wiring substrate with a stiffener according to the present disclosure includes: a wiring substrate; a mounting region located on an upper surface of the wiring substrate; and a stiffener that is located on the upper surface of the wiring substrate so as to surround the mounting region and that has a first surface facing the wiring substrate and a second surface located on the opposite side from the first surface. The wiring substrate has a first coefficient of thermal expansion. The stiffener includes: a first region that faces the wiring substrate, includes the first surface, and has a second coefficient of thermal expansion; and a second region that is located on the front surface side opposite the first region, includes the second surface, and has a third coefficient of thermal expansion. The absolute value of the difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion is less than the absolute value of the difference between the first coefficient of thermal expansion and the third coefficient of thermal expansion.

Description

[Technical Field]

[0001] The present invention relates to a wiring board with a stiffener. [Background technology]

[0002] Known LSI packages in which LSI electronic components are mounted on a wiring board include FC-BGA (Flip Chip Ball Grid Array), etc. Wiring boards used in such LSI packages are provided with stiffeners for the purposes of reinforcement and warpage correction, as described in Patent Document 1, for example. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2020 / 162417 Summary of the Invention [Means for solving the problem]

[0004] A wiring board with a stiffener according to the present disclosure includes a wiring board, a mounting area located on the upper surface of the wiring board, and a stiffener located on the upper surface of the wiring board so as to surround the mounting area, the stiffener having a first surface facing the wiring board and a second surface located opposite the first surface. The wiring board has a first thermal expansion coefficient. The stiffener includes a first region facing the wiring board, including the first surface, and having a second thermal expansion coefficient, and a second region located on the surface opposite the first region, including the second surface, and having a third thermal expansion coefficient. The absolute value of the difference between the first and second thermal expansion coefficients is smaller than the absolute value of the difference between the first and third thermal expansion coefficients.

[0005] An electronic component mounting structure according to the present disclosure includes the above-described wiring board with a stiffener and an electronic component positioned in a mounting area. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is an explanatory diagram illustrating a state in which an electronic component is mounted on a wiring board with a stiffener according to an embodiment of the present disclosure. FIG. [Figure 2] 2 is an enlarged explanatory view for explaining an area X shown in FIG. 1. FIG. [Figure 3] 10 is a graph showing the results of a stress simulation at a corner and the results of a warpage simulation for a stiffened wiring board equipped with a copper stiffener (a conventional stiffener). [Figure 4] 10 is a graph showing the results of a stress simulation of a corner and the results of a warpage simulation for a wiring board with a stiffener, the thermal expansion coefficient of which is assumed to be 20 ppm / ° C.; [Figure 5] 10 is a graph showing the results of a stress simulation of a corner and the results of a warpage simulation for a wiring board with a stiffener, the thermal expansion coefficient of which is assumed to be 15 ppm / ° C.; [Figure 6] 10 is a graph showing the results of a stress simulation of a corner and the results of a warpage simulation for a wiring board with a stiffener (conventional stiffener) made of AlSiC (SiC 40%). [Figure 7] 10 is a graph showing the results of a stress simulation of a corner and the results of a warpage simulation for a wiring board with a stiffener (conventional stiffener) made of AlSiC (SiC 45%). [Figure 8] 10 is a graph showing the results of a stress simulation of a corner and the results of a warpage simulation for a wiring board with a stiffener (a stiffener outside the scope of this disclosure) having a copper lower layer and an AlSiC (SiC 40%) upper layer. [Figure 9] 10 is a graph showing the results of a stress simulation of a corner and the results of a warpage simulation for a wiring board with a stiffener (a stiffener outside the scope of this disclosure) having a copper lower layer and an AlSiC (SiC 45%) upper layer. [Figure 10]10 is a graph showing the results of a stress simulation of a corner and the results of a warpage simulation for a wiring board with a stiffener (stiffener of the present disclosure) having an upper layer of copper and a lower layer of AlSiC (SiC 40%). [Figure 11] 10 is a graph showing the results of a stress simulation of a corner and the results of a warpage simulation for a wiring board with a stiffener (stiffener of the present disclosure) having an upper layer of copper and a lower layer of AlSiC (SiC 45%). [Figure 12] 10 is a graph showing the degree of stress relaxation for a wiring board with a stiffener (stiffener of the present disclosure) having an upper layer of copper and a lower layer of AlSiC (SiC 40% and 45%). DETAILED DESCRIPTION OF THE INVENTION

[0007] In wiring boards with stiffeners, the stiffeners are generally made of copper, which has a relatively large thermal expansion coefficient, and the difference in expansion and contraction between the stiffener and the board is used to correct warpage of the board. During such correction, stress tends to concentrate in the area between the electronic component and the stiffener (the edge of the stiffener), as shown in Figure 3 (described later). As a result, cracks are likely to occur in the plane conductors (especially the plane conductors around the solder) on the surface facing this area (the opposite surface). Therefore, there is a demand for wiring boards that are less likely to crack, even when used repeatedly in high- and low-temperature environments.

[0008] As described above, in the wiring board according to the present disclosure, the absolute value of the difference between the first and second thermal expansion coefficients is smaller than the absolute value of the difference between the first and third thermal expansion coefficients, and as a result, the wiring board according to the present disclosure is less likely to crack even when used repeatedly in high-temperature and low-temperature environments.

[0009] A stiffener-equipped wiring board according to an embodiment of the present disclosure will be described with reference to FIGS. 1 and 2. FIG. 1 is an explanatory diagram illustrating a state in which an electronic component is mounted on a stiffener-equipped wiring board according to an embodiment of the present disclosure (an electronic component mounting structure). As shown in FIG. 1, a stiffener-equipped wiring board 1 according to an embodiment includes a wiring board 11 and a stiffener 6. The wiring board 11 includes a first insulating layer 21, a second insulating layer 22, a third insulating layer 23, a conductor layer 4, and a solder resist 5.

[0010] First insulating layer 21 has upper surface 211 and lower surface 212 located opposite upper surface 211. Upper surface 211 and lower surface 212 correspond to the main surfaces of first insulating layer 21. In wiring board 11, first insulating layer 21 corresponds to a core insulating layer.

[0011] There are no particular limitations on the first insulating layer 21 as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together. There are no particular limitations on the thickness of the first insulating layer 21, and it is, for example, 400 μm or more and 1800 μm or less.

[0012] The first insulating layer 21 may contain a reinforcing material. Examples of the reinforcing material include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Furthermore, the first insulating layer 21 may have dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, or titanium oxide.

[0013] In the first insulating layer 21, a through-hole conductor (not shown) is usually located to electrically connect the upper and lower surfaces of the first insulating layer 21. The through-hole conductor is located in a through-hole that penetrates from the upper surface 211 to the lower surface 212 of the first insulating layer 21. The through-hole conductor is formed, for example, by metal plating such as copper plating. The through-hole conductor is connected to the conductor layers 4 formed on both surfaces of the first insulating layer 21. The through-hole conductor may be formed only on the inner wall surface of the through-hole, or may fill the through-hole.

[0014] Conductive layers 4 and insulating layers are alternately stacked on the upper surface 211 of the first insulating layer 21. In this specification, the outermost insulating layer among the insulating layers located on the upper surface 211 side is defined as the second insulating layer 22. Excluding the solder resist 5, the conductive layer 4 is located on the outermost surface on the upper surface 211 side of the wiring board 11. In other words, at least two conductive layers 4 and one insulating layer are stacked on the upper surface 211 side, and this one insulating layer corresponds to the second insulating layer 22.

[0015] There are no particular limitations on the conductor layer 4 as long as it is made of a conductor such as a metal. Specifically, the conductor layer 4 is made of a metal foil such as copper foil, a metal plating such as copper plating, etc. The thickness of the conductor layer 4 is not particularly limited and is, for example, 10 μm or more and 30 μm or less.

[0016] The insulating layers including the second insulating layer 22 are not particularly limited as long as they are formed of an insulating material, similar to the first insulating layer 21. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used. The insulating layers including the second insulating layer 22 may be formed of the same resin or different resins. The insulating layer including the second insulating layer 22 and the first insulating layer 21 may be formed of the same resin or different resins.

[0017] Furthermore, inorganic insulating fillers such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide may be dispersed in the insulating layers including second insulating layer 22. The thickness of the insulating layers including second insulating layer 22 is not particularly limited and is, for example, 5 μm or more and 50 μm or less. The insulating layers including second insulating layer 22 may each have the same thickness or different thicknesses.

[0018] Via-hole conductors (not shown) for electrically connecting layers are formed in the insulating layers including the second insulating layer 22. The via-hole conductors are located in via holes that penetrate the top and bottom surfaces of the insulating layers including the second insulating layer 22. The via-hole conductors are formed by metal plating such as copper plating. The via-hole conductors are connected to conductor layers 4 that are located on both sides of the insulating layer including the second insulating layer 22. The via-hole conductors may fill the via holes, or may be located only on the inner wall surfaces of the via holes.

[0019] As shown in Fig. 1, solder resist 5 may be located on the surface of conductor layer 4, which is the outermost layer stacked on the upper surface 211 side. In Fig. 1, solder resist 5 is located only on the surface of conductor layer 4. However, conductor layer 4 is a wiring pattern, and solder resist 5 is located on the surface of second insulating layer 22 in areas where conductor layer 4 does not exist.

[0020] The solder resist 5 is made of a resin, such as an acrylic-modified epoxy resin. The solder resist 5 has openings 51 formed therein to electrically connect the conductor layer 4 and the electrodes of the electronic components 7 via solder 8. The openings 51 are formed, for example, in the mounting area 3. The shape of the openings 51 is not limited, and is usually circular when viewed from above, but may be any other shape (for example, a polygonal shape such as a square or octagon).

[0021] The mounting area 3 is an area for mounting electronic components 7, and is located on the outermost surface on the upper surface 211 side. The mounting area 3 has a polygonal shape such as a square when viewed in a plane, depending on the shape of the electronic components 7. Examples of electronic components 7 mounted in the mounting area 3 include semiconductor integrated circuit devices and optoelectronic devices. The electronic components 7 are mounted so that the corners of the mounting area 3 and the corners of the electronic components 7 overlap each other when viewed in a plane. The shape of the mounting area 3 is not limited, and is not limited to a polygonal shape such as a square when viewed in a plane, but may also be a circle or an ellipse.

[0022] As with the upper surface 211, the lower surface 212 of the first insulating layer 21 also has conductor layers 4 and insulating layers laminated alternately. In this specification, the insulating layer located on the uppermost surface of the insulating layers located on the lower surface 212 side is defined as the third insulating layer 23. Excluding the solder resist 5, the conductor layer 4 is located on the outermost surface on the lower surface 212 side of the wiring board 11. In other words, at least two conductor layers 4 and one insulating layer are laminated on the lower surface 212 side, and this one insulating layer corresponds to the third insulating layer 23.

[0023] The conductor layer 4 and insulating layer stacked on the lower surface 212 are the same as those described for the conductor layer 4 and insulating layer stacked on the upper surface 211, and a detailed description thereof will be omitted. As shown in FIG. 1 , the conductor layer 4 stacked on the outermost layer on the lower surface 212 side, i.e., the conductor layer 4 located on the surface of the third insulating layer 23, is a plain conductor layer 41.

[0024] As shown in FIG. 1, a solder resist 5 is located on the surface of the plain conductor layer 41. The solder resist 5 has been described above, and a detailed description thereof will be omitted. In FIG. 1, the solder resist 5 is located only on the surface of the plain conductor layer 41. However, although the plain conductor layer 41 is basically a solid layer, a wiring pattern is formed in part of it. In the part where the plain conductor layer 41 is not present, the solder resist 5 is located on the surface of the third insulating layer 23. The solder resist 5 located on the surface of the third insulating layer 23 and the surface of the plain conductor layer 41 has openings 51 for electrically connecting the plain conductor layer 41 to electrodes of another wiring board (e.g., a motherboard) via solder 8. The shape of the openings 51 is not limited as described above.

[0025] As shown in FIG. 1, stiffener-equipped wiring board 1 has stiffener 6 positioned to surround mounting area 3. Stiffener 6 is used to improve the rigidity of wiring board 11 and correct warpage of wiring board 11. As shown in FIG. 2, stiffener 6 includes a first region 61 facing wiring board 11, including a first surface 6a, and having a second thermal expansion coefficient, and a second region 62 located on the surface opposite to first region 61, including a second surface 6b, and having a third thermal expansion coefficient. It is preferable that first surface 6a and second surface 6b have the same thermal expansion coefficient within each plane. The boundary between first region 61 and second region 62 does not have to be flat. FIG. 2 is an enlarged explanatory view for explaining region X shown in FIG. 1.

[0026] In stiffener 6, the absolute value of the difference between the thermal expansion coefficient of wiring board 11 (defined as the first thermal expansion coefficient) and the second thermal expansion coefficient is smaller than the absolute value of the difference between the first thermal expansion coefficient and the third thermal expansion coefficient. By using such a stiffener 6, stress generated in the region between electronic component 7 and stiffener 6 (edge ​​portion of stiffener 6) is reduced. As a result, cracks are less likely to occur even when used repeatedly in high-temperature and low-temperature environments.

[0027] The stiffener 6 may have a single-layer structure or a multi-layer structure as shown in Fig. 2, provided that it has a structure including a first region 61 and a second region 62. When the stiffener 6 has a single-layer structure, it may have a structure in which the thermal expansion coefficient changes from the first region 61 to the second region 62.

[0028] The thermal expansion coefficients of stiffener 6 are not limited as long as they satisfy the above-described relationship, and for example, the second thermal expansion coefficient may be greater than the first thermal expansion coefficient and less than the third thermal expansion coefficient. That is, the thermal expansion coefficient of second region 62 of stiffener 6 (third thermal expansion coefficient) may be the greatest, and the thermal expansion coefficient of wiring board 11 (first thermal expansion coefficient) may be the smallest. When the thermal expansion coefficients satisfy such a relationship, stress generated in the region between electronic component 7 and stiffener 6 is further reduced while suppressing an increase in warpage of stiffened wiring board 1.

[0029] The first thermal expansion coefficient of the wiring substrate 11 is, for example, 10 ppm / °C or more and 20 ppm / °C or less. The second thermal expansion coefficient of the first region 61 of the stiffener 6 is, for example, 10 ppm / °C or more and 25 ppm / °C or less. The third thermal expansion coefficient of the second region 62 of the stiffener 6 is, for example, 15 ppm / °C or more and 30 ppm / °C or less.

[0030] There are no limitations on the material of the stiffener 6 as long as it satisfies the above-mentioned relationship of thermal expansion coefficients. When the stiffener 6 has a single-layer structure, for example, a metal material that has been heat-treated on only one side is used, and the material is processed so that the thermal expansion coefficient changes from the second to the third thermal expansion coefficient from the first surface 6a to the second surface 6b.

[0031] On the other hand, when the stiffener 6 has a multilayer structure, the material of the first region (first layer) 61 having the second thermal expansion coefficient may be, for example, a metal matrix composite material, an aluminum alloy material, or a ceramic material. An example of a metal matrix composite material is a composite material (AlSiC) in which fine silicon carbide (SiC) is dispersed in an aluminum alloy. An example of a material of the second region (second layer) 62 having the third thermal expansion coefficient may be a metal such as copper. The thickness of the first region (first layer) 61 is 0.2 mm or more and 2 mm or less, and the thickness of the second region (second layer) 62 is 0.2 mm or more and 2 mm or less.

[0032] The absolute value of the difference between the first and second thermal expansion coefficients may be, for example, 10 ppm / °C or less, and is preferably closer to 0. If the absolute value of the difference between the first and second thermal expansion coefficients is 20 ppm / °C or less, the stress generated in the region between the electronic component 7 and the stiffener 6 is further reduced while suppressing an increase in warpage of the stiffener-equipped wiring board 1.

[0033] The stiffener 6 is positioned on the upper surface of the wiring board 11 via, for example, solder, adhesive, etc. Among these, when it is positioned via solder, it is possible to reduce warping and stress while , electric This can improve the heat dissipation of heat generated when the electronic components 7 are mounted or when the electronic component mounting structure is in operation. Furthermore, when the stiffener 6 has a multi-layer structure, the layers are bonded together, for example, via solder, adhesive, or the like. Among these, bonding via solder can improve the heat dissipation of heat generated when the electronic components 7 are mounted or when the electronic component mounting structure is in operation. On the other hand, when bonding via solder, the first region (first layer) must be made of a metal that can be bonded to the solder. For this reason, ceramic materials are not suitable, and the material used for bonding should be selected appropriately depending on the situation.

[0034] When stiffener 6 has a multi-layer structure, it may be a two-layer structure consisting of a first region (first layer) 61 and a second region (second layer) 62, or it may be a layer structure of three or more layers with at least one layer located between first region (first layer) 61 and second region (second layer) 62. When stiffener 6 has a layer structure of three or more layers, it is preferable that the thermal expansion coefficient of each layer decreases from the third thermal expansion coefficient to the second thermal expansion coefficient.

[0035] The second surface of stiffener 6 may have a fin shape. By having the second surface of stiffener 6 have a fin shape, it is possible to improve the heat dissipation properties of heat generated when electronic components 7 are mounted or when the electronic component mounting structure is in operation. A fin shape refers to, for example, a plurality of linear protrusions provided on the upper surface of stiffener 6.

[0036] The above-described stiffener-equipped wiring board 1 is formed, for example, as follows. First, a first insulating layer 21 is prepared. Through-holes are formed in the first insulating layer 21 by drilling, blasting, or laser processing. Next, conductor layers 4 and insulating layers are alternately laminated on the upper surface 211 and lower surface 212 of the first insulating layer 21. When forming the conductor layer 4 on the surface of the first insulating layer 21 by copper plating using, for example, a semi-additive method, the through-hole conductors may be formed in the through-holes, or the through-hole conductors may be formed in the through-holes in advance. The method for forming the conductor layer 4 and the through-hole conductors is as described above, and a detailed description thereof will be omitted.

[0037] The insulating layer is formed by applying a film made of a resin such as epoxy resin, bismaleimide-triazine resin, polyimide resin, or polyphenylene ether resin under vacuum and then thermally curing it. Next, the insulating layer is laser processed to form a via hole with the conductor layer 4 at the bottom. After the laser processing, a desmear process is performed to remove carbides and other impurities, improving the adhesion strength between the via hole and the via-hole conductor. When the conductor layer 4 is formed on the surface of the insulating layer, a via-hole conductor is formed in the via hole using plated metal.

[0038] By repeating the steps of forming the conductor layer 4 and the insulating layer, the desired number of conductor layers 4 and insulating layers can be formed. Of the insulating layers stacked on the upper surface 211 side, the outermost insulating layer is referred to as the second insulating layer 22, and of the insulating layers stacked on the lower surface 212 side, the outermost insulating layer is referred to as the third insulating layer 23. The conductor layer 4 formed on the surface of the third insulating layer 23 is referred to as the plain conductor layer 41.

[0039] Next, the surface of the second insulating layer 22 and the surface of the conductor layer 4 laminated on the outermost layer on the upper surface 211 side, as well as the surface of the third insulating layer 23 and the surface of the plain conductor layer 41, are covered with a solder resist 5. The solder resist 5 covering the upper surface 211 side has an opening 51 formed in an area that will become the mounting area 3. The solder resist 5 covering the lower surface 212 side has an opening 51 formed in an area that will become the mounting area 3. layer An opening 51 is formed to expose a part of 41 as an electrode.

[0040] Next, stiffener 6 is formed so as to surround the area that will become mounting area 3. Stiffener 6 is as described above, and detailed description thereof will be omitted.

[0041] In this way, a stiffener-equipped wiring board 1 according to one embodiment is obtained. In the stiffener-equipped wiring board 1, the absolute value of the difference between the thermal expansion coefficient of the wiring board 11 (defined as the first thermal expansion coefficient) and the second thermal expansion coefficient in the stiffener 6 is smaller than the absolute value of the difference between the first thermal expansion coefficient and the third thermal expansion coefficient. By using such a stiffener 6, stress generated in the region between the electronic component 7 and the stiffener 6 (the edge portion of the stiffener 6) is reduced. As a result, cracks are less likely to occur even when the stiffener-equipped wiring board 1 is used repeatedly in high-temperature and low-temperature environments.

[0042] Next, an electronic component mounting structure according to the present disclosure will be described. The electronic component mounting structure according to one embodiment includes a stiffener-equipped wiring board 1 and an electronic component 7 located in a mounting area 3. As described above, examples of the electronic component 7 include a semiconductor integrated circuit element and an optoelectronic element.

[0043] In an electronic component mounting structure according to one embodiment, the top of electronic component 7 may be located lower than second surface 6b of stiffener 6. If the top of electronic component 7 is located lower than second surface 6b of stiffener 6, the height of the electronic component mounting structure can be reduced and damage to electronic component 7 due to contact with the outside can be more easily prevented.

[0044] Next, stress simulation and warpage measurements were performed on the stiffener-equipped wiring board according to the present disclosure and on a stiffener-equipped wiring board outside the scope of the present disclosure. These measurements were performed on one of four equal cross-shaped sections of the stiffener-equipped wiring board.

[0045] The results of the stress simulation show that areas with concentrated stress are darker (blacker). Warpage was measured diagonally from the electronic component side to the corner of the board. The same applies to the stress simulation results and warpage measurement results for the corners below.

[0046] Figure 3 is a graph showing the results of a stress simulation at the corners and the results of a warpage simulation for a wiring board equipped with a copper stiffener (a conventional stiffener). This copper stiffener (2.5 mm thick) has a thermal expansion coefficient of approximately 17.6 ppm / °C and is placed on the top surface of the wiring board via an adhesive.

[0047] The results of the stress simulation show that the area between the electronic component 7 and the stiffener 6 (the edge of the stiffener 6) is dark, and that the generated stress is concentrated in this area. On the other hand, although this wiring board with a stiffener is warped, the warp converges to nearly zero at the edges (corners) of the wiring board. Therefore, although this wiring board with a stiffener can be mounted on a motherboard in terms of warp, in terms of stress, it is prone to cracking when used repeatedly in high and low temperature environments.

[0048] Figure 4 is a graph showing the results of a stress simulation and a warpage simulation for a wiring board with a stiffener, assuming that the stiffener has a thermal expansion coefficient of 20 ppm / °C (Young's modulus is set to the same as copper). The results of the stress simulation show that the area between the electronic component 7 and the stiffener 6 (the edge of the stiffener 6) is darker than the results shown in Figure 3, indicating that the generated stress is more concentrated in this area. It also shows that the warpage of the wiring board with a stiffener is in the opposite direction (positive direction) at the edge (corner) of the wiring board. Therefore, this wiring board with a stiffener cannot be mounted on a motherboard.

[0049] Figure 5 is a graph showing the results of a stress simulation and a warpage simulation for a corner of a wiring board with a stiffener, where the thermal expansion coefficient of the stiffener is assumed to be 15 ppm / °C (Young's modulus is set to the same as that of copper). The results of the stress simulation show that the area between the electronic component 7 and the stiffener 6 (the edge of the stiffener 6) is thinner than the results shown in Figure 3, and the stress generated is smaller than in Figure 3. However, the warpage of the wiring board with the stiffener is larger than in Figure 3, and it can be seen that it does not converge to near zero even at the edge (corner) of the wiring board.

[0050] Therefore, this wiring board with a stiffener cannot be mounted on a motherboard. Figures 4 and 5 above show that if the thermal expansion coefficient of the stiffener is made larger than that of copper, the correction force against warping will be greater, but the stress will increase. Also, if the thermal expansion coefficient of the stiffener is made smaller than that of copper, the stress will decrease, but the correction force against warping will be smaller.

[0051] 6 is a graph showing the results of a stress simulation at the corners and the results of a warpage simulation for a wiring board equipped with a stiffener made of AlSiC (SiC 40%) (a conventional stiffener). This AlSiC (SiC 40%) stiffener (thickness: 2.5 mm) has a thermal expansion coefficient of approximately 12.4 ppm / °C and is placed on the top surface of the wiring board via an adhesive.

[0052] The results of the stress simulation show that the area between the electronic component 7 and the stiffener 6 (the edge of the stiffener 6) is thinner than the results shown in Figure 3, and the stress generated is smaller than that shown in Figure 3. However, the warpage of the wiring board with the stiffener is larger than that shown in Figure 3, and it can be seen that the warpage increases toward the edges (corners) of the wiring board. Therefore, this wiring board with a stiffener cannot be mounted on a motherboard.

[0053] 7 is a graph showing the results of a stress simulation at the corners and the results of a warpage simulation for a wiring board equipped with a stiffener made of AlSiC (SiC 45%) (a conventional stiffener). This AlSiC (SiC 45%) stiffener (thickness: 2.5 mm) has a thermal expansion coefficient of approximately 10.5 ppm / °C and is located on the top surface of the wiring board via solder.

[0054] The results of the stress simulation show that the area between the electronic component 7 and the stiffener 6 (the edge of the stiffener 6) is thinner than the results shown in Figure 3, and the stress generated is smaller than that shown in Figure 3. However, the wiring board with the stiffener warps significantly, and the warpage increases toward the edges (corners) of the wiring board. Therefore, this wiring board with the stiffener cannot be mounted on a motherboard. Figures 6 and 7 show that as the thermal expansion coefficient of the stiffener is reduced, the stress decreases, but the corrective force against the warpage also decreases.

[0055] 8 is a graph showing the results of a stress simulation at a corner and a warpage simulation for a stiffener-equipped wiring board with a copper lower layer and an AlSiC (SiC 40%) upper layer (a stiffener outside the scope of this disclosure). The thermal expansion coefficients of copper and AlSiC (SiC 40%) are as described above. This stiffener (2.5 mm thick) is bonded between the lower and upper layers with an adhesive, and is located on the top surface of the wiring board via the adhesive.

[0056] The results of the stress simulation show that the area between the electronic component 7 and the stiffener 6 (the edge of the stiffener 6) is thinner than the results shown in Figure 3, and the stress generated is smaller than that shown in Figure 3. However, it can be seen that the wiring board with the stiffener warps significantly, and the warping increases toward the edges (corners) of the wiring board. Therefore, this wiring board with the stiffener cannot be mounted on a motherboard.

[0057] 9 is a graph showing the results of a stress simulation at a corner and a warpage simulation for a stiffener-equipped wiring board with a copper lower layer and an AlSiC (SiC 45%) upper layer (a stiffener outside the scope of this disclosure). The thermal expansion coefficients of copper and AlSiC (SiC 45%) are as described above. This stiffener (2.5 mm thick) is bonded between the lower and upper layers with an adhesive, and is located on the top surface of the wiring board via the adhesive.

[0058] The stress simulation results show that the area between the electronic component 7 and the stiffener 6 (the edge of the stiffener 6) is thinner than the results shown in Figure 3, and the generated stress is smaller than that shown in Figure 3. However, the stiffener-equipped wiring board exhibits significant warpage, with the warpage increasing toward the edges (corners) of the wiring board. Therefore, this stiffener-equipped wiring board cannot be mounted on a motherboard. Figures 8 and 9 show that a two-layer structure with copper on the lower layer and a material (AlSiC) with a smaller thermal expansion coefficient than copper on the upper layer reduces stress compared to a copper-only structure, but the correction force against warpage is smaller. Furthermore, for materials with a smaller thermal expansion coefficient than copper, as the thermal expansion coefficient decreases, stress is further reduced, but the correction force against warpage becomes smaller, which is the same trend as in Figures 6 and 7.

[0059] 10 is a graph showing the results of a stress simulation at a corner and a warpage simulation for a stiffener-equipped wiring board (a stiffener according to the present disclosure) with a lower layer of AlSiC (SiC 40%) and an upper layer of copper. The thermal expansion coefficients of copper and AlSiC (SiC 40%) are as described above. This stiffener (2.5 mm thick) is bonded between the lower and upper layers with an adhesive, and is positioned on the top surface of the wiring board via the adhesive.

[0060] The results of the stress simulation show that the region between the electronic component 7 and the stiffener 6 (the edge of the stiffener 6) is thinner than the results shown in FIG. 3, and the stress generated is smaller than that shown in FIG. 3. Furthermore, although this wiring board with a stiffener is warped, the warpage converges to nearly zero at the edges (corners) of the wiring board, just like the wiring board with a stiffener that uses a copper stiffener shown in FIG. 3. Therefore, this wiring board with a stiffener can be mounted on a motherboard in terms of warpage.

[0061] 11 is a graph showing the results of a stress simulation of a corner and a warpage simulation for a stiffener-equipped wiring board (stiffener of the present disclosure) with a lower layer of AlSiC (SiC 45%) and an upper layer of copper. The thermal expansion coefficients of copper and AlSiC (SiC 45%) are as described above. This stiffener (2.5 mm thick) is solder-bonded between the lower and upper layers, and is located on the upper surface of the wiring board via solder.

[0062] The results of the stress simulation show that the region between the electronic component 7 and the stiffener 6 (the edge of the stiffener 6) is thinner than the results shown in Figure 3, and that the generated stress is smaller than that shown in Figure 3. Furthermore, although this stiffener-equipped wiring board warps, the warpage converges to nearly zero at the edges (corners) of the wiring board, just like the stiffener-equipped wiring board using a copper stiffener shown in Figure 3. Therefore, this stiffener-equipped wiring board can be mounted on a motherboard in terms of warpage. Figures 10 and 11 above show that by using a two-layer structure with copper on the upper layer and a material (AlSiC) with a smaller thermal expansion coefficient than copper on the lower layer, it is possible to reduce stress while suppressing an increase in warpage compared to a copper-only structure.

[0063] Fig. 12 is a graph showing the degree of stress relaxation for a stiffener-equipped wiring board equipped with a stiffener (stiffener of the present disclosure) having an upper layer of copper and a lower layer of AlSiC (SiC 40% and 45%). The graph shown in Fig. 12 shows the relative value of stress generated in a stiffener-equipped wiring board using a stiffener of the present disclosure, when the stress generated in the stiffener-equipped wiring board using the copper stiffener shown in Fig. 3 is set to 100. Stress is reduced more when AlSiC (SiC 45%), which has a smaller thermal expansion coefficient, is used.

[0064] As shown in FIG. 12, the stress generated in a stiffener-equipped wiring board having a stiffener (stiffener of the present disclosure) with a lower layer of AlSiC (SiC 40%) and an upper layer of copper is 90% of the stress generated in a stiffener-equipped wiring board using a copper stiffener, which shows a 10% reduction in the generated stress.

[0065] The stress generated in a stiffener-equipped wiring board having a stiffener (stiffener of the present disclosure) with a lower layer of AlSiC (SiC 45%) and an upper layer of copper is 85% of the stress generated in a stiffener-equipped wiring board using a copper stiffener, which shows a 15% reduction in the generated stress. [Explanation of symbols]

[0066] 1 Stiffener-equipped wiring board 11 Wiring board 21 First insulating layer 22 Second insulating layer 23 Third insulating layer 3. Implementation Area 4 Conductor Layer 41 Plane Conductor Layer 5 Solder resist 51 Aperture 6 Stiffna 61 1st area (1st layer) 62 2nd area (2nd layer) 6a 1st page 6b 2nd side 7. Electronic Components 8 Solder

Claims

1. A wiring board; a mounting area located on an upper surface of the wiring board; a stiffener located on the upper surface of the wiring board so as to surround the mounting area, the stiffener having a first surface facing the wiring board and a second surface located on the opposite side of the first surface; Including, the wiring substrate has a first thermal expansion coefficient; the stiffener has a multilayer structure including at least a first layer facing the wiring board, including the first surface, and having a second thermal expansion coefficient, and a second layer located on a surface opposite to the first layer, including the second surface, and having a third thermal expansion coefficient; the second coefficient of thermal expansion is greater than the first coefficient of thermal expansion and less than the third coefficient of thermal expansion; an absolute value of the difference between the first thermal expansion coefficient and the second thermal expansion coefficient is smaller than an absolute value of the difference between the first thermal expansion coefficient and the third thermal expansion coefficient; Wiring board with stiffener.

2. the stiffener has a layer structure of three or more layers including at least one third layer between the first layer and the second layer, a thermal expansion coefficient of each layer of the third layer is smaller than the third thermal expansion coefficient and larger than the second thermal expansion coefficient, and the thermal expansion coefficient decreases from the second layer side to the first layer side; The wiring board with a stiffener according to claim 1 .

3. 2. The wiring board with a stiffener according to claim 1, wherein an absolute value of a difference between the first thermal expansion coefficient and the second thermal expansion coefficient is 10 ppm / [deg.] C. or less.

4. 2. The wiring board with a stiffener according to claim 1, wherein the stiffener is located on the upper surface of the wiring board via solder.

5. 2. The wiring board with a stiffener according to claim 1, wherein the stiffener has a structure in which each layer is joined via solder.

6. The wiring board with stiffener according to claim 1 , wherein the second surface of the stiffener has a fin shape.

7. a wiring board with a stiffener according to any one of claims 1 to 6; an electronic component located in the mounting area; An electronic component mounting structure comprising:

8. The electronic component packaging structure according to claim 7 , wherein a top of the electronic component is located at a portion lower than the second surface of the stiffener.

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