Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device that can reduce a resistance value for conductive paths electrically connecting upper and lower substrates, and a method for manufacturing the semiconductor device.SOLUTION: A semiconductor device includes: a first semiconductor layer provided with a first active element; a first insulating layer covering the first semiconductor layer; a second semiconductor layer that is disposed on the first insulating layer and includes a second active element provided in each of a plurality of element formation regions delimited by element isolation regions; a second insulating layer covering the second semiconductor layer; and conductive plugs each embedded, via an insulating film, in a through-hole penetrating the second insulating layer from the second insulating layer. The element isolation region includes a separation groove separating the element formation regions from one another like islands, insulating films provided on side walls of the separation groove, and a conductive material embedded into inside of the insulating films in the separation groove.SELECTED DRAWING: Figure 31

Description

[Technical Field]

[0001] The technology according to the present disclosure (the present technology) relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Conventionally, a method for increasing element density in the vertical direction by stacking multiple substrates on which elements such as transistors are formed is known (see Patent Document 1). This method is characterized by the fact that the number of elements is increased to two or three planes with each stack, rather than using just one plane. When used for elements with limited area, it is possible to increase the number of elements and configure a complex circuit in a small area.

[0003] In image sensors, the pixel size is fixed, and the area of ​​the element formed for each pixel is limited by the pixel size. Therefore, the size of the element cannot be freely changed, and there is a limit to increasing the number of elements to make the circuit more complex. Therefore, for devices with limited element area such as image sensors, increasing the element area by stacking multiple substrates is a very effective method. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-99582 Summary of the Invention [Problem to be solved by the invention]

[0005] In a stacked structure of multiple substrates, it is desirable to reduce the resistance of the conductive paths that electrically connect the upper and lower substrates.

[0006] The present technology aims to provide a semiconductor device capable of reducing the resistance value of a conductive path that electrically connects upper and lower substrates, and a method for manufacturing the same. [Means for solving the problem]

[0007] A semiconductor device according to one aspect of the present technology includes a first semiconductor layer having a plurality of element formation regions arranged adjacent to each other via an element isolation region, each having a first active element provided therein; a contact region provided on the element isolation region side of the surface layer of each of the plurality of element formation regions; a conductive pad connected to each of the contact regions of the plurality of element formation regions across the element isolation region; a first insulating layer covering the first semiconductor layer and the conductive pad; a second semiconductor layer arranged on the first insulating layer and having a second active element provided therein; a second insulating layer covering the second semiconductor layer; and a conductive plug embedded in a connection hole extending from the second insulating layer to the conductive pad, and formed integrally with the conductive pad using the same material.

[0008] a step of forming a contact region on the surface of each of the plurality of element formation regions adjacent to each other via the element isolation region, the step of forming a pad core on the contact region of each of the plurality of element formation regions via an etching stopper film across the element isolation region, the step of forming a first active element in each of the plurality of element formation regions, the step of forming a first insulating layer covering the first semiconductor layer and the pad core, the step of arranging a second semiconductor layer on the first insulating layer, the step of forming a second active element in the second semiconductor layer by performing a process including a heat treatment, the step of forming a second insulating layer covering the second semiconductor layer, the step of forming a connection hole from the second insulating layer to reach the pad core, the step of removing the pad core and the etching stopper film through the connection hole to form a space portion communicating with the connection hole, and the step of filling the space portion and the connection hole with a conductive material to form a conductive pad connected to the contact region and a conductive plug integral with the conductive pad. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram illustrating an outline of a solid-state imaging device according to a first embodiment of the present technology. [Figure 2]1 is an equivalent circuit diagram of a pixel unit of a solid-state imaging device according to a first embodiment of the present technology. [Figure 3] 3 is a diagram showing an arrangement of contact regions in a pixel unit of a solid-state imaging device according to a first embodiment of the present technology. FIG. [Figure 4] 1 is a cross-sectional view of a main part of a pixel unit of a solid-state imaging device according to a first embodiment of the present technology. [Figure 5] 3A to 3C are cross-sectional views illustrating steps in a method for manufacturing a solid-state imaging device according to a first embodiment of the present technology. [Figure 6] 6A to 6C are cross-sectional views illustrating steps subsequent to FIG. 5 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 7] 7A to 7C are cross-sectional views illustrating steps subsequent to FIG. 6 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 8] 8A to 8C are cross-sectional views illustrating steps subsequent to FIG. 7 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 9] 9A to 9C are cross-sectional views illustrating steps subsequent to FIG. 8 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 10] 10A to 10C are cross-sectional views illustrating steps subsequent to FIG. 9 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 11] 11A to 11C are cross-sectional views illustrating steps subsequent to FIG. 10 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 12] 12A to 12C are cross-sectional views illustrating steps subsequent to FIG. 11 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 13] 13A to 13C are cross-sectional views illustrating steps subsequent to FIG. 12 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 14] 14A to 14C are cross-sectional views illustrating steps subsequent to FIG. 13 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 15] 15A to 15C are cross-sectional views illustrating steps subsequent to FIG. 14 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 16] 16A to 16C are cross-sectional views illustrating steps subsequent to FIG. 15 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 17]17A to 17C are cross-sectional views illustrating steps subsequent to FIG. 16 in the method for manufacturing the solid-state imaging device according to the first embodiment of the present technology. [Figure 18] 10 is a cross-sectional view of a main part of a pixel unit of a solid-state imaging device according to a second embodiment of the present technology. FIG. [Figure 19] 6A to 6C are cross-sectional views illustrating steps in a method for manufacturing a solid-state imaging device according to a second embodiment of the present technology. [Figure 20] 20A to 20C are cross-sectional views illustrating steps subsequent to FIG. 19 in the method for manufacturing the solid-state imaging device according to the second embodiment of the present technology. [Figure 21] 21A to 21C are cross-sectional views illustrating steps subsequent to FIG. 20 in the method for manufacturing the solid-state imaging device according to the second embodiment of the present technology. [Figure 22] 22A to 22D are cross-sectional views illustrating steps subsequent to FIG. 21 in the method for manufacturing the solid-state imaging device according to the second embodiment of the present technology. [Figure 23] 23A to 23C are cross-sectional views illustrating steps subsequent to FIG. 22 in the method for manufacturing the solid-state imaging device according to the second embodiment of the present technology. [Figure 24] 24A to 24C are cross-sectional views illustrating steps subsequent to FIG. 23 in the method for manufacturing the solid-state imaging device according to the second embodiment of the present technology. [Figure 25] 25A to 25C are cross-sectional views illustrating steps subsequent to FIG. 24 in the method for manufacturing the solid-state imaging device according to the second embodiment of the present technology. [Figure 26] 10 is a cross-sectional view of a main part of a pixel unit of a solid-state imaging device according to a third embodiment of the present technology. FIG. [Figure 27] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a solid-state imaging device according to a third embodiment of the present technology. [Figure 28] 28A to 28D are cross-sectional views illustrating steps subsequent to FIG. 27 in the method for manufacturing the solid-state imaging device according to the third embodiment of the present technology. [Figure 29] 29A to 29C are cross-sectional views illustrating steps subsequent to FIG. 28 in the method for manufacturing the solid-state imaging device according to the third embodiment of the present technology. [Figure 30] 10 is a plan view of a main part of a pixel unit of a solid-state imaging device according to a fourth embodiment of the present technology. FIG. [Figure 31] 31 is a cross-sectional view of a main part showing a cross-sectional structure taken along the AA cutting line in FIG. 30. FIG. [Figure 32]10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a solid-state imaging device according to a fourth embodiment of the present technology. [Figure 33] 33A to 33C are cross-sectional views illustrating steps subsequent to FIG. 32 in the method for manufacturing the solid-state imaging device according to the fourth embodiment of the present technology. [Figure 34] 34A to 34C are cross-sectional views illustrating steps subsequent to FIG. 33 in the method for manufacturing the solid-state imaging device according to the fourth embodiment of the present technology. [Figure 35] 35A to 35C are cross-sectional views illustrating steps subsequent to FIG. 34 in the method for manufacturing the solid-state imaging device according to the fourth embodiment of the present technology. [Figure 36] 36A to 36C are cross-sectional views illustrating steps subsequent to FIG. 35 in the method for manufacturing the solid-state imaging device according to the fourth embodiment of the present technology. [Figure 37] 13 is a cross-sectional view of a main part of a pixel unit of a solid-state imaging device according to a fifth embodiment of the present technology. FIG. [Figure 38] 10A to 10C are cross-sectional views illustrating steps in a method for manufacturing a solid-state imaging device according to a fifth embodiment of the present technology. [Figure 39] 39A to 39C are cross-sectional views illustrating steps subsequent to FIG. 38 in the method for manufacturing the solid-state imaging device according to the fifth embodiment of the present technology. [Figure 40] 40A to 40C are cross-sectional views illustrating steps subsequent to FIG. 39 in the method for manufacturing the solid-state imaging device according to the fifth embodiment of the present technology. [Figure 41] 41A to 41C are cross-sectional views illustrating steps subsequent to FIG. 40 in the method for manufacturing the solid-state imaging device according to the fifth embodiment of the present technology. [Figure 42] 42A to 42D are cross-sectional views illustrating steps subsequent to FIG. 41 in the method for manufacturing the solid-state imaging device according to the fifth embodiment of the present technology. [Figure 43] 43A to 43C are cross-sectional views illustrating steps subsequent to FIG. 42 in the method for manufacturing the solid-state imaging device according to the fifth embodiment of the present technology. [Figure 44] 44A to 44C are cross-sectional views illustrating steps subsequent to FIG. 43 in the method for manufacturing the solid-state imaging device according to the fifth embodiment of the present technology. [Figure 45] 45A to 45C are cross-sectional views illustrating steps subsequent to FIG. 44 in the method for manufacturing the solid-state imaging device according to the fifth embodiment of the present technology. [Figure 46] 13 is a cross-sectional view of a main part of a pixel unit of a solid-state imaging device according to a sixth embodiment of the present technology. FIG. [Figure 47]FIG. 13 is a diagram showing a modified example of the sixth embodiment. [Figure 48] FIG. 13 is a block diagram illustrating an example of the functional configuration of an imaging device according to a seventh embodiment. [Figure 49] FIG. 49 is a plan view showing a schematic configuration of the imaging device shown in FIG. 48. [Figure 50] FIG. 50 is a schematic diagram showing a cross-sectional configuration taken along line III-III' shown in FIG. 49. [Figure 51] FIG. 49 is an equivalent circuit diagram of the pixel sharing unit shown in FIG. 48. [Figure 52] 10 is a diagram illustrating an example of a connection mode between a plurality of pixel sharing units and a plurality of vertical signal lines. FIG. [Figure 53] FIG. 51 is a cross-sectional view showing an example of a specific configuration of the imaging device shown in FIG. 50. [Figure 54A] 54 is a schematic diagram illustrating an example of a planar configuration of a main part of the first substrate shown in FIG. 53. FIG. [Figure 54B] 54B is a schematic diagram showing the planar configuration of the pad section together with the main part of the first substrate shown in FIG. 54A. FIG. [Figure 55] 54 is a schematic diagram illustrating an example of a planar configuration of the second substrate (semiconductor layer) shown in FIG. 53. FIG. [Figure 56] 54 is a schematic diagram showing an example of a planar configuration of the pixel circuit and the main part of the first substrate together with the first wiring layer shown in FIG. 53. FIG. [Figure 57] 54 is a schematic diagram illustrating an example of a planar configuration of the first wiring layer and the second wiring layer illustrated in FIG. 53. FIG. [Figure 58] 54 is a schematic diagram illustrating an example of a planar configuration of the second wiring layer and the third wiring layer illustrated in FIG. 53. FIG. [Figure 59] 54 is a schematic diagram illustrating an example of a planar configuration of the third wiring layer and the fourth wiring layer illustrated in FIG. 53. FIG. [Figure 60] FIG. 51 is a schematic diagram for explaining the path of an input signal to the imaging device shown in FIG. 50. [Figure 61] FIG. 51 is a schematic diagram for explaining the signal path of pixel signals in the imaging device shown in FIG. 50. [Figure 62]FIG. 56 is a schematic diagram illustrating a modified example of the planar configuration of the second substrate (semiconductor layer) shown in FIG. [Figure 63] 63 is a schematic diagram showing the planar configuration of the pixel circuit shown in FIG. 62 as well as the main parts of the first wiring layer and the first substrate. [Figure 64] FIG. 64 is a schematic diagram showing an example of the planar configuration of the second wiring layer together with the first wiring layer shown in FIG. 63. [Figure 65] FIG. 65 is a schematic diagram showing an example of the planar configuration of the third wiring layer together with the second wiring layer shown in FIG. 64. [Figure 66] FIG. 66 is a schematic diagram showing an example of the planar configuration of the fourth wiring layer together with the third wiring layer shown in FIG. 65. [Figure 67] FIG. 54B is a schematic diagram illustrating a modified example of the planar configuration of the first substrate shown in FIG. 54A. [Figure 68] 68 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) laminated on the first substrate shown in FIG. 67. FIG. [Figure 69] FIG. 69 is a schematic diagram showing an example of the planar configuration of the first wiring layer together with the pixel circuit shown in FIG. 68. [Figure 70] FIG. 70 is a schematic diagram showing an example of the planar configuration of the second wiring layer together with the first wiring layer shown in FIG. 69. [Figure 71] 71 is a schematic diagram showing an example of the planar configuration of the third wiring layer together with the second wiring layer shown in FIG. 70. FIG. [Figure 72] 72 is a schematic diagram showing an example of the planar configuration of the fourth wiring layer together with the third wiring layer shown in FIG. 71. FIG. [Figure 73] FIG. 68 is a schematic diagram illustrating another example of the planar configuration of the first substrate shown in FIG. 67. [Figure 74] 74 is a schematic diagram showing an example of a planar configuration of a second substrate (semiconductor layer) laminated on the first substrate shown in FIG. 73. FIG. [Figure 75] FIG. 75 is a schematic diagram showing an example of the planar configuration of the first wiring layer together with the pixel circuit shown in FIG. 74. [Figure 76] FIG. 76 is a schematic diagram showing an example of the planar configuration of the second wiring layer together with the first wiring layer shown in FIG. 75. [Figure 77]FIG. 77 is a schematic diagram showing an example of the planar configuration of the third wiring layer together with the second wiring layer shown in FIG. 76. [Figure 78] FIG. 78 is a schematic diagram showing an example of the planar configuration of the fourth wiring layer together with the third wiring layer shown in FIG. 77. [Figure 79] 51 is a cross-sectional view showing another example of the imaging device shown in FIG. 50. FIG. [Figure 80] FIG. 80 is a schematic diagram for explaining the path of an input signal to the imaging device shown in FIG. 79. [Figure 81] FIG. 80 is a schematic diagram for explaining the signal paths of pixel signals in the imaging device shown in FIG. 79. [Figure 82] FIG. 54 is a cross-sectional view illustrating another example of the imaging device shown in FIG. 53. [Figure 83] FIG. 52 is a diagram illustrating another example of the equivalent circuit shown in FIG. 51. [Figure 84] FIG. 54B is a schematic plan view illustrating another example of the pixel separating portion shown in FIG. 54A etc. [Figure 85] FIG. 1 is a diagram illustrating an example of a schematic configuration of an imaging system including an imaging device according to the above embodiment and its modified example. [Figure 86] FIG. 86 is a diagram illustrating an example of an imaging procedure of the imaging system shown in FIG. 85. [Figure 87] 1 is a block diagram showing an example of a schematic configuration of a vehicle control system; [Figure 88] FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit. [Figure 89] FIG. 1 is a diagram illustrating an example of a schematic configuration of an endoscopic surgery system. [Figure 90] FIG. 2 is a block diagram showing an example of the functional configuration of a camera head and a CCU. [Figure 91A] 13 is a cross-sectional view of a main part of a pixel unit of a solid-state imaging device according to an eighth embodiment of the present technology. FIG. [Figure 91B] FIG. 91B is an enlarged cross-sectional view of a main part of FIG. 91A. [Figure 91C] 13A and 13B are diagrams showing the arrangement of contact regions and the shape of conductive pads in a pixel unit of a solid-state imaging device according to an eighth embodiment of the present technology. [Figure 92] 13A to 13C are cross-sectional views illustrating steps in a method for manufacturing a solid-state imaging device according to an eighth embodiment of the present technology. [Figure 93] 93A to 93C are cross-sectional views illustrating steps subsequent to FIG. 92 in the method for manufacturing the solid-state imaging device according to the eighth embodiment of the present technology. [Figure 94] 94A to 94C are cross-sectional views illustrating steps subsequent to FIG. 93 in the method for manufacturing the solid-state imaging device according to the eighth embodiment of the present technology. [Figure 95] 95A to 95C are cross-sectional views illustrating steps subsequent to FIG. 94 in the method for manufacturing the solid-state imaging device according to the eighth embodiment of the present technology. [Figure 96] 96 is a cross-sectional view illustrating a process subsequent to FIG. 95 in the method for manufacturing a solid-state imaging device according to the eighth embodiment of the present technology. [Figure 97] 97A to 97C are cross-sectional views illustrating steps subsequent to FIG. 96 in the method for manufacturing the solid-state imaging device according to the eighth embodiment of the present technology. [Figure 98] 98A to 98C are cross-sectional views illustrating steps subsequent to FIG. 97 in the method for manufacturing the solid-state imaging device according to the eighth embodiment of the present technology. [Figure 99] 99A to 99C are cross-sectional views illustrating steps subsequent to FIG. 98 in the method for manufacturing the solid-state imaging device according to the eighth embodiment of the present technology. [Figure 100] 99A to 99C are cross-sectional views illustrating steps in the manufacturing method of the solid-state imaging device according to the eighth embodiment of the present technology. [Figure 101] FIG. 13 is a diagram showing a first modified example of the eighth embodiment. [Figure 102] FIG. 13 is a diagram showing a second modified example of the eighth embodiment. [Figure 103] 13 is a cross-sectional view of a main part of a pixel unit of a solid-state imaging device according to a ninth embodiment of the present technology. FIG. [Figure 104] 19 is a cross-sectional view in the thickness direction showing an example of the configuration of an imaging device according to a tenth embodiment of the present technology. FIG. [Figure 105] 19 is a cross-sectional view in the thickness direction showing an example of the configuration of an imaging device according to a tenth embodiment of the present technology. FIG. [Figure 106] 19 is a cross-sectional view in the thickness direction showing an example of the configuration of an imaging device according to a tenth embodiment of the present technology. FIG. [Figure 107]FIG. 23 is a horizontal cross-sectional view showing an example of the layout of a plurality of pixel units according to a tenth embodiment of the present technology. [Figure 108] FIG. 23 is a horizontal cross-sectional view showing an example of the layout of a plurality of pixel units according to a tenth embodiment of the present technology. [Figure 109] FIG. 23 is a horizontal cross-sectional view showing an example of the layout of a plurality of pixel units according to a tenth embodiment of the present technology. [Figure 110] 19 is a cross-sectional view in the thickness direction showing a modified example of the imaging device according to the tenth embodiment of the present technology. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, first to tenth embodiments of the present technology will be described with reference to the drawings. In the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that there are parts in which the dimensional relationships and ratios differ between the drawings. Note that the effects described in this specification are merely examples and are not limited to the present invention, and other effects may also be present.

[0011] (First embodiment) <Configuration of solid-state imaging device> As a solid-state imaging device according to a first embodiment of the present technology, a back-illuminated CMOS image sensor (solid-state imaging device) is exemplified. As shown in Fig. 1, the solid-state imaging device 1A according to the first embodiment of the present technology includes a first substrate unit (first floor unit) 10, a second substrate unit (second floor unit) 20, and a third substrate unit (third floor unit) 30. The solid-state imaging device 1A has a three-dimensional structure in which the first substrate unit 10, the second substrate unit 20, and the third substrate unit 30 are stacked in this order.

[0012] The first substrate unit 10 has a plurality of sensor pixels 12 that perform photoelectric conversion in a semiconductor layer 701. The plurality of sensor pixels 12 are arranged in a matrix within a pixel region 13 of the first substrate unit 10. The second substrate unit 20 has a readout circuit 22 for every four sensor pixels 12, which outputs a pixel signal based on the charge output from the sensor pixels 12. The second substrate unit 20 has a plurality of pixel drive lines 23 extending in the row direction and a plurality of vertical signal lines 24 extending in the column direction. The third substrate unit 30 may also be called a bottom substrate.

[0013] The third substrate unit 30 has a logic circuit 32 that processes pixel signals. The logic circuit 32 has, for example, a vertical drive circuit 33, a column signal processing circuit 34, a horizontal drive circuit 35, and a system control circuit 36. The logic circuit 32 (specifically, the horizontal drive circuit 35) outputs an output voltage Vout for each sensor pixel 12 to the outside. In the logic circuit 32, for example, a low-resistance region made of silicide formed using a salicide (self-aligned silicide) process such as CoSi2 or NiSi may be formed on the surface of an impurity diffusion region (semiconductor region) that contacts the source electrode and the drain electrode.

[0014] The vertical drive circuit 33, for example, sequentially selects a plurality of sensor pixels 12 row by row. The column signal processing circuit 34, for example, performs correlated double sampling (CDS) processing on pixel signals output from each sensor pixel 12 in the row selected by the vertical drive circuit 33. The column signal processing circuit 34 extracts signal levels of the pixel signals by performing CDS processing, for example, and holds pixel data corresponding to the amount of light received by each sensor pixel 12. The horizontal drive circuit 35, for example, sequentially outputs the pixel data held in the column signal processing circuit 34 to the outside. The system control circuit 36, for example, controls the driving of each block (the vertical drive circuit 33, the column signal processing circuit 34, and the horizontal drive circuit 35) in the logic circuit 32.

[0015] Fig. 2 is an equivalent circuit diagram showing a configuration example of a pixel unit PU of a solid-state imaging device 1A according to the first embodiment of the present technology. As shown in Fig. 2, in the solid-state imaging device 1A, four sensor pixels 12 are electrically connected to one readout circuit 22 to configure one pixel unit PU. The four sensor pixels 12 share one readout circuit 22, and the outputs of the four sensor pixels 12 are input to the shared readout circuit 22.

[0016] The sensor pixels 12 have common components. In Fig. 2, in order to distinguish the components of the sensor pixels 12 from one another, identification numbers (1, 2, 3, 4) are added to the end of the reference numerals (e.g., PD, TG, FD, which will be described later) of the components of the sensor pixels 12. Hereinafter, when it is necessary to distinguish the components of the sensor pixels 12 from one another, identification numbers are added to the end of the reference numerals of the components of the sensor pixels 12. However, when it is not necessary to distinguish the components of the sensor pixels 12 from one another, the identification numbers at the end of the reference numerals of the components of the sensor pixels 12 are omitted.

[0017] Each sensor pixel 12 includes, for example, a photodiode PD (an example of a photoelectric conversion element), a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD that temporarily holds the charge output from the photodiode PD via the transfer transistor TR. The photodiode PD performs photoelectric conversion to generate a charge according to the amount of light received. The cathode region of the photodiode PD is electrically connected to the source region of the transfer transistor TR, and the anode region of the photodiode PD is electrically connected to a reference potential line (e.g., ground). The drain region of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate electrode of the transfer transistor TR is electrically connected to a pixel drive line 23. The transfer transistor TR is, for example, a complementary metal oxide semiconductor (CMOS) transistor. The floating diffusion FD is formed by an n-type contact region 705 (see FIG. 4), which will be described later.

[0018] The floating diffusions FD of the sensor pixels 12 that share one readout circuit 22 are electrically connected to each other and to the input terminal of the common readout circuit 22. The readout circuit 22 includes, for example, an amplification transistor AMP (an example of a first transistor), a reset transistor RST, and a selection transistor SEL (an example of a second transistor). Note that the selection transistor SEL may be omitted if necessary.

[0019] The source region of the reset transistor RST (the input terminal of the readout circuit 22) is electrically connected to the floating diffusion FD, and the drain region of the reset transistor RST is electrically connected to the power supply line VDD and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a pixel drive line 23 (see FIG. 1). The source region of the amplifier transistor AMP is electrically connected to the drain region of the select transistor SEL, and the gate electrode of the amplifier transistor AMP is electrically connected to the source region of the reset transistor RST. The source region of the select transistor SEL (the output terminal of the readout circuit 22) is electrically connected to a vertical signal line 24, and the gate electrode of the select transistor SEL is electrically connected to the pixel drive line 23 (see FIG. 1).

[0020] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. For example, as shown in FIG. 4 (described later), the gate electrode 710 of the transfer transistor TR extends from the surface of the semiconductor layer 701 through the well region 704 to a depth reaching the photodiode PD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The select transistor SEL controls the output timing of the pixel signal from the readout circuit 22.

[0021] The amplification transistor AMP generates a pixel signal having a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplification transistor AMP constitutes a source follower amplifier and outputs a pixel signal having a voltage corresponding to the level of the charge generated in the photodiode PD. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the column signal processing circuit 34 via the vertical signal line 24. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, CMOS transistors.

[0022] FIG. 3 is a diagram showing the arrangement of contact regions in a pixel unit of a solid-state imaging device according to a first embodiment of the present technology. FIG. 4 is a cross-sectional view of a main part of a pixel unit of a solid-state imaging device according to a first embodiment of the present technology. Note that the cross-sectional view of the main part shown in FIG. 4 is merely a schematic view and is not intended to accurately show the actual structure. In the cross-sectional view of the main part shown in FIG. 4, the horizontal positions of the transistors and impurity diffusion regions (semiconductor regions) are intentionally changed in order to easily explain the configuration of the solid-state imaging device 1A on paper. Also, in FIG. 4, the third substrate portion is not shown.

[0023] 4, a second substrate unit 20 is laminated on one of the surfaces, that is, the main surface (front surface), of a first substrate unit (bottom substrate) 10. Then, although not shown, a third substrate unit 20 is laminated on one of the surfaces, that is, the main surface, of the second substrate unit 20.

[0024] The first substrate unit 10 has a semiconductor layer 701 as a first semiconductor layer and an insulating layer 720 as a first insulating layer covering the semiconductor layer 701. The back surface of the first substrate unit 10, which is the surface opposite to the one surface, is an incident surface. A planarization film 831, a color filter 832, a microlens 833, and the like are provided on the back surface side of the first substrate unit 10. The planarization film 831 flattens the back surface side of the first substrate unit 10. The microlens 833 collects light incident on the first substrate unit 10. The color filter 832 separates the light incident on the first substrate unit 10 into colors. The color filter 832 and the microlens 833 are each provided for each sensor pixel 12.

[0025] The semiconductor layer 701 has a plurality of island regions 703 as a plurality of element formation regions, each of which is disposed adjacent to one another in a plane with an element isolation region 702 interposed therebetween, and each of which is provided with a first active element. In the manufacturing process, the semiconductor layer 701 is formed by grinding the back surface side of the semiconductor substrate by, for example, a CMP method until the plurality of element formation regions partitioned by the element isolation regions 702 become individual island regions 703. A single-crystal silicon substrate of a first conductivity type (for example, n-type) is used as the semiconductor substrate. That is, each of the plurality of island regions 703 is mainly composed of the n-type semiconductor layer 701.

[0026] The element isolation region 702 electrically isolates adjacent island regions 703. The element isolation region 702 has, for example, an STI (Shallow Trench Isolation) structure and extends from the main surface of the semiconductor layer 701 in the depth direction.

[0027] One island region 703 corresponds to one sensor pixel 12. A well region 704 of a second conductivity type (e.g., p-type) is provided in a surface layer portion of the island region 703. An n-type photodiode PD is provided as a first active element in a region deeper than the well region 704. A transfer transistor TR is also provided as the first active element in the surface layer portion of the island region 703. Although not shown in detail, the transfer transistor TR has a gate insulating film 109 provided along the inner wall of a gate groove extending in the depth direction from the main surface of the island region 703, a T-shaped gate electrode 710 partially embedded in the gate groove via the gate insulating film 709 and partially protruding from the gate groove, and a source region and a drain region (not shown).

[0028] 3 and 4, an n-type contact region 705 is provided inside a well region 704 on the side of the element isolation region 702 in the surface layer portion of the island region 703. As shown in Fig. 3, the contact region 705 is provided in contact with a first intersection 702a located in the center of a pixel unit PU, each unit consisting of four sensor pixels 12, among intersections between the element isolation region 702 extending in the row direction and the element isolation region 702 extending in the column direction. The contact region 705 reduces ohmic contact resistance with a conductive pad 824a (described later) and shares a floating diffusion FD.

[0029] 3 and 4, a p-type contact region 706 having a higher impurity concentration than the well region 704 is provided inside the well region 704 on the side of the element isolation region 702 in the surface layer portion of the island region 703. As shown in Fig. 3, the contact region 706 is provided in contact with a second intersection 702b located at a corner of the pixel unit PU among the intersections of the element isolation region 702. The contact region 706 reduces ohmic contact resistance with a conductive pad 742b, which will be described later.

[0030] 4, at the center of the pixel unit PU, the above-mentioned conductive pad 824a is electrically and mechanically connected across the first intersection 702a of the element isolation region 702 to the contact region 705 of each of the four island regions 703 arranged via the first intersection 702a of the element isolation region 702. Also, at the corners of the pixel unit PU, the above-mentioned conductive pad 824b is electrically and mechanically connected across the second intersection 702b of the element isolation region 702 to the contact region 706 of each of the four island regions 703 arranged via the second intersection 702b of the element isolation region 702.

[0031] The insulating layer 720 is provided on the semiconductor layer 701 so as to cover the island region 703 and the conductive pads 824a and 824b. The first insulating layer 720 is formed of, for example, one of a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), or a silicon carbonitride film (SiCN), or a laminated film of two or more of these.

[0032] 4, the second substrate unit 20 has a semiconductor layer 801 as a second semiconductor layer, and an insulating layer 820 as a second insulating layer provided on the semiconductor layer 801. The second substrate unit 20 also has an insulating film 802 on the back surface of the semiconductor layer 801 opposite the insulating layer 820 side. The semiconductor layer 801 is disposed on the insulating layer 720 via the insulating film 802. The insulating film 802 is formed of, for example, a silicon oxide film, and is bonded to the underlying insulating layer 720.

[0033] 4, the solid-state imaging device 1A according to the first embodiment of the present technology further includes a conductive plug 823a that is embedded in a connection hole 821a that reaches from the surface of the insulating layer 820 to the surface of the conductive pad 824a and is formed integrally with the conductive pad 824a using the same material. The conductive pad 824a has a larger area than the conductive plug 823a when viewed in a plan view. The solid-state imaging device 1A according to the first embodiment of the present technology also includes a conductive plug 823b that is embedded in a connection hole 821b that reaches from the surface of the insulating layer 820 to the surface of the conductive pad 824b and is formed integrally with the conductive pad 824b using the same material. The conductive pad 824b has a larger area than the conductive plug 823b when viewed in a plan view. The conductive plug 823a and conductive pad 824a, as well as the conductive plug 823b and conductive pad 824b, can be made of high-melting point metal materials such as titanium (Ti), tungsten (W), cobalt (Co), molybdenum (Mo), etc., and tungsten (W) is used, for example.

[0034] The insulating layer 820 is provided with a contact hole 825a that extends from the surface of the insulating layer 820 to the surface of the gate electrode 806a on the island region 803a, a contact hole 825b that extends from the surface of the insulating layer 820 to the surface of the island region 803a, and a contact hole 825c that extends from the surface of the insulating layer 820 to the surface of the gate electrode 806b on the island region 803b. Conductive plugs 826a to 826c are embedded in these contact holes 825a to 825c. A high-melting-point metal material, such as tungsten (W), can be used for the conductive plugs 826a to 826c.

[0035] A wiring 827a is provided on the insulating layer 820, covering the conductive plugs 823a and 826a and electrically and mechanically connected to the conductive plugs 823a and 826a. A wiring 827b is provided on the insulating layer 820, covering the conductive plugs 826b and electrically and mechanically connected to the conductive plugs 826b. A wiring 827c is provided on the insulating layer 820, covering the conductive plugs 823b and 826c and electrically and mechanically connected to the conductive plugs 823b and 826c.

[0036] An insulating film 828 is provided on the insulating layer 820 so as to cover the wirings 827a to 827c. A wiring 829 is provided on the surface layer of the insulating film 828. The wirings 827a to 827c and the wiring 829 are made of a metal such as copper (Cu). The amplifier transistor AMP has a gate insulating film 205 formed on the main surface of the island region 803a, a gate electrode 806a provided on the gate insulating film 805, and source and drain regions formed in the surface layer of the island region 803a. The reset transistor RST has a gate insulating film 805 formed on the main surface of the island region 803b, a gate electrode 806b provided on the gate insulating film 805, and source and drain regions formed in the surface layer of the island region 803b.

[0037] The gate electrode 806a of the amplifier transistor AMP provided on the second substrate unit 20 is electrically connected to four contact regions 705 adjacent to the first intersection 702a of the element isolation region 702 on the lower first substrate unit 10 via a conductive path including a conductive plug 826a, a wiring 827a, a conductive plug 823a, and a conductive pad 824a. In this conductive path, the conductive plug 823a and the conductive pad 824a are integrally formed from the same material, resulting in one less heterojunction than when the conductive plug 823a is formed from, for example, a polycrystalline silicon film. Therefore, according to the solid-state imaging device 1A of the first embodiment, the resistance of the conductive path electrically connecting the gate electrode 806a of the amplifier transistor AMP provided on the upper second substrate unit 20 and the contact region 705 provided on the lower first substrate unit 10 can be reduced. Furthermore, the contact region 705 shares the floating diffusion FD, thereby increasing the operating speed of the pixel unit PU.

[0038] The island region 803b provided in the second substrate unit 20 is electrically connected to four contact regions 706 adjacent to the second intersection 702b of the element isolation region 702 in the lower first substrate unit 10 via a conductive path including a conductive plug 826c, a wiring 827c, a conductive plug 823b, and a conductive pad 824b. In this conductive path, the conductive plug 823b and the conductive pad 824b are integrally formed from the same material, so there is one less heterojunction than when the conductive plug 823b is formed from, for example, a polycrystalline silicon film. Therefore, according to the solid-state imaging device 1A of the first embodiment, it is possible to reduce the resistance of the conductive path electrically connecting the island region 803b provided in the upper second substrate unit 20 and the contact region 706 provided in the lower first substrate unit 10.

[0039] <Method of manufacturing a solid-state imaging device> Next, an example of a method for manufacturing the solid-state imaging device according to the first embodiment will be described with reference to FIGS. First, a semiconductor layer 701 made of a semiconductor substrate of single crystal silicon is prepared.

[0040] 5, an element isolation region 702 is formed on the main surface side of the semiconductor layer 701, and an island region 703 is formed as an element formation region surrounded and partitioned by the element isolation region 702. The element isolation region 702 is formed, for example, by forming an isolation trench extending in the depth direction from the main surface of the semiconductor layer 701 using well-known photolithography and anisotropic dry etching techniques, and then selectively filling the isolation trench with an insulating film. The filling with the insulating film is performed by forming, for example, a silicon oxide film by CVD over the entire main surface of the semiconductor layer 701, including the inside of the isolation trench, and then selectively removing the insulating film on the main surface of the semiconductor layer 701 by etch-back or CMP.

[0041] Next, using well-known photolithography, ion implantation, and heat treatment techniques, a p-type well region 704 and an n-type charge generation region (not shown) that constitute a photodiode are formed in the surface layer (upper portion) of the semiconductor layer 1. Through this process, a photodiode PD is formed in the island region 703.

[0042] 6, n-type contact regions 705 are formed on the surface of each of the island regions 703 adjacent to each other with the isolation region 702 interposed therebetween (on the side of the first intersection 702a), and p-type contact regions 706 are formed on the surface of each of the island regions 703 adjacent to each other with the isolation region 702 interposed therebetween (on the side of the second intersection 702b). The n-type contact regions 705 and the p-type contact regions 706 are formed every other one at the intersections between the isolation regions extending in the row direction and the isolation regions 702 extending in the column direction. The contact regions 705 and 706 are formed using well-known photolithography, ion implantation, and heat treatment techniques.

[0043] 7, a pad core 708a is formed on each of the n-type contact regions 705 of the four island regions 703 across the first intersection 702a of the isolation region 702, with an etching stopper film 707 interposed therebetween. A pad core 708b is also formed on each of the p-type contact regions 706 of the four island regions 703 across the second intersection 702b of the isolation region 702, with the etching stopper film 707 interposed therebetween. The etching stopper film 707 and the pad cores 708a, 708b are formed, for example, by forming a silicon oxide film and a polycrystalline silicon film in this order over the entire surface of the semiconductor layer 701, including the island regions 703 and the isolation region 702, by CVD, and then patterning the polycrystalline silicon film and the silicon oxide film in this order. The polycrystalline silicon film used is a non-doped type, in which no impurities that reduce resistance are introduced during or after deposition.

[0044] Next, a gate trench extending in the depth direction from the main surface of the semiconductor layer 701 is formed in the island region 703. Then, a thermal oxidation process is performed to form a gate insulating film 709 made of a thermally oxidized silicon film on the main surface of the semiconductor layer 701, including inside the gate trench. Then, a polycrystalline silicon film, for example, is formed as a gate electrode material by CVD on the entire surface of the gate insulating film 709, including inside the gate trench. Impurities that reduce resistance are introduced into the polycrystalline silicon film during or after deposition. The polycrystalline silicon film and gate insulating film 709 are then patterned in this order to form a T-shaped gate electrode 710, part of which is embedded in the gate trench via the gate insulating film 709, and the other part of which protrudes from the gate trench, as shown in FIG. 8 . This process forms a transfer transistor TR.

[0045] Next, as shown in FIG. 9, an insulating layer 720 as a first insulating layer is formed on the entire main surface of the semiconductor layer 701 so as to cover the gate electrode 710 and the pad cores 708a and 708b.

[0046] Next, a semiconductor layer 801 made of, for example, monocrystalline silicon is prepared as a second semiconductor layer. An insulating film 802 made of, for example, a silicon oxide film is provided on the back surface of the semiconductor layer 801 opposite to the main surface. Then, as shown in FIG. 10 , the semiconductor layer 801 is bonded to the main surface side of the semiconductor layer 701. Specifically, the insulating layer 720 on the main surface side of the semiconductor layer 701 and the insulating film 802 on the back surface side of the semiconductor layer 801 are placed face to face and in close contact with each other, and then heat treatment is performed. As a result, as shown in FIG. 10 , the insulating film 802 and the insulating layer 720 are integrated, and the upper semiconductor layer 801 and the lower semiconductor layer 701 are bonded to each other via the insulating film 802 and the insulating layer 720. The semiconductor layer 801 is also disposed on the insulating layer 720. Thereafter, the main surface side of the semiconductor layer 801 is ground by, for example, a CMP method to reduce the thickness of the semiconductor layer 801.

[0047] Next, the semiconductor layer 801 is patterned into a plurality of island regions 803 using well-known photolithography and anisotropic dry etching techniques, and then, as shown in Fig. 11, the spaces between the island regions 803 are filled with an insulating film 804. The filling with the insulating film 804 is performed, for example, by forming the insulating film 804 made of a silicon oxide film over the entire surface of the semiconductor layer 801, including on the island regions 803 and between the island regions 803, by a CVD method, and then selectively removing the insulating film 804 on the island regions 803 by an etch-back method or a CMP method.

[0048] Next, as shown in FIG. 12, an amplifier transistor AMP and a select transistor SEL (not shown) are formed as second active elements in the island region 803a of the multiple island regions 803, and a reset transistor RST is formed as a second active element in the island region 803b of the multiple island regions 803. To form these second active elements, the island region 803 is first subjected to thermal oxidation to form a gate insulating film 805 made of a thermally oxidized silicon film on the main surface of the island region 803. Then, a polycrystalline silicon film, for example, is formed as a gate electrode material over the entire surface of the gate insulating film 805 by CVD. Impurities are introduced into this polycrystalline silicon film during or after deposition to reduce resistance. The polycrystalline silicon film and the gate insulating film 705 are then patterned in this order to form gate electrodes 806a and 806b on the island regions 803a and 803b, with the gate insulating film 805 interposed therebetween. Then, impurities are ion-implanted into the island regions 803a and 803b using the gate electrodes 806a and 806b as masks. Then, the island regions 703a and 703b are subjected to a heat treatment (heat treatment to activate the impurities) to repair crystal defects caused by the ion implantation, thereby forming a source region and a drain region, whereby an amplifier transistor AMP and a select transistor SEL are formed in the island region 803a, and a reset transistor RST is formed in the island region 803b.

[0049] In this process, thermal oxidation and crystal defect recovery are performed in an atmosphere at a temperature of approximately 1000°C, but because the pad cores 708a and 708b are formed from non-doped polycrystalline silicon films, impurities do not diffuse from the pad cores 708a and 708b to the contact regions 705 and 706, preventing the expansion of the contact regions 705 and 706. In particular, because the contact region 705 shares the floating diffusion FD, charge accumulation in the contact region 705 can be stabilized.

[0050] Next, an insulating layer 820 is formed as a second insulating layer to cover the island regions 703a and 703b, and the surface of the insulating layer 820 is then planarized as shown in FIG.

[0051] 13, a connection hole 821a is formed from the surface of the insulating layer 820 to the surface of the pad core 708a, and a connection hole 821b is formed from the surface of the insulating layer 820 to the surface of the pad core 708b. These connection holes 821a and 821b are formed using well-known photolithography and anisotropic dry etching techniques.

[0052] 14, the pad core 708a and the etching stopper film 707 are removed through the connection hole 821a to form a space 822a communicating with the connection hole 821a, and the pad core 708b and the etching stopper film 707 are removed through the connection hole 821b to form a space 822b communicating with the connection hole 821a. The pad cores 708a and 708b are removed under etching conditions that are selective to the insulating layer 820, the insulating film 802, the insulating layer 720, and the etching stopper film 707. At this time, the surfaces of the contact regions 705 and 706 are slightly etched, but the reduction in thickness of the contact regions 705 and 706 can be suppressed compared to when the pad cores 708a and 708b are removed by etching without providing the etching stopper film 707.

[0053] 15, conductive material is embedded in the spaces 822a and 822b and the connection holes 821a and 821b to form conductive pads 824a and 824b connected to the contact regions 705 and 706, and conductive plugs 823a and 823b integrally formed with the same material as the conductive pads 824a and 824b. To form the conductive pads 824a and 824b and the conductive plugs 823a and 823b, first, a barrier metal film is formed along the inner walls of the connection holes 821a and 821b, the inner walls of the spaces 822a and 822b, and the surfaces of the contact regions 705 and 706, using, for example, a PVD method. The barrier metal film is formed of a composite film including a titanium (Ti) film and a titanium nitride (TiN) film from the bottom. The titanium film and titanium nitride film are formed to a thickness of, for example, several tens of nanometers. Then, a high-melting-point material such as a tungsten (W) film is formed by CVD so as to completely fill the interiors of the spaces 822a, 822b and the connection holes 821a, 821b. The tungsten film and barrier metal film are then etched back by dry etching such as RIE, thereby selectively removing the tungsten film and barrier metal film on the contact regions 705, 706 and on the insulating layer 820. This forms conductive pads 824a, 824b and conductive plugs 823a, 823b, which are integrally formed from the same material.

[0054] Next, a contact hole 825a is formed that reaches the surface of the gate electrode 806a of the amplifying transistor AMP from the surface of the insulating layer 820, a contact hole 825b is formed that reaches the surface of the island region 803a from the surface of the insulating layer 820, and a contact hole 825c is formed that reaches the surface of the island region 803b from the surface of the insulating layer 820. Then, as shown in Fig. 16, conductive plugs 826a to 826c are embedded in the contact holes 825a to 825c, respectively, in the same manner as the above-mentioned conductive plugs 823a and 823b.

[0055] Next, a wiring 827a electrically and mechanically connected to the conductive plugs 823a and 826a, a wiring 827b electrically and mechanically connected to the conductive plugs 826b, and a wiring 827c electrically and mechanically connected to the conductive plugs 823b and 826c are formed on the surface of the insulating layer 820. These wirings 827a to 827c are formed by forming a metal film, such as a copper film, on the surface of the insulating layer 820 by a CVD method, and then patterning the copper film using well-known photolithography and anisotropic dry etching techniques.

[0056] Next, an insulating film 828 is formed on the insulating layer 820 to cover the insulating layer 820 including the wirings 827a to 827c, and then wirings 829 are formed embedded in the surface layer of the insulating layer 820.

[0057] Next, the third substrate unit 30, on which the logic circuit 32 and the like are formed, is bonded to the second substrate unit 20. Then, the back surface side of the semiconductor layer 701 is ground by CMP or the like until the element isolation region 702 is exposed, thereby isolating the island region 103. Furthermore, a planarizing film, a color filter, a microlens, and the like are formed on the back surface of the semiconductor layer 701. This almost completes the solid-state imaging device 1A according to the first embodiment shown in FIG. 1.

[0058] According to the method for manufacturing the solid-state imaging device 1A according to the first embodiment, the conductive plug 823a and the conductive pad 824a are integrally formed from the same material, and the conductive plug 823b and the conductive pad 824b are also integrally formed from the same material, so that one heterojunction can be reduced compared to when the conductive pad 824a is formed from, for example, a polycrystalline silicon film. As a result, it is possible to manufacture the solid-state imaging device 1A in which the resistance value of the conductive path including the conductive plug 823a and the conductive pad 824a, and the resistance value of the conductive path including the conductive plug 823a and the conductive pad 824a are reduced.

[0059] Furthermore, according to the manufacturing method of the solid-state imaging device 1A of the first embodiment, no diffusion of impurities occurs from the conductive pads 824a, 824b to the contact regions 705, 706, and therefore it is possible to manufacture a solid-state imaging device 1A in which the expansion of the contact regions 705, 706 is suppressed. In the solid-state imaging device 1A according to the first embodiment, the semiconductor layer 801 in which the insulating film 804 fills the spaces between the island regions 803 has been described. However, the semiconductor layer 801 may be formed of a single semiconductor, as in the semiconductor substrate 21 shown in FIG. 104 of the tenth embodiment, which will be described later. In this case, an element isolation layer 213 surrounding the periphery of the transistor is formed in the semiconductor layer 801, similar to the semiconductor substrate 21 in FIG. 104. In this case, a through hole through which the conductive plug 823a passes and a through hole through which the conductive plug 823b passes may be formed in the semiconductor layer 801, and then an upper insulating layer 820 may be formed to fill the through holes. When the conductive plugs 823a and 823b pass through the through holes formed in the semiconductor layer 801, it is preferable to provide insulation and isolation by interposing an insulating film between the semiconductor layer 801 and the conductive plugs 823a and 823b. The second substrate part 20 of the first embodiment may also have a configuration in which semiconductor substrates 21 and 21A are stacked, as in the second substrate part 20 of the tenth embodiment described later and shown in Fig. 104. In this case, it is preferable that the conductive plugs 823a and 823b are formed so as to penetrate the plurality of semiconductor substrates while being insulated and isolated from the plurality of semiconductor substrates.

[0060] (Second embodiment) <Configuration of solid-state imaging device> A solid-state imaging device 1B1 according to the second embodiment of the present technology has basically the same configuration as the solid-state imaging device 1A according to the first embodiment described above, but differs in the following configuration. That is, as shown in Fig. 18 , the solid-state imaging device 1B1 according to the second embodiment of the present technology includes MIS contact portions 840a and 240b between the contact regions 705 and 706 and the conductive plugs 823a and 823b. Furthermore, the solid-state imaging device 1B1 according to the second embodiment of the present technology includes a compound semiconductor layer 850 as a second semiconductor layer, instead of the semiconductor layer 801 of the first embodiment described above.

[0061] The MIS contact unit 840a has a contact region 705, an insulating film 841 provided on the contact region 705, and a conductive pad 842a provided on the insulating film 841. The MIS contact unit 840b has a contact region 706, an insulating film 841 provided on the contact region 706, and a conductive pad 842b provided on the insulating film 841.

[0062] The insulating film 841 and conductive pads 842a of the MIS contact section 840a are arranged on the four contact regions 705 across the first intersection 702a of the element isolation region 702. Similarly, the insulating film 841 and conductive pads 842b of the MIS contact section 840b are arranged on the four contact regions 706 across the second intersection 702b of the element isolation region 702. The conductive pads 842a and 842b are formed of a polycrystalline silicon (doped polysilicon) film into which impurities for reducing resistance are introduced during or after film formation. The insulating film 841 is an amorphous film, and may be, for example, a titanium oxide (TiO2) film or a strontium titanate (SrTiO x ) membrane can be used.

[0063] The MIS contact portions 840a and 840b enable contact with lower resistance than the junction between polycrystalline silicon (conductive pads 842a, 842b) and crystalline silicon (contact regions 805, 806) by using the insulating film 841 to block the wave function of electrons that penetrate from the metal (polycrystalline silicon film) side into the band gap of the semiconductor (contact regions 805, 806) and by utilizing the interface dipole generated at the insulating film / semiconductor (contact regions 805, 806) interface to generate an electric field that effectively reduces the Schottky barrier. MIS contacts are described in the following literature.

[0064] k.-W. Ang, et al., IEDM 2012, P.439. S. Datta et al., VLSI tech.pp. 174-1752014

[0065] The compound semiconductor layer 850 has a plurality of island regions 853 as element formation regions, each of which is arranged adjacent to one another in a plane with an insulating film 802 interposed therebetween and each of which is provided with a second active element. The compound semiconductor layer 850 is formed in a manufacturing process by bonding a compound semiconductor substrate having an insulating film 802 on its back surface to the first substrate unit 10, patterning the compound semiconductor substrate to form a plurality of island regions 853, and then filling the spaces between the island regions 853 with an insulating film 804. The compound semiconductor substrate may be a III-V material or a IV material. The III-V material may be indium gallium arsenide (InGaAs), and the IV material may be silicon germanium (SiGe) or germanium (Ge). In the second embodiment, an InGaAs substrate is used. That is, each of the island regions 853 is mainly composed of the compound semiconductor layer 850 made of InGaAs.

[0066] An amplifier transistor AMP and a select transistor SEL (not shown) serving as second active elements are provided in an island region 853a of the multiple island regions 853. A reset transistor RST serving as a second active element is provided in an island region 853b of the multiple island regions 853. The island regions 853a and 853b are arranged on four island regions 703 that constitute one pixel unit PU.

[0067] Although not shown in detail, the amplifier transistor AMP has a gate insulating film 855, a gate electrode 856a, a source region, and a drain region provided in the island region 853a. The select transistor SEL also has a gate insulating film, a gate electrode, a source region, and a drain region provided in the island region 853a. Although not shown in detail, the reset transistor RST has a gate insulating film 855, a gate electrode 856b, a source region, and a drain region provided in the island region 853b. The gate insulating film 855 is formed of an aluminum oxide film formed on the island region by, for example, the ALD method.

[0068] According to the solid-state imaging device 1B1 according to the second embodiment of the present technology, a low-resistance floating diffusion shared contact structure can be obtained because the MIS contact portion 840a can be formed by forming a thin insulating film between the contact region 705 and the conductive pad 842a. Also, a low-resistance contact structure can be obtained because the MIS contact portion can be formed by forming a thin insulating film 841 between the contact region 706 and the conductive pad 842b.

[0069] <Method of manufacturing a solid-state imaging device> Next, a method for manufacturing the solid-state imaging device 1B1 according to the second embodiment of the present technology will be described.

[0070] First, as shown in FIG. 19, an element isolation region 702, an island region 703, a well region 704, a photodiode PD, a transfer transistor TR, contact regions 705 and 706, etc. are formed in a semiconductor layer 701.

[0071] Next, titanium oxide (TiO ) having a thickness of about 10 to 20 nm is deposited on the entire surface of the semiconductor layer 701 including the island region 703. x 20 , a MIS contact portion 840a is formed on the four contact regions 705 of the four island regions 703 via an insulating film 841 across the first intersection 702a of the element isolation region 702, and a MIS contact portion 840b is formed on the four contact regions 706 of the four island regions 703 via an insulating film 841 across the second intersection 702b of the element isolation region 702. This process forms MIS contact portions 840a on the four contact regions 705 adjacent to the first intersection 702a of the element isolation region 702, and forms MIS contact portions 840b on the four contact regions 706 adjacent to the second intersection 702b of the element isolation region 702.

[0072] Next, as shown in FIG. 21, an insulating layer 720 as a first insulating layer is formed on the entire main surface of the semiconductor layer 701 so as to cover the gate electrode 710 and the MIS contact portions 840a and 840b.

[0073] Next, a compound semiconductor layer 850 made of, for example, InGaAs is prepared as a second semiconductor layer. An insulating film 801 made of, for example, a silicon oxide film is provided on the back surface of the compound semiconductor layer 850 opposite to the main surface. Then, as shown in FIG. 22 , the compound semiconductor layer 850 is bonded to the main surface side of the semiconductor layer 701. Specifically, the insulating layer 720 on the main surface side of the semiconductor layer 701 and the insulating film 802 provided on the back surface side of the compound semiconductor layer 850 are placed face to face and in close contact with each other, and then heat treatment is performed. As a result, as shown in FIG. 22 , the insulating film 802 and the insulating layer 720 are integrated, and the upper compound semiconductor layer 850 and the lower semiconductor layer 701 are bonded to each other via the insulating film 802 and the insulating layer 720. The compound semiconductor layer 850 is disposed on the insulating layer 720. Thereafter, the main surface side of the compound semiconductor layer 840 is ground by, for example, a CMP method to reduce the thickness of the compound semiconductor layer 850.

[0074] Next, as shown in FIG. 23 , the compound semiconductor layer 850 is patterned into a plurality of island regions 853 using well-known photolithography techniques and anisotropic dry etching techniques, and then, as shown in FIG. 23 , the spaces between the island regions 853 are filled with an insulating film 804 to flatten the main surface side of the compound semiconductor layer 850.

[0075] Next, as shown in FIG. 24, an amplifier transistor AMP and a select transistor SEL (not shown) are formed as second active elements in island region 853a of the multiple island regions 853, and a reset transistor RST is formed as second active elements in island region 853b of the multiple island regions 853. To form these second active elements, first, a gate insulating film 855 made of an Al2O3 film with a thickness of approximately 10 nm is formed by ALD on the entire main surface of the compound semiconductor layer 850, including the island regions 853. Then, a gate electrode material made of an aluminum (Al) or aluminum alloy film with a thickness of approximately 100 nm is formed by sputtering on the entire surface of the gate insulating film 855. The gate electrode material and gate insulating film 855 are then patterned in this order to form gate electrodes 856a and 856b on the island regions 853a and 853b with the gate insulating film 855 interposed therebetween. Then, source and drain regions are formed by low-temperature doped epitaxial growth at 550°C or less. As a result, the amplifier transistor AMP and the select transistor SEL are formed in the island region 853a, and the reset transistor RST is formed in the island region 853b.

[0076] In this process, the insulating film 841 of the MIS contact portions 840a, 840b is also exposed to the heat treatment temperature used when forming the second active element. The characteristics of the insulating film 841 of the MIS contact portions 840a, 840b tend to become unstable when exposed to high temperatures, making it difficult to maintain a low resistance. However, because the second active element is formed by a low-temperature process at 550°C or less, the low resistance of the MIS contact portions 840a, 840b can be maintained even after the second active element is formed.

[0077] Next, an insulating layer 820 is formed as a second insulating layer to cover the island regions 853a and 853b, and the surface of the insulating layer 820 is then planarized, as shown in FIG.

[0078] 25, a connection hole 821a is formed from the surface of the insulating layer 820 to the surface of the conductive pad 842a, and a connection hole 821b is formed from the surface of the insulating layer 820 to the surface of the conductive pad 842b. These connection holes 821a and 821b are formed using well-known photolithography and anisotropic dry etching techniques.

[0079] Next, a conductive material is buried in the contact holes 821a and 821b by a method similar to that of the first embodiment described above, to form conductive plugs 823a and 823b in the contact holes 821a and 821b. Then, using a method similar to that of the first embodiment described above, contact holes 825a to 825c, conductive plugs 826a to 826c, wirings 827a to 827c, an insulating film 828, wiring 829, etc. are formed. After the third substrate unit 30 is attached, a planarization film 831, a color filter 832, a microlens 833, etc. are formed on the back surface of the semiconductor layer 701. This almost completes the solid-state imaging device 1B1 according to the second embodiment shown in FIG.

[0080] According to the manufacturing method of the solid-state imaging device 1B1 according to the second embodiment of the present technology, the second active element is formed by a low-temperature process after the MIS contact portion is formed, so it is possible to provide the solid-state imaging device 1B1 having the MIS contact portions 840a, 840b that maintain low resistance. This also makes it possible to stack the second active element and the logic circuit on the photodiode PD, so that the pixel area can be increased and an ultra-high sensitivity solid-state imaging device 1B1 can be provided. In addition, in the solid-state imaging device 1B1 according to the second embodiment, the second substrate portion 20 may also be configured as a stack of semiconductor substrates 21 and 21A (a stack of multiple semiconductor substrates), as in the second substrate portion 20 shown in Figure 104 of the tenth embodiment described below.

[0081] (Third embodiment) <Configuration of solid-state imaging device> In the above-described second embodiment, the case where the compound semiconductor layer 850 is used as the second semiconductor layer has been described. However, in the present technology, as in the above-described first embodiment, a semiconductor layer 801 made of single crystal silicon can also be used as the second semiconductor layer, as shown in FIG.

[0082] Specifically, as shown in Fig. 27, a substrate portion is prepared in which an insulating layer 720 is formed as a first insulating layer on a semiconductor layer 701, and as shown in Fig. 28, a substrate portion is prepared in which an insulating layer 820 is formed as a second insulating layer covering the semiconductor layer 801. Then, as shown in Fig. 29, the insulating layer 720 on the main surface side of the semiconductor layer 701 and the insulating film 802 on the back surface side of the semiconductor layer 801 are placed face to face and bonded together by heat treatment in a state of being in close contact with each other. Then, the same steps as in the second embodiment described above are performed to form connection holes 825a-825c, wirings 825a-825c, an insulating film 828, wirings 829, etc., as shown in Fig. 26.

[0083] According to the manufacturing method of the solid-state imaging device 1B2 of the third embodiment, a substrate portion having a second active element that has already been formed by high-temperature heat treatment is bonded to a substrate portion having pre-formed MIS contact portions 840a, 840b, thereby providing a solid-state imaging device 1B2 having MIS contact portions 840a, 840b that maintain low resistance. In addition, in the solid-state imaging device 1B2 of this third embodiment, the second substrate portion 20 may also be configured in such a way that semiconductor substrates 21 and 21A are stacked (multiple semiconductor substrates are stacked) as in the second substrate portion 20 shown in Figure 104 of the tenth embodiment described below.

[0084] (Fourth embodiment) <Configuration of solid-state imaging device> A solid-state imaging device 1C according to the fourth embodiment of the present technology basically has the same configuration as the solid-state imaging device 1 according to the first embodiment described above, but differs in the following configuration.

[0085] 30 and 31 , the solid-state imaging device 1C according to the fourth embodiment of the present technology includes conductive plugs 875a and 875b embedded in through holes 871a and 871b extending from the surface of the insulating layer 820 to the surfaces of the conductive pads 864a and 864b, with an insulating film 873 interposed therebetween. The solid-state imaging device 1C according to the fourth embodiment of the present technology also includes an isolation trench 872 that separates the element formation region of the semiconductor layer 801 into island regions 803, an insulating film 873 provided on a sidewall of the isolation trench 872, and an element isolation region 876 including a conductive material 874 embedded inside the insulating film 873 in the isolation trench.

[0086] The conductive pad 864a is formed separately from the conductive plug 875a. The conductive pad 864a is disposed on the four contact regions 705 across the first intersection 702a of the element isolation region 702 and is electrically and mechanically connected to the four contact regions 705. Similarly, the conductive pad 864b is formed separately from the conductive plug 875b. The conductive pad 864b is disposed on the four contact regions 706 across the second intersection 702b of the element isolation region 702 and is electrically and mechanically connected to the four contact regions 706. The conductive pads 864a and 864b are formed of, for example, a polycrystalline silicon (doped polysilicon) film into which impurities that reduce resistance are introduced during or after film formation. On the other hand, the conductive plugs 875a and 875b are formed of tungsten, a high-melting-point metal material, like the conductive plugs 823a and 823b of the first embodiment.

[0087] In the solid-state imaging device 1C according to the fourth embodiment of the present technology, the island region 803 in which the second active element is formed is surrounded in a planar manner by the conductive material 874. Therefore, according to the solid-state imaging device 1C according to the fourth embodiment of the present technology, scattering of incident light can be blocked, thereby suppressing color mixing and providing the solid-state imaging device 1C with ultra-high sensitivity.

[0088] <Method of manufacturing a solid-state imaging device> Next, an example of a method for manufacturing the solid-state imaging device according to the fourth embodiment will be described with reference to FIGS. First, as shown in FIG. 32, an element isolation region 702, an island region 703, a well region 704, a photodiode PD, a transfer transistor TR, contact regions 705 and 706, conductive pads 864a and 864b, etc. are formed in a semiconductor layer 701.

[0089] Next, as shown in FIG. 32, an insulating layer 720 as a first insulating layer is formed on the entire main surface of the semiconductor layer 701 so as to cover the gate electrode 710 and the conductive pads 864a and 864b.

[0090] Next, as shown in FIG. 33, a semiconductor layer 801 is bonded to the principal surface side of the semiconductor layer 101 by the same method as in the first embodiment described above. Specifically, a heat treatment is performed while the insulating layer 720 on the principal surface side of the semiconductor layer 101 and the insulating film 802 provided on the back surface side of the semiconductor layer 801 are placed face to face and in close contact with each other. As a result, as shown in FIG. 33, the insulating film 802 and the insulating layer 720 are integrated, and the upper semiconductor layer 801 and the lower semiconductor layer 701 are bonded to each other via the insulating film 802 and the insulating layer 720. The semiconductor layer 801 is then disposed on the insulating layer 720. Thereafter, the principal surface side of the semiconductor layer 801 is ground by, for example, a CMP method to reduce the thickness of the semiconductor layer 801.

[0091] 34, while leaving the element isolation region of the semiconductor layer 801, an amplifier transistor AMP and a select transistor are formed as second active elements in an element formation region corresponding to the island region 803a among the plurality of element formation regions of the semiconductor layer 801, and a reset transistor RST is formed as a second active element in an element formation region corresponding to the island region 803b among the plurality of element formation regions. These second active elements are formed by the same method as in the first embodiment described above.

[0092] Next, an insulating layer 820 is formed as a second insulating layer to cover the island regions 803a and 803b, and the surface of the insulating layer 820 is then planarized as shown in FIG.

[0093] 35, a connection hole 871a is formed from the surface of the insulating layer 820 to the surface of the conductive pad 864a, and a connection hole 871b is formed from the surface of the insulating layer 820 to the surface of the conductive pad 864b. Furthermore, the element isolation region of the semiconductor layer 801 is removed by etching to form an island region 803. The island region 803 can be formed in the same process as the formation of the connection holes 871a and 871b. That is, by using a photomask (reticle) having a pattern for the connection holes 871a and 871b and a pattern for the island region 803, the etching for forming the connection holes 871a and 871b and the etching for forming the island region 803 can be performed on the semiconductor layer 801 in the same process. By etching the element isolation region of the semiconductor layer 801 to form the island region 803, an isolation groove 872 is formed between adjacent island regions 803.

[0094] Next, an insulating film 873 such as a silicon oxide film is formed by, for example, a CVD method to cover the semiconductor layer 801 in the contact holes 871a and 871b and in the isolation trench 872. Then, the insulating film 873 existing on the surface of the insulating layer 820 and at the bottoms of the contact holes 871a and 871b and the isolation trench 872 is selectively removed by, for example, an anisotropic etching technique such as RIE.

[0095] 36 , a conductive material 874 is embedded inside the insulating film 873 in the connection holes 871a and 871b to form conductive plugs 875a and 875b made of the conductive material 874 inside the connection holes 871a and 871b, and a conductive material 874 is embedded inside the insulating film 873 in the isolation trench 872. The conductive plugs 875a and 875b are insulated from the semiconductor layer 801 in the connection holes 871a and 871b by the insulating film 873 in the connection holes 871a and 871b. Furthermore, the conductive material 874 in the isolation trench 872 is insulated from the semiconductor layer 801 in the isolation trench 872 by the insulating film 873 in the isolation trench 872.

[0096] Next, using the same method as in the first embodiment described above, connection holes 825a-825c, conductive plugs 826a-826c, wirings 827a-827c, an insulating film 828, wirings 829, etc. are formed, and after the third substrate unit 30 is attached, a planarization film 831, a color filter 832, a microlens 833, etc. are formed on the back surface of the semiconductor layer 701. This almost completes the solid-state imaging device 1C according to the fourth embodiment shown in FIGS.

[0097] According to the method for manufacturing the solid-state imaging device 1C according to the fourth embodiment of the present technology, it is possible to provide the solid-state imaging device 1C in which the island region 803 where the second active element is formed is surrounded by a conductive material in a planar manner.

[0098] Furthermore, according to the manufacturing method of the solid-state imaging device 1C of the fourth embodiment of the present technology, the island region can be surrounded by a conductive material in the process of forming the conductive plugs 875a, 875b in the connection holes 871a, 871b, thereby reducing the number of manufacturing processes and enabling the cost of the solid-state imaging device 1C to be reduced. In the solid-state imaging device 1C according to the fourth embodiment, the second substrate unit 20 may also have a configuration in which semiconductor substrates 21 and 21A are stacked (a configuration in which a plurality of semiconductor substrates are stacked), like the second substrate unit 20 shown in Fig. 104 of the tenth embodiment described later. In this case, the conductive plugs 875a and 875b embedded in the through holes 871a and 871b via the insulating film 873 may penetrate the plurality of semiconductor substrates.

[0099] (Fifth embodiment) <Configuration of solid-state imaging device> The solid-state imaging device 1D according to the fifth embodiment of the present technology differs from the solid-state imaging device 1A according to the first embodiment in the configuration of its pixel unit. Specifically, the pixel unit PU of the solid-state imaging device 1A according to the first embodiment has four sensor pixels 12 connected to one readout circuit. In contrast, the pixel unit of the solid-state imaging device 1D according to the fifth embodiment of the present technology has one pixel unit connected to one readout circuit. As shown in FIG. 37 , a conductive path is also provided for each sensor pixel, electrically connecting the gate electrode 882 of the amplification transistor AMP of the readout circuit to the contact region 705 that shares the floating diffusion FD of the sensor pixel. The conductive path includes a conductive plug 889 embedded in a connection hole 888 that extends from the surface of an insulating layer 887 serving as a second insulating layer to the surface of the contact region 705.

[0100] The amplifier transistors AMP are provided in island regions 884 that are obtained by dividing an element formation region of a semiconductor layer 801 serving as a second semiconductor layer. In Fig. 37, the amplifier transistors AMP of two adjacent readout circuits are provided in parallel in one island region 884. The amplifier transistor AMP has, for example, a gate insulating film 881 made of a thermally oxidized silicon film provided on the main surface of the island region 884, a gate electrode 882 made of a polycrystalline silicon film on the gate insulating film 881, and source and drain regions made of semiconductor regions formed in the surface layer portion of the island region 884.

[0101] A through hole 885 penetrating in the vertical direction is provided in the island region 884 corresponding to the conductive plug 889. Sidewalls 886 made of a material having a higher etching ratio than an insulating layer 887 covering the island region 884 are provided on the wall surface within the through hole 885 and the side surface on the periphery of the island region 884. The conductive plug 889 is formed along the sidewalls 886. The sidewalls 886 are made of at least one film selected from a SiN film, a SiBN film, and a SiBCN film, which have an etching selectivity relative to a silicon oxide film.

[0102] <Method of manufacturing a solid-state imaging device> Next, a method for manufacturing the solid-state imaging device 1D according to the fifth embodiment will be described with reference to FIGS. First, as shown in FIG. 38, an element isolation region 702, an island region 703, a well region 704, a photodiode PD, a transfer transistor TR, a contact region 705, and the like are formed in a semiconductor layer 701.

[0103] Next, as shown in FIG. 38, an insulating layer 720 is formed as a first insulating layer on the entire main surface of the semiconductor layer 701 so as to cover the gate electrode 710.

[0104] Next, as shown in FIG. 39 , a semiconductor layer 801 is bonded to the main surface side of the semiconductor layer 701 using a method similar to that of the first embodiment described above. Specifically, a heat treatment is performed with the insulating layer 720 on the main surface side of the semiconductor layer 701 and the insulating film 802 on the back surface side of the semiconductor layer 801 facing each other and in close contact with each other. As a result, as shown in FIG. 39 , the insulating film 802 and the insulating layer 720 are integrated, and the upper semiconductor layer 801 and the lower semiconductor layer 701 are bonded to each other via the insulating film 802 and the insulating layer 720. Furthermore, the semiconductor layer 801 is disposed on the insulating layer 720. Thereafter, the main surface side of the semiconductor layer 801 is ground by, for example, a CMP method to reduce the thickness of the semiconductor layer 801.

[0105] 40, amplifier transistors AMP are formed as second active elements in multiple element formation regions of the semiconductor layer 801 while leaving the element isolation regions of the semiconductor layer 801. Furthermore, although not shown, select transistors and reset transistors RST are formed as second active elements. These second active elements are formed by the same method as in the first embodiment described above.

[0106] 41 , the element formation region of the semiconductor layer 801 is divided into a plurality of island regions 884 using well-known photolithography technology, anisotropic dry etching technology, etc., and through holes 885 for passing conductive plugs 889 through are formed in the island regions 884. The through holes 885 are arranged at positions overlapping the contact regions 705 in a plan view.

[0107] 42, sidewalls 886 are formed on the sidewalls within the through-holes 885 of the island regions 884 and on the sidewalls on the periphery of the island regions 884. The sidewalls 886 can be formed, for example, by depositing an insulating film by a CVD method so as to cover the sidewalls within the through-holes 885 of the island regions 884 and the sidewalls on the periphery of the island regions 884, and then performing anisotropic dry etching on this insulating film. The sidewalls 886 are formed, for example, from a silicon nitride film.

[0108] 43, an insulating layer 887 is formed by, for example, a CVD method as a second insulating layer covering the island regions 884 so as to fill the spaces between adjacent island regions 884 and the insides of the sidewalls 886 of the through holes 885 of the island regions 884. The insulating layer 887 is formed of silicon oxide that is selective to the sidewalls 886.

[0109] 44, a connection hole 888 is formed, which extends from the surface of the insulating layer 887 through the through-hole 885 in the island region 884 to the surface of the contact region 705. At this time, since the connection hole 888 is formed using photolithography, the connection hole 888 is formed along the side wall 886 even if the photoresist pattern is misaligned in a direction that overlaps the side wall 886 in plan view due to misalignment of the mask.

[0110] 45, a conductive material is embedded in the contact hole 888 by the same method as in the first embodiment described above to form a conductive plug 889. Then, the same method as in the first embodiment described above is applied to form a contact hole 825, a conductive plug 826, a wiring 890, an insulating film 828, a wiring 829, etc., and after bonding the third substrate unit 30, a planarizing film, a color filter, a microlens, etc. are formed on the back surface of the semiconductor layer 701. This almost completes the solid-state imaging device 1D according to the fifth embodiment shown in FIG.

[0111] According to the manufacturing method of the solid-state imaging device 1D of the fifth embodiment of the present technology, the connection hole 888 is formed along the sidewall 886, and therefore the conductive plug 889 embedded in this connection hole 888 is also formed along the connection hole 888. This makes it possible to reduce misalignment between the conductive plug 889 and the semiconductor layer (island region 884). Meanwhile, the parasitic capacitance parasitic on the conductive plug 889 varies depending on the misalignment between the conductive plug 889 and the semiconductor layer (island region 884). Therefore, according to the manufacturing method of the solid-state imaging device 1D of the fifth embodiment of the present technology, it is possible to reduce variation in the parasitic capacitance parasitic on the conductive plug 889. Furthermore, variation in the parasitic capacitance parasitic on the conductive plug 889 affects variation in conversion efficiency. Therefore, since variation in the parasitic capacitance parasitic on the conductive plug 889 can be reduced, it is possible to stabilize the conversion efficiency. In the solid-state imaging device 1D according to the fifth embodiment, the second substrate unit 20 may also have a configuration in which semiconductor substrates 21 and 21A are stacked (a configuration in which a plurality of semiconductor substrates are stacked), like the second substrate unit 20 shown in Fig. 104 of the tenth embodiment described later. In this case, the conductive plug 889 may be formed along the sidewalls 286 formed on each of the plurality of semiconductor substrates.

[0112] (Sixth embodiment) <Configuration of solid-state imaging device> As shown in FIG. 46, a solid-state imaging device 1E according to the sixth embodiment of the present technology has almost the same configuration as the solid-state imaging device 1D according to the fifth embodiment described above, but differs in the following configuration.

[0113] That is, the solid-state imaging device 1E according to the sixth embodiment of the present technology includes a low-dielectric film 891 between the island region 884 (semiconductor layer) and the sidewall 886, the low-dielectric film 891 having a lower dielectric constant than the sidewall 886. As the low-dielectric film 891, it is preferable to use a Si-based low-dielectric material having a lower N content than the sidewall 886 and containing added B, O, C, etc. Furthermore, the low-dielectric film 891 may be porous and contain bubbles, or may be a laminated film of two or more layers.

[0114] According to the solid-state imaging device 1E according to the sixth embodiment of the present technology, it is possible to reduce the variation in parasitic capacitance and also reduce the parasitic capacitance itself.

[0115] In the sixth embodiment described above, the case where the conductive plug 889 penetrates the island region 884 as shown in Fig. 47(a) has been described. However, the present technology is not limited to this, and can be applied to a case where the conductive plug 889 passes between two island regions 884 in the vertical direction as shown in Fig. 47(b), for example. Furthermore, the present technology can be applied to a case where two conductive plugs 889 pass individually between the island region 884 and another island region as shown in Fig. 47(c).

[0116] Seventh embodiment The seventh embodiment will be described in detail below with reference to the drawings. The description will be made in the following order. 1. Embodiment (Image capture device having a stacked structure of three substrates) 2. Modification 1 (Planar Configuration Example 1) 3. Modification 2 (Planar Configuration Example 2) 4. Modification 3 (Planar Configuration Example 3) 5. Modification 4 (Example in which a contact portion between substrates is provided in the center of the pixel array portion) 6. Modification 5 (Example with Planar-Type Transfer Transistor) 7. Modification 6 (Example in which one pixel is connected to one pixel circuit) 8. Modification 7 (Configuration Example of Pixel Separation Unit) 9. Application Examples (Imaging Systems) 10. Application Examples

[0117] <1. Embodiment> [Functional configuration of imaging device 1] FIG. 48 is a block diagram showing an example of a functional configuration of an imaging device (imaging device 1) according to an embodiment of the present disclosure.

[0118] The imaging device 1 in FIG. 48 includes, for example, an input section 510A, a row driver section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0119] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, pixel-sharing units 539 each including a plurality of pixels are repeating units, and these repeating units are repeatedly arranged in an array having a row direction and a column direction. Note that, for convenience, the row direction may be referred to as the H direction and the column direction perpendicular to the row direction as the V direction in this specification. In the example of FIG. 48, one pixel-sharing unit 539 includes four pixels (pixels 541A, 541B, 541C, and 541D). Each of the pixels 541A, 541B, 541C, and 541D has a photodiode PD (shown in FIG. 53, etc., described later). The pixel-sharing unit 539 is a unit that shares one pixel circuit (pixel circuit 210 in FIG. 50, described later). In other words, four pixels (pixels 541A, 541B, 541C, and 541D) have one pixel circuit (pixel circuit 210, described later). By operating this pixel circuit in a time-division manner, pixel signals from each of the pixels 541A, 541B, 541C, and 541D are sequentially read out. The pixels 541A, 541B, 541C, and 541D are arranged, for example, in two rows and two columns. The pixel array section 540 is provided with the pixels 541A, 541B, 541C, and 541D, as well as multiple row drive signal lines 542 and multiple vertical signal lines (column readout lines) 543. The row drive signal line 542 drives the pixels 541 included in each of multiple pixel-sharing units 539 arranged side by side in the row direction in the pixel array section 540. The row drive signal line 542 drives each pixel arranged side by side in the row direction within the pixel-sharing unit 539. As will be described in detail later with reference to FIG. 51 , each pixel-sharing unit 539 is provided with multiple transistors. To drive each of these multiple transistors, multiple row drive signal lines 542 are connected to one pixel-sharing unit 539. The pixel sharing unit 539 is connected to the vertical signal line (column readout line) 543. Pixel signals are read out via the vertical signal line (column readout line) 543 from each of the pixels 541A, 541B, 541C, and 541D included in the pixel sharing unit 539.

[0120] The row driving unit 520 includes, for example, a row address control unit that determines the position of the row for pixel driving, in other words, a row decoder unit, and a row driving circuit unit that generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0121] The column signal processing unit 550 includes, for example, a load circuit unit that is connected to the vertical signal line 543 and forms a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (pixel sharing units 539). The column signal processing unit 550 may include an amplifier circuit unit that amplifies the signal read out from the pixel sharing unit 539 via the vertical signal line 543. The column signal processing unit 550 may include a noise processing unit. The noise processing unit removes the system noise level from the signal read out from the pixel sharing unit 539 as a result of photoelectric conversion, for example.

[0122] The column signal processing unit 550 includes, for example, an analog-to-digital converter (ADC). The analog-to-digital converter converts the signal read from the pixel shared unit 539 or the analog signal that has undergone the noise processing into a digital signal. The ADC includes, for example, a comparator unit and a counter unit. The comparator unit compares the analog signal to be converted with a reference signal to be compared with the analog signal. The counter unit measures the time until the comparison result in the comparator unit is inverted. The column signal processing unit 550 may also include a horizontal scanning circuit unit that controls scanning of the readout columns.

[0123] The timing control section 530 supplies signals for controlling timing to the row driving section 520 and the column signal processing section 550 based on the reference clock signal and timing control signal input to the device.

[0124] The image signal processing unit 560 is a circuit that performs various signal processing operations on data obtained as a result of photoelectric conversion, in other words, data obtained as a result of the imaging operation in the imaging device 1. The image signal processing unit 560 includes, for example, an image signal processing circuit unit and a data holding unit. The image signal processing unit 560 may also include a processor unit.

[0125] One example of signal processing executed by the image signal processing unit 560 is tone curve correction processing, which increases the gradation of AD converted imaging data when the data is of a dark subject, and decreases the gradation when the data is of a bright subject. In this case, it is desirable to store in advance in the data storage unit of the image signal processing unit 560 characteristic data of the tone curve based on which the gradation of the imaging data is to be corrected.

[0126] The input unit 510A is for inputting, for example, the above-mentioned reference clock signal, timing control signal, characteristic data, etc. from outside the device to the imaging device 1. The timing control signal is, for example, a vertical synchronization signal and a horizontal synchronization signal. The characteristic data is, for example, for storage in a data holding unit of the image signal processing unit 560. The input unit 510A includes, for example, an input terminal 511, an input circuit unit 512, an input amplitude changing unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0127] The input terminal 511 is an external terminal for inputting data. The input circuit unit 512 is for inputting a signal input to the input terminal 511 into the imaging device 1. The input amplitude change unit 513 changes the amplitude of the signal input by the input circuit unit 512 to an amplitude that is easily usable inside the imaging device 1. The input data conversion circuit unit 514 changes the arrangement of the data string of the input data. The input data conversion circuit unit 514 is configured, for example, by a serial-parallel conversion circuit. This serial-parallel conversion circuit converts a serial signal received as input data into a parallel signal. Note that the input amplitude change unit 513 and the input data conversion circuit unit 514 may be omitted from the input unit 510A. The power supply unit supplies power set to various voltages required inside the imaging device 1 based on power supplied from an external source to the imaging device 1.

[0128] When the imaging device 1 is connected to an external memory device, the input unit 510A may be provided with a memory interface circuit that receives data from the external memory device, such as a flash memory, an SRAM, or a DRAM.

[0129] Output unit 510B outputs image data to the outside of the device. This image data is, for example, image data captured by imaging device 1 and image data that has been signal-processed by image signal processing unit 560. Output unit 510B includes, for example, output data conversion circuit unit 515, output amplitude change unit 516, output circuit unit 517, and output terminal 518.

[0130] The output data conversion circuit unit 515 is configured with, for example, a parallel-serial conversion circuit, and converts parallel signals used inside the imaging device 1 into serial signals. The output amplitude change unit 516 changes the amplitude of the signals used inside the imaging device 1. Signals with changed amplitudes are easier to use in external devices connected to the outside of the imaging device 1. The output circuit unit 517 is a circuit that outputs data from inside the imaging device 1 to outside the device, and the output circuit unit 517 drives wiring outside the imaging device 1 connected to an output terminal 518. Data is output from the imaging device 1 to outside the device through the output terminal 518. The output data conversion circuit unit 515 and the output amplitude change unit 516 may be omitted from the output unit 510B.

[0131] When the imaging device 1 is connected to an external memory device, the output unit 510B may be provided with a memory interface circuit that outputs data to the external memory device, such as a flash memory, an SRAM, or a DRAM.

[0132] [Schematic configuration of imaging device 1] 49 and 50 show an example of a schematic configuration of the imaging device 1. The imaging device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). FIG. 49 schematically shows the planar configuration of each of the first substrate 100, the second substrate 200, and the third substrate 300, and FIG. 50 schematically shows the cross-sectional configuration of the first substrate 100, the second substrate 200, and the third substrate 300 stacked on top of each other. FIG. 50 corresponds to the cross-sectional configuration taken along line III-III′ shown in FIG. 49. The imaging device 1 is a three-dimensional imaging device formed by bonding together three substrates (the first substrate 100, the second substrate 200, and the third substrate 300). The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for convenience, the combination of the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the surrounding interlayer insulating film is referred to as the wiring layer (100T, 200T, 300T) provided on each substrate (first substrate 100, second substrate 200, and third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order, with the semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring layer 200T, the wiring layer 300T, and the semiconductor layer 300S arranged in this order along the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. The arrows in FIG. 50 indicate the direction of incidence of light L into the imaging device 1. For convenience, in the following cross-sectional views, the light incident side of the imaging device 1 may be referred to as "bottom," "lower side," or "bottom," and the side opposite the light incident side may be referred to as "top," "upper side," or "upper." Furthermore, for convenience, in the present specification, with respect to a substrate having a semiconductor layer and a wiring layer, the wiring layer side may be referred to as the front surface, and the semiconductor layer side may be referred to as the back surface. The description in the specification is not limited to the above terms. The imaging device 1 is, for example, a back-illuminated imaging device in which light is incident from the back surface side of the first substrate 100 having a photodiode.

[0133] The pixel array section 540 and the pixel-shared unit 539 included in the pixel array section 540 are both configured using both the first substrate 100 and the second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C, and 541D included in the pixel-shared unit 539. Each of these pixels 541 has a photodiode (a photodiode PD described below) and a transfer transistor (a transfer transistor TR described below). The second substrate 200 is provided with a pixel circuit (a pixel circuit 210 described below) included in the pixel-shared unit 539. The pixel circuit reads out pixel signals transferred from the photodiodes of the pixels 541A, 541B, 541C, and 541D via the transfer transistors, or resets the photodiodes. In addition to these pixel circuits, the second substrate 200 has a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 further includes power lines 544 extending in the row direction. The third substrate 300 includes, for example, an input section 510A, a row driver 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. The row driver 520 is provided, for example, in a region that partially overlaps with the pixel array section 540 in the stacking direction of the first substrate 100, the second substrate 200, and the third substrate 300 (hereinafter simply referred to as the stacking direction). More specifically, the row driver 520 is provided, in the stacking direction, in a region that partially overlaps with the pixel array section 540 near the end of the pixel array section 540 in the H direction ( FIG. 49 ). The column signal processing section 550 is provided, for example, in a region that partially overlaps with the pixel array section 540 in the stacking direction. More specifically, the column signal processing section 550 is provided in a region overlapping the vicinity of the end of the pixel array section 540 in the V direction in the stacking direction (FIG. 49). Although not shown, the input section 510A and the output section 510B may be provided in a portion other than the third substrate 300, for example, on the second substrate 200. Alternatively, the input section 510A and the output section 510B may be provided on the back surface (light incident surface) side of the first substrate 100.The pixel circuits provided on the second substrate 200 may also be called pixel transistor circuits, pixel transistor groups, pixel transistors, pixel readout circuits, or readout circuits. In this specification, the term pixel circuits will be used.

[0134] The first substrate 100 and the second substrate 200 are electrically connected by, for example, through electrodes (through electrodes 120E and 121E in FIG. 53 described below). The second substrate 200 and the third substrate 300 are electrically connected by, for example, contact portions 201, 202, 301, and 302. The second substrate 200 is provided with contact portions 201 and 202, and the third substrate 300 is provided with contact portions 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 has a contact region 201R in which a plurality of contact portions 201 are provided, and a contact region 202R in which a plurality of contact portions 202 are provided. The third substrate 300 has a contact region 301R in which a plurality of contact portions 301 are provided and a contact region 302R in which a plurality of contact portions 302 are provided. The contact regions 201R and 301R are provided between the pixel array section 540 and the row driver section 520 in the stacking direction (FIG. 50). In other words, the contact regions 201R and 301R are provided, for example, in a region where the row driver section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) overlap in the stacking direction, or in a region nearby this. The contact regions 201R and 301R are disposed, for example, at the end of such a region in the H direction (FIG. 49). In the third substrate 300, the contact region 301R is provided, for example, at a position overlapping with a part of the row driver section 520, specifically, the end of the row driver section 520 in the H direction (FIGS. 49 and 50). The contact portions 201 and 301 connect, for example, the row drive section 520 provided on the third substrate 300 and the row drive line 542 provided on the second substrate 200. The contact portions 201 and 301 may connect, for example, the input section 510A provided on the third substrate 300 to a power supply line 544 and a reference potential line (a reference potential line VSS described later). The contact regions 202R and 302R are provided between the pixel array section 540 and the column signal processing section 550 in the stacking direction (FIG. 50).In other words, the contact regions 202R and 302R are provided, for example, in a region where the column signal processing unit 550 (third substrate 300) and the pixel array unit 540 (second substrate 200) overlap in the stacking direction, or in a region adjacent thereto. The contact regions 202R and 302R are arranged, for example, at the end of such a region in the V direction ( FIG. 49 ). On the third substrate 300, for example, a contact region 301R is provided in a position overlapping with a part of the column signal processing unit 550, specifically, the end of the column signal processing unit 550 in the V direction ( FIGS. 49 and 50 ). The contact regions 202 and 302 are used to connect pixel signals (signals corresponding to the amount of charge generated as a result of photoelectric conversion in the photodiodes) output from each of the multiple pixel sharing units 539 included in the pixel array unit 540 to the column signal processing unit 550 provided on the third substrate 300. The pixel signals are sent from the second substrate 200 to the third substrate 300.

[0135] As described above, FIG. 50 is an example cross-sectional view of the imaging device 1. The first substrate 100, the second substrate 200, and the third substrate 300 are electrically connected via wiring layers 100T, 200T, and 300T. For example, the imaging device 1 has an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300. Specifically, the contact portions 201, 202, 301, and 302 are formed with electrodes made of a conductive material. The conductive material is made of a metal material such as copper (Cu), aluminum (Al), or gold (Au). The contact regions 201R, 202R, 301R, and 302R electrically connect the second substrate and the third substrate, enabling input and / or output of signals between the second substrate 200 and the third substrate 300, for example, by directly bonding wiring formed as electrodes.

[0136] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 can be provided in a desired location. For example, as described as contact regions 201R, 202R, 301R, and 302R in FIG. 50 , the electrical connection portion may be provided in a region that overlaps with the pixel array section 540 in the stacking direction. The electrical connection portion may also be provided in a region that does not overlap with the pixel array section 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region that overlaps with a peripheral portion disposed outside the pixel array section 540 in the stacking direction.

[0137] The first substrate 100 and the second substrate 200 are provided with, for example, connection holes H1 and H2. The connection holes H1 and H2 penetrate the first substrate 100 and the second substrate 200 (FIG. 50). The connection holes H1 and H2 are provided outside the pixel array section 540 (or a portion overlapping the pixel array section 540) (FIG. 49). For example, the connection hole H1 is disposed outside the pixel array section 540 in the H direction, and the connection hole H2 is disposed outside the pixel array section 540 in the V direction. For example, the connection hole H1 reaches the input section 510A provided on the third substrate 300, and the connection hole H2 reaches the output section 510B provided on the third substrate 300. The connection holes H1 and H2 may be hollow or may contain a conductive material at least in part. For example, there is a configuration in which a bonding wire is connected to an electrode formed as the input portion 510A and / or the output portion 510B. Alternatively, there is a configuration in which an electrode formed as the input portion 510A and / or the output portion 510B is connected to a conductive material provided in the connection holes H1, H2. The conductive material provided in the connection holes H1, H2 may be embedded in part or all of the connection holes H1, H2, or the conductive material may be formed on the side walls of the connection holes H1, H2.

[0138] 50 shows a structure in which the input unit 510A and the output unit 510B are provided on the third substrate 300, but the present invention is not limited to this. For example, the input unit 510A and / or the output unit 510B can be provided on the second substrate 200 by sending signals from the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T. Similarly, the input unit 510A and / or the output unit 510B can be provided on the first substrate 100 by sending signals from the second substrate 200 to the first substrate 1000 via the wiring layers 100T and 200T.

[0139] FIG. 51 is an equivalent circuit diagram illustrating an example of the configuration of a pixel-shared unit 539. The pixel-shared unit 539 includes a plurality of pixels 541 (four pixels 541: pixels 541A, 541B, 541C, and 541D are illustrated in FIG. 51), one pixel circuit 210 connected to the plurality of pixels 541, and a vertical signal line 5433 connected to the pixel circuit 210. The pixel circuit 210 includes, for example, four transistors, specifically, an amplification transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FD. As described above, the pixel-shared unit 539 operates one pixel circuit 210 in a time-division manner to sequentially output pixel signals of each of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) included in the pixel-shared unit 539 to the vertical signal line 543. A state in which one pixel circuit 210 is connected to multiple pixels 541 and the pixel signals of these multiple pixels 541 are output in a time-division manner by one pixel circuit 210 is said to be "multiple pixels 541 sharing one pixel circuit 210."

[0140] Pixels 541A, 541B, 541C, and 541D have common components. Hereinafter, in order to distinguish the components of pixels 541A, 541B, 541C, and 541D from one another, the identification number 1 is added to the end of the reference numeral for the component of pixel 541A, the identification number 2 is added to the end of the reference numeral for the component of pixel 541B, the identification number 3 is added to the end of the reference numeral for the component of pixel 541C, and the identification number 4 is added to the end of the reference numeral for the component of pixel 541D. When it is not necessary to distinguish the components of pixels 541A, 541B, 541C, and 541D from one another, the identification numbers added to the end of the reference numerals for the components of pixels 541A, 541B, 541C, and 541D are omitted.

[0141] Each of the pixels 541A, 541B, 541C, and 541D includes, for example, a photodiode PD, a transfer transistor TR electrically connected to the photodiode PD, and a floating diffusion FD electrically connected to the transfer transistor TR. The cathode of the photodiode PD (PD1, PD2, PD3, and PD4) is electrically connected to the source of the transfer transistor TR, and the anode is electrically connected to a reference potential line (e.g., ground). The photodiode PD photoelectrically converts incident light and generates a charge corresponding to the amount of light received. The transfer transistors TR (transfer transistors TR1, TR2, TR3, and TR4) are, for example, n-type complementary metal oxide semiconductor (CMOS) transistors. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate is electrically connected to a drive signal line. This drive signal line is one of multiple row drive signal lines 542 (see FIG. 48) connected to one pixel sharing unit 539. The transfer transistor TR transfers the charge generated in the photodiode PD to the floating diffusion FD. The floating diffusion FD (floating diffusions FD1, FD2, FD3, and FD4) is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding means that temporarily holds the charge transferred from the photodiode PD, and is also a charge-to-voltage conversion means that generates a voltage according to the amount of charge.

[0142] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one pixel-shared unit 539 are electrically connected to each other and to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to a drive signal line. This drive signal line is one of multiple row drive signal lines 542 connected to one pixel-shared unit 539. The drain of the reset transistor RST is connected to a power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. This drive signal line is one of multiple row drive signal lines 542 connected to one pixel-shared unit 539. The gate of the amplification transistor AMP is connected to the floating diffusion FD, the drain of the amplification transistor AMP is connected to the power supply line VDD, and the source of the amplification transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to a vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. This drive signal line is part of a plurality of row drive signal lines 542 connected to one pixel sharing unit 539 .

[0143] When the transfer transistor TR is turned on, it transfers the charge of the photodiode PD to the floating diffusion FD. The gate (transfer gate TG) of the transfer transistor TR includes, for example, a so-called vertical electrode, and as shown in FIG. 53, extends from the surface of the semiconductor layer (semiconductor layer 100S in FIG. 53) to a depth reaching the PD. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is turned on, it resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplification transistor AMP generates, as the pixel signal, a signal with a voltage corresponding to the level of the charge held in the floating diffusion FD. The amplification transistor AMP is connected to a vertical signal line 543 via the selection transistor SEL. In the column signal processing unit 550, this amplification transistor AMP forms a source follower together with a load circuit unit (see FIG. 48) connected to the vertical signal line 543. When the selection transistor SEL is turned on, the amplification transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing unit 550 via the vertical signal line 543. The reset transistor RST, the amplification transistor AMP, and the selection transistor SEL are, for example, N-type CMOS transistors.

[0144] The FD conversion gain switching transistor FDG is used to change the gain of charge-to-voltage conversion in the floating diffusion FD. Generally, pixel signals are small when shooting in dark locations. Based on Q = CV, if the capacitance (FD capacitance C) of the floating diffusion FD is large during charge-to-voltage conversion, the V when converted to voltage by the amplifier transistor AMP will be small. On the other hand, in bright locations, pixel signals are large, so if the FD capacitance C is not large, the floating diffusion FD cannot fully absorb the charge from the photodiode PD. Furthermore, the FD capacitance C must be large so that the V when converted to voltage by the amplifier transistor AMP does not become too large (in other words, to reduce it). Given these factors, when the FD conversion gain switching transistor FDG is turned on, the gate capacitance of the FD conversion gain switching transistor FDG increases, increasing the overall FD capacitance C. On the other hand, when the FD conversion gain switching transistor FDG is turned off, the overall FD capacitance C decreases. In this way, by switching the FD conversion gain switching transistor FDG on and off, the FD capacitance C can be varied, thereby changing the conversion efficiency. The FD conversion gain switching transistor FDG is, for example, an N-type CMOS transistor.

[0145] It is also possible to configure the pixel circuit 210 without the FD conversion gain switching transistor FDG. In this case, for example, the pixel circuit 210 is configured with three transistors, for example, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST. The pixel circuit 210 has at least one pixel transistor, for example, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG.

[0146] The selection transistor SEL may be provided between the power supply line VDD and the amplification transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power supply line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplification transistor AMP, and the gate of the selection transistor SEL is electrically connected to a row drive signal line 542 (see FIG. 48). The source of the amplification transistor AMP (the output terminal of the pixel circuit 210) is electrically connected to a vertical signal line 543, and the gate of the amplification transistor AMP is electrically connected to the source of the reset transistor RST. Although not shown, the number of pixels 541 sharing one pixel circuit 210 may be other than four. For example, two or eight pixels 541 may share one pixel circuit 210.

[0147] FIG. 52 shows an example of a connection between multiple pixel-sharing units 539 and vertical signal lines 543. For example, four pixel-sharing units 539 arranged in a column direction are divided into four groups, and a vertical signal line 543 is connected to each of the four groups. For simplicity of explanation, FIG. 52 shows an example in which each of the four groups includes one pixel-sharing unit 539. However, each of the four groups may include multiple pixel-sharing units 539. In this way, in the imaging device 1, the multiple pixel-sharing units 539 arranged in the column direction may be divided into groups including one or more pixel-sharing units 539. For example, a vertical signal line 543 and a column signal processing circuit 550 are connected to each of these groups, allowing pixel signals to be read out simultaneously from each group. Alternatively, in the imaging device 1, one vertical signal line 543 may be connected to multiple pixel-sharing units 539 arranged in a column direction. In this case, pixel signals are read out sequentially in a time-division manner from the multiple pixel-sharing units 539 connected to one vertical signal line 543.

[0148] [Specific Configuration of Imaging Device 1] FIG. 53 illustrates an example of a cross-sectional configuration perpendicular to the main surfaces of the first substrate 100, the second substrate 200, and the third substrate 300 of the imaging device 1. FIG. 53 is a schematic representation to facilitate understanding of the positional relationships of the components, and may differ from the actual cross section. In the imaging device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. The imaging device 1 further includes a light-receiving lens 401 on the back surface (light incident surface) of the first substrate 100. A color filter layer (not shown) may be provided between the light-receiving lens 401 and the first substrate 100. The light-receiving lens 401 is provided for each of the pixels 541A, 541B, 541C, and 541D, for example. The imaging device 1 is, for example, a back-illuminated imaging device. The imaging device 1 includes a pixel array section 540 located in the center and a peripheral section 540B located outside the pixel array section 540.

[0149] The first substrate 100 has, in order from the light receiving lens 401 side, an insulating film 111, a fixed charge film 112, a semiconductor layer 100S, and a wiring layer 100T. The semiconductor layer 100S is made of, for example, a silicon substrate. The semiconductor layer 100S has, for example, a p-well layer 115 in and near a part of the surface (the surface on the wiring layer 100T side), and an n-type semiconductor region 114 in the other region (a region deeper than the p-well layer 115). For example, the n-type semiconductor region 114 and the p-well layer 115 form a pn junction photodiode PD. The p-well layer 115 is a p-type semiconductor region.

[0150] Fig. 54A shows an example of the planar configuration of the first substrate 100. Fig. 54A mainly shows the planar configuration of the pixel isolation portion 117, photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR of the first substrate 100. The configuration of the first substrate 100 will be described using Fig. 54A together with Fig. 53.

[0151] A floating diffusion FD and a VSS contact region 118 are provided near the surface of the semiconductor layer 100S. The floating diffusion FD is composed of an n-type semiconductor region provided in the p-well layer 115. The floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of the pixels 541A, 541B, 541C, and 541D are provided close to each other in the center of the pixel shared unit 539 ( FIG. 54A ). As will be described in detail later, the four floating diffusions (floating diffusions FD1, FD2, FD3, and FD4) included in this shared unit 539 are electrically connected to each other via electrical connection means (pad portions 120, described later) within the first substrate 100 (more specifically, within the wiring layer 100T). Furthermore, the floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via electrical means (through electrodes 120E, which will be described later). In the second substrate 200 (more specifically, inside the wiring layer 200T), the floating diffusion FD is electrically connected by this electrical means to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG.

[0152] The VSS contact region 118 is a region electrically connected to the reference potential line VSS and is arranged apart from the floating diffusion FD. For example, in the pixels 541A, 541B, 541C, and 541D, the floating diffusion FD is arranged at one end of each pixel in the V direction, and the VSS contact region 118 is arranged at the other end (FIG. 54A). The VSS contact region 118 is formed of, for example, a p-type semiconductor region. The VSS contact region 118 is connected to, for example, a ground potential or a fixed potential. This supplies a reference potential to the semiconductor layer 100S.

[0153] The first substrate 100 is provided with a photodiode PD, a floating diffusion FD, a VSS contact region 118, and a transfer transistor TR. The photodiode PD, floating diffusion FD, VSS contact region 118, and transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front surface side of the semiconductor layer 100S (the side opposite the light incident surface, the second substrate 200 side). The transfer transistor TR has a transfer gate TG. The transfer gate TG includes, for example, a horizontal portion TGb facing the front surface of the semiconductor layer 100S and a vertical portion TGa provided within the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is in contact with the horizontal portion TGb, and the other end is provided within the n-type semiconductor region 114. By configuring the transfer transistor TR with such a vertical transistor, transfer failure of pixel signals is less likely to occur, and the readout efficiency of pixel signals can be improved.

[0154] The horizontal portion TGb of the transfer gate TG extends, for example, in the H direction from a position facing the vertical portion TGa toward the center of the pixel sharing unit 539 ( FIG. 54A ). This allows the H direction position of the through electrode (through electrode TGV described later) that reaches the transfer gate TG to be closer to the H direction positions of the through electrodes (through electrodes 120E and 121E described later) that are connected to the floating diffusion FD and the VSS contact region 118. For example, the multiple pixel sharing units 539 provided on the first substrate 100 have the same configuration ( FIG. 54A ).

[0155] The semiconductor layer 100S is provided with a pixel separator 117 that separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 is formed to extend in the normal direction of the semiconductor layer 100S (a direction perpendicular to the surface of the semiconductor layer 100S). The pixel separator 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from one another, and has, for example, a lattice-like planar shape (FIGS. 54A and 54B). The pixel separator 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from one another. The pixel separator 117 includes, for example, a light-shielding film 117A and an insulating film 117B. The light-shielding film 117A is made of, for example, tungsten (W). The insulating film 117B is provided between the light-shielding film 117A and the p-well layer 115 or the n-type semiconductor region 114. The insulating film 117B is made of, for example, silicon oxide (SiO). The pixel separating portion 117 has, for example, an FTI (Full Trench Isolation) structure and penetrates the semiconductor layer 100S. Although not shown, the pixel separating portion 117 is not limited to an FTI structure that penetrates the semiconductor layer 100S. For example, it may have a DTI (Deep Trench Isolation) structure that does not penetrate the semiconductor layer 100S. The pixel separating portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0156] The semiconductor layer 100S is provided with, for example, a first pinning region 113 and a second pinning region 116. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S and is disposed between the n-type semiconductor region 114 and the fixed charge film 112. The second pinning region 116 is provided on a side surface of the pixel separating section 117, specifically, between the pixel separating section 117 and the p-well layer 115 or the n-type semiconductor region 114. The first pinning region 113 and the second pinning region 116 are formed of, for example, a p-type semiconductor region.

[0157] A fixed charge film 112 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 111. An electric field induced by the fixed charge film 112 forms a first pinning region 113 of the hole accumulation layer at the interface on the light-receiving surface (back surface) side of the semiconductor layer 100S. This suppresses the generation of dark current due to the interface state on the light-receiving surface side of the semiconductor layer 100S. The fixed charge film 112 is formed, for example, from an insulating film having a negative fixed charge. Examples of materials for this insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, and tantalum oxide.

[0158] A light-shielding film 117A is provided between the fixed charge film 112 and the insulating film 111. This light-shielding film 117A may be provided continuously with the light-shielding film 117A that constitutes the pixel separating section 117. The light-shielding film 117A between the fixed charge film 112 and the insulating film 111 is selectively provided, for example, at a position facing the pixel separating section 117 in the semiconductor layer 100S. The insulating film 111 is provided so as to cover this light-shielding film 117A. The insulating film 111 is made of, for example, silicon oxide.

[0159] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has, from the semiconductor layer 100S side, an interlayer insulating film 119, pad portions 120 and 121, a passivation film 122, an interlayer insulating film 123, and a bonding film 124, in this order. The horizontal portion TGb of the transfer gate TG is provided in this wiring layer 100T, for example. The interlayer insulating film 119 is provided over the entire surface of the semiconductor layer 100S and is in contact with the semiconductor layer 100S. The interlayer insulating film 119 is made of, for example, a silicon oxide film. Note that the configuration of the wiring layer 100T is not limited to the above, and may be any configuration including wiring and an insulating film.

[0160] FIG. 54B shows the planar configuration shown in FIG. 54A as well as the configuration of pad portions 120 and 121. Pad portions 120 and 121 are provided in selective regions on interlayer insulating film 119. Pad portion 120 is used to connect the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of pixels 541A, 541B, 541C, and 541D to one another. Pad portion 120 is disposed, for example, for each pixel sharing unit 539 in the center of pixel sharing unit 539 in plan view ( FIG. 54B ). This pad portion 120 is disposed so as to straddle pixel separating portion 117 and overlap at least a portion of each of floating diffusions FD1, FD2, FD3, and FD4 ( FIGS. 53 and 54B ). Specifically, the pad section 120 is formed in a region that overlaps, in a direction perpendicular to the surface of the semiconductor layer 100S, at least a portion of each of the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) that share the pixel circuit 210 and at least a portion of the pixel isolation section 117 formed between the photodiodes PD (photodiodes PD1, PD2, PD3, and PD4) that share the pixel circuit 210. The interlayer insulating film 119 is provided with connection vias 120C for electrically connecting the pad section 120 to the floating diffusions FD1, FD2, FD3, and FD4. The connection vias 120C are provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a portion of the pad section 120 is embedded in the connection vias 120C, thereby electrically connecting the pad section 120 to the floating diffusions FD1, FD2, FD3, and FD4.

[0161] The pad portion 121 is used to connect the multiple VSS contact regions 118 to each other. For example, the pad portion 121 electrically connects the VSS contact regions 118 provided in pixels 541C and 541D of one pixel sharing unit 539 adjacent to each other in the V direction with the VSS contact regions 118 provided in pixels 541A and 541B of the other pixel sharing unit 539. The pad portion 121 is provided, for example, to straddle the pixel isolation portion 117 and is arranged to overlap at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is formed in a region that overlaps at least a portion of each of the multiple VSS contact regions 118 and at least a portion of the pixel isolation portion 117 formed between the multiple VSS contact regions 118 in a direction perpendicular to the surface of the semiconductor layer 100S. The interlayer insulating film 119 is provided with a connection via 121C for electrically connecting the pad portion 121 and the VSS contact region 118. The connection via 121C is provided in each of the pixels 541A, 541B, 541C, and 541D. For example, a part of the pad portion 121 is embedded in the connection via 121C, thereby electrically connecting the pad portion 121 to the VSS contact region 118. For example, the pad portions 120 and 121 of each of the multiple pixel sharing units 539 aligned in the V direction are arranged at approximately the same position in the H direction ( FIG. 54B ).

[0162] By providing the pad section 120, it is possible to reduce the amount of wiring for connecting each floating diffusion FD to the pixel circuit 210 (for example, the gate electrode of the amplification transistor AMP) across the entire chip. Similarly, by providing the pad section 121, it is possible to reduce the amount of wiring for supplying potential to each VSS contact region 118 across the entire chip. This makes it possible to reduce the area of ​​the entire chip, suppress electrical interference between wiring in miniaturized pixels, and / or reduce costs by reducing the number of components.

[0163] The pad portions 120 and 121 can be provided at desired positions on the first substrate 100 and the second substrate 200. Specifically, the pad portions 120 and 121 can be provided on either the wiring layer 100T or the insulating region 2112 of the semiconductor layer 200S. When provided on the wiring layer 100T, the pad portions 120 and 121 may be in direct contact with the semiconductor layer 100S. Specifically, the pad portions 120 and 121 may be configured to be directly connected to at least a portion of each of the floating diffusion FD and / or the VSS contact region 118. Alternatively, connection vias 120C and 121C may be provided from each of the floating diffusion FD and / or the VSS contact region 118 connected to the pad portions 120 and 121, and the pad portions 120 and 121 may be provided at desired positions in the insulating region 2112 of the wiring layer 100T and the semiconductor layer 200S.

[0164] In particular, when the pad portions 120, 121 are provided in the wiring layer 100T, it is possible to reduce the wiring connected to the floating diffusion FD and / or the VSS contact region 118 in the insulating region 212 of the semiconductor layer 200S. This makes it possible to reduce the area of ​​the insulating region 212, in the second substrate 200 on which the pixel circuit 210 is formed, for forming the through wiring for connecting the floating diffusion FD to the pixel circuit 210. This makes it possible to ensure a large area for the second substrate 200 on which the pixel circuit 210 is formed. By ensuring the area for the pixel circuit 210, it is possible to form a large pixel transistor, which can contribute to improving image quality by reducing noise, etc.

[0165] In particular, when an FTI structure is used for the pixel separation section 117, it is preferable to provide a floating diffusion FD and / or a VSS contact region 118 in each pixel 541, and therefore, by using the configuration of the pad sections 120, 121, the wiring connecting the first substrate 100 and the second substrate 200 can be significantly reduced.

[0166] 54B, for example, pad portions 120 to which a plurality of floating diffusions FD are connected and pad portions 121 to which a plurality of VSS contacts 118 are connected are alternately arranged linearly in the V direction. Furthermore, the pad portions 120 and 121 are formed in positions surrounded by a plurality of photodiodes PD, a plurality of transfer gates TG, and a plurality of floating diffusions FD. This allows elements other than the floating diffusions FD and VSS contact regions 118 to be freely arranged on the first substrate 100 on which a plurality of elements are formed, thereby improving the efficiency of the layout of the entire chip. Furthermore, symmetry is ensured in the layout of the elements formed in each pixel shared unit 539, thereby suppressing variations in the characteristics of each pixel 541.

[0167] The pad portions 120 and 121 are made of, for example, polysilicon (Poly Si), more specifically, doped polysilicon to which impurities are added. The pad portions 120 and 121 are preferably made of a highly heat-resistant conductive material such as polysilicon, tungsten (W), titanium (Ti), or titanium nitride (TiN). This makes it possible to form the pixel circuit 210 after bonding the semiconductor layer 200S of the second substrate 200 to the first substrate 100. The reason for this will be explained below. In the following explanation, the method of forming the pixel circuit 210 after bonding the semiconductor layer 200S of the first substrate 100 to the semiconductor layer 200S of the second substrate 200 will be referred to as the first manufacturing method.

[0168] Here, it is also conceivable to form the pixel circuits 210 on the second substrate 200 and then bond this to the first substrate 100 (hereinafter referred to as a second manufacturing method). In this second manufacturing method, electrodes for electrical connection are formed in advance on the surface of the first substrate 100 (the surface of the wiring layer 100T) and the surface of the second substrate 200 (the surface of the wiring layer 200T). When the first substrate 100 and the second substrate 200 are bonded together, the electrodes for electrical connection formed on the surface of the first substrate 100 and the surface of the second substrate 200 simultaneously come into contact with each other. This forms an electrical connection between the wiring included in the first substrate 100 and the wiring included in the second substrate 200. Therefore, by configuring the imaging device 1 using the second manufacturing method, it is possible to manufacture the imaging device using an appropriate process depending on the configuration of the first substrate 100 and the second substrate 200, for example, and thus a high-quality, high-performance imaging device can be manufactured.

[0169] In this second manufacturing method, when bonding the first substrate 100 and the second substrate 200 together, alignment errors may occur due to the manufacturing equipment used for bonding. Furthermore, the first substrate 100 and the second substrate 200 each have a diameter of, for example, several tens of centimeters. When bonding the first substrate 100 and the second substrate 200 together, expansion and contraction of the substrates may occur in microscopic regions of each of the first substrate 100 and the second substrate 200. This expansion and contraction of the substrates is caused by a slight difference in the timing at which the substrates contact each other. Due to this expansion and contraction of the first substrate 100 and the second substrate 200, errors may occur in the positions of the electrical connection electrodes formed on the surfaces of the first substrate 100 and the second substrate 200, respectively. In the second manufacturing method, it is preferable to take measures to ensure that the electrodes of the first substrate 100 and the second substrate 200 contact each other even if such errors occur. Specifically, at least one, and preferably both, of the electrodes of the first substrate 100 and the second substrate 200 are made large in consideration of the above-mentioned error. Therefore, when the second manufacturing method is used, for example, the size (size in the substrate planar direction) of the electrode formed on the surface of the first substrate 100 or the second substrate 200 becomes larger than the size of the internal electrode extending in the thickness direction from the inside of the first substrate 100 or the second substrate 200 to the surface.

[0170] On the other hand, by forming the pad portions 120, 121 from a heat-resistant conductive material, the first manufacturing method can be used. In the first manufacturing method, after forming the first substrate 100 including the photodiode PD, the transfer transistor TR, etc., the first substrate 100 and the second substrate 200 (semiconductor layer 2000S) are bonded together. At this time, the second substrate 200 is in a state where patterns such as active elements and wiring layers that constitute the pixel circuits 210 have not yet been formed. Because the second substrate 200 is in a state before patterns are formed, even if an error occurs in the bonding position when the first substrate 100 and the second substrate 200 are bonded together, this bonding error will not cause an error in alignment between the patterns of the first substrate 100 and the second substrate 200. This is because the pattern of the second substrate 200 is formed after the first substrate 100 and the second substrate 200 are bonded together. It should be noted that when a pattern is formed on the second substrate, for example, an exposure apparatus for pattern formation uses the pattern formed on the first substrate as a target for alignment when forming the pattern. For the reasons described above, errors in the bonding position between the first substrate 100 and the second substrate 200 do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method. For the same reason, errors caused by expansion and contraction of the substrates in the second manufacturing method do not pose a problem in manufacturing the imaging device 1 in the first manufacturing method.

[0171] In the first manufacturing method, after bonding the first substrate 100 and the second substrate 200 (semiconductor layer 200S) together in this manner, active elements are formed on the second substrate 200. Then, through electrodes 120E, 121E and through electrodes TGV (FIG. 53) are formed. In forming these through electrodes 120E, 121E, and TGV, for example, a pattern of the through electrodes is formed from above the second substrate 200 using reduced projection exposure with an exposure device. Because reduced projection exposure is used, even if an error occurs in the alignment between the second substrate 200 and the exposure device, the magnitude of the error in the second substrate 200 is only a fraction (the reciprocal of the reduced projection magnification) of the error in the second manufacturing method. Therefore, by configuring the imaging device 1 using the first manufacturing method, it becomes easier to align the elements formed on the first substrate 100 and the second substrate 200, and a high-quality, high-performance imaging device can be manufactured.

[0172] The imaging device 1 manufactured using such a first manufacturing method has different characteristics from the imaging device manufactured using the second manufacturing method. Specifically, in the imaging device 1 manufactured using the first manufacturing method, for example, the through electrodes 120E, 121E, and TGV have a substantially constant thickness (size in the substrate planar direction) from the second substrate 200 to the first substrate 100. Alternatively, when the through electrodes 120E, 121E, and TGV have a tapered shape, the tapered shape has a constant inclination. The imaging device 1 having such through electrodes 120E, 121E, and TGV facilitates miniaturization of the pixels 541.

[0173] Here, when the imaging device 1 is manufactured using the first manufacturing method, the first substrate 100 and the second substrate 200 (semiconductor layer 200S) are bonded together, and then active elements are formed on the second substrate 200. Therefore, the first substrate 100 is also affected by the heat treatment required for forming the active elements. For this reason, as described above, it is preferable to use a conductive material with high heat resistance for the pad portions 120, 121 provided on the first substrate 100. For example, it is preferable to use a material with a higher melting point (i.e., higher heat resistance) for the pad portions 120, 121 than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200. For example, a conductive material with high heat resistance, such as doped polysilicon, tungsten, titanium, or titanium nitride, is used for the pad portions 120, 121. This makes it possible to manufacture the imaging device 1 using the first manufacturing method.

[0174] The passivation film 122 is provided over the entire surface of the semiconductor layer 100S so as to cover, for example, the pad portions 120 and 121 (FIG. 53). The passivation film 122 is made of, for example, a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 with the passivation film 122 in between. This interlayer insulating film 123 is provided over the entire surface of the semiconductor layer 100S. The interlayer insulating film 123 is made of, for example, a silicon oxide (SiO) film. The bonding film 124 is provided on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. That is, the bonding film 124 is in contact with the second substrate 200. This bonding film 124 is provided over the entire main surface of the first substrate 100. The bonding film 124 is made of, for example, a silicon nitride film.

[0175] The light receiving lens 401 faces the semiconductor layer 100S with the fixed charge film 112 and the insulating film 111 interposed therebetween (FIG. 53). The light receiving lens 401 is provided at a position facing the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D, for example.

[0176] The second substrate 200 has, from the first substrate 100 side, a semiconductor layer 200S and a wiring layer 200T, in this order. The semiconductor layer 200S is made of a silicon substrate. A well region 211 is provided in the semiconductor layer 200S across the thickness direction. The well region 211 is, for example, a p-type semiconductor region. The second substrate 200 is provided with a pixel circuit 210 arranged for each pixel sharing unit 539. The pixel circuit 210 is provided, for example, on the front surface side (the wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is bonded to the first substrate 100 such that the back surface side (the semiconductor layer 200S side) of the second substrate 200 faces the front surface side (the wiring layer 100T side) of the first substrate 100. In other words, the second substrate 200 is bonded to the first substrate 100 face-to-back.

[0177] 55 to 59 schematically show an example of the planar configuration of the second substrate 200. FIG. 55 shows the configuration of the pixel circuit 210 provided near the surface of the semiconductor layer 200S. FIG. 56 schematically shows the configuration of the wiring layer 200T (specifically, the first wiring layer W1 described below), the semiconductor layer 200S connected to the wiring layer 200T, and each part of the first substrate 100. FIGS. 57 to 59 show an example of the planar configuration of the wiring layer 200T. The configuration of the second substrate 200 will be described below using FIGS. 55 to 59 along with FIG. 53. In FIGS. 55 and 56, the outline of the photodiode PD (the boundary between the pixel isolation portion 117 and the photodiode PD) is shown by a dashed line, and the boundary between the semiconductor layer 200S and the element isolation region 213 or the insulating region 214 in the portion overlapping the gate electrode of each transistor constituting the pixel circuit 210 is shown by a dotted line. In the portion overlapping the gate electrode of the amplification transistor AMP, a boundary between the semiconductor layer 200S and the isolation region 213 and a boundary between the isolation region 213 and the insulating region 213 are provided on one side in the channel width direction.

[0178] The second substrate 200 is provided with an insulating region 212 that divides the semiconductor layer 200S and an element isolation region 213 provided in a part of the semiconductor layer 200S in the thickness direction (FIG. 53). For example, in the insulating region 212 provided between two pixel circuits 210 adjacent to each other in the H direction, the through electrodes 120E and 121E and through electrodes TGVs (through electrodes TGV1, TGV2, TGV3, TGV4) of two pixel sharing units 539 connected to the two pixel circuits 210 are arranged (FIG. 56).

[0179] The insulating region 212 has approximately the same thickness as the semiconductor layer 200S (FIG. 53). The semiconductor layer 200S is divided by this insulating region 212. The through electrodes 120E, 121E and the through electrodes TGV are arranged in this insulating region 212. The insulating region 212 is made of, for example, silicon oxide.

[0180] The through electrodes 120E, 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper ends of the through electrodes 120E, 121E are connected to the wiring (first wiring W1, second wiring W2, third wiring W3, and fourth wiring W4 described below) of the wiring layer 200T. The through electrodes 120E, 121E are provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122, and the lower ends thereof are connected to the pad portions 120, 121 (FIG. 53). The through electrode 120E serves to electrically connect the pad portion 120 and the pixel circuit 210. That is, the floating diffusion FD of the first substrate 100 is electrically connected to the pixel circuit 210 of the second substrate 200 by the through electrode 120E. The through electrode 121E is for electrically connecting the pad portion 121 and the reference potential line VSS of the wiring layer 200T. That is, the through electrode 121E electrically connects the VSS contact region 118 of the first substrate 100 to the reference potential line VSS of the second substrate 200.

[0181] The through electrode TGV is provided to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring of the wiring 200T. This through electrode TGV is provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, the passivation film 122, and the interlayer insulating film 119, and its lower end is connected to the transfer gate TG (FIG. 53). Such a through electrode TGV is intended to electrically connect the transfer gate TG (transfer gates TG1, TG2, TG3, TG4) of each of the pixels 541A, 541B, 541C, 541D to the wiring of the wiring layer 200T (part of the row drive signal line 542, specifically, the wiring TRG1, TRG2, TRG3, TRG4 in FIG. 58 described later). That is, the through-electrode TGV electrically connects the transfer gate TG of the first substrate 100 to the wiring TRG of the second substrate 200, and a drive signal is sent to each of the transfer transistors TR (transfer transistors TR1, TR2, TR3, TR4).

[0182] The insulating region 212 is a region for providing the through electrodes 120E, 121E and through electrodes TGV for electrically connecting the first substrate 100 and the second substrate 200, while insulating them from the semiconductor layer 200S. For example, the through electrodes 120E, 121E and through electrodes TGV (through electrodes TGV1, TGV2, TGV3, TGV4) connected to two pixel circuits 210 (shared units 539) adjacent to each other in the H direction are arranged in the insulating region 212. The insulating region 212 is provided, for example, extending in the V direction (FIGS. 55 and 56). Here, by devising the position of the horizontal portion TGb of the transfer gate TG, the position of the through electrode TGV in the H direction is closer to the position of the through electrodes 120E, 121E in the H direction than the position of the vertical portion TGa (FIGS. 54A and 56). For example, the through electrode TGV is disposed at approximately the same position as the through electrodes 120E, 120E in the H direction. This allows the through electrodes 120E, 121E and the through electrode TGV to be provided together in an insulating region 212 extending in the V direction. As another arrangement example, it is possible to provide the horizontal portion TGb only in the region overlapping the vertical portion TGa. In this case, the through electrode TGV is formed approximately directly above the vertical portion TGa, and the through electrode TGV is disposed, for example, in the approximately center of each pixel 541 in the H and V directions. In this case, the position of the through electrode TGV in the H direction is significantly different from the position of the through electrodes 120E, 121E in the H direction. For example, an insulating region 212 is provided around the through electrodes TGV and the through electrodes 120E, 121E to electrically insulate them from the adjacent semiconductor layer 200S. When the position of the through electrode TGV in the H direction is significantly different from the position of the through electrodes 120E, 121E in the H direction, it is necessary to provide an insulating region 212 independently around each of the through electrodes 120E, 121E, and TGV. This results in the semiconductor layer 200S being divided into small pieces. In contrast, a layout in which the through electrodes 120E, 121E and the through electrode TGV are collectively arranged in the insulating region 212 extending in the V direction can increase the size of the semiconductor layer 200S in the H direction. This makes it possible to secure a large area for forming semiconductor elements in the semiconductor layer 200S.This makes it possible to increase the size of the amplification transistor AMP and suppress noise, for example.

[0183] As described with reference to FIG. 51, the pixel-sharing unit 539 has a structure in which the floating diffusions FD provided in each of the plurality of pixels 541 are electrically connected to each other, and these plurality of pixels 541 share one pixel circuit 210. The floating diffusions FD are electrically connected to each other by pad portions 120 provided on the first substrate 100 (FIGS. 53 and 54B). The electrical connection portion (pad portion 120) provided on the first substrate 100 and the pixel circuit 210 provided on the second substrate 200 are electrically connected via one through-electrode 120E. As another structural example, it is also possible to provide the electrical connection portion between the floating diffusions FD on the second substrate 200. In this case, the pixel-sharing unit 539 is provided with four through-electrodes connected to the floating diffusions FD1, FD2, FD3, and FD4, respectively. Therefore, in the second substrate 200, the number of through electrodes penetrating the semiconductor layer 200S increases, and the insulating region 212 that insulates the periphery of these through electrodes becomes larger. In contrast, the structure in which the pad portion 120 is provided on the first substrate 100 (FIGS. 53 and 54B) reduces the number of through electrodes and makes it possible to reduce the insulating region 212. This makes it possible to secure a large area for forming a semiconductor element in the semiconductor layer 200S. This makes it possible, for example, to increase the size of the amplification transistor AMP and suppress noise.

[0184] The element isolation region 213 is provided on the surface side of the semiconductor layer 200S. The element isolation region 213 has an STI (Shallow Trench Isolation) structure. In this element isolation region 213, the semiconductor layer 200S is dug in the thickness direction (perpendicular to the main surface of the second substrate 200), and an insulating film is buried in this dug portion. This insulating film is made of, for example, silicon oxide. The element isolation region 213 separates the multiple transistors that make up the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S (specifically, the well region 211) extends below the element isolation region 213 (deep in the semiconductor layer 200S).

[0185] Here, with reference to Figures 54A, 54B, and 55, the difference between the outer shape (outer shape in the substrate planar direction) of the pixel sharing unit 539 on the first substrate 100 and the outer shape of the pixel sharing unit 539 on the second substrate 200 will be described.

[0186] In the imaging device 1, pixel-sharing units 539 are provided across both the first substrate 100 and the second substrate 200. For example, the outer shape of the pixel-sharing units 539 provided on the first substrate 100 and the outer shape of the pixel-sharing units 539 provided on the second substrate 200 are different from each other.

[0187] 54A and 54B, the outlines of pixels 541A, 541B, 541C, and 541D are represented by dashed dotted lines, and the outline shape of pixel-sharing unit 539 is represented by thick lines. For example, pixel-sharing unit 539 of first substrate 100 is composed of two pixels 541 (pixels 541A and 541B) arranged adjacent to each other in the H direction and two pixels 541 (pixels 541C and 541D) arranged adjacent to each other in the V direction. That is, pixel-sharing unit 539 of first substrate 100 is composed of four pixels 541 arranged adjacently in two rows and two columns, and pixel-sharing unit 539 of first substrate 100 has a substantially square outline shape. In the pixel array section 540, such pixel sharing units 539 are arranged adjacent to each other at a pitch of two pixels in the H direction (a pitch equivalent to two pixels 541) and at a pitch of two pixels in the V direction (a pitch equivalent to two pixels 541).

[0188] 55 and 56, the outlines of the pixels 541A, 541B, 541C, and 541D are represented by dashed dotted lines, and the outline shape of the pixel-sharing unit 539 is represented by a thick line. For example, the outline shape of the pixel-sharing unit 539 of the second substrate 200 is smaller in the H direction than the pixel-sharing unit 539 of the first substrate 100, and is larger in the V direction than the pixel-sharing unit 539 of the first substrate 100. For example, the pixel-sharing unit 539 of the second substrate 200 is formed to have a size (area) equivalent to one pixel in the H direction, and is formed to have a size equivalent to four pixels in the V direction. In other words, the pixel-sharing unit 539 of the second substrate 200 is formed to have a size equivalent to adjacent pixels arranged in one row and four columns, and the pixel-sharing unit 539 of the second substrate 200 has a substantially rectangular outline shape.

[0189] For example, in each pixel circuit 210, the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG are arranged in this order in the V direction ( FIG. 55 ). By providing each pixel circuit 210 with a substantially rectangular outer shape as described above, it is possible to arrange four transistors (the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG) side by side in one direction (the V direction in FIG. 55 ). This allows the drain of the amplification transistor AMP and the drain of the reset transistor RST to share a single diffusion region (a diffusion region connected to the power supply line VDD). For example, it is also possible to provide the formation region of each pixel circuit 210 in a substantially square shape (see FIG. 68 , described later). In this case, two transistors are arranged along one direction, making it difficult to share a single diffusion region for the drain of the amplification transistor AMP and the drain of the reset transistor RST. Therefore, providing the formation region of the pixel circuit 210 in a substantially rectangular shape makes it easier to arrange the four transistors closely together, thereby reducing the formation region of the pixel circuit 210. In other words, it is possible to miniaturize pixels. Furthermore, when it is not necessary to reduce the area in which the pixel circuit 210 is formed, it is possible to increase the area in which the amplification transistor AMP is formed and suppress noise.

[0190] For example, near the surface of the semiconductor layer 200S, in addition to the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG, a VSS contact region 218 connected to the reference potential line VSS is provided. The VSS contact region 218 is configured, for example, by a p-type semiconductor region. The VSS contact region 218 is electrically connected to the VSS contact region 118 of the first substrate 100 (semiconductor layer 100S) via the wiring of the wiring layer 200T and the through-electrode 121E. This VSS contact region 218 is provided, for example, at a position adjacent to the source of the FD conversion gain switching transistor FDG with the element isolation region 213 interposed therebetween (FIG. 55).

[0191] Next, with reference to Figures 54B and 55, the positional relationship between the pixel-sharing units 539 provided on the first substrate 100 and the pixel-sharing units 539 provided on the second substrate 200 will be described. For example, of two pixel-sharing units 539 aligned in the V direction on the first substrate 100, one pixel-sharing unit 539 (for example, the upper side of the paper in Figure 54B) is connected to one pixel-sharing unit 539 (for example, the left side of the paper in Figure 55) of two pixel-sharing units 539 aligned in the H direction on the second substrate 200. For example, of the two pixel-sharing units 539 aligned in the V direction on the first substrate 100, the other pixel-sharing unit 539 (for example, the lower side of the paper in Figure 54B) is connected to the other pixel-sharing unit 539 (for example, the right side of the paper in Figure 55) of two pixel-sharing units 539 aligned in the H direction on the second substrate 200.

[0192] For example, of two pixel sharing units 539 lined up in the H direction on the second substrate 200, the internal layout (arrangement of transistors, etc.) of one pixel sharing unit 539 is substantially equal to a layout obtained by inverting the internal layout of the other pixel sharing unit 539 in the V and H directions. The effects obtained by this layout will be described below.

[0193] In two pixel-sharing units 539 aligned in the V direction on the first substrate 100, each pad section 120 is disposed at the center of the external shape of the pixel-sharing unit 539, i.e., the center of the pixel-sharing unit 539 in the V and H directions ( FIG. 54B ). On the other hand, the pixel-sharing unit 539 on the second substrate 200 has a substantially rectangular external shape that is long in the V direction as described above, and therefore, for example, the amplification transistor AMP connected to the pad section 120 is disposed at a position shifted upward in the plane of the drawing from the center of the pixel-sharing unit 539 in the V direction. For example, when two pixel-sharing units 539 aligned in the H direction on the second substrate 200 have the same internal layout, the distance between the amplification transistor AMP of one pixel-sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel-sharing unit 539 on the upper side in the plane of the drawing in FIG. 54 ) is relatively short. However, the distance between the amplification transistor AMP of the other pixel sharing unit 539 and the pad section 120 (for example, the pad section 120 of the pixel sharing unit 539 on the lower side of the paper surface of FIG. 54) becomes longer. This increases the area of ​​the wiring required to connect this amplification transistor AMP and the pad section 120, which may complicate the wiring layout of the pixel sharing unit 539. This may affect the miniaturization of the imaging device 1.

[0194] In contrast, by inverting the internal layouts of two pixel-sharing units 539 aligned in the H direction of the second substrate 200 with respect to each other at least in the V direction, it is possible to shorten the distance between the amplification transistors AMP and the pad section 120 of both of these two pixel-sharing units 539. Therefore, compared to a configuration in which the internal layouts of two pixel-sharing units 539 aligned in the H direction of the second substrate 200 are the same, it is easier to miniaturize the imaging device 1. Note that the planar layout of each of the multiple pixel-sharing units 539 of the second substrate 200 is symmetrical within the range shown in FIG. 55, but becomes asymmetrical when the layout of the first wiring layer W1 shown in FIG. 56, which will be described later, is included.

[0195] Furthermore, it is preferable that the internal layouts of two pixel sharing units 539 aligned in the H direction on the second substrate 200 are also inverted relative to each other in the H direction. The reason for this will be explained below. As shown in FIG. 56 , the two pixel sharing units 539 aligned in the H direction on the second substrate 200 are respectively connected to the pad portions 120, 121 on the first substrate 100. For example, the pad portions 120, 121 are disposed in the central portions in the H direction of the two pixel sharing units 539 aligned in the H direction on the second substrate 200 (between the two pixel sharing units 539 aligned in the H direction). Therefore, by inverting the internal layouts of the two pixel sharing units 539 aligned in the H direction on the second substrate 200 relative to each other in the H direction, it is possible to reduce the distance between each of the multiple pixel sharing units 539 on the second substrate 200 and the pad portions 120, 121. That is, it becomes easier to miniaturize the imaging device 1.

[0196] Furthermore, the positions of the outlines of the pixel-sharing units 539 on the second substrate 200 do not have to align with the positions of any of the outlines of the pixel-sharing units 539 on the first substrate 100. For example, of two pixel-sharing units 539 aligned in the H direction on the second substrate 200, in one pixel-sharing unit 539 (for example, on the left side of the paper in FIG. 56 ), the outline on one side in the V direction (for example, the upper side of the paper in FIG. 56 ) is arranged outside the outline on one side in the V direction of the corresponding pixel-sharing unit 539 on the first substrate 100 (for example, the upper side of the paper in FIG. 54B ). Furthermore, of two pixel-sharing units 539 aligned in the H direction on the second substrate 200, in the other pixel-sharing unit 539 (for example, on the right side of the paper in FIG. 56 ), the outline on the other side in the V direction (for example, the lower side of the paper in FIG. 56 ) is arranged outside the outline on the other side in the V direction of the corresponding pixel-sharing unit 539 on the first substrate 100 (for example, the lower side of the paper in FIG. 54B ). In this way, by arranging the pixel sharing unit 539 of the second substrate 200 and the pixel sharing unit 539 of the first substrate 100 together, it is possible to shorten the distance between the amplification transistor AMP and the pad section 120. Therefore, it becomes easier to miniaturize the imaging device 1.

[0197] Furthermore, the positions of the outlines of the multiple pixel sharing units 539 on the second substrate 200 do not have to be aligned with each other. For example, two pixel sharing units 539 aligned in the H direction on the second substrate 200 are arranged with the positions of the outlines in the V direction shifted. This makes it possible to shorten the distance between the amplification transistor AMP and the pad section 120. This makes it easier to miniaturize the imaging device 1.

[0198] 54B and 56, the repeated arrangement of pixel-sharing units 539 in the pixel array section 540 will be described. The pixel-sharing unit 539 of the first substrate 100 has a size equivalent to two pixels 541 in the H direction and a size equivalent to two pixels 541 in the V direction (FIG. 54B). For example, in the pixel array section 540 of the first substrate 100, pixel-sharing units 539 each having a size equivalent to four pixels 541 are repeatedly arranged adjacent to each other at a two-pixel pitch in the H direction (a pitch equivalent to two pixels 541) and at a two-pixel pitch in the V direction (a pitch equivalent to two pixels 541). Alternatively, the pixel array section 540 of the first substrate 100 may be provided with a pair of pixel-sharing units 539 in which two pixel-sharing units 539 are arranged adjacent to each other in the V direction. In the pixel array section 540 of the first substrate 100, for example, this pair of pixel-sharing units 539 is repeatedly arranged adjacent to each other at a two-pixel pitch in the H direction (a pitch equivalent to two pixels 541) and at a four-pixel pitch in the V direction (a pitch equivalent to four pixels 541). The pixel-sharing unit 539 of the second substrate 200 has a size equivalent to one pixel 541 in the H direction and a size equivalent to four pixels 541 in the V direction ( FIG. 56 ). For example, the pixel array section 540 of the second substrate 200 is provided with a pair of pixel-sharing units 539, each including two pixel-sharing units 539 each having a size equivalent to four pixels 541. The pixel-sharing units 539 are arranged adjacent to each other in the H direction and offset in the V direction. In the pixel array section 540 of the second substrate 200, for example, a pair of pixel-sharing units 539 are repeatedly arranged adjacent to each other with no gaps at a pitch of two pixels in the H direction (a pitch corresponding to two pixels 541) and at a pitch of four pixels in the V direction (a pitch corresponding to four pixels 541). By repeatedly arranging the pixel-sharing units 539 in this manner, it is possible to arrange the pixel-sharing units 539 without any gaps. This makes it easier to miniaturize the imaging device 1.

[0199] The amplification transistor AMP preferably has a three-dimensional structure, such as a Fin type (FIG. 53). This increases the effective gate width, making it possible to suppress noise. The selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG have, for example, a planar structure. The amplification transistor AMP may have a planar structure. Alternatively, the selection transistor SEL, reset transistor RST, or FD conversion gain switching transistor FDG may have a three-dimensional structure.

[0200] The wiring layer 200T includes, for example, a passivation film 221, an interlayer insulating film 222, and a plurality of wirings (a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, and a fourth wiring layer W4). The passivation film 221 is in contact with, for example, the surface of the semiconductor layer 200S and covers the entire surface of the semiconductor layer 200S. The passivation film 221 covers the gate electrodes of the selection transistor SEL, the amplification transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is provided between the passivation film 221 and the third substrate 300. The interlayer insulating film 222 separates the plurality of wirings (the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the fourth wiring layer W4). The interlayer insulating film 222 is made of, for example, silicon oxide.

[0201] The wiring layer 200T includes, for example, a first wiring layer W1, a second wiring layer W2, a third wiring layer W3, a fourth wiring layer W4, and contact portions 201 and 202 arranged in this order from the semiconductor layer 200S side, and these are insulated from each other by an interlayer insulating film 222. The interlayer insulating film 222 includes a plurality of connection portions connecting the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, or the fourth wiring layer W4 to the layers below them. The connection portions are formed by filling connection holes in the interlayer insulating film 222 with a conductive material. For example, the interlayer insulating film 222 includes a connection portion 218V connecting the first wiring layer W1 and the VSS contact region 218 of the semiconductor layer 200S. For example, the hole diameter of such connection portions connecting elements of the second substrate 200 is different from the hole diameters of the through electrodes 120E and 121E and the through electrodes TGV. Specifically, the diameter of the connection holes connecting the elements of the second substrate 200 is preferably smaller than the diameters of the through electrodes 120E, 121E and the through electrodes TGV. The reason for this is explained below. The depth of the connection portions (such as the connection portion 218V) provided in the wiring layer 200T is smaller than the depths of the through electrodes 120E, 121E and the through electrodes TGV. Therefore, it is easier to fill the connection holes with a conductive material in the connection portions than in the through electrodes 120E, 121E and the through electrodes TGV. Making the diameter of the connection portions smaller than the diameters of the through electrodes 120E, 121E and the through electrodes TGV makes it easier to miniaturize the imaging device 1.

[0202] For example, the first wiring layer W1 connects the through electrode 120E to the gate of the amplification transistor AMP and the source of the FD conversion gain switching transistor FDG (specifically, a connection hole reaching the source of the FD conversion gain switching transistor FDG). The first wiring layer W1 connects the through electrode 121E to the connection portion 218V, for example, thereby electrically connecting the VSS contact region 218 of the semiconductor layer 200S to the VSS contact region 118 of the semiconductor layer 100S.

[0203] Next, the planar configuration of the wiring layer 200T will be described with reference to Figures 57 to 59. Figure 57 shows an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2. Figure 58 shows an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3. Figure 59 shows an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4.

[0204] For example, the third wiring layer W3 includes wirings TRG1, TRG2, TRG3, TRG4, SELL, RSTL, and FDGL extending in the H direction (row direction) (FIG. 58). These wirings correspond to the plurality of row drive signal lines 542 described with reference to FIG. 51. The wirings TRG1, TRG2, TRG3, and TRG4 are for sending drive signals to the transfer gates TG1, TG2, TG3, and TG4, respectively. The wirings TRG1, TRG2, TRG3, and TRG4 are connected to the transfer gates TG1, TG2, TG3, and TG4 via the second wiring layer W2, the first wiring layer W1, and the through-electrode 120E, respectively. The wiring SELL is for sending drive signals to the gate of the selection transistor SEL, the wiring RSTL is for sending drive signals to the gate of the reset transistor RST, and the wiring FDGL is for sending drive signals to the gate of the FD conversion gain switching transistor FDG, respectively. The wirings SELL, RSTL, and FDGL are connected to the gates of the selection transistor SEL, reset transistor RST, and FD conversion gain switching transistor FDG, respectively, via the second wiring layer W2, the first wiring layer W1, and a connection portion.

[0205] For example, the fourth wiring layer W4 includes a power supply line VDD, a reference potential line VSS, and a vertical signal line 543 extending in the V direction (column direction) (FIG. 59). The power supply line VDD is connected to the drain of the amplifier transistor AMP and the drain of the reset transistor RST via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection portion. The reference potential line VSS is connected to the VSS contact region 218 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection portion 218V. The reference potential line VSS is also connected to the VSS contact region 118 of the first substrate 100 via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, the through electrode 121E, and the pad portion 121. The vertical signal line 543 is connected to the source (Vout) of the select transistor SEL via the third wiring layer W3, the second wiring layer W2, the first wiring layer W1, and a connection portion.

[0206] The contact portions 201 and 202 may be provided at positions overlapping the pixel array section 540 in a plan view (e.g., FIG. 50), or may be provided in a peripheral section 540B outside the pixel array section 540 (e.g., FIG. 53). The contact portions 201 and 202 are provided on the surface of the second substrate 200 (the surface on the wiring layer 200T side). The contact portions 201 and 202 are made of a metal such as Cu (copper) or Al (aluminum). The contact portions 201 and 202 are exposed on the surface of the wiring layer 200T (the surface on the third substrate 300 side). The contact portions 201 and 202 are used for electrical connection between the second substrate 200 and the third substrate 300 and for bonding the second substrate 200 and the third substrate 300 together.

[0207] 53 shows an example in which a peripheral circuit is provided in the peripheral portion 540B of the second substrate 200. This peripheral circuit may include a part of the row driving section 520 or a part of the column signal processing section 550. Alternatively, as shown in FIG. 50, the peripheral circuit may not be provided in the peripheral portion 540B of the second substrate 200, and the connection holes H1 and H2 may be provided in the vicinity of the pixel array section 540.

[0208] The third substrate 300 includes, for example, a wiring layer 300T and a semiconductor layer 300S in this order from the second substrate 200 side. For example, the surface of the semiconductor layer 300S is provided on the second substrate 200 side. The semiconductor layer 300S is made of a silicon substrate. A circuit is provided on the surface side of the semiconductor layer 300S. Specifically, the surface side of the semiconductor layer 300S includes, for example, at least some of an input unit 510A, a row driver unit 520, a timing control unit 530, a column signal processing unit 550, an image signal processing unit 560, and an output unit 510B. The wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes, for example, an interlayer insulating film, multiple wiring layers separated by the interlayer insulating film, and contact units 301 and 302. The contact portions 301 and 302 are exposed on the surface of the wiring layer 300T (the surface facing the second substrate 200). The contact portion 301 is in contact with the contact portion 201 of the second substrate 200, and the contact portion 302 is in contact with the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are electrically connected to circuits formed in the semiconductor layer 300S (e.g., at least one of the input portion 510A, the row driver portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, and the output portion 510B). The contact portions 301 and 302 are made of metal such as Cu (copper) and aluminum (Al). For example, an external terminal TA is connected to the input portion 510A via a connection hole H1, and an external terminal TB is connected to the output portion 510B via a connection hole H2.

[0209] Here, the features of the imaging device 1 will be described.

[0210] Generally, an imaging device mainly consists of a photodiode and a pixel circuit. Increasing the area of ​​the photodiode increases the amount of charge generated as a result of photoelectric conversion, thereby improving the signal-to-noise ratio (S / N ratio) of the pixel signal and enabling the imaging device to output better image data (image information). On the other hand, increasing the size of the transistors included in the pixel circuit (especially the size of the amplification transistor) reduces the noise generated in the pixel circuit, thereby improving the S / N ratio of the imaging signal and enabling the imaging device to output better image data (image information).

[0211] However, in an imaging device in which a photodiode and a pixel circuit are provided on the same semiconductor substrate, if the area of ​​the photodiode is increased within the limited area of ​​the semiconductor substrate, the size of the transistor provided in the pixel circuit may be reduced, and if the size of the transistor provided in the pixel circuit is increased, the area of ​​the photodiode may be reduced.

[0212] To solve these problems, for example, the imaging device 1 of this embodiment uses a structure in which multiple pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it possible to maximize the area of ​​the photodiode PD and maximize the size of the transistors provided in the pixel circuit 210 within the limited area of ​​the semiconductor substrate. This improves the S / N ratio of the pixel signal, allowing the imaging device 1 to output better image data (image information).

[0213] When realizing a structure in which multiple pixels 541 share one pixel circuit 210 and this pixel circuit 210 is arranged overlapping the photodiode PD, multiple wirings connected to one pixel circuit 210 extend from the floating diffusion FD of each of the multiple pixels 541. In order to secure a large area of ​​the semiconductor substrate 200 on which the pixel circuit 210 is formed, for example, it is possible to form a connection wiring that interconnects these multiple extending wirings and combines them into one. Similarly, it is possible to form a connection wiring that interconnects the multiple extending wirings and combines them into one for the multiple wirings extending from the VSS contact region 118.

[0214] For example, if connection wiring that interconnects the multiple wirings extending from the floating diffusion FD of each of the multiple pixels 541 is formed on the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that the area for forming the transistors included in the pixel circuit 210 will be reduced. Similarly, if connection wiring that interconnects the multiple wirings extending from the VSS contact region 118 of each of the multiple pixels 541 and combines them into one is formed on the semiconductor substrate 200 that forms the pixel circuit 210, it is conceivable that this will result in a reduction in the area for forming the transistors included in the pixel circuit 210.

[0215] In order to solve these problems, for example, the imaging device 1 of this embodiment can have a structure in which multiple pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged superimposed on the photodiode PD, and can have a structure in which connection wiring that interconnects the floating diffusions FD of each of the multiple pixels 541 to combine them into one, and connection wiring that interconnects the VSS contact regions 118 provided in each of the multiple pixels 541 to combine them into one, provided on the first substrate 100.

[0216] Here, when the second manufacturing method described above is used as a manufacturing method for providing, on the first substrate 100, the connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541 and the connection wiring that interconnects and combines the VSS contact regions 118 of the plurality of pixels 541, it is possible to manufacture the first substrate 100 and the second substrate 200 using an appropriate process depending on their respective configurations, thereby manufacturing a high-quality, high-performance imaging device. Furthermore, the connection wiring of the first substrate 100 and the second substrate 200 can be formed through a simple process. Specifically, when the second manufacturing method is used, electrodes connected to the floating diffusions FD and electrodes connected to the VSS contact regions 118 are provided on the surfaces of the first substrate 100 and the second substrate 200, which are the bonding interface between the first substrate 100 and the second substrate 200, respectively. Furthermore, it is preferable to make the electrodes formed on the surfaces of these two substrates large so that the electrodes formed on the surfaces of these two substrates will contact each other even if misalignment occurs between the electrodes formed on the surfaces of these two substrates when the first substrate 100 and the second substrate 200 are bonded together. In this case, it may be difficult to arrange the electrodes within the limited area of ​​each pixel provided in the imaging device 1.

[0217] To solve the problem of needing a large electrode at the bonding interface between the first substrate 100 and the second substrate 200, for example, the imaging device 1 of this embodiment can use the first manufacturing method described above as a manufacturing method in which multiple pixels 541 share one pixel circuit 210 and the shared pixel circuit 210 is arranged so as to overlap the photodiode PD. This makes it easy to align the elements formed on the first substrate 100 and the second substrate 200, making it possible to manufacture an imaging device with high quality and high performance. Furthermore, it is possible to have a unique structure that is created by using this manufacturing method. That is, it has a structure in which the semiconductor layer 100S and wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and wiring layer 200T of the second substrate 200 are stacked in this order, in other words, a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back, and it also has through electrodes 120E, 121E that pass from the surface side of the semiconductor layer 200S of the second substrate 200, through the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reach the surface of the semiconductor layer 100S of the first substrate 100.

[0218] In a structure in which a first substrate 100 is provided with connection wiring that interconnects the floating diffusions FD of each of the multiple pixels 541 to combine them into one, and connection wiring that interconnects the VSS contact regions 118 of each of the multiple pixels 541 to combine them into one, if this structure and a second substrate 200 are stacked using the first manufacturing method to form a pixel circuit 210 on the second substrate 200, there is a possibility that the influence of the heating process required to form the active elements provided in the pixel circuit 210 will extend to the connection wiring formed on the first substrate 100.

[0219] Therefore, in order to solve the problem that the connection wiring is affected by the heat treatment when forming the active elements, the imaging device 1 of this embodiment desirably uses a highly heat-resistant conductive material for the connection wiring that interconnects and combines the floating diffusions FD of each of the plurality of pixels 541 and for the connection wiring that interconnects and combines the VSS contact regions 118 of each of the plurality of pixels 541. Specifically, the highly heat-resistant conductive material can be a material with a higher melting point than at least a portion of the wiring material included in the wiring layer 200T of the second substrate 200.

[0220] In this way, for example, the imaging device 1 of this embodiment has: (1) a structure in which the first substrate 100 and the second substrate 200 are stacked face-to-back (specifically, a structure in which the semiconductor layer 100S and the wiring layer 100T of the first substrate 100 and the semiconductor layer 200S and the wiring layer 200T of the second substrate 200 are stacked in this order); (2) a structure in which the through electrodes 120E, 121E are provided from the front surface side of the semiconductor layer 200S of the second substrate 200, penetrating the semiconductor layer 200S and the wiring layer 100T of the first substrate 100, and reaching the front surface of the semiconductor layer 100S of the first substrate 100; and (3) a structure in which the floating diffusions FD provided in each of the plurality of pixels 541 are provided. By providing a structure in which the connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541 into one and the connection wiring that interconnects and combines the VSS contact regions 118 of each of the plurality of pixels 541 and the connection wiring that interconnects and combines the VSS contact regions 118 of each of the plurality of pixels 541 is formed from a highly heat-resistant conductive material, it is possible to provide the connection wiring that interconnects and combines the floating diffusions FD of the plurality of pixels 541 into one and the connection wiring that interconnects and combines the VSS contact regions 118 of each of the plurality of pixels 541 on the first substrate 100 without providing a large electrode at the interface between the first substrate 100 and the second substrate 200.

[0221] [Operation of imaging device 1] Next, the operation of the imaging device 1 will be described using FIGS. 60 and 61. FIGS. 60 and 61 are diagrams similar to FIG. 50, with arrows added to indicate the paths of each signal. FIG. 60 uses arrows to indicate the paths of input signals input to the imaging device 1 from the outside, as well as the paths of the power supply potential and the reference potential. FIG. 61 uses arrows to indicate the signal paths of pixel signals output from the imaging device 1 to the outside. For example, an input signal (e.g., a pixel clock and a synchronization signal) input to the imaging device 1 via the input unit 510A is transmitted to the row driver 520 of the third substrate 300, and a row drive signal is generated in the row driver 520. This row drive signal is sent to the second substrate 200 via the contact units 301 and 201. Furthermore, this row drive signal reaches each pixel sharing unit 539 of the pixel array unit 540 via a row drive signal line 542 in the wiring layer 200T. Of the row drive signals that reach the pixel sharing unit 539 on the second substrate 200, the drive signals other than those for the transfer gate TG are input to the pixel circuit 210, driving each transistor included in the pixel circuit 210. The drive signal for the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 on the first substrate 100 via the through-electrodes TGV, driving the pixels 541A, 541B, 541C, and 541D ( FIG. 60 ). In addition, a power supply potential and a reference potential supplied from the outside of the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via the contact sections 301 and 201, and are supplied to the pixel circuit 210 of each pixel sharing unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D on the first substrate 100 via the through-electrode 121E. Meanwhile, pixel signals photoelectrically converted in the pixels 541A, 541B, 541C, and 541D of the first substrate 100 are sent to the pixel circuit 210 of the second substrate 200 for each pixel sharing unit 539 via the through-electrode 120E. Pixel signals based on these pixel signals are sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact units 202 and 302. These pixel signals are processed by the column signal processing unit 550 and the image signal processing unit 560 of the third substrate 300, and then output to the outside via the output unit 510B.

[0222] [effect] In this embodiment, the pixels 541A, 541B, 541C, and 541D (pixel shared unit 539) and the pixel circuit 210 are provided on different substrates (first substrate 100 and second substrate 200). This allows the areas of the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 to be larger than when the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 are formed on the same substrate. As a result, the amount of pixel signal obtained by photoelectric conversion can be increased and the transistor noise of the pixel circuit 210 can be reduced. This improves the signal-to-noise ratio of the pixel signal, allowing the imaging device 1 to output better pixel data (image information). Furthermore, this allows the imaging device 1 to be miniaturized (in other words, reduced pixel size and miniaturized). By reducing the pixel size, the imaging device 1 can increase the number of pixels per unit area and output high-quality images.

[0223] Furthermore, in the imaging device 1, the first substrate 100 and the second substrate 200 are electrically connected to each other by through electrodes 120E and 121E provided in the insulating region 212. For example, other possible methods include connecting the first substrate 100 and the second substrate 200 by bonding pad electrodes together, or connecting them by through wiring (for example, TSV (Thorough Si Via)) that penetrates the semiconductor layer. Compared to such a method, by providing the through electrodes 120E, 121E in the insulating region 212, the area required for connecting the first substrate 100 and the second substrate 200 can be reduced. This reduces the pixel size, allowing the imaging device 1 to be made more compact. Furthermore, by further miniaturizing the area per pixel, the resolution can be increased. When miniaturization of the chip size is not necessary, the formation area of ​​the pixels 541A, 541B, 541C, and 541D and the pixel circuit 210 can be expanded. As a result, it is possible to increase the amount of pixel signals obtained by photoelectric conversion and reduce noise in the transistors provided in the pixel circuit 210. This improves the signal-to-noise ratio of the pixel signals, allowing the imaging device 1 to output better pixel data (image information).

[0224] Furthermore, in the imaging device 1, the pixel circuit 210, the column signal processing unit 550, and the image signal processing unit 560 are provided on different substrates (the second substrate 200 and the third substrate 300). This allows the area of ​​the pixel circuit 210 and the areas of the column signal processing unit 550 and the image signal processing unit 560 to be increased compared to when the pixel circuit 210, the column signal processing unit 550, and the image signal processing unit 560 are formed on the same substrate. This makes it possible to reduce noise generated in the column signal processing unit 550 and to install a more advanced image processing circuit in the image signal processing unit 560. This improves the signal-to-noise ratio of the pixel signals, allowing the imaging device 1 to output better pixel data (image information).

[0225] In the imaging device 1, the pixel array section 540 is provided on the first substrate 100 and the second substrate 200, and the column signal processing section 550 and the image signal processing section 560 are provided on the third substrate 300. Furthermore, contact sections 201, 202, 301, and 302 connecting the second substrate 200 and the third substrate 300 are formed above the pixel array section 540. Therefore, the contact sections 201, 202, 301, and 302 can be freely laid out without being interfered with by various wirings provided in the pixel array. This allows the contact sections 201, 202, 301, and 302 to be used for electrical connection between the second substrate 200 and the third substrate 300. Using the contact sections 201, 202, 301, and 302 increases the degree of freedom in the layout of the column signal processing section 550 and the image signal processing section 560, for example. This makes it possible to reduce noise generated in the column signal processing unit 550 and to install a more advanced image processing circuit in the image signal processing unit 560. Therefore, the signal-to-noise ratio of pixel signals is improved, and the imaging device 1 can output better pixel data (image information).

[0226] Furthermore, in the imaging device 1, the pixel separator 117 penetrates the semiconductor layer 100S. This makes it possible to suppress color mixing between the pixels 541A, 541B, 541C, and 541D even when the distance between adjacent pixels (pixels 541A, 541B, 541C, and 541D) decreases due to miniaturization of the area per pixel. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).

[0227] Furthermore, in the imaging device 1, a pixel circuit 210 is provided for each pixel shared unit 539. This allows for a larger formation area for the transistors (amplification transistor AMP, reset transistor RST, selection transistor SEL, FD conversion gain switching transistor FDG) that constitute the pixel circuit 210 compared to when a pixel circuit 210 is provided for each of the pixels 541A, 541B, 541C, and 541D. For example, by increasing the formation area for the amplification transistor AMP, it becomes possible to suppress noise. This improves the signal-to-noise ratio of the pixel signal, enabling the imaging device 1 to output better pixel data (image information).

[0228] Furthermore, in the imaging device 1, a pad section 120 that electrically connects the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of four pixels (pixels 541A, 541B, 541C, and 541D) is provided on the first substrate 100. This allows the number of through electrodes (through electrodes 120E) connecting the first substrate 100 and the second substrate 200 to be reduced compared to when such pad section 120 is provided on the second substrate 200. This makes it possible to reduce the insulating region 212 and ensure a sufficient size for the formation region (semiconductor layer 200S) of the transistors that constitute the pixel circuit 210. This makes it possible to reduce noise from the transistors provided in the pixel circuit 210, improve the signal-to-noise ratio of the pixel signal, and enable the imaging device 1 to output better pixel data (image information).

[0229] Modifications of the imaging device 1 according to the above embodiment will be described below. In the following modifications, the same components as those in the above embodiment will be denoted by the same reference numerals.

[0230] <2. Variation 1> FIGS. 62 to 66 illustrate a modified planar configuration of the imaging device 1 according to the above embodiment. FIG. 62 schematically illustrates a planar configuration near the surface of the semiconductor layer 200S of the second substrate 200, corresponding to FIG. 55 described in the above embodiment. FIG. 63 schematically illustrates the configuration of the first wiring layer W1 and the semiconductor layer 200S and each part of the first substrate 100 connected to the first wiring layer W1, corresponding to FIG. 56 described in the above embodiment. FIG. 64 illustrates an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, corresponding to FIG. 57 described in the above embodiment. FIG. 65 illustrates an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, corresponding to FIG. 58 described in the above embodiment. FIG. 66 illustrates an example of the planar configuration of the third wiring layer W3 and the fourth wiring layer W4, corresponding to FIG. 59 described in the above embodiment.

[0231] In this modification, as shown in Fig. 63 , of two pixel-sharing units 539 aligned in the H direction on the second substrate 200, the internal layout of one pixel-sharing unit 539 (for example, the right side of the paper) is configured to be inverted in only the H direction from the internal layout of the other pixel-sharing unit 539 (for example, the left side of the paper). Also, the deviation in the V direction between the outline of one pixel-sharing unit 539 and the outline of the other pixel-sharing unit 539 is larger than the deviation described in the above embodiment (Fig. 56). Increasing the deviation in the V direction in this way can reduce the distance between the amplification transistor AMP of the other pixel-sharing unit 539 and the pad section 120 connected thereto (the pad section 120 on the other (lower side of the paper) of the two pixel-sharing units 539 aligned in the V direction shown in Fig. 54). With this layout, in Modification 1 of the imaging device 1 shown in FIGS. 62 to 66, the area of ​​two pixel sharing units 539 arranged in the H direction can be made the same as the area of ​​the pixel sharing unit 539 on the second substrate 200 described in the above embodiment, without having to invert the planar layouts of these units in the V direction. The planar layout of the pixel sharing units 539 on the first substrate 100 is the same as the planar layout ( FIGS. 54A and 54B ) described in the above embodiment. Therefore, the imaging device 1 of this modification can achieve the same effects as the imaging device 1 described in the above embodiment. The arrangement of the pixel sharing units 539 on the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification.

[0232] <3. Variation 2> 67 to 72 illustrate a modified planar configuration of the imaging device 1 according to the above embodiment. FIG. 67 schematically illustrates the planar configuration of the first substrate 100, corresponding to FIG. 54A described in the above embodiment. FIG. 68 schematically illustrates the planar configuration of the surface vicinity of the semiconductor layer 200S of the second substrate 200, corresponding to FIG. 55 described in the above embodiment. FIG. 69 schematically illustrates the configuration of the first wiring layer W1 and the semiconductor layer 200S and each part of the first substrate 100 connected to the first wiring layer W1, corresponding to FIG. 56 described in the above embodiment. FIG. 70 illustrates an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, corresponding to FIG. 57 described in the above embodiment. FIG. 71 illustrates an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, corresponding to FIG. 58 described in the above embodiment. FIG. 72 shows an example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 59 described in the above embodiment.

[0233] In this modification, the outline of each pixel circuit 210 has a substantially square planar shape (see FIG. 68, etc.). In this respect, the planar configuration of the imaging device 1 of this modification differs from the planar configuration of the imaging device 1 described in the above embodiment.

[0234] For example, the pixel-sharing unit 539 on the first substrate 100 is formed across a 2-row by 2-column pixel region, as described in the above embodiment, and has a substantially square planar shape ( FIG. 67 ). For example, in each pixel-sharing unit 539, the horizontal portions TGb of the transfer gates TG1 and TG3 of the pixels 541A and 541C in one pixel column extend in the H direction from a position where they overlap with the vertical portion TGa toward the center of the pixel-sharing unit 539 (more specifically, in the direction toward the outer edges of the pixels 541A and 541C and toward the center of the pixel-sharing unit 539), and the horizontal portions TGb of the transfer gates TG2 and TG4 of the pixels 541B and 541D in the other pixel column extend in the H direction from a position where they overlap with the vertical portion TGa toward the outside of the pixel-sharing unit 539 (more specifically, in the direction toward the outer edges of the pixels 541B and 541D and toward the outside of the pixel-sharing unit 539). The pad portion 120 connected to the floating diffusion FD is provided in the center of the pixel sharing unit 539 (the center of the pixel sharing unit 539 in the H and V directions), and the pad portion 121 connected to the VSS contact region 118 is provided at the end of the pixel sharing unit 539 at least in the H direction (in the H and V directions in Figure 67).

[0235] As another example of arrangement, it is possible to provide the horizontal portions TGb of the transfer gates TG1, TG2, TG3, and TG4 only in the regions facing the vertical portions TGa. In this case, as described in the above embodiment, the semiconductor layer 200S is likely to be divided into small pieces. Therefore, it becomes difficult to form large transistors in the pixel circuit 210. On the other hand, if the horizontal portions TGb of the transfer gates TG1, TG2, TG3, and TG4 are extended in the H direction from positions overlapping the vertical portions TGa, as in the above modification, the width of the semiconductor layer 200S can be increased, as described in the above embodiment. Specifically, the H-direction positions of the through electrodes TGV1 and TGV3 connected to the transfer gates TG1 and TG3 can be arranged close to the H-direction position of the through electrode 120E, and the H-direction positions of the through electrodes TGV2 and TGV4 connected to the transfer gates TG2 and TG4 can be arranged close to the H-direction position of the through electrode 121E (FIG. 69). This allows the width (size in the H direction) of the semiconductor layer 200S extending in the V direction to be increased, as in the above embodiment. This allows the size of the transistors in the pixel circuit 210, particularly the size of the amplifying transistor AMP, to be increased. As a result, the signal-to-noise ratio of the pixel signal is improved, and the imaging device 1 can output better pixel data (image information).

[0236] The pixel-sharing unit 539 of the second substrate 200 has, for example, approximately the same size in the H direction and V direction as the pixel-sharing unit 539 of the first substrate 100, and is provided, for example, across an area corresponding to a pixel area of ​​approximately 2 rows by 2 columns. For example, in each pixel circuit 210, a selection transistor SEL and an amplification transistor AMP are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction, and an FD conversion gain switching transistor FDG and a reset transistor RST are arranged side by side in the V direction in one semiconductor layer 200S extending in the V direction. The one semiconductor layer 200S provided with the selection transistor SEL and the amplification transistor AMP and the one semiconductor layer 200S provided with the FD conversion gain switching transistor FDG and the reset transistor RST are arranged side by side in the H direction via an insulating region 212. This insulating region 212 extends in the V direction ( FIG. 68 ).

[0237] Here, the outer shape of the pixel shared unit 539 on the second substrate 200 will be described with reference to Figures 68 and 69. For example, the pixel shared unit 539 on the first substrate 100 shown in Figure 67 is connected to an amplifier transistor AMP and a select transistor SEL provided on one side in the H direction of the pad section 120 (the left side of the paper in Figure 69), and an FD conversion gain switching transistor FDG and a reset transistor RST provided on the other side in the H direction of the pad section 120 (the right side of the paper in Figure 69). The outer shape of a shared unit 541 on the second substrate 200 including this amplifier transistor AMP, select transistor SEL, FD conversion gain switching transistor FDG, and reset transistor RST is determined by the following four outer edges.

[0238] The first outer edge is the outer edge of one end in the V direction (the end on the upper side of the paper in FIG. 69 ) of the semiconductor layer 200S including the select transistor SEL and the amplifier transistor AMP. This first outer edge is provided between the amplifier transistor AMP included in the pixel sharing unit 539 and the select transistor SEL included in the pixel sharing unit 539 adjacent to this pixel sharing unit 539 on one side in the V direction (the upper side of the paper in FIG. 69 ). More specifically, the first outer edge is provided in the center in the V direction of the element isolation region 213 between the amplifier transistor AMP and the select transistor SEL. The second outer edge is the outer edge of the other end in the V direction (the end on the lower side of the paper in FIG. 69 ) of the semiconductor layer 200S including the select transistor SEL and the amplifier transistor AMP. This second outer edge is provided between the select transistor SEL included in the pixel sharing unit 539 and the amplifier transistor AMP included in the pixel sharing unit 539 adjacent to this pixel sharing unit 539 on the other side in the V direction (the lower side of the paper in FIG. 69 ). More specifically, the second outer edge is provided in the center in the V direction of the element isolation region 213 between the select transistor SEL and the amplification transistor AMP. The third outer edge is the outer edge of the other end in the V direction (the end on the lower side of the paper in FIG. 69 ) of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. This third outer edge is provided between the FD conversion gain switching transistor FDG included in the pixel shared unit 539 and the reset transistor RST included in the pixel shared unit 539 adjacent to the other end in the V direction (the lower side of the paper in FIG. 69 ) of this pixel shared unit 539. More specifically, the third outer edge is provided in the center in the V direction of the element isolation region 213 between the FD conversion gain switching transistor FDG and the reset transistor RST. The fourth outer edge is the outer edge of one end in the V direction (the end on the upper side of the paper in FIG. 69 ) of the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. This fourth outer edge is provided between the reset transistor RST included in the pixel sharing unit 539 and the FD conversion gain switching transistor FDG (not shown) included in the pixel sharing unit 539 adjacent to this pixel sharing unit 539 on one side of the V direction (the upper side of the paper in Figure 69).More specifically, the fourth outer edge is provided at the center in the V direction of the element isolation region 213 (not shown) between the reset transistor RST and the FD conversion gain switching transistor FDG.

[0239] In the outline of the pixel shared unit 539 on the second substrate 200, which includes the first, second, third, and fourth outer edges, the third and fourth outer edges are arranged to be shifted to one side in the V direction relative to the first and second outer edges (in other words, offset to one side in the V direction). Using such a layout allows the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG to be arranged as close as possible to the pad section 120. This reduces the area of ​​the wiring connecting them, facilitating miniaturization of the imaging device 1. The VSS contact region 218 is provided between the semiconductor layer 200S including the select transistor SEL and the amplifier transistor AMP and the semiconductor layer 200S including the reset transistor RST and the FD conversion gain switching transistor FDG. For example, multiple pixel circuits 210 have the same layout.

[0240] The same effects as those described in the above embodiment can be obtained with the imaging device 1 having such a second substrate 200. The arrangement of the pixel sharing units 539 on the second substrate 200 is not limited to the arrangements described in the above embodiment and this modification.

[0241] <4. Variation 3> 73 to 78 illustrate a modified example of the planar configuration of the imaging device 1 according to the above embodiment. FIG. 73 schematically illustrates the planar configuration of the first substrate 100, corresponding to FIG. 54B described in the above embodiment. FIG. 74 schematically illustrates the planar configuration of the surface vicinity of the semiconductor layer 200S of the second substrate 200, corresponding to FIG. 55 described in the above embodiment. FIG. 75 schematically illustrates the configuration of the first wiring layer W1 and the semiconductor layer 200S and each part of the first substrate 100 connected to the first wiring layer W1, corresponding to FIG. 56 described in the above embodiment. FIG. 76 illustrates an example of the planar configuration of the first wiring layer W1 and the second wiring layer W2, corresponding to FIG. 57 described in the above embodiment. FIG. 77 illustrates an example of the planar configuration of the second wiring layer W2 and the third wiring layer W3, corresponding to FIG. 58 described in the above embodiment. FIG. 78 shows an example of a planar configuration of the third wiring layer W3 and the fourth wiring layer W4, and corresponds to FIG. 59 described in the above embodiment.

[0242] In this modification, the semiconductor layer 200S of the second substrate 200 extends in the H direction (FIG. 75). That is, this configuration roughly corresponds to the planar configuration of the imaging device 1 shown in FIG. 68 and the like rotated by 90 degrees.

[0243] For example, the pixel-sharing unit 539 of the first substrate 100 is formed across two rows and two columns of pixel regions, as described in the above embodiment, and has a substantially square planar shape ( FIG. 73 ). For example, in each pixel-sharing unit 539, the transfer gates TG1 and TG2 of pixels 541A and 541B in one pixel row extend toward the center of the pixel-sharing unit 539 in the V direction, and the transfer gates TG3 and TG4 of pixels 541C and 541D in the other pixel row extend outward from the pixel-sharing unit 539 in the V direction. The pad section 120 connected to the floating diffusion FD is provided in the center of the pixel-sharing unit 539, and the pad section 121 connected to the VSS contact region 118 is provided at an end of the pixel-sharing unit 539 at least in the V direction (in the V and H directions in FIG. 73 ). At this time, the V-direction positions of the through electrodes TGV1 and TGV2 of the transfer gates TG1 and TG2 approach the V-direction position of the through electrode 120E, and the V-direction positions of the through electrodes TGV3 and TGV4 of the transfer gates TG3 and TG4 approach the V-direction position of the through electrode 121E (FIG. 75). Therefore, for the same reasons as those described in the above embodiment, the width (size in the V-direction) of the semiconductor layer 200S extending in the H-direction can be increased. This makes it possible to increase the size of the amplification transistor AMP and suppress noise.

[0244] In each pixel circuit 210, the selection transistor SEL and the amplification transistor AMP are arranged side by side in the H direction, and the reset transistor RST is arranged adjacent to the selection transistor SEL in the V direction with the insulating region 212 between them (FIG. 74). The FD conversion gain switching transistor FDG is arranged side by side with the reset transistor RST in the H direction. The VSS contact region 218 is provided in an island shape in the insulating region 212. For example, the third wiring layer W3 extends in the H direction (FIG. 77), and the fourth wiring layer W4 extends in the V direction (FIG. 78).

[0245] The imaging device 1 having such a second substrate 200 also provides the same effects as those described in the above embodiment. The arrangement of the pixel sharing units 539 on the second substrate 200 is not limited to the arrangement described in the above embodiment and this modification. For example, the semiconductor layer 200S described in the above embodiment and modification 1 may extend in the H direction.

[0246] <5. Variation 4> Fig. 79 is a schematic diagram illustrating a modified cross-sectional configuration of the imaging device 1 according to the above embodiment. Fig. 79 corresponds to Fig. 50 described in the above embodiment. In this modified example, the imaging device 1 has contact portions 203, 204, 303, and 304 at positions facing the center of the pixel array section 540, in addition to contact portions 201, 202, 301, and 302. In this respect, the imaging device 1 of this modified example differs from the imaging device 1 described in the above embodiment.

[0247] Contact portions 203 and 204 are provided on second substrate 200 and are exposed on the bonding surface with third substrate 300. Contact portions 303 and 304 are provided on third substrate 300 and are exposed on the bonding surface with second substrate 200. Contact portion 203 contacts contact portion 303, and contact portion 204 contacts contact portion 304. That is, in this imaging device 1, second substrate 200 and third substrate 300 are connected by contact portions 203, 204, 303, and 304 in addition to contact portions 201, 202, 301, and 302.

[0248] Next, the operation of the imaging device 1 will be described using FIGS. 80 and 81. In FIG. 80, arrows indicate the paths of input signals input from the outside to the imaging device 1, as well as the paths of the power supply potential and the reference potential. In FIG. 81, arrows indicate the signal paths of pixel signals output from the imaging device 1 to the outside. For example, an input signal input to the imaging device 1 via the input unit 510A is transmitted to the row driver 520 of the third substrate 300, and a row drive signal is generated in the row driver 520. This row drive signal is sent to the second substrate 200 via contact units 303 and 203. Furthermore, this row drive signal reaches each pixel sharing unit 539 of the pixel array section 540 via a row drive signal line 542 in the wiring layer 200T. Of the row drive signals that reach the pixel sharing units 539 of the second substrate 200, the drive signals other than those for the transfer gate TG are input to the pixel circuits 210, and each transistor included in the pixel circuits 210 is driven. A drive signal for the transfer gate TG is input to the transfer gates TG1, TG2, TG3, and TG4 of the first substrate 100 via the through-electrode TGV, and the pixels 541A, 541B, 541C, and 541D are driven. In addition, a power supply potential and a reference potential supplied from outside the imaging device 1 to the input section 510A (input terminal 511) of the third substrate 300 are sent to the second substrate 200 via contact sections 303 and 203, and supplied to the pixel circuits 210 of each pixel sharing unit 539 via wiring in the wiring layer 200T. The reference potential is also supplied to the pixels 541A, 541B, 541C, and 541D of the first substrate 100 via the through-electrode 121E. Meanwhile, pixel signals photoelectrically converted by the pixels 541A, 541B, 541C, and 541D on the first substrate 100 are sent to the pixel circuit 210 on the second substrate 200 for each pixel sharing unit 539. Pixel signals based on these pixel signals are sent from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact units 204 and 304. These pixel signals are processed by the column signal processing unit 550 and the image signal processing unit 560 on the third substrate 300, and then output to the outside via the output unit 510B.

[0249] The imaging device 1 having such contact portions 203, 204, 303, and 304 can also achieve the same effects as those described in the above embodiment. The positions and number of the contact portions can be changed depending on the design of the circuitry of the third substrate 300, to which the wiring via the contact portions 303 and 304 is connected.

[0250] <6. Variation 5> Fig. 82 shows a modified cross-sectional configuration of the imaging device 1 according to the above embodiment. Fig. 82 corresponds to Fig. 53 described in the above embodiment. In this modified example, a transfer transistor TR having a planar structure is provided on the first substrate 100. In this respect, the imaging device 1 of this modified example differs from the imaging device 1 described in the above embodiment.

[0251] In this transfer transistor TR, the transfer gate TG is formed only by the horizontal portion TGb, ie, the transfer gate TG does not have the vertical portion TGa and is provided opposite to the semiconductor layer 100S.

[0252] An imaging device 1 having such a planar-structure transfer transistor TR can also achieve the same effects as those described in the above embodiment. Furthermore, by providing a planar-type transfer gate TG on the first substrate 100, the photodiode PD can be formed closer to the surface of the semiconductor layer 100S than when a vertical-type transfer gate TG is provided on the first substrate 100, which can be considered to increase the saturation signal amount (Qs). Furthermore, the method of forming a planar-type transfer gate TG on the first substrate 100 requires fewer manufacturing steps than the method of forming a vertical-type transfer gate TG on the first substrate 100, and can be considered to be less likely to have adverse effects on the photodiode PD due to the manufacturing steps.

[0253] <7. Variation 6> FIG. 83 shows a modified example of the pixel circuit of the imaging device 1 according to the above embodiment. FIG. 83 corresponds to FIG. 51 described in the above embodiment. In this modified example, a pixel circuit 210 is provided for each pixel (pixel 541A). That is, the pixel circuit 210 is not shared by multiple pixels. In this respect, the imaging device 1 of this modified example differs from the imaging device 1 described in the above embodiment.

[0254] The imaging device 1 of this modification is the same as the imaging device 1 described in the above embodiment in that the pixel 541A and the pixel circuit 210 are provided on different substrates (first substrate 100 and second substrate 200). Therefore, the imaging device 1 according to this modification can also obtain the same effects as those described in the above embodiment.

[0255] <8. Variation 7> Figure 84 shows a modified planar configuration of pixel separation section 117 described in the above embodiment. Gaps may be provided in pixel separation section 117 surrounding each of pixels 541A, 541B, 541C, and 541D. That is, pixels 541A, 541B, 541C, and 541D do not have to be entirely surrounded by pixel separation section 117. For example, the gaps in pixel separation section 117 are provided near pad sections 120 and 121 (see Figure 54B).

[0256] In the above embodiment, an example has been described in which the pixel separating section 117 has an FTI structure that penetrates the semiconductor layer 100S (see FIG. 53), but the pixel separating section 117 may have a configuration other than the FTI structure. For example, the pixel separating section 117 does not have to be provided so as to penetrate completely through the semiconductor layer 100S, and may have a so-called DTI (Deep Trench Isolation) structure. That's fine.

[0257] <9. Application Examples> FIG. 85 shows an example of a schematic configuration of an imaging system 7 including the imaging device 1 according to the above embodiment and its modifications.

[0258] The imaging system 7 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal. The imaging system 7 includes, for example, the imaging device 1 according to the above-described embodiment and its modifications, a DSP circuit 243, a frame memory 244, a display unit 245, a storage unit 246, an operation unit 247, and a power supply unit 248. In the imaging system 7, the imaging device 1 according to the above-described embodiment and its modifications, the DSP circuit 243, the frame memory 244, the display unit 245, the storage unit 246, the operation unit 247, and the power supply unit 248 are connected to each other via a bus line 249.

[0259] The imaging device 1 according to the above embodiment and its modified examples outputs image data corresponding to incident light. The DSP circuit 243 is a signal processing circuit that processes the signal (image data) output from the imaging device 1 according to the above embodiment and its modified examples. The frame memory 244 temporarily stores the image data processed by the DSP circuit 243 on a frame-by-frame basis. The display unit 245 is formed of a panel display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays moving or still images captured by the imaging device 1 according to the above embodiment and its modified examples. The storage unit 246 records image data of moving or still images captured by the imaging device 1 according to the above embodiment and its modified examples in a recording medium such as a semiconductor memory or a hard disk. The operation unit 247 issues operation commands for various functions of the imaging system 7 in accordance with user operations. The power supply unit 248 appropriately supplies various power sources to these power sources as operating power for the imaging device 1, DSP circuit 243, frame memory 244, display unit 245, storage unit 246, and operation unit 247 according to the above embodiment and its modified examples.

[0260] Next, the imaging procedure in the imaging system 7 will be described.

[0261] 86 shows an example of a flowchart of the imaging operation in the imaging system 7. The user operates the operation unit 247 to instruct the start of imaging (step S101). Then, the operation unit 247 transmits an imaging command to the imaging device 1 (step S102). Upon receiving the imaging command, the imaging device 1 (specifically, the system control circuit 36) performs imaging in a predetermined imaging method (step S103).

[0262] The imaging device 1 outputs image data obtained by imaging to the DSP circuit 243. Here, the image data refers to data for all pixels of pixel signals generated based on the charges temporarily stored in the floating diffusion FD. The DSP circuit 243 performs predetermined signal processing (e.g., noise reduction processing) based on the image data input from the imaging device 1 (step S104). The DSP circuit 243 stores the image data that has undergone the predetermined signal processing in the frame memory 244, and the frame memory 244 stores the image data in the storage unit 246 (step S105). In this manner, imaging is performed in the imaging system 7.

[0263] In this application example, the imaging device 1 according to the above-described embodiment and its modification example is applied to an imaging system 7. This allows the imaging device 1 to be made smaller or have higher resolution, and therefore a small or high-resolution imaging system 7 can be provided. The solid-state imaging devices 1A, 1B1, 1B2, 1C, 1D, and 1E according to the first to sixth embodiments are also applied to the imaging system 7. The solid-state imaging devices 1F, 1G, and 1H according to eighth to tenth embodiments, which will be described later, are also applied to the imaging system 7.

[0264] <10. Application Examples> [Application example 1] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0265] FIG. 87 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0266] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 87, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0267] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, etc.

[0268] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0269] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc., based on the received images.

[0270] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0271] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0272] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drivetrain control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including avoiding or mitigating collisions between vehicles, following based on the distance between vehicles, maintaining vehicle speed, warning of vehicle collisions, or warning of vehicle lane departure.

[0273] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0274] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control for the purpose of preventing glare, such as switching from high beams to low beams.

[0275] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 87, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0276] FIG. 88 is a diagram showing an example of the installation position of the imaging unit 12031.

[0277] In FIG. 88, a vehicle 12100 has imaging units 12101, 12102, 12103, 12104, and 12105 as the imaging unit 12031.

[0278] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided at the front nose and the imaging unit 12105 provided at the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided at the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided at the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The forward images acquired by the imaging units 12101 and 12105 are mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0279] 88 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 viewed from above can be obtained.

[0280] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera made up of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0281] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (for example, 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of automatic driving, which runs autonomously without relying on driver operation.

[0282] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines the collision risk, which indicates the degree of risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drivetrain control unit 12010.

[0283] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the images captured by the image capturing units 12101 to 12104. The pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104, which are infrared cameras, and then performing pattern matching on a series of feature points that indicate the outline of an object to determine whether or not the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0284] The foregoing has described an example of a mobile object control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to the imaging unit 12031 in the configuration described above. Specifically, the imaging device 1 according to the above embodiment and its modifications, the solid-state imaging devices 1A to 1E according to the first to sixth embodiments described above, and the solid-state imaging devices 1F, 1G, and 1H according to the eighth to tenth embodiments described below can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain high-resolution captured images with little noise, thereby enabling high-precision control using the captured images in the mobile object control system.

[0285] [Application example 2] FIG. 89 is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0286] Figure 89 shows an operator (doctor) 11131 performing surgery on a patient 11132 on a patient bed 11133 using an endoscopic surgery system 11000. As shown in the figure, the endoscopic surgery system 11000 is composed of an endoscope 11100, other surgical instruments 11110 such as an insufflation tube 11111 and an energy treatment instrument 11112, a support arm device 11120 that supports the endoscope 11100, and a cart 11200 on which various devices for endoscopic surgery are mounted.

[0287] The endoscope 11100 is composed of a lens barrel 11101, a region of a predetermined length from the tip of which is inserted into a body cavity of a patient 11132, and a camera head 11102 connected to the base end of the lens barrel 11101. In the example shown, the endoscope 11100 is configured as a so-called rigid scope having a rigid lens barrel 11101, but the endoscope 11100 may also be configured as a so-called flexible scope having a flexible lens barrel.

[0288] An opening into which an objective lens is fitted is provided at the tip of the lens barrel 11101. A light source device 11203 is connected to the endoscope 11100, and light generated by the light source device 11203 is guided to the tip of the lens barrel by a light guide extending inside the lens barrel 11101, and is irradiated via the objective lens towards an object to be observed inside the body cavity of the patient 11132. The endoscope 11100 may be a direct-viewing endoscope, an oblique-viewing endoscope, or a side-viewing endoscope.

[0289] An optical system and an image sensor are provided inside the camera head 11102, and light reflected from the object of observation (observation light) is collected onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor to generate an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. The image signal is sent to a camera control unit (CCU) 11201 as RAW data.

[0290] The CCU 11201 is configured with a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. Furthermore, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing on the image signal, such as development processing (demosaic processing), to display an image based on the image signal.

[0291] Under the control of the CCU 11201, the display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201.

[0292] The light source device 11203 is configured from a light source such as an LED (Light Emitting Diode), and supplies irradiation light to the endoscope 11100 when photographing an operation site or the like.

[0293] The input device 11204 is an input interface for the endoscopic surgery system 11000. A user can input various information and instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs an instruction to change the imaging conditions (type of irradiating light, magnification, focal length, etc.) of the endoscope 11100.

[0294] The treatment tool control device 11205 controls the driving of the energy treatment tool 11112 for cauterizing tissue, incising, sealing blood vessels, etc. The insufflation device 11206 inflates the body cavity of the patient 11132 through the insufflation tube 11111 in order to ensure a clear field of view for the endoscope 11100 and a working space for the surgeon. The recorder 11207 is a device capable of recording various types of information related to the surgery. The printer 11208 is a device capable of printing various types of information related to the surgery in various formats such as text, images, or graphs.

[0295] The light source device 11203 that supplies illumination light to the endoscope 11100 when photographing the surgical site can be configured from a white light source configured from, for example, an LED, a laser light source, or a combination of these. When the white light source is configured from a combination of RGB laser light sources, the output intensity and output timing of each color (each wavelength) can be controlled with high precision, making it possible to adjust the white balance of the captured image in the light source device 11203. In this case, it is also possible to capture images corresponding to each RGB in a time-division manner by irradiating the object of observation with laser light from each RGB laser light source in a time-division manner and controlling the drive of the image sensor of the camera head 11102 in synchronization with the irradiation timing. According to this method, a color image can be obtained without providing a color filter to the image sensor.

[0296] Furthermore, the light source device 11203 may be controlled to change the intensity of light it outputs at predetermined time intervals. By controlling the driving of the image sensor of the camera head 11102 in synchronization with the timing of the change in light intensity to acquire images in a time-division manner and combining the images, it is possible to generate an image with a high dynamic range that is free of so-called blocked-up shadows and blown-out highlights.

[0297] The light source device 11203 may also be configured to supply light in a predetermined wavelength band corresponding to special light observation. Special light observation, for example, utilizes the wavelength dependence of light absorption in body tissues to irradiate light with a narrower band than the light irradiated during normal observation (i.e., white light), thereby capturing high-contrast images of specific tissues, such as blood vessels on the surface of mucous membranes, known as narrow-band imaging. Alternatively, special light observation may be performed using fluorescence observation, in which images are obtained using fluorescence generated by irradiating excitation light. Fluorescence observation can involve irradiating excitation light onto body tissues and observing the fluorescence from the tissues (autofluorescence observation), or locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with excitation light corresponding to the fluorescent wavelength of the reagent to obtain a fluorescent image. The light source device 11203 may be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0298] FIG. 90 is a block diagram showing an example of the functional configuration of the camera head 11102 and the CCU 11201 shown in FIG.

[0299] The camera head 11102 has a lens unit 11401, an imaging unit 11402, a drive unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 has a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other by a transmission cable 11400 so that they can communicate with each other.

[0300] The lens unit 11401 is an optical system provided at the connection point with the lens barrel 11101. Observation light taken in from the tip of the lens barrel 11101 is guided to the camera head 11102 and enters the lens unit 11401. The lens unit 11401 is composed of a combination of multiple lenses including a zoom lens and a focus lens.

[0301] The imaging unit 11402 is configured with an imaging element. The imaging element constituting the imaging unit 11402 may be one (a so-called single-chip type) or multiple (a so-called multi-chip type). When the imaging unit 11402 is configured with a multi-chip type, for example, each imaging element may generate an image signal corresponding to each of RGB, and a color image may be obtained by combining these signals. Alternatively, the imaging unit 11402 may be configured with a pair of imaging elements for acquiring image signals for the right eye and the left eye corresponding to 3D (dimensional) display. 3D display enables the surgeon 11131 to more accurately grasp the depth of the biological tissue at the surgical site. Note that when the imaging unit 11402 is configured with a multi-chip type, multiple lens units 11401 may be provided corresponding to each imaging element.

[0302] Furthermore, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101, immediately after the objective lens.

[0303] The driving unit 11403 is configured by an actuator, and moves the zoom lens and focus lens of the lens unit 11401 by a predetermined distance along the optical axis under the control of the camera head control unit 11405. This allows the magnification and focus of the image captured by the imaging unit 11402 to be adjusted appropriately.

[0304] The communication unit 11404 is configured by a communication device for transmitting and receiving various types of information to and from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0305] Furthermore, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201 and supplies the control signal to the camera head control unit 11405. The control signal includes information on the imaging conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value at the time of imaging, and / or information specifying the magnification and focus of the captured image.

[0306] The image capturing conditions such as the frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set by the control unit 11413 of the CCU 11201 based on the acquired image signal. In the latter case, the endoscope 11100 is equipped with so-called AE (Auto Exposure) function, AF (Auto Focus) function, and AWB (Auto White Balance) function.

[0307] The camera head control unit 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication unit 11404 .

[0308] The communication unit 11411 is configured by a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0309] Furthermore, the communication unit 11411 transmits to the camera head 11102 a control signal for controlling the driving of the camera head 11102. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0310] The image processing unit 11412 performs various image processing operations on the image signal, which is RAW data sent from the camera head 11102 .

[0311] The control unit 11413 performs various controls related to the imaging of the surgical site, etc. by the endoscope 11100 and the display of the captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0312] Furthermore, the control unit 11413 causes the display device 11202 to display a captured image showing the surgical site, etc., based on the image signal that has been image processed by the image processing unit 11412. At this time, the control unit 11413 may recognize various objects in the captured image using various image recognition technologies. For example, the control unit 11413 can recognize surgical tools such as forceps, specific biological parts, bleeding, mist generated when using the energy treatment tool 11112, etc., by detecting the shape and color of the edges of objects included in the captured image. When displaying the captured image on the display device 11202, the control unit 11413 may use the recognition results to superimpose various surgical support information on the image of the surgical site. By superimposing the surgical support information and presenting it to the surgeon 11131, the burden on the surgeon 11131 can be reduced and the surgeon 11131 can proceed with the surgery reliably.

[0313] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable of these.

[0314] In the illustrated example, communication is performed by wire using the transmission cable 11400, but communication between the camera head 11102 and the CCU 11201 may also be performed wirelessly.

[0315] The above describes an example of an endoscopic surgery system to which the technology according to the present disclosure can be applied. Of the configurations described above, the technology according to the present disclosure can be suitably applied to the imaging unit 11402 provided in the camera head 11102 of the endoscope 11100. By applying the technology according to the present disclosure to the imaging unit 11402, it is possible to reduce the size or increase the resolution of the imaging unit 11402, thereby providing a compact or high-resolution endoscope 11100.

[0316] (Eighth embodiment) <Configuration of solid-state imaging device> The solid-state imaging device 1F of the eighth embodiment of the present technology is basically configured in the same manner as the solid-state imaging device 1B2 of the third embodiment described above, except for the configurations of the MIS contact portion, the first insulating layer, and the conductive plug.

[0317] That is, as shown in Fig. 91A, a solid-state imaging device 1F according to the eighth embodiment of the present technology includes MIS contact portions 906a and 906b, an insulating layer 721 as a first insulating layer, and conductive plugs 923a and 923b instead of the MIS contact portions 840a and 840b, the insulating layer 720 as a first insulating layer, and the conductive plugs 823a and 823b of the third embodiment shown in Fig. 26. The other configurations are generally similar to those of the third embodiment described above.

[0318] 91A, the insulating layer 721 has an interlayer insulating film 901 provided on the semiconductor layer 701 so as to cover the island region 703 and the element isolation region (isolation region) 702, and an interlayer insulating film 907 provided on the interlayer insulating film 901 so as to cover conductive pads 905a and 905b (described later). Each of the interlayer insulating films 901 and 907 is formed of, for example, one of a silicon oxide film (SiO), a silicon nitride film (SiN), a silicon oxynitride film (SiON), or a silicon carbonitride film (SiCN), or a laminated film formed by laminating two or more of these films.

[0319] 91A, the MIS contact portion 906a is configured such that a conductive pad 905a is connected to the side surface of each contact region 705 via an insulating film 903 between adjacent contact regions 705 with an element isolation region 702 interposed therebetween. That is, the MIS contact portion 906a has the contact region 705, the insulating film 903, and the conductive pad 905a. 91A, the MIS contact portion 906b is configured such that a conductive pad 905b is connected to the side surface of each contact region 706 via an insulating film 903 between adjacent contact regions 706 separated by an element isolation region 702. That is, the MIS contact portion 906b includes the contact region 706, the insulating film 903, and the conductive pad 905b.

[0320] As shown in FIGS. 91B and 91C, the conductive pad 905a of the MIS contact portion 906a is connected to each side surface of four adjacent contact regions 705 via an insulating film 903 at a first intersection 702a of the element isolation region 702. The conductive pad 905a has a body portion 905a1 connected to each side surface of the four contact regions 705 via the insulating film 903 in a recess 902a provided on the main surface side of the semiconductor layer 701 (the first surface side of the first and second surfaces located opposite each other), and a head portion 905a2 that is wider than the body portion 905a1 and formed integrally with the body portion 905a1. In this eighth embodiment, the recess 902a extends from the upper surface side of the interlayer insulating film 901 to the semiconductor layer 701. The body portion 905a1 is embedded in the recess 902a. A head 905a2 of the conductive pad 905a protrudes from the recess 902a. The insulating film 903 is provided so as to cover the sidewall and bottom surfaces of the recess 902a. The recess 902a is preferably formed so that its bottom surface is deeper than the contact region 705, in other words, so that its bottom surface is located closer to the light incident surface of the semiconductor layer 701 than the contact region 705 (the second surface side of the first surface and second surface side that are located opposite each other). Furthermore, a body 905a1 of the conductive pad 905a is preferably formed so as to protrude closer to the light incident surface of the semiconductor layer 701 than the contact region 705.

[0321] As shown in FIGS. 91B and 91C, the conductive pad 905b of the MIS contact portion 906b is connected to each side surface of four adjacent contact regions 706 via an insulating film 903 at the second intersection 702b of the element isolation region 702. The conductive pad 905b has a body portion 905b1 connected to each side surface of the four contact regions 706 via the insulating film 903 in a recess 902b provided on the main surface side of the semiconductor layer 701, and a head portion 905b2 that is wider than the body portion 905b1 and formed integrally with the body portion 905b1. In this eighth embodiment, the recess 902b extends from the upper surface side of the interlayer insulating film 901 to the semiconductor layer 701. The body portion 905a1 is embedded in the recess 902b. The head portion 905b2 of the conductive pad 905b protrudes from the recess 902b. The insulating film 903 is provided so as to cover the sidewall surfaces and bottom surface of the recess 902b. It is preferable that the bottom surface of this recess 902b is also formed at a position deeper than the contact region 706, in other words, at a depth where the bottom surface is located closer to the light incident surface of the semiconductor layer 701 than the contact region 706. It is also preferable that the body portion 905b1 of the conductive pad 905b is formed so as to protrude closer to the light incident surface of the semiconductor layer 701 than the contact region 706.

[0322] 91B and 91C, the heads 905a2 and 905b2 of the conductive pads 905a and 905b, respectively, have a rectangular planar shape in plan view. The body portions 905a1 and 905b1 of the conductive pads 905a and 905b, respectively, and the recesses 901a and 901b also have a rectangular cross-sectional shape in plan view. The conductive pads 905a and 905b are formed of, for example, a polycrystalline silicon film (doped polysilicon film) into which impurities for reducing resistance are introduced during or after film formation. The insulating film 903 is an amorphous film, for example, a titanium oxide film (TiO film) or a strontium titanate film (SrTiO x membrane) can be used.

[0323] Similar to the MIS contact portions 840a and 840b of the second and third embodiments, the MIS contact portions 906a and 906b use the insulating film 903 to block the wave function of electrons penetrating from the metal (polycrystalline silicon film) side into the band gap of the semiconductor (contact regions 705, 706), and utilize the interface dipole generated at the insulating film / semiconductor (contact regions 705, 706) interface to generate an electric field that effectively reduces the Schottky barrier, thereby enabling a contact with lower resistance than that between the polycrystalline silicon (conductive pads 905a, 905b) and the crystalline silicon (contact regions 705, 706). MIS contacts are described in the literature cited in paragraph

[0064] .

[0324] 91A, the conductive pad 905a of the MIS contact unit 906a is electrically connected to a wiring 827a via a conductive plug 923a embedded in a connection hole 921a that extends from the surface (upper surface) of the insulating layer 820 to the surface of the head 905a2 of the conductive pad 905a. As in the first and third embodiments described above, this wiring 827a is electrically connected to a gate electrode 806a of the amplification transistor AMP provided on the second substrate unit 20 via a conductive plug 826a embedded in a connection hole 825a.

[0325] 91A, the conductive pad 905b of the MIS contact unit 906b is electrically connected to a wiring 827c via a conductive plug 923b embedded in a connection hole 921b that extends from the surface (upper surface) of the insulating layer 820 to the surface of the head 905b2 of the conductive pad 905b. This wiring 827c is also electrically connected to an island region 803b provided in the second substrate unit 20 via a conductive plug 826c embedded in a connection hole 825c, as in the first and third embodiments described above.

[0326] <Method of manufacturing a solid-state imaging device> Next, a method for manufacturing the solid-state imaging device 1F according to the eighth embodiment of the present technology will be described. First, as shown in FIG. 92, an element isolation region 702, an island region 703, a well region 704, a photodiode PD, a transfer transistor TR, contact regions 705 and 706, etc. are formed in a semiconductor layer 701.

[0327] Next, as shown in FIG. 93, an interlayer insulating film 901 is formed as an insulating layer 721 on the entire main surface of the semiconductor layer 701 so as to cover the island region 703 and the gate electrode 710 .

[0328] 93, recesses 902a and 902b are individually formed from the upper surface of the interlayer insulating film 901 to reach the semiconductor layer 701 at the first intersection 702a and the second intersection 702b of the element isolation region 702 in a plan view. It is preferable that the recess 902a is formed to a depth that protrudes further toward the light incident surface of the semiconductor layer 701 than the contact region 705, and the recess 902b is formed to a depth that protrudes further toward the light incident surface of the semiconductor layer 701 than the contact region 706. In this step, the side surfaces of the four contact regions 705 are exposed on the inner sidewall surfaces of the recess 902a, and the side surfaces of the four contact regions 706 are exposed on the inner sidewall surfaces of the recess 902b.

[0329] Next, as shown in FIG. 94, a titanium oxide film (TiOx film) or a strontium titanate film (SrTiO x An insulating film 903 made of a SiO 2 film is formed by ALD or sputtering. The insulating film 903 is formed along the sidewall and bottom surfaces of the recess 902a, and the side surfaces of each of the four contact regions 705 exposed on the inner sidewall surfaces of the recess 902a are covered with the insulating film 903. The insulating film 903 is also formed along the sidewall and bottom surfaces of the recess 903b, and the side surfaces of each of the four contact regions 706 exposed on the inner sidewall surfaces of the recess 903b are covered with the insulating film 903.

[0330] 94, a polycrystalline silicon film 904 is formed on the entire surface of the insulating film 903, including the recesses 902a and 902b, by a low-temperature CVD method at 550°C to a thickness that allows the polycrystalline silicon film 904 to fill the recesses 902a and 902b as a pad material. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film 904 during or after its formation. In this embodiment, the polycrystalline silicon film 904 is formed to a thickness of, for example, about 100 nm.

[0331] 95, a conductive pad 905a is formed at a first intersection 702a of the element isolation region 702 in a plan view, and a conductive pad 905b is formed at a second intersection 702b of the element isolation region 702. The conductive pad 905a has a body 905a1 connected via the insulating film 903 to each side surface of the four contact regions 705 in a recess 902a provided on the main surface side of the semiconductor layer 701, and a head 905a2 that is wider than the body 905a1 and formed integrally with the body 905a1. Furthermore, the conductive pad 905b has a body portion 905b1 connected to each side surface of the four contact regions 706 via the insulating film 903 in a recess 902b provided on the main surface side of the semiconductor layer 701, and a head portion 905b2 that is wider than the body portion 905b1 and formed integrally with the body portion 905b1. This process forms an MIS contact portion 906a including the conductive pad 905a, the insulating film 903, and the contact regions 705. Furthermore, an MIS contact portion 906b including the conductive pad 905b, the insulating film 903, and the contact regions 706 is formed.

[0332] 96, an interlayer insulating film 907 is formed as the insulating layer 721 on the entire surface of the interlayer insulating film 901 so as to cover the conductive pads 905a and 905b. By this process, a substrate part is constructed on the semiconductor layer 701, in which up to the insulating layer 721 is formed.

[0333] 97, a substrate portion is prepared on which insulating layer 820 is formed as a second insulating layer covering semiconductor layer 801. Then, as shown in Fig. 98, insulating layer 721 on the main surface side of semiconductor layer 701 and insulating film 802 on the back surface side of semiconductor layer 801 are placed face to face and bonded together by heat treatment in a state of being in close contact with each other.

[0334] 99, a connection hole 921a is formed from the surface of the insulating layer 820 to the surface of the conductive pad 905a, and a connection hole 921b is formed from the surface of the insulating layer 820 to the surface of the conductive pad 905b. These connection holes 921a and 921b are formed using well-known photolithography and anisotropic dry etching techniques.

[0335] 100, a conductive material is embedded in the contact holes 921a and 921b by a method similar to that of the first and second embodiments described above, to form conductive plugs 923a and 923b in the contact holes 921a and 921b. Then, using a method similar to that of the first and second embodiments described above, contact holes 825a-825c, conductive plugs 826a-826c, wirings 827a-827c, an insulating film 828, wiring 829, etc. are formed. After the third substrate unit 30 is bonded, a planarization film 831, a color filter 832, a microlens 833, etc. are formed on the back surface of the semiconductor layer 701. This substantially completes the solid-state imaging device 1F according to the eighth embodiment shown in FIGS. 91A-91C.

[0336] <Effects of the Eighth Embodiment> Next, the main effects of the eighth embodiment will be described. According to the solid-state imaging device 1F according to the eighth embodiment of the present technology, a low-resistance floating diffusion shared contact structure can be obtained because the MIS contact portion 906a can be configured by forming a thin insulating film 903 between the contact region 705 and the conductive pad 905a. Also, the MIS contact portion 906b can be formed by forming a thin insulating film 903 between the contact region 706 and the conductive pad 905b, so a low-resistance contact structure can be obtained.

[0337] Furthermore, in the solid-state imaging device 1F according to the eighth embodiment, the conductive plug 923a and the contact region 705 are electrically connected by the MIS contact portion 906a, thereby reducing the resistance value of the conductive path electrically connecting the gate electrode 806a of the amplification transistor AMP provided in the upper second substrate portion 20 and the contact region 705 provided in the lower first substrate portion 10. Furthermore, the contact region 705 shares the floating diffusion FD, thereby enabling an increase in the operating speed of the pixel unit PU.

[0338] Furthermore, in the solid-state imaging device 1F of this eighth embodiment, the conductive plug 923b and the contact region 706 are electrically connected by the MIS contact portion 906b, thereby reducing the resistance value of the conductive path electrically connecting the island region 803b provided in the upper second substrate portion 20 and the contact region 706 provided in the lower first substrate portion 10.

[0339] The MIS contact section 906a is configured such that a conductive pad 905a is connected to the side surface of each contact region 705, via an insulating film 903, between contact regions 705 adjacent to each other with the element isolation region 702 interposed therebetween. The MIS contact section 906b is configured such that a conductive pad 905b is connected to the side surface of each contact region 706, via an insulating film 903, between contact regions 706 adjacent to each other with the element isolation region 702 interposed therebetween. Therefore, according to the solid-state imaging device 1F according to the eighth embodiment, it is possible to narrow the distance between shared pixels, thereby enabling miniaturization and increased sensitivity through enlargement of the pixel area.

[0340] Furthermore, the conductive pad 905a of the MIS contact portion 906a has a body portion 905a1 connected via an insulating film 903 to each side surface of the four contact regions 705 within a recess 902a provided on the principal surface side of the semiconductor layer 701, and a head portion 905a2 that is wider than the body portion 905a1 and formed integrally with the body portion 905a1. Therefore, according to the solid-state imaging device 1F of the eighth embodiment, it is possible to narrow the distance between the shared pixels and to suppress poor connection between the conductive plug 923a and the MIS contact portion 906a due to mask misalignment.

[0341] Furthermore, the conductive pad 905b of the MIS contact portion 906b has a body portion 905b1 connected via an insulating film 903 to each side surface of the four contact regions 706 in a recess 902b provided on the main surface side of the semiconductor layer 701, and a head portion 905b2 that is wider than the body portion 905b1 and formed integrally with the body portion 905b1. Therefore, according to the solid-state imaging device 1F of the eighth embodiment, it is possible to narrow the space between the shared pixels and to suppress poor connection between the conductive plug 923b and the MIS contact portion 906b due to mask misalignment.

[0342] Furthermore, according to the manufacturing method of the solid-state imaging device 1F of the eighth embodiment, conductive pads 905a are formed in recesses 902a provided between adjacent contact regions 705, connected to each of the contact regions 705 via insulating films 903, and conductive pads 905b are formed in recesses 902b provided between adjacent contact regions 706, connected to each of the contact regions 706 via insulating films 903, thereby making it possible to provide a solid-state imaging device 1F that can be made more sensitive by miniaturizing the device and expanding the pixel area.

[0343] Furthermore, according to the manufacturing method of the solid-state imaging device 1F of the eighth embodiment, a substrate portion having a second active element that has already been formed by high-temperature heat treatment is bonded to a substrate portion having pre-formed MIS contact portions 906a, 906b, so that a solid-state imaging device 1F having MIS contact portions 906a, 906b that maintain low resistance can be provided.

[0344] <Modification of the Eighth Embodiment> In the above-described eighth embodiment, the cross-sectional shape of each of the body portions 905a1 and 905b1 of the conductive pads 905a and 905b in a plan view is rectangular. However, the present technology is not limited to the cross-sectional shape of the eighth embodiment. For example, as a first modification, as shown in FIG. 101, the cross-sectional shape of each of body portions 905a1 and 905b1 of conductive pads 905a and 905b may be circular in plan view. As a second modification, as shown in FIG. 102, the cross-sectional shape of each of body portions 905a1, 905b1 of conductive pads 905a and 905b may be configured to be rectangular in plan view, with the diagonal line positioned on the element isolation region 702. As a third modification, although not shown, the cross-sectional shape of each of the body portions 905a1, 905b1 of the conductive pads 905a and 905b in plan view may be configured as a rhombus, with the diagonal line positioned on the element isolation region 702. The circular shape of the first modified example, the rectangular shape of the second modified example, and the diamond shape of the third modified example are characterized by high contact reliability, ease of scaling, and ease of enlarging the pixel portion. Furthermore, the circular shape of the first modified example, the rectangular shape of the second modified example, and the diamond shape of the third modified example have a high tolerance for alignment variations in the patterning of the recesses 902a and 902b.

[0345] In the above-described eighth embodiment, the heads 905a2 and 905b2 of the conductive pads 905a and 905b have a rectangular planar shape in a planar view. However, the present technology is not limited to the cross-sectional shape of the eighth embodiment. For example, as shown in FIG. 101, the heads 905a2 and 905b2 of the conductive pads 905a and 905b may have a circular planar shape in a planar view. As shown in FIG. 102, the heads 905a2 and 905b2 of the conductive pads 905a and 905b may have a rectangular planar shape in a planar view, with the diagonal line positioned on the element isolation region 702. Although not shown, the heads 905a2 and 905b2 of the conductive pads 905a and 905b may have a diamond planar shape in a planar view.

[0346] Furthermore, the cross-sectional shape of each of the body portions 905a1 and 905b1 of the conductive pads 905a and 905b in a plan view and the planar shape of each of the head portions 905a2 and 905b2 in a plan view may be the same or different. In addition, in the solid-state imaging device 1F of the above-mentioned eighth embodiment, the second substrate portion 20 may also be configured in such a way that semiconductor substrates 21 and 21A are stacked (a configuration in which multiple semiconductor substrates are stacked), as in the second substrate portion 20 shown in Figure 104 of the tenth embodiment described below.

[0347] (Ninth embodiment) A solid-state imaging device 1G according to the ninth embodiment of the present technology has basically the same configuration as the solid-state imaging device 1B2 according to the eighth embodiment described above, but differs in the configurations of the first insulating layer and the recess. 103, a solid-state imaging device 1F according to the ninth embodiment of the present technology includes recesses 932a and 932b and an insulating layer 720 as a first insulating layer, instead of the recesses 902a and 902b and the insulating layer 721 as a first insulating layer of the eighth embodiment shown in Fig. 91A. The other configurations are generally similar to those of the above-described eighth embodiment.

[0348] The recess 932a extends from the principal surface side of the semiconductor layer 701 to the light incident surface side at the first intersection 702a of the element isolation region 702. A body portion 905a1 of the conductive pad 905a is embedded in the recess 902a. A head portion 905a2 of the conductive pad 905a protrudes from the recess 902a. The insulating film 903 is provided so as to cover the side and bottom surfaces of the recess 932a. That is, the conductive pad 905a of the ninth embodiment has a body portion 905a1 connected to each side surface of the four contact regions 705 via the insulating film 903 within the recess 932a provided on the principal surface side of the semiconductor layer 701, and a head portion 905a2 that is wider than the body portion 905a1 and formed integrally with the body portion 905a1.

[0349] The recess 932b extends from the principal surface side of the semiconductor layer 701 to the light incident surface side at the second intersection 702b of the element isolation region 702. A body 905b1 of a conductive pad 905b is embedded in the recess 902b. A head 905b2 of the conductive pad 905b protrudes from the recess 932b. The insulating film 903 is provided so as to cover the side and bottom surfaces of the recess 932b. That is, the conductive pad 905b of this ninth embodiment has a body 905b1 connected to each side surface of the four contact regions 706 via the insulating film 903 within the recess 932b provided on the principal surface side of the semiconductor layer 701, and a head 905b2 wider than the body 905b1 and formed integrally with the body 905b1.

[0350] The insulating layer 720 is similar to the insulating layer 720 of the first embodiment described above. The insulating layer 720 is provided on the semiconductor layer 701 so as to cover the island region 703 and the conductive pads 935a and 935b.

[0351] The solid-state imaging device 1G of the ninth embodiment configured in this manner also provides the same effects as those of the eighth embodiment described above. In addition, in the solid-state imaging device 1F of the above-mentioned eighth embodiment, the second substrate portion 20 may also be configured in such a way that semiconductor substrates 21 and 21A are stacked (a configuration in which multiple semiconductor substrates are stacked), as in the second substrate portion 20 shown in Figure 104 of the tenth embodiment described below.

[0352] (Tenth embodiment) 104 to 106 are cross-sectional views in the thickness direction showing a configuration example of a solid-state imaging device 1G according to a tenth embodiment of the present technology. 107 to 109 are cross-sectional views in the horizontal direction showing a layout example of a plurality of pixel units PU according to a tenth embodiment of the present technology. It should be noted that the cross-sectional views shown in FIGS. 104 to 106 are merely schematic diagrams and are not intended to accurately show the actual structure. In the cross-sectional views shown in FIGS. 104 to 106, the horizontal positions of the transistors and impurity diffusion layers are intentionally changed at positions sec1 to sec3 in order to easily explain the configuration of the solid-state imaging device 1H on paper.

[0353] Specifically, in pixel unit PU of solid-state imaging device 1H shown in Fig. 104, the cross section at position sec1 is a cross section taken along line A1-A1' in Fig. 107, the cross section at position sec2 is a cross section taken along line B1-B1' in Fig. 108, and the cross section at position sec3 is a cross section taken along line C1-C1' in Fig. 109. Similarly, in solid-state imaging device 1H shown in Fig. 105, the cross section at position sec1 is a cross section taken along line A2-A2' in Fig. 107, the cross section at position sec2 is a cross section taken along line B2-B2' in Fig. 108, and the cross section at position sec3 is a cross section taken along line C2-C2' in Fig. 109. In the solid-state imaging device 1H shown in Figure 106, the cross section at position sec1 is a cross section of Figure 107 taken along line A3-A3', the cross section at position sec2 is a cross section of Figure 108 taken along line B3-B3', and the cross section at position sec3 is a cross section of Figure 109 taken along line C3-C3'.

[0354] As shown in FIG. 104, the second substrate unit 20 is stacked on the front surface 10a side of the first substrate unit 10. A photodiode PD, a transfer transistor TR, and a floating diffusion FD are provided on the front surface 10a side of the first substrate unit 10. The photodiode PD, the transfer transistor TR, and the floating diffusion FD are each provided for each sensor pixel 12. The other surface of the first substrate unit 10 is a light incident surface. The imaging device 1H is a back-illuminated imaging device, and a color filter and a light-receiving lens are provided on the back surface. The color filter and the light-receiving lens are each provided for each sensor pixel 12.

[0355] The semiconductor substrate 11 of the first substrate unit 10 is made of, for example, a silicon substrate. A well layer WE of a first conductivity type (e.g., p-type) is provided in a part of the front surface of the semiconductor substrate 11 and in the vicinity thereof, and a photodiode PD of a second conductivity type (e.g., n-type) is provided in a region deeper than the well layer WE. A well contact layer having a higher p-type concentration than the well layer WE, and an n-type floating diffusion FD are provided within the well layer WE.

[0356] The semiconductor substrate 11 is provided with an element isolation layer 16 that electrically isolates adjacent sensor pixels 12 from each other. The element isolation layer 16 has, for example, an STI (Shallow Trench Isolation) structure and extends in the depth direction of the semiconductor substrate 11. In the semiconductor substrate 11, an impurity diffusion layer 17 is provided between the element isolation layer 16 and the photodiode PD. For example, the impurity diffusion layer 17 has a p-type layer and an n-type layer that extend in the thickness direction of the semiconductor substrate 11. The p-type layer is located on the element isolation layer 16 side, and the n-type layer is located on the photodiode PD side. An insulating film 15 is provided on the front surface 11a side of the semiconductor substrate 11.

[0357] The second substrate unit 20 has a lower substrate 20a and an upper substrate 20b. The lower substrate 20a has a first semiconductor substrate 21. The first semiconductor substrate 21 is a silicon substrate made of, for example, single crystal silicon. An amplifier transistor AMP and an element isolation layer 213 surrounding the amplifier transistor AMP are provided on one surface 211a of the first semiconductor substrate 21. The element isolation layer 213 electrically isolates one amplifier transistor AMP from the other amplifier transistor AMP of adjacent pixel units PU. The lower substrate 20a has an insulating film 215 covering the front surface 211a of the first semiconductor substrate 21. The amplifier transistor AMP and the element isolation layer 213 are covered by the insulating film 215. The lower substrate 20a also has an insulating film 217 covering the other surface 211b of the first semiconductor substrate 21. The insulating film 15 of the first substrate unit 10 and the insulating film 217 of the lower substrate 20 a are bonded to each other to form an interlayer insulating film 228 .

[0358] The upper substrate 20b has a second semiconductor substrate 21A. The second semiconductor substrate 21A is a silicon substrate made of, for example, single crystal silicon. A reset transistor RST, a select transistor SEL, and an element isolation layer 223 are provided on one surface 221a of the second semiconductor substrate 21A. For example, the element isolation layer 223 is provided between the reset transistor RST and the select transistor SEL, and between the select transistor SEL and the well layer of the second semiconductor substrate 21A. The upper substrate 20b has an insulating film 225 that covers the front surface 221a, back surface 221b, and side surfaces of the second semiconductor substrate 21A. The insulating film 215 of the lower substrate 20a and the insulating film 225 of the upper substrate 20b are bonded to each other to form an interlayer insulating film 226.

[0359] The imaging device 1H includes a plurality of wirings L1 to L10 provided in the interlayer insulating films 226, 228 and electrically connected to at least one of the first substrate unit 10 or the second substrate unit 20. The wiring L1 electrically connects the drain of the amplification transistor AMP to a power supply line VDD. The wiring L2 electrically connects four floating diffusions FD included in one pixel unit PU to a gate electrode AG of the amplification transistor AMP. The wiring L3 electrically connects the source of the amplification transistor AMP to the drain of the selection transistor SEL. The wiring L4 electrically connects the gate electrode SG of the selection transistor SEL to a pixel drive line 23 (see FIG. 1).

[0360] The wiring L5 electrically connects the source of the selection transistor SEL to the vertical signal line 24. The wiring L6 electrically connects the drain of the reset transistor RST to the power supply line VDD. The wiring L7 electrically connects the gate electrode RG of the reset transistor RST (see FIG. 4A described later) to the pixel drive line 23. The wiring L8 electrically connects the source of the reset transistor RST to the wiring L2. The wiring L9 (an example of a first wiring) electrically connects the gate electrode TG of the transfer transistor TR to the pixel drive line 23 (see FIG. 1). The wiring L10 electrically connects the well contact layer to a reference potential line that supplies a reference potential (for example, ground potential: 0 V).

[0361] In the wirings L1 to L10, the portions extending in the thickness direction of the laminate are made...

Claims

1. a first semiconductor layer provided with a first active element; a first insulating layer covering the first semiconductor layer; a second semiconductor layer disposed on the first insulating layer, and having a plurality of element formation regions partitioned by element isolation regions, each of which has a second active element provided therein; a second insulating layer covering the second semiconductor layer; a conductive plug embedded in a through hole extending from the second insulating layer to the first insulating layer via an insulating film, the element isolation region includes an isolation trench that isolates the element formation region into an island shape, an insulating film provided on a sidewall of the isolation trench, and a conductive material embedded inside the insulating film in the isolation trench, The semiconductor device, wherein the conductive plug and the element isolation region each terminate within the first insulating layer.

2. the first active element includes a photodiode and a transfer transistor having a source region electrically connected to a cathode region of the photodiode and a drain region electrically connected to the conductive plug; 2. The semiconductor device according to claim 1, wherein said second active element includes an amplifying transistor having a gate electrode electrically connected to said conductive plug.

3. forming a first insulating layer covering the first semiconductor layer in which the first active element is provided; disposing a second semiconductor layer on the first insulating layer; forming a second active element in an element formation region of the second semiconductor layer while leaving an element isolation region of the second semiconductor layer; forming a second insulating layer on the second semiconductor layer; forming a connection hole penetrating the second insulating layer, the second semiconductor layer, and the first insulating layer, and forming an isolation trench in an isolation region of the second semiconductor layer to isolate an element formation region of the second semiconductor layer into island regions; forming an insulating film covering side surfaces of the element formation region in the connection hole and the isolation trench; a step of embedding a conductive material inside the insulating film in the connection hole to form a conductive plug inside the insulating film in the connection hole, and embedding the conductive material inside the insulating film in the isolation trench.

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