A / D conversion circuit

Abstract

To provide an A / D conversion circuit that can accurately perform A / D conversion without complicating a circuit.SOLUTION: An A / D conversion circuit 1 includes: a comparison target signal generation unit 10 that generates a comparison target signal Sc synchronized with a sampling clock signal CLKsamp; a comparator 20 that compares the voltage of an input signal Sin with the voltage of the comparison target signal to generate a trigger signal TRG1; a time-digital converter 100A that calculates a first time-digital value TD1; and a digital signal generation unit 40 that generates a digital signal DO corresponding to the voltage of the input signal Sin based on the first time-digital value TD1 and a second time-digital value TD2. The time-digital converter includes a state transition unit that starts a transition of state based on the trigger signal and outputs state information, and a weighting operation unit that calculates the first time-digital value according to the number of times of the transition of state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an A / D conversion circuit. [Background technology]

[0002] Patent Document 1 describes an A / D conversion device that supplies an input signal to multiple delay units that make up a pulse delay circuit to modulate the delay time of each delay unit and digitize the pulse position, which is the number of delay units through which the pulse signal passes per sampling clock cycle, thereby A / D converting the input signal. In the A / D conversion device described in Patent Document 1, multiple pulse position digitizing units each receive multiple sampling clocks with different phases and digitize the pulse position, and then average the numerical data obtained by each pulse position digitizing unit to generate numerical data representing the final A / D conversion result. Therefore, the A / D conversion device described in Patent Document 1 reduces accuracy degradation due to variations in the delay amounts of the multiple delay units, allowing analog signals to be converted to digital values ​​with high accuracy. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-7385 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the A / D conversion device described in Patent Document 1, in order to reduce accuracy degradation due to variations in the delay amounts of multiple delay units, multiple pulse position digitization units and a circuit that generates multiple sampling clocks with different phases were required, which made the circuitry more complex. [Means for solving the problem]

[0005] One aspect of the A / D conversion circuit according to the present invention is a comparison signal generation unit that generates a comparison signal with a specific waveform synchronized with a sampling clock signal; a comparator that generates a first trigger signal by comparing a voltage of an input signal with a voltage of the comparison signal; a first time-to-digital converter that calculates a first time-to-digital value corresponding to a phase difference between a reference clock signal and the first trigger signal; a digital signal generating unit that generates a digital signal corresponding to a voltage of the input signal based on the first time digital value and a second time digital value that corresponds to a phase difference between the reference clock signal and a second trigger signal that is based on the sampling clock signal, wherein the first time digital converter a first state transition unit that starts a state transition based on the first trigger signal and outputs first state information indicating the state; and a first weighting calculation unit that calculates the first time digital value according to the number of state transitions of the first state transition unit by performing a predetermined calculation by weighting a value based on the first state information according to the passage of time in synchronization with the reference clock signal.

[0006] In one aspect of the A / D conversion circuit, the first state transition unit starts the state transition based on the second trigger signal, and outputs second state information indicating the state; The first weighting calculation unit The second time digital value corresponding to the number of state transitions of the first state transition unit may be calculated by performing the calculation in synchronization with the reference clock signal and weighting a value based on the second state information according to the passage of time.

[0007] One aspect of the A / D conversion circuit is a second time-to-digital converter that calculates the second time digital value; The second time-to-digital converter a second state transition unit that starts a state transition based on the second trigger signal and outputs second state information indicating the state; The second weighting calculation unit may also include a second weighting calculation unit that calculates the second time digital value according to the number of state transitions of the second state transition unit by performing the calculation by weighting a value based on the second state information according to the passage of time in synchronization with the reference clock signal.

[0008] One aspect of the A / D conversion circuit is a third time-to-digital converter that calculates a third time-to-digital value corresponding to a phase difference between the reference clock signal and a third trigger signal that is synchronized with the first trigger signal; The third time-to-digital converter a third state transition unit that starts a state transition based on the third trigger signal and outputs third state information indicating the state; a third weighting calculation unit that calculates the third time digital value according to the number of transitions of the state of the third state transition unit by performing the calculation by weighting a value based on the third state information according to the passage of time in synchronization with the reference clock signal, The digital signal generation unit The digital signal may be generated based on the first time digital value, the second time digital value, and the third time digital value.

[0009] In one aspect of the A / D conversion circuit, The comparison signal generation unit The signal generator may further include an integrating circuit that integrates the sampling clock signal, and may generate the comparison signal based on an output signal from the integrating circuit.

[0010] In one aspect of the A / D conversion circuit, The digital signal generation unit The amount of fluctuation in the time constant of the integrator circuit may be calculated based on the first time digital value, the second time digital value, and a third time digital value corresponding to a phase difference between the reference clock signal and a third trigger signal synchronized with the first trigger signal, and the digital signal in which the amount of fluctuation has been compensated may be generated.

[0011] One aspect of the A / D conversion circuit is a sample-and-hold circuit that samples and holds the input signal based on the sampling clock signal; The comparator may generate the first trigger signal by comparing the voltage of the input signal held by the sample-and-hold circuit with the voltage of the comparison target signal.

[0012] In one aspect of the A / D conversion circuit, The sampling clock signal may be synchronized with the reference clock signal.

[0013] In one aspect of the A / D conversion circuit, The digital signal generation unit An offset value may be subtracted from the first time digital value, and the digital signal may be generated based on the first time digital value from which the offset value has been subtracted. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a diagram showing the configuration of an A / D conversion circuit according to a first embodiment. [Figure 2] FIG. 1 is a diagram showing an example of the configuration of a time-to-digital converter. [Figure 3] FIG. 4 is a diagram showing an example of the configuration of a state transition unit. [Figure 4] FIG. 2 is a diagram showing a configuration example of an oscillation unit. [Figure 5] FIG. 4 is a timing chart showing an example of operation timing of the oscillator section. [Figure 6] FIG. 2 is a diagram showing an example of the configuration of a weighting calculation unit. [Figure 7]FIG. 4 is a timing chart showing an example of operation timing of the time-to-digital converter. [Figure 8] FIG. 4 is a timing chart showing an example of operation timing of the time-to-digital converter. [Figure 9] FIG. 10 is a diagram showing the configuration of a modified example of a time-to-digital converter. [Figure 10] FIG. 10 is a timing chart showing an example of operation timing of a modified example of the time-to-digital converter. [Figure 11] FIG. 10 is a timing chart showing an example of operation timing of a modified example of the time-to-digital converter. [Figure 12] 10 is a diagram showing the relationship between the phase difference PD and the state value ST and the time digital value TD. [Figure 13] 10 is a diagram showing the relationship between a phase difference PD and a time digital value TD. [Figure 14] FIG. 3 is a timing chart showing an example of operation timing of the A / D conversion circuit according to the first embodiment. [Figure 15] FIG. 10 is a diagram showing the configuration of an A / D conversion circuit according to a second embodiment. [Figure 16] FIG. 10 is a timing chart showing an example of operation timing of the A / D conversion circuit according to the second embodiment. [Figure 17] FIG. 10 is a diagram showing the configuration of an A / D conversion circuit according to a third embodiment. [Figure 18] FIG. 11 is a timing chart showing an example of operation timing of the A / D conversion circuit according to the third embodiment. [Figure 19] FIG. 10 is a diagram showing the configuration of an A / D conversion circuit according to a fourth embodiment. [Figure 20] FIG. 10 is a timing chart showing an example of operation timing of the A / D conversion circuit according to the fourth embodiment. [Figure 21] FIG. 10 is a diagram showing a modified configuration of the state transition unit and the transition state acquisition unit. [Figure 22] FIG. 4 is a diagram showing an example of waveforms of signals in a state transition unit. [Figure 23] FIG. 10 is a diagram showing a modified configuration of the state transition unit and the transition state acquisition unit. [Figure 24] FIG. 10 is a diagram showing a state transition table of a synchronous transition section. [Figure 25]FIG. 4 is a diagram showing an example of waveforms of signals in a state transition unit. DETAILED DESCRIPTION OF THE INVENTION

[0015] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0016] 1. First embodiment 1-1.A / D conversion circuit configuration Fig. 1 is a diagram showing the configuration of an A / D conversion circuit according to the first embodiment. As shown in Fig. 1, the A / D conversion circuit 1 according to the first embodiment includes a comparison signal generation unit 10, a comparator 20, a timing generation unit 30, a digital signal generation unit 40, and time-to-digital converters 100A and 100B.

[0017] The comparison signal generating unit 10 generates a sampling clock signal CLK samp Specific to synchronize In this embodiment, the comparison signal generating section 10 includes a resistor 11 and a capacitor 12. One end of the resistor 11 is electrically connected to one end of the capacitor 12, the other end of the capacitor 12 is grounded, and the other end of the resistor 11 is supplied with a sampling clock signal CLK samp is input. The resistor 11 and the capacitor 12 are used to sample the Clock signal CLK samp In this way, an integrating circuit is configured to integrate the In this embodiment, the comparison signal generating unit 10 generates a sampling clock signal CLK samp Integrate The signal to be compared Sc is generated based on an output signal of the integration circuit. For example, the comparison signal Sc may be the output signal of the integrator circuit itself, a signal obtained by buffering the output signal of the integrator circuit, or a signal obtained by inverting the logic of the output signal of the integrator circuit.

[0018] The comparator 20 generates a trigger signal TRG1 by comparing the voltage of the input signal Sin, which is an analog signal, with the voltage of the comparison target signal Sc.

[0019] The timing generating section 30 generates a trigger signal TRG1n for instructing the operation timing of the time-to-digital converter 100A based on the trigger signal TRG1.

[0020] The time-to-digital converter 100A receives a reference clock signal CLK ref and the trigger signal TRG 1n is input, and the reference clock signal CLK ref and the phase difference between the trigger signal TRG1n Specifically, the time-to-digital converter 100A calculates a time digital value TD1 corresponding to the reference clock signal CLK ref Reference time event and trigger signal TRG1n A time digital value TD1 corresponding to the phase difference PD1 between the time event is calculated.

[0021] The time event of the trigger signal TRG1n is the timing at which the trigger signal TRG1n changes, and may be, for example, a rising edge or a falling edge of the trigger signal TRG1n, or a rising edge and a falling edge of the trigger signal TRG1n.

[0022] Reference clock signal CLK ref The time event is the time between the reference clock signal CLK ref but For example, the reference clock signal CLK ref The rising edge of Alternatively, it may be a falling edge of the reference clock signal CLK ref The rise of It may be a rising edge and a falling edge.

[0023] Reference clock signal CLK refThe time event that is the reference for The reference clock signal CLK before the time event of RG1n occurs and before the time event of the trigger signal TRG2 (to be described later) occurs. ref It may be a time event stomach.

[0024] In this embodiment, the time event of the trigger signal TRG1n has almost the same timing as the time event of the trigger signal TRG1. For example, if the time event of the trigger signal TRG1n is a rising edge and the time event of the trigger signal TRG1 is also a rising edge, the rising edge of the trigger signal TRG1n has almost the same timing as the rising edge of the trigger signal TRG1. Therefore, the time-to-digital converter 100A converts the reference clock signal CLK ref and the phase difference PD1 between the trigger signal TRG1 and It can be said that the time digital value TD1 is calculated.

[0025] The time-to-digital converter 100B receives a reference clock signal CLK ref and the trigger signal TRG 2 and the reference clock signal CLK ref and the trigger signal TRG2 Specifically, the time-to-digital converter 100A calculates a time digital value TD2 corresponding to the reference clock signal CLK ref The reference time event and the time of the trigger signal TRG2 A time digital value TD2 is calculated according to the phase difference PD2 from the event.

[0026] The trigger signal TRG2 is the sampling clock signal CLK samp It is a signal based on For example, the sampling clock signal CLK samp It can be itself or Pulling clock signal CLK samp It can be a buffered signal or a sampled signal. Pulling clock signal CLKsamp It may be a signal with the logic of the inverted signal.

[0027] The time event of the trigger signal TRG2 is the timing at which the trigger signal TRG2 changes, and may be, for example, a rising edge or a falling edge of the trigger signal TRG2, or a rising edge and a falling edge of the trigger signal TRG2.

[0028] The digital signal generator 40 generates a digital signal DO corresponding to the voltage of the input signal Sin based on the time digital value TD1 and the time digital value TD2. The details of the calculation by which the digital signal generator 40 generates the digital signal DO will be described later.

[0029] In FIG. 1, trigger signal TRG1 corresponds to the "first trigger signal," and trigger signal TRG2 corresponds to the "second trigger signal." Furthermore, time digital value TD1 corresponds to the "first time digital value," and time digital value TD2 corresponds to the "second time digital value." Furthermore, time-to-digital converter 100A corresponds to the "first time-to-digital converter," and time-to-digital converter 100B corresponds to the "second time-to-digital converter."

[0030] 1-2. Configuration of time-to-digital converter In this embodiment, the time-to-digital converter 100A and the time-to-digital converter 100B have the same configuration, but the input signals are different. Therefore, hereinafter, a configuration example of the time-to-digital converter 100, which is the time-to-digital converter 100A or the time-to-digital converter 100B, will be described.

[0031] 2 is a diagram showing an example of the configuration of the time-to-digital converter 100. The time-to-digital converter 100 shown in FIG. 2 receives a reference clock signal CLK ref and the phase difference between the trigger signal TRG The trigger signal TRG is the trigger signal TRG1 or the trigger signal TRG2, and the time digital value TD is the time digital value TD1 or the time digital value TD2.

[0032] As shown in FIG. 2, the time-to-digital converter 100 includes a state transition section 110 and a weighting calculation section 120.

[0033] The state transition unit 110 starts a state transition based on the trigger signal TRG, and outputs a state value ST indicating the state.

[0034] The weighting calculation unit 120 calculates the reference clock signal CLK ref Synchronously with the state value ST, By performing a predetermined calculation and weighting the value based on the reference clock signal CLK according to the passage of time, a time digital value TD according to the number of state transitions of the state transition unit 110 is calculated. ref Weight according to the number of time events The weighting calculation unit 120 may include a transition state acquisition unit 130 and a calculation unit 140. The transition state acquisition unit 130 calculates a reference clock signal CLK ref The event occurs at The calculation unit 140 calculates and stores the state value ST every time the state value ST is calculated, and outputs the stored value as the state value LST. The calculation unit 140 calculates and stores the state value LST based on the state value ST in accordance with the reference clock signal CLK. ref Time A predetermined calculation is performed after weighting according to the number of events, thereby generating a time digital value TD.

[0035] The state transition unit 110 of the time-to-digital converter 100A corresponds to the "first state transition unit," and the state transition unit 110 of the time-to-digital converter 100B corresponds to the "second state transition unit." The state value ST output from the state transition unit 110 of the time-to-digital converter 100A corresponds to the "first state information," and the state value ST output from the state transition unit 110 of the time-to-digital converter 100B corresponds to the "second state information." The weighting calculation unit 120 of the time-to-digital converter 100A corresponds to the "first weighting calculation unit," and the weighting calculation unit 120 of the time-to-digital converter 100B corresponds to the "second weighting calculation unit."

[0036] 3 is a diagram showing an example of the configuration of the state transition unit 110. As shown in FIG.

[0037] The oscillator 111 starts oscillation based on a time event of the trigger signal TRG, and outputs a clock signal CK including a predetermined number of pulses.

[0038] The accumulator 112 adds up 1 every time a time event of the clock signal CK occurs and outputs the state value ST. In other words, the accumulator 112 counts the time events of the clock signal CK and outputs the state value ST.

[0039] If it is considered that the state of the state transition unit 110 transitions every time a time event of the clock signal CK occurs, the state value ST corresponds to the number of state transitions of the state transition unit 110.

[0040] Fig. 4 is a diagram showing an example of the configuration of the oscillator 111. As shown in Fig. 4, the oscillator 111 includes an exclusive OR circuit 201, a NAND circuit 202, an integrator 203, a modulo calculator 204, a quantizer 205, and a buffer circuit 206.

[0041] The exclusive OR circuit 201 outputs an exclusive OR signal EX of the trigger signal TRG and the quantized signal QT output from the quantizer 205. The exclusive OR signal EX goes to high level when the logical level of the trigger signal TRG and the logical level of the quantized signal QT are different, and goes to low level when the logical level of the trigger signal TRG and the logical level of the quantized signal QT are the same.

[0042] The NAND circuit 202 outputs a clock signal CK, which is an NAND signal of the exclusive OR signal EX and the output signal of the buffer circuit 206. The clock signal CK goes low when both the exclusive OR signal EX and the output signal of the buffer circuit 206 are high, and goes high when at least one of the exclusive OR signal EX and the output signal of the buffer circuit 206 is low.

[0043] The accumulator 203 adds up by 1 every time a time event of the clock signal CK occurs, and outputs an integrated value CE. In other words, the accumulator 203 counts the time events of the clock signal CK and outputs an integrated value CE. The time events of the clock signal CK may be rising edges, falling edges, or both rising and falling edges.

[0044] The modulo calculator 204 performs a modulo operation using the accumulated value CE as the dividend and a predetermined value as the divisor. That is, the modulo calculator 204 outputs a remainder value MD when dividing the accumulated value CE as the dividend and the predetermined value as the divisor. The predetermined value that is the divisor is set appropriately.

[0045] The quantizer 205 compares the remainder value MD with a predetermined threshold value to quantize the remainder value MD and output a quantized signal QT. In other words, the quantizer 205 divides the remainder value MD as the dividend by the threshold value as the divisor, and outputs the quotient as the quantized signal QT.

[0046] The buffer circuit 206 outputs a signal obtained by buffering the clock signal CK. The output signal of the buffer circuit 206 is a signal obtained by delaying the clock signal CK.

[0047] Fig. 5 is a timing chart showing an example of the operation timing of the oscillator 111 shown in Fig. 4. Fig. 5 shows an example in which the divisor in the modulo operation by the modulo operator 204 is 16 and the threshold value of quantization by the quantizer 205 is 8.

[0048] In the example of Figure 5, when the logic level of the trigger signal TRG changes, the exclusive OR signal EX changes from low to high, and pulses of the clock signal CK are generated continuously while the exclusive OR signal EX is high. The integrated value CE increases by one with each rising edge of the clock signal CK, and the remainder value MD increases as the integrated value CE increases, and is initialized to 0 each time the integrated value CE becomes an integer multiple of 16. The quantized signal QT goes low when the remainder value MD is 7 or less, and goes high when the remainder value MD is 8 or more. When the logic level of the quantized signal QT changes, the exclusive OR signal EX changes from high to low, and the generation of pulses of the clock signal CK stops.

[0049] 5, each time the logic level of the trigger signal TRG changes, the oscillator 111 oscillates eight times, the logic level of the clock signal CK is inverted 16 times, and eight pulses are generated. However, if the divisor in the modulo calculation by the modulo calculator 204 and the threshold value for quantization by the quantizer 205 are changed, the number of oscillations of the oscillator 111 changes, and the number of pulses of the clock signal CK also changes. For example, if the divisor in the modulo calculation by the modulo calculator 204 is 2p and the threshold value for quantization by the quantizer 205 is p, each time the logic level of the trigger signal TRG changes, the oscillator 111 oscillates p times, the logic level of the clock signal CK is inverted 2p times, and p pulses are generated. In this case, the upper limit value of the state value ST, which corresponds to the number of state transitions of the state transition unit 110, is p.

[0050] 6 is a diagram showing an example of the configuration of the weighting calculation unit 120. As shown in FIG. 6, the weighting calculation unit 120 includes a register 131, a register 141, a subtractor 142, an accumulator 143, a multiplier 144, and an accumulator 145.

[0051] The register 131 receives the reference clock signal CLK ref Synchronize with the time event of The value ST is taken in and stored as the state value LST. The register 131 is configured, for example, with one or more D-type flip-flops.

[0052] The register 141 receives the reference clock signal CLK ref Synchronize with the time event of The register 141 captures and holds the value LST. The register 141 is made up of, for example, one or more D-type flip-flops.

[0053] The subtractor 142 subtracts the value held by the register 141 from the state value LST and outputs the count value CNT. The count value CNT is calculated based on the reference clock signal CLK ref A series of This corresponds to the increment of the state value LST between two time events. For example, the reference clock signal CLK ref If the time event is a rising edge, the count value CNT is Reference clock signal CLK ref The number of state transitions in the state transition unit 110 during one period is Correct.

[0054] In this way, the register 141 and the subtractor 142 constitute a state transition counter 150 that counts the number of state transitions in the state transition unit 110 .

[0055] The accumulator 143 calculates the reference clock signal CLK with respect to the initial value. ref The event occurs at In other words, the accumulator 143 accumulates the weighting coefficient value WC by -1 every time the reference clock signal CLK ref Each time a time event occurs, the initial value is decreased by 1. The weighting coefficient value WC is output. The initial value of the weighting coefficient value WC is set appropriately.

[0056] The multiplier 144 multiplies the count value CNT by the weighting coefficient value WC and outputs a weighted count value WCNT.

[0057] In this way, the accumulator 143 and the multiplier 144 multiply the count value CNT by the reference clock signal CLK ref The weighting unit 160 performs weighting according to the number of time events.

[0058] The integrator 145 receives the reference clock signal CLK ref Each time a time event occurs, The accumulator 145 integrates the weighted count value WCNT and outputs the time digital value TD. In this way, the accumulator 145 constitutes an integration section 170 that integrates the weighted count value WCNT.

[0059] The register 131 corresponds to the transition state acquisition unit 130 in Fig. 2. The state transition counting unit 150, the weighting unit 160, and the accumulating unit 170 correspond to the calculation unit 140 in Fig. 2.

[0060] In the time-to-digital converter 100 configured in this manner, the i-th count value CNT, i.e., the reference clock signal CLK ref State transition during the i-th period of The number of state transitions of the unit 110 is m i and the reference clock signal CLK ref During the i-th period of The weighting coefficient value WC in w i Then, the reference clock signal CLK ref N periods later The digital value TD is expressed by the following equation (1).

[0061]

number

[0062] This time digital value TD is a reference clock signal CLK ref Time events and triggers The value corresponds to the phase difference PD from the time event of the signal TRG. The phase difference PD is the above-mentioned phase difference PD1 or phase difference PD2.

[0063] 7 and 8 are timing charts showing an example of the operation timing of the time-to-digital converter 100. In FIGS. 7 and 8, the reference clock signal CLK ref Time Event The reference clock signal CLK ref At time T of one period of On the other hand, the reference clock signal CLK ref time event of the trigger signal TRG The phase difference PD between the trigger signal TRG and the reference clock signal CLK is T×0.5 in the example of FIG. 7 and T×0.7 in the example of FIG. 8. In the example of FIG. 7, when a time event of the trigger signal TRG occurs, ref Each time a time event occurs, the time digital value TD changes to 0, 16, 40, or 56. , 65, . . . In the example of FIG. 8, when a time event of the trigger signal TRG occurs, the reference clock signal CLK ref Each time an event occurs, The time digital value TD increases as follows: 0, 8, 32, 50, 58, .... Comparing Fig. 7 and Fig. 8, the time digital value TD in the example of Fig. 8 where the phase difference PD is larger is smaller than the time digital value TD in the example of Fig. 7 where the phase difference PD is smaller. In other words, the time-to-digital converter 100 outputs a time digital value TD that decreases as the phase difference PD increases. However, the time-to-digital converter 100 may also output a time digital value TD that increases as the phase difference PD increases.

[0064] Although not shown in Figures 3 and 6, after the state value ST reaches the upper limit value, the state value ST and the time digital value TD are reset to 0 at a predetermined timing before the next change in the logic level of the trigger signal TRG.

[0065] The time-to-digital converter 100 described above is a weighted ΔΣ count value accumulation type time-to-digital converter that generates a time digital value TD by weighting and accumulating the difference between the state values ​​ST, which are obtained by counting the number of state transitions in the state transition section 110, by time.This produces a high noise shaping effect due to the delta-sigma modulation, and a time digital value TD with a high S / N ratio is obtained.

[0066] 1-3. Modified time-to-digital converter FIG. 9 is a diagram showing the configuration of a modified example of the time-to-digital converter 100 shown in FIGS.

[0067] The time-to-digital converter 100 shown in FIG.

[0068] The oscillator 111 starts oscillation based on a time event of the trigger signal TRG and outputs a clock signal CK including a predetermined number of pulses. The oscillator 111 has, for example, the same configuration as that shown in FIG.

[0069] The accumulator 112 adds up by 1 each time a time event of the clock signal CK occurs, and outputs the state value ST. In other words, the accumulator 112 counts the time events of the clock signal CK and outputs the state value ST. As described above, the state value ST corresponds to the number of state transitions of the state transition unit 110.

[0070] The accumulator 121 accumulates the state value ST every time a time event of the clock signal CK occurs, and outputs a time digital value TD. The time digital value TD corresponds to the accumulated value of the number of state transitions of the state transition unit 110.

[0071] The oscillator 111 and the integrator 112 correspond to the state transition unit 110 in Fig. 2. The integrator 112 corresponds to the weighting calculation unit 120 in Fig. 2.

[0072] In the time-to-digital converter 100 configured in this manner, the reference clock signal CLK ref The state value ST after i periods of the reference clock signal CLK ref The first one? The integrated value M of the number of state transitions of the state transition unit 110 in each period from the i-th to the i-th i is expressed by the following equation (2).

[0073]

number

[0074] Therefore, the reference clock signal CLK ref The time digital value TD after N periods is calculated by the following formula: (3)

[0075]

number

[0076] Substituting equation (2) into equation (3) gives the following equation (4).

[0077]

number

[0078] Comparing equation (4) with equation (1), N+1-i is the reference clock signal CLK ref i The weighting coefficient value w during the first period i Therefore, the time digital value TD generated by the time digital converter 100 shown in Fig. 9 is the same as that generated by the time digital converter 100 shown in Figs. 2, 3 and 6, and corresponds to the reference clock signal CLK ref Time events and The value corresponds to the phase difference PD with respect to the time event of the trigger signal TRG.

[0079] 10 and 11 are timing charts showing an example of the operation timing of the time-to-digital converter 100 shown in Fig. 9. In Fig. 10 and 11, the reference clock signal CLK ref The time event of the reference clock signal CLK is a rising edge. re f For one period T of the reference clock signal CLK ref Time events and triggers The phase difference PD with respect to the time event of the signal TRG is T×0.5 in the example of Fig. 10, and T×0.7 in the example of Fig. 11. In the example of Fig. 10, when a time event of the trigger signal TRG occurs, the reference clock signal CLK refEach time a time event occurs, the time digital value TD increases as follows: 4, 16, 36, 65, 102, ... In the example of FIG. 11, when a time event of the trigger signal TRG occurs, the reference clock signal CLK ref 2, 3 and 6, the time digital value TD outputs a time digital value TD that decreases as the phase difference PD increases. Each time a time event occurs, the time digital value TD increases as follows: 2, 12, 31, 58, 93, .... Comparing Fig. 10 with Fig. 11, the time digital value TD in the example of Fig. 11 where the phase difference PD is larger is smaller than the time digital value TD in the example of Fig. 10 where the phase difference PD is smaller. In other words, the time-to-digital converter 100 shown in Fig. 9 outputs a time digital value TD that decreases as the phase difference PD increases, similar to the time-to-digital converters 100 shown in Figs. 2, 3 and 6.

[0080] Although not shown in Figure 9, after the state value ST reaches the upper limit value, the state value ST and the time digital value TD are reset to 0 at a predetermined timing before the next change in the logic level of the trigger signal TRG.

[0081] FIG. 12 is a diagram showing the relationship between the phase difference PD and the state value ST and the time digital value TD. In Fig. 12, the upper limit of the state value ST is 64. As shown in Fig. 12, the reference clock signal CLK ref Each time a time event occurs, the state value ST is accumulated and the time digital value T D increases. Reference clock signal CLK ref The time event of the 0th rising edge When the phase difference PD is T×0.5 or T×0.7, the state value ST reaches the upper limit of 64 at the 9th rising edge. When the phase difference PD is T×1.7, T×2.7, or T×3.7, the state value ST reaches the upper limit of 64 at the 10th, 11th, or 12th rising edge, respectively.

[0082] 13 is a diagram showing the relationship between the phase difference PD and the time digital value TD obtained at the 12th rising edge after the state value ST reaches its upper limit in FIG. 12. When the phase difference PD is T×0.5, T×0.7, T×1.7, T×2.7, and T×3.7, the time digital values ​​TD are 519, 505, 441, 377, and 313, respectively, and the difference values ​​ΔTD of the time digital values ​​TD are -14, -64, -64, and -64, respectively. In other words, the larger the phase difference PD, the slower it takes for the state value ST to reach the upper limit of 64, so the time digital value TD becomes a smaller value, and the phase difference PD becomes smaller than the reference clock signal CLK. ref The time for one cycle is T. When the time digital value TD increases by 64, the time digital value TD decreases by 64, which is the upper limit of the state value ST.

[0083] 1-4.Calculation of digital signal generation section An example of the calculation performed by the digital signal generator 40 to obtain the digital signal DO will be described with reference to Fig. 14. Fig. 14 is a timing chart showing an example of the operation timing of the A / D converter circuit 1 of the first embodiment.

[0084] As shown in FIG. 14, the voltage of the comparison signal Sc is equal to the voltage of the sampling clock signal CLK sa mp In synchronization with the rising edge of It increases with a time constant determined by RC.

[0085] Therefore, the sampling clock signal CLK samp Elapsed time from the rising edge of If the time is t, the sampling clock signal CLK samp During the period when The voltage V of the comparison signal Sc c is expressed by equation (5). In equation (5), the reference voltage V ref For example, the voltage V c is the maximum voltage.

[0086]

number

[0087] As shown in FIG. 14, the sampling clock signal CLK samp Is it the rising edge of The elapsed time t a In this case, the voltage V of the comparison signal Sc c is the voltage V of the input signal Sin in When it crosses the voltage V in is expressed by equation (6).

[0088]

number

[0089] In equation (6), the reference voltage V ref , the resistance value R of the resistor 11 and the capacitance of the capacitor 12 Since the quantity C is known, these digital values ​​are also known, and the elapsed time t a Once the digital value of is obtained, the voltage V of the input signal Sin in The digital value of is obtained.

[0090] As shown in Figure 14, the voltage V of the input signal Sin in is the voltage V of the comparison signal Sc c twist The trigger signal TRG1 becomes high level when the trigger signal TRG1n is also high. The rising edge of the trigger signal TRG1n occurs at approximately the same timing as the rising edge of the trigger signal TRG1. As described above, the time-to-digital converter 100A generates p pulses of the clock signal CK while the trigger signal TRG1n is at high level, and generates p pulses of the reference clock signal CLK ref The phase difference PD between the reference time event and the time event of the trigger signal TRG1 A time digital value TD1 corresponding to 1 is generated.

[0091] As shown in FIG. 14, the trigger signal TRG2 is synchronized with the sampling clock signal CLK sampAs described above, the time-to-digital converter 100B is a trigger -While the signal TRG2 is at high level, the clock signal CK is pulsed p times, and the reference clock signal CLK ref The time event that is the reference for the trigger signal TRG2 A time digital value TD2 corresponding to the phase difference PD2 between the input and output is generated.

[0092] In the example of FIG. 14, the time required from when the state transition units 110 of the time-to-digital converters 100A and 100B start state transition until the time digital values ​​TD1 and TD2 are obtained is the sampling clock signal CLK samp It is set so that the time does not exceed the half period of this By setting in this way, even when the time-to-digital converters 100A and 100B generate the time digital values ​​TD1 and TD2 consecutively, the current state transition can be completed before the state transition unit 110 starts the next state transition.

[0093] As shown in Figure 14, the elapsed time t a is equal to the difference between the phase difference PD1 and the phase difference PD2, the difference between the time digital value TD1 and the time digital value TD2 is equal to the elapsed time t a Therefore, the digital signal generator 40 calculates the elapsed time t based on the time digital value TD1 and the time digital value TD2. a Then, the digital signal generator 40 calculates a time digital value corresponding to the elapsed time t a The voltage V of the input signal Sin is calculated using the digital value corresponding to the time in The digital value of A digital signal DO can be generated.

[0094] In addition, the elapsed time t a In order to calculate the time constant RC in equation (6), it is necessary to know the time constant RC. For example, the voltage Vin is known, and the time constant RC is calculated from the time digital values ​​TD1 and TD2 obtained using the input signal Sin. aCalculate the elapsed time t a Therefore, in advance The constant RC can be calculated in advance.

[0095] Here, offset values ​​OF1 and OF2 resulting from delays in wiring when trigger signals TRG1 and TRG2 propagate to time-to-digital converters 100A and 100B are superimposed on time digital values ​​TD1 and TD2, respectively. The offset values ​​OF1 and OF2 can be calculated in advance from the difference between the theoretical values ​​and the time digital values ​​TD1 and TD2 obtained using input signal Sin, whose voltage Vin is known. The digital signal generator 40 may then subtract the offset value OF1 from time digital value TD1 and the offset value OF2 from time digital value TD2, and generate digital signal DO based on the time digital value TD1 from which the offset value OF1 has been subtracted and the time digital value TD2 from which the offset value OF2 has been subtracted. This reduces A / D conversion errors resulting from the offset values ​​OF1 and OF2 superimposed on time digital values ​​TD1 and TD2, improving A / D conversion accuracy.

[0096] 1-5.Effects As described above, in the A / D conversion circuit 1 of the first embodiment, the comparison signal generation unit 10 generates the sampling clock signal CLK samp A comparison signal Sc of a specific waveform synchronized with The comparator 20 generates the trigger signal TRG1 by comparing the voltage Vin of the input signal Sin with the voltage Vc of the comparison target signal Sc, so that the sampling clock signal CLK samp Trigger signal TRG for On the other hand, the timing at which the trigger signal TRG2 occurs changes with the sampling clock signal CLK. samp Since it is a signal based on the sampling clock signal CLK samp Against The timing at which the trigger signal TRG2 is generated is constant regardless of the voltage Vin of the input signal Sin. Therefore, the phase difference between the trigger signals TRG1 and TRG2 changes depending on the voltage Vin of the input signal Sin.

[0097] The time-to-digital converter 100A then converts the reference clock signal CLK ref and trigger signal The time digital converter 100B calculates a time digital value TD1 corresponding to the phase difference PD1 between the reference clock signal CLK ref and the phase difference PD between the trigger signal TRG2 2. Therefore, the difference between the time digital values ​​TD1 and TD2 corresponds to the phase difference between the trigger signals TRG1 and TRG2, i.e., the value corresponding to the voltage Vin of the input signal Sin, and the digital signal generator 40 can generate a digital signal DO corresponding to the voltage Vin of the input signal Sin based on the time digital values ​​TD1 and TD2.

[0098] In the time-to-digital converters 100A and 100B, the state transition unit 110 starts the state transition based on the trigger signals TRG1 and TRG2, outputs the state value ST, and the weighting calculation unit 120 calculates the reference clock signal CLK ref Synchronously with the state value ST, the value is changed over time. By performing a predetermined calculation and weighting the delay time in accordance with the number of state transitions in the state transition unit 110, time digital values ​​TD1 and TD2 are calculated according to the number of state transitions in the state transition unit 110. This produces a noise shaping effect, shifting noise components caused by variations in the amount of delay of each element constituting the A / D conversion circuit 1 to a high frequency band, and obtaining time digital values ​​TD1 and TD2 with a high S / N ratio.

[0099] As described above, according to the A / D conversion circuit 1 of the first embodiment, by using the time-to-digital converters 100A and 100B, time digital values ​​TD1 and TD2 with a high S / N ratio can be obtained, thereby enabling highly accurate A / D conversion without complicating the circuitry.

[0100] 2. Second embodiment In the following, the A / D conversion circuit of the second embodiment will be described mainly with respect to the differences from the first embodiment, with the same components as those of the first embodiment being given the same reference numerals and their description being omitted or simplified.

[0101] Fig. 15 is a diagram showing the configuration of an A / D conversion circuit according to the second embodiment. As shown in Fig. 15, the A / D conversion circuit 1 according to the second embodiment includes a comparison signal generation unit 10, a comparator 20, timing generation units 30 and 31, a digital signal generation unit 41, a frequency divider circuit 50, a sample-and-hold circuit 52, logic inversion circuits 54 and 56, and time-to-digital converters 100A, 100B, and 100C.

[0102] The frequency divider circuit 50 divides the reference clock signal CLK ref is divided to generate the sampling clock signal CLK samp Therefore, in this embodiment, the sampling clock signal C LK samp is the reference clock signal CLK ref is synchronized with.

[0103] The logic inversion circuit 54 outputs the sampling clock signal CLK samp Invert the logic level of Therefore, the sampling clock signal CLK sa mp When the logic level of trigger signal TRG1 changes, the logic level of trigger signal TRG2 also changes. The trigger signal TRG2 is the sampling clock signal CLK samp It is a signal synchronized with

[0104] The sample and hold circuit 52 receives the sampling clock signal CLK samp Based on The force signal Sin is sampled and held, and a held signal Sinx is output.

[0105] The comparison signal generating unit 10 generates a sampling clock signal CLK samp Specific to synchronize In the second embodiment, similarly to the first embodiment, the comparison signal generating section 10 generates a comparison signal Sc having a waveform of the sampling clock signal CLK samp Construct an integrator circuit to integrate The frequency divider circuit 50 includes a resistor 11 and a capacitor 12 that form a resistor and a capacitor, and generates a comparison signal Sc based on the output signal of the integrator circuit. The division ratio of the frequency divider circuit 50 is set appropriately depending on the time constant of the integrator circuit.

[0106] The comparator 20 generates a trigger signal TRG1 by comparing the voltage of a held signal Sinx, which is the input signal Sin held by the sample-and-hold circuit 52, with the voltage of a comparison target signal Sc.

[0107] The timing generating section 30 generates a trigger signal TRG1n for instructing the operation timing of the time-to-digital converter 100A based on the trigger signal TRG1.

[0108] The logic inversion circuit 56 outputs a trigger signal TRG3 that is the inverted logic level of the trigger signal TRG1. Therefore, when the logic level of the trigger signal TRG1 changes, the logic level of the trigger signal TRG3 also changes, so the trigger signal TRG3 is a signal that is synchronized with the trigger signal TRG1.

[0109] The timing generation unit 31 generates a trigger signal TRG3n for instructing the operation timing of the time-to-digital converter 100C based on the trigger signal TRG3.

[0110] The time-to-digital converter 100A receives a reference clock signal CLK ref and the trigger signal TRG 1n is input, and the reference clock signal CLK ref and the phase difference between the trigger signal TRG1n Specifically, the time-to-digital converter 100A calculates a time digital value TD1 corresponding to the reference clock signal CLKref Reference time event and trigger signal TRG1n A time digital value TD1 corresponding to the phase difference PD1 between the time event is calculated.

[0111] The time-to-digital converter 100B receives a reference clock signal CLK ref and the trigger signal TRG 2 and the reference clock signal CLK ref and the trigger signal TRG2 Specifically, the time-to-digital converter 100A calculates a time digital value TD2 corresponding to the reference clock signal CLK ref The reference time event and the time of the trigger signal TRG2 A time digital value TD2 is calculated according to the phase difference PD2 from the event.

[0112] The time-to-digital converter 100C receives a reference clock signal CLK ref and the trigger signal TRG 3n is input, and the reference clock signal CLK ref and the phase difference between the trigger signal TRG3n Specifically, the time-to-digital converter 100C calculates a time digital value TD3 corresponding to the reference clock signal CLK ref Reference time event and trigger signal TRG3n A time digital value TD3 corresponding to the phase difference PD3 between the time event is calculated.

[0113] In this embodiment, the time event of the trigger signal TRG3n has approximately the same timing as the time event of the trigger signal TRG3. For example, if the time event of the trigger signal TRG3n is a rising edge and the time event of the trigger signal TRG3 is a rising edge, the rising edge of the trigger signal TRG3n has approximately the same timing as the rising edge of the trigger signal TRG3. Therefore, the time-to-digital converter 100A converts the reference clock signal CLK ref and the phase difference PD3 with the trigger signal TRG3 It can be said that the time digital value TD3 is calculated.

[0114] The digital signal generator 41 generates a digital signal DO corresponding to the voltage of the input signal Sin based on the time digital value TD1, the time digital value TD2, and the time digital value TD3.

[0115] In Figure 15, trigger signal TRG1 corresponds to the "first trigger signal," trigger signal TRG2 corresponds to the "second trigger signal," and trigger signal TRG3 corresponds to the "third trigger signal." Also, time digital value TD1 corresponds to the "first time digital value," time digital value TD2 corresponds to the "second time digital value," and time digital value TD3 corresponds to the "third time digital value." Also, time-to-digital converter 100A corresponds to the "first time-to-digital converter," time-to-digital converter 100B corresponds to the "second time-to-digital converter," and time-to-digital converter 100C corresponds to the "third time-to-digital converter."

[0116] In this embodiment, the time-to-digital converter 100A, the time-to-digital converter 100B, and the time-to-digital converter 100C have the same configuration but different input signals. The configuration and operation of the time-to-digital converter 100, which is the time-to-digital converter 100A, the time-to-digital converter 100B, or the time-to-digital converter 100C, are as described above with reference to FIGS. 2 to 13.

[0117] The state transition unit 110 of the time-to-digital converter 100A corresponds to the "first state transition unit," the state transition unit 110 of the time-to-digital converter 100B corresponds to the "second state transition unit," and the state transition unit 110 of the time-to-digital converter 100C corresponds to the "third state transition unit." Furthermore, the state value ST output from the state transition unit 110 of the time-to-digital converter 100A corresponds to the "first state information," the state value ST output from the state transition unit 110 of the time-to-digital converter 100B corresponds to the "second state information," and the state value ST output from the state transition unit 110 of the time-to-digital converter 100C corresponds to the "third state information." Furthermore, the weighting calculation unit 120 of the time-to-digital converter 100A corresponds to the "first weighting calculation unit," the weighting calculation unit 120 of the time-to-digital converter 100B corresponds to the "second weighting calculation unit," and the weighting calculation unit 120 of the time-to-digital converter 100C corresponds to the "third weighting calculation unit."

[0118] FIG. 16 is a timing chart showing an example of the operation timing of the A / D conversion circuit 1 of the second embodiment.

[0119] As shown in FIG. 16, the voltage of the comparison signal Sc is equal to the voltage of the sampling clock signal CLK sa mp In synchronization with the rising and falling of It increases or decreases with the time constant RC, which is determined by the product RC of the capacitance value C.

[0120] Therefore, the sampling clock signal CLK samp Let t be the time elapsed after the logical inversion of Then, the sampling clock signal CLK samp Comparison during periods when Voltage V of signal Sc c is expressed by the above-mentioned formula (5). Also, the sampling clock signal CLK samp The voltage V of the comparison signal Sc during the low level period c is expressed as equation (7). will be done.

[0121]

number

[0122] As shown in FIG. 16, the sampling clock signal CLK samp The rising edge of The elapsed time t a In this case, the voltage V of the comparison signal Sc c is the voltage V of the holding signal Sinx i n When it crosses the voltage V in is expressed by the above equation (6). Clock signal CLK samp The time t elapsed from the falling edge of b In this case, the comparison signal S Voltage V at c c is the voltage V of the holding signal Sinx in When it crosses the voltage V in is expressed as equation (8). is represented.

[0123]

number

[0124] In equations (6) and (8), the reference voltage V ref is known, and the time constant RC is known. If so, these digital values ​​are also known, and the elapsed time t a digital value and elapsed time t b Once the digital value of is obtained, the voltage V of the holding signal Sinx in The digital value of is obtained. For example, the voltage V of the hold signal Sinx obtained from equation (6) in The digital value of the formula (8 ) The voltage V of the hold signal Sinx obtained from in The average value of the digital value of the input signal Sin The voltage may be set to .

[0125] Also, the voltage V of the holding signal Sinx in Since the probability of is not constant, the elapsed time t a ,t b The voltage V of the comparison signal Sc at c From the absolute value of the slope of and equation (6) and equation (8), Desired voltage V of the hold signal Sinx in It is thought that there is a correlation between the accuracy of the For example, the voltage V of the comparison signal Sc c The smaller the absolute value of the slope of the hold signal Sinx, the greater the voltage V in Assuming that the probability of is high, the elapsed time t a Voltage V at c The slope of The absolute value is the elapsed time t b Voltage V at c If the absolute value of the slope is smaller than The voltage V of the hold signal Sinx obtained from in The digital value of is converted to the digital value of the voltage of the input signal Sin. The t value is the elapsed time t b Voltage V at c The absolute value of the slope of a Voltage at V c If the absolute value of the slope is smaller than the voltage V of the hold signal Sinx obtained from equation (8), in The digital value of may be the digital value of the voltage of the input signal Sin.

[0126] Alternatively, the digital value of the voltage of the input signal Sin may be calculated as follows: By differentiating both sides of equation (5) with respect to time t, the sampling clock signal CLK is calculated as follows according to equation (9): sam p The voltage V of the comparison signal Sc during the high level period c The slope of is calculated. By differentiating both sides of equation (7) with respect to time t, the sampling clock signal CLK is obtained from equation (10). samp The voltage V of the comparison signal Sc during the low level periodc The slope of can be.

[0127]

number

[0128]

number

[0129] Voltage V of the comparison signal Sc c The weighted average value using the absolute value of the slope of is calculated by equation (11).

[0130]

number

[0131] Substituting equations (9) and (10) into equation (11) and rearranging it, equation (12) is obtained.

[0132]

number

[0133] The weighted average value obtained from equation (12) may be used as the digital value of the voltage of the input signal Sin.

[0134] As shown in Figure 16, the voltage V of the holding signal Sinx in is the voltage V of the comparison signal Sc c Yo The trigger signal TRG1n goes high when the trigger signal TRG1n is higher than the reference clock signal CLK. The rising edge of the trigger signal TRG1n occurs at approximately the same timing as the rising edge of the trigger signal TRG1. The time-to-digital converter 100A generates p pulses of the clock signal CK during the period when the trigger signal TRG1n is high, and generates a reference clock signal CLK ref Based on A time digital value TD1 corresponding to a phase difference PD1 between the reference time event and the time event of the trigger signal TRG1 is generated.

[0135] As shown in FIG. 16, the trigger signal TRG2 is synchronized with the sampling clock signal CLK. samp The time-to-digital converter 100B then converts the trigger signal During the period when the trigger signal TRG2 is at a high level, the clock signal CK is pulsed p times to generate a time digital value TD2 corresponding to the phase difference PD2 between the reference time event of the reference clock signal CLKref and the time event of the trigger signal TRG2.

[0136] 16, the trigger signal TRG3 is a logically inverted signal of the trigger signal TRG1. The rising edge of the trigger signal TRG3n occurs at approximately the same timing as the rising edge of the trigger signal TRG3. The time-to-digital converter 100C generates p pulses of the clock signal CK while the trigger signal TRG3n is at a high level, and generates a reference clock signal CLK ref Reference time event and trigger signal TRG3 A time digital value TD3 corresponding to the phase difference PD3 between the time event TD1 and TD2 is generated.

[0137] In the example of FIG. 16, the time required from when the state transition units 110 of the time-to-digital converters 100A, 100B, and 100C start state transition until the time digital values ​​TD1, TD2, and TD3 are obtained is the sampling clock signal CLK samp It is set so that the time does not exceed the half period of By setting in this way, even when the time-to-digital converters 100A, 100B, and 100C successively generate the time digital values ​​TD1, TD2, and TD3, respectively, the current state transition can be completed before the state transition unit 110 starts the next state transition.

[0138] As shown in FIG. 16, the difference between the time digital value TD2 and the time digital value TD1 is a time τ a is the time digital value corresponding to Sampling clock signal CLK samp The time for one period of is known, and the elapsed time t a teeth , sampling clock signal CLK samp From the half-period time to the time τ a Time subtracted Therefore, the elapsed time t a The digital value corresponding to the elapsed time t b teeth Since the difference between the phase difference PD3 and the phase difference PD2 is equal to the difference between the time digital value TD3 and the time digital value TD2, the difference between the time digital value TD3 and the time digital value TD2 is equal to the elapsed time t b Therefore, the digital signal generator 41 calculates the elapsed time t based on the time digital values ​​TD1, TD2, and TD3. a ,t b The digital value corresponding to the time can be calculated. Then, the digital signal generator 41 calculates the elapsed time t a ,t b Time digital The value can be used to determine a digital value of the voltage of the input signal Sin, and a digital signal DO having the digital value can be generated.

[0139] In addition, the elapsed time t a ,t b To calculate this, the time constant R in Equation (6) and Equation (8) It is necessary that C is known. For example, the elapsed time t a ,t b Calculate , elapsed time t a ,t b Therefore, the time constant RC can be calculated in advance.

[0140] Here, offset values ​​OF1, OF2, OF3 resulting from delays in wiring when trigger signals TRG1, TRG2, TRG3 propagate to time-to-digital converters 100A, 100B, 100C are superimposed on time digital values ​​TD1, TD2, TD3, respectively. These offset values ​​OF1, OF2, OF3 can be calculated in advance from the difference between theoretical values ​​and the time digital values ​​TD1, TD2, TD3 obtained using input signal Sin, whose voltage Vin is known. Digital signal generator 41 may then subtract offset value OF1 from time digital value TD1, subtract offset value OF2 from time digital value TD2, and subtract offset value OF3 from time digital value TD3, and generate digital signal DO based on the time digital value TD1 from which offset value OF1 has been subtracted, the time digital value TD2 from which offset value OF2 has been subtracted, and the time digital value TD3 from which offset value OF3 has been subtracted. In this way, A / D conversion errors caused by the offset values ​​OF1, OF2, and OF3 superimposed on the time digital values ​​TD1, TD2, and TD3 are reduced, improving the A / D conversion accuracy.

[0141] In addition, when the time constant RC of the integrating circuit formed by the resistor 11 and the capacitor 12 varies due to temperature changes or aging, the elapsed time t a ,t b Therefore, in this embodiment, the input signal Sin is held by the sample-and-hold circuit 52, and the voltage Vin of the held signal Sinx changes over the elapsed time t a ,t b The time is determined as follows, taking advantage of the fact that the Compensates for variations in the number RC.

[0142] First, as a preparation, consider the Taylor expansion of the function f(x) = exp(-t / x). The Taylor expansion of f(x) around RC is given by equation (13).

[0143]

number

[0144] Considering the Taylor expansion of equation (13) up to first order, f'(x)~t / x 2 Since exp(-t / x), equation (14) is derived.

[0145]

number

[0146] Assuming that RC changes by ε so that R'C'=RC+ε, and that equations (6) and (8) are equal, we obtain equation (15).

[0147]

number

[0148] By expanding the exp term in Taylor series of equation (15) using equation (14), equation (16) is obtained.

[0149]

number

[0150] Equation (16) is solved for the fluctuation amount ε to obtain equation (17).

[0151]

number

[0152] In equation (17), the time constant RC is known, and the elapsed time t a ,t b The digital value of Then, the amount of fluctuation ε can be obtained.

[0153] As described above, the digital signal generator 41 calculates the elapsed time t based on the time digital value TD1, the time digital value TD2, and the time digital value TD3. a ,tb The time digital value corresponding to Therefore, the digital signal generating unit 41 may calculate the fluctuation amount ε of the time constant RC based on the time digital value TD1, the time digital value TD2, and the time digital value TD3, and generate a digital signal DO in which the fluctuation amount ε is compensated. In this way, the fluctuation amount of the time constant RC is compensated for, and the A / D conversion accuracy is improved.

[0154] The value of ε may be updated sequentially online or offline. The digital signal generator 41 may also compensate for the amount of fluctuation in the time constant RC by using filtered or statistically processed values ​​of multiple ε. While the above example considers a first-order Taylor expansion of equation (13), the digital signal generator 41 may also compensate for the amount of fluctuation in the time constant RC by taking into account a higher-order Taylor expansion of equation (13).

[0155] As described above, in the A / D conversion circuit 1 of the second embodiment, the sample-and-hold circuit 52 receives the sampling clock signal CLK samp Sampling the input signal Sin based on The comparison signal generating unit 10 generates the sampling clock signal CLK samp Same as A comparison signal Sc having a specific waveform is generated, and the comparator 20 compares the voltage Vin of the hold signal Sinx with the voltage Vc of the comparison signal Sc to generate a trigger signal TRG1. The trigger signal TRG3 is synchronized with the trigger signal TRG1. Therefore, the sampling clock signal CLK samp The timing at which the trigger signals TRG1 and TRG3 are generated changes. The trigger signal TRG2 is the sampling clock signal CLK samp Since the signal is based on Sampling clock signal CLK samp The timing of the trigger signal TRG2 The phase difference between the trigger signals TRG1 and TRG3 and the trigger signal TRG2 changes depending on the voltage Vin of the hold signal Sinx.

[0156] The time-to-digital converter 100A then converts the reference clock signal CLK ref and trigger signal The time digital converter 100B calculates a time digital value TD1 corresponding to the phase difference PD1 between the reference clock signal CLK ref and the phase difference PD between the trigger signal TRG2 2, and the time-to-digital converter 100C calculates a time digital value TD2 corresponding to the reference clock signal CLK ref and the time digital signal corresponding to the phase difference PD3 between the trigger signal TRG3 The digital signal generator 41 calculates a digital signal DO corresponding to the voltage Vin of the hold signal Sinx, based on the time digital values ​​TD1, TD2, and TD3. Therefore, the difference between the time digital values ​​TD1 and TD2 corresponds to the phase difference between the trigger signals TRG1 and TRG2, i.e., the voltage Vin of the hold signal Sinx. The difference between the time digital values ​​TD3 and TD2 corresponds to the phase difference between the trigger signals TRG3 and TRG2, i.e., the voltage Vin of the hold signal Sinx. Therefore, the digital signal generator 41 can generate a digital signal DO corresponding to the voltage Vin of the hold signal Sinx, based on the time digital values ​​TD1, TD2, and TD3.

[0157] In the time-to-digital converters 100A, 100B, and 100C, the state transition unit 110 starts state transition based on the trigger signals TRG1, TRG2, and TRG3, outputs a state value ST, and the weighting calculation unit 120 calculates the reference clock signal CLK. ref In synchronization with this, the state value S By weighting the value based on T according to the passage of time and performing a predetermined calculation, time digital values ​​TD1, TD2, and TD3 are calculated according to the number of state transitions of the state transition unit 110. This produces a noise shaping effect, shifting noise components caused by variations in the amount of delay of each element constituting the A / D conversion circuit 1 to a high frequency band, and obtaining time digital values ​​TD1, TD2, and TD3 with a high S / N ratio.

[0158] Thus, according to the A / D conversion circuit 1 of the second embodiment, by using the time-to-digital converters 100A, 100B, and 100C, time digital values ​​TD1, TD2, and TD3 with a high S / N ratio can be obtained, thereby enabling high-precision A / D conversion without complicating the circuitry.

[0159] In the A / D conversion circuit 1 of the second embodiment, the sample-and-hold circuit 52 receives the sampling clock signal CLK samp The input signal Sin is sampled and held based on Therefore, according to the A / D conversion circuit 1 of the second embodiment, the voltage of the hold signal Sinx is constant even if the voltage of the input signal Sin fluctuates, so that fluctuations in the sampling timing according to the voltage of the input signal Sin are reduced, enabling A / D conversion to be performed with high accuracy.

[0160] In the A / D conversion circuit 1 of the second embodiment, the frequency divider circuit 50 divides the reference clock signal CLK ref is divided to generate the sampling clock signal CLK samp Since it generates Clock signal CLK samp is the reference clock signal CLK ref It is synchronized with Therefore, the reference clock signal CLK ref and the sampling clock signal CLK samp Phase with The difference is constant, and the time digital value TD2 corresponding to the phase difference PD2 is a known constant value, so the logic inversion circuit 54 and the time-to-digital converter 100B may be omitted, which allows the size of the A / D conversion circuit 1 to be reduced.

[0161] 3. Third embodiment Below, for the A / D conversion circuit of the third embodiment, components similar to those of the first or second embodiment will be given the same symbols, and their explanation will be omitted or simplified, and the differences from the first and second embodiments will mainly be explained.

[0162] Fig. 17 is a diagram showing the configuration of an A / D conversion circuit according to the third embodiment. As shown in Fig. 17, the A / D conversion circuit 1 according to the third embodiment includes a comparison signal generation unit 10, a comparator 20, a timing generation unit 32, a digital signal generation unit 42, a sample-and-hold circuit 52, and a time-to-digital converter 100A.

[0163] The sample and hold circuit 52 receives the sampling clock signal CLK samp Based on The force signal Sin is sampled and held, and a held signal Sinx is output.

[0164] The comparison signal generating unit 10 generates a sampling clock signal CLK samp Specific to synchronize In the third embodiment, similarly to the first and second embodiments, the comparison signal generating section 10 generates a comparison signal Sc having a waveform of the sampling clock signal CLK samp Integrate The integrated circuit includes a resistor 11 and a capacitor 12 that constitute an integrating circuit, and generates a comparison signal Sc based on the output signal of the integrating circuit.

[0165] The comparator 20 generates a trigger signal TRG1 by comparing the voltage of a held signal Sinx, which is the input signal Sin held by the sample-and-hold circuit 52, with the voltage of a comparison target signal Sc.

[0166] The timing generation unit 32 generates a trigger signal TRG1 and a sampling clock signal CLK. samp A timing chart for instructing the operation timing of the time-to-digital converter 100A based on the Specifically, the timing generation unit 32 generates a time event of the trigger signal TRG1n based on the time event of the trigger signal TRG1, and further generates a sampling clock signal CLK samp Trigger signals based on time events Triggers the next time event for number TRG1n.

[0167] The time-to-digital converter 100A receives a reference clock signal CLK ref and the trigger signal TRG 1n is input, and the reference clock signal CLK ref and the phase difference between the trigger signal TRG1n Specifically, the time-to-digital converter 100A calculates a time digital value TD1n corresponding to the reference clock signal CLK ref Reference time event and trigger signal TRG1 Furthermore, the time-to-digital converter 100A calculates a time digital value TD1n corresponding to the phase difference PD1 between the time event n and the reference clock signal CLK ref The time event that serves as the basis for A time digital value TD1n is calculated according to a phase difference PD2 between the first time event and the next time event of the trigger signal TRG1n.

[0168] In this embodiment, a predetermined time event of the trigger signal TRG1n has approximately the same timing as the time event of the trigger signal TRG1. For example, if the time event of the trigger signal TRG1n is a rising edge and the time event of the trigger signal TRG1 is also a rising edge, the rising edge of the trigger signal TRG1n has approximately the same timing as the rising edge of the trigger signal TRG1. In addition, the next time event of the trigger signal TRG1n is the rising edge of the sampling clock signal CLK. samp The time event is almost the same as For example, the time event of the trigger signal TRG1n is a rising edge, and the time event of the sampling clock signal CLK samp The time event is a rising edge. In this case, the rising edge of the trigger signal TRG1n is synchronized with the sampling clock signal CLK samp Therefore, the timing is almost the same as the rising edge of the time digital The converter 100A receives a reference clock signal CLK ref and the phase difference P between the trigger signal TRG1 A time digital value TD1n corresponding to D1 is calculated, and further, a reference clock signal CLK re f and the sampling clock signal CLK samp The phase difference between PD2 and the digital time It can be said that the value TD1n is calculated.

[0169] The digital signal generating section 42 generates a digital signal DO corresponding to the voltage of the input signal Sin based on a time digital value TD1n corresponding to the phase difference PD1 and a time digital value TD1n corresponding to the phase difference PD2.

[0170] In FIG. 17, the trigger signal TRG1 corresponds to the "first trigger signal", and the sampling clock signal CLK samp corresponds to the "second trigger signal." Also, the phase difference P The time digital value TD1n corresponding to D1 corresponds to the “first time digital value,” and the time digital value TD1n corresponding to the phase difference PD2 corresponds to the “second time digital value.” Furthermore, the time-to-digital converter 100A corresponds to the “first time-to-digital converter.”

[0171] In this embodiment, the configuration and functions of the time-to-digital converter 100A are as described above with reference to FIGS.

[0172] However, in this embodiment, the state transition unit 110 starts a state transition based on the trigger signal TRG1n and outputs a state value ST1 indicating the state, and further starts a state transition based on the trigger signal TRG1n and outputs a state value ST2 indicating the state. Specifically, the state transition unit 110 starts a state transition based on a time event of the trigger signal TRG1n and outputs a state value ST1 indicating the state, and further starts a state transition based on the next time event of the trigger signal TRG1n and outputs a state value ST2 indicating the next state.

[0173] The weighting calculation unit 120 also calculates the reference clock signal CLK ref In synchronization with this, the state value S A time digital value TD1n corresponding to the number of state transitions of the state transition unit 110 is calculated by weighting the value based on T1 according to the passage of time and performing a predetermined calculation. ref In synchronization with this, a weight according to the passage of time is applied to the value based on the state value ST2. By weighting the weights and performing a predetermined calculation, the weighting calculation unit 120 calculates a time digital value TD1n corresponding to the number of state transitions of the state transition unit 110. Specifically, the weighting calculation unit 120 calculates a time digital value TD1n corresponding to the phase difference PD1 based on the state value ST1, and further calculates a time digital value TD1n corresponding to the phase difference PD2 based on the state value ST2.

[0174] The state transition unit 110 of the time-to-digital converter 100A corresponds to the "first state transition unit." Furthermore, the state value ST1 output from the state transition unit 110 of the time-to-digital converter 100A corresponds to the "first state information," and the state value ST2 output from the state transition unit 110 of the time-to-digital converter 100B corresponds to the "second state information." Furthermore, the weighting calculation unit 120 of the time-to-digital converter 100A corresponds to the "first weighting calculation unit."

[0175] FIG. 18 is a timing chart showing an example of the operation timing of the A / D conversion circuit 1 of the third embodiment.

[0176] As shown in FIG. 18, the voltage of the comparison signal Sc is equal to the voltage of the sampling clock signal CLK sa mp In synchronization with the rising edge of It increases with a time constant determined by RC.

[0177] Sampling clock signal CLK samp The time t elapsed from the rising edge of a To The voltage V of the comparison signal Sc c is the voltage V of the input signal Sin in If it crosses, the voltage V in is expressed by the above-mentioned equation (6). In equation (6), the reference voltage V ref , resistor 11 Since the resistance value R and the capacitance value C of the capacitor 12 are known, their digital values ​​are also known. a Once the digital value of is obtained, the voltage V of the holding signal Sinx in Digital The value is calculated.

[0178] As shown in Figure 18, the voltage V of the holding signal Sinx in is the voltage V of the comparison signal Sc c Yo The first rising edge of the trigger signal TRG1n occurs at almost the same timing as the rising edge of the trigger signal TRG1, and the second rising edge of the trigger signal TRG1n occurs at the same timing as the rising edge of the sampling clock signal CLK. samp It occurs at almost the same time as the rising edge of The digital converter 100A generates p pulses of the clock signal CK while the trigger signal TRG1n is at a high level, and outputs the reference clock signal CLK ref The time event that serves as the basis for The time-to-digital converter 100A generates a time digital value TD1n corresponding to the phase difference PD1 between the time event of the trigger signal TRG1 and the time event of the trigger signal TRG1. The time-to-digital converter 100A also generates p pulses of the clock signal CK during the period when the trigger signal TRG1n is at a high level, and generates a time digital value TD1n corresponding to the phase difference PD1 between the time event of the trigger signal TRG1 and the time event of the trigger signal TRG1. ref The reference time event and the sampling clock signal CLK samp Time I A time digital value TD1n corresponding to the phase difference PD2 with the vent is generated.

[0179] In the example of FIG. 18, the time required from when the state transition unit 110 of the time-to-digital converter 100A starts the state transition until the time digital value TD1n is obtained is the sampling clock signal CLK samp The time is set so that it does not exceed the half-cycle time of the Thus, even when the time-to-digital converter 100A continuously generates the time digital values ​​TD1n, the current state transition can be completed before the state transition unit 110 starts the next state transition.

[0180] As shown in FIG. 18, the difference between the time digital value TD1n corresponding to the phase difference PD2 and the time digital value TD1n corresponding to the phase difference PD1 is a time τ a The sampling clock signal CLK is a digital value corresponding to the time. s amp The time for one period of is known, and the elapsed time t a is the sampling clock signal CLK samp From the time of one period of a Since it is equal to the time subtracted from the elapsed time t a Compatible with Therefore, the digital signal generator 42 calculates the elapsed time t based on the time digital value TD1n. a Then, the digital signal generator 42 calculates a time digital value corresponding to the elapsed time t aA digital value of the voltage of the input signal Sin can be obtained using the time digital value corresponding to the time, and a digital signal DO having the digital value can be generated.

[0181] In addition, the elapsed time t a In order to calculate the time constant RC in equation (6), it is necessary to know the time constant RC. For example, the voltage Vin is known, and the time constant RC is calculated from the time digital values ​​TD1 and TD2 obtained using the input signal Sin. a Calculate the elapsed time t a Therefore, in advance The constant RC can be calculated in advance.

[0182] Here, the time digital values ​​TD1n corresponding to the phase differences PD1 and PD2 are calculated based on the trigger signal TRG1 and the sampling clock signal CLK. samp Time-to-digital converter 1 Offset values ​​OF1 and OF2 resulting from delays in wiring when the signal propagates to 00A are superimposed on the time digital values ​​TD1n. The offset values ​​OF1 and OF2 can be calculated in advance from the difference between the theoretical value and time digital values ​​TD1n corresponding to the phase differences PD1 and PD2, respectively, obtained using an input signal Sin with a known voltage Vin. The digital signal generator 42 may then subtract the offset value OF1 from the time digital value TD1n corresponding to the phase difference PD1 and subtract the offset value OF2 from the time digital value TD1n corresponding to the phase difference PD2, and generate the digital signal DO based on the time digital value TD1n from which the offset value OF1 has been subtracted and the time digital value TD1n from which the offset value OF2 has been subtracted. This reduces A / D conversion errors resulting from the offset values ​​OF1 and OF2 superimposed on the time digital value TD1n, improving A / D conversion accuracy.

[0183] As described above, in the A / D conversion circuit 1 of the third embodiment, the sample-and-hold circuit 52 receives the sampling clock signal CLK samp Sampling the input signal Sin based on The comparison signal generating unit 10 generates the sampling clock signal CLKsamp Same as The comparison signal Sc having a specific waveform is generated, and the comparator 20 generates the trigger signal TRG1 by comparing the voltage Vin of the hold signal Sinx with the voltage Vc of the comparison signal Sc. Therefore, the sampling clock signal CLK samp The timing of the trigger signal TRG1 for The timing of generating the trigger signal TRG1n generated based on the sampling clock signal TRG1 also changes. samp Trigger signal generated based on The timing at which the trigger signal TRG1n is generated is constant regardless of the voltage Vin of the holding signal Sinx. Therefore, the timing at which the trigger signal TRG1n is generated based on the trigger signal TRG1 and the sampling clock signal CLK samp Trigger signal TRG1n generated based on The phase difference between the voltage Vin and the voltage Sinx changes depending on the voltage Vin of the hold signal Sinx.

[0184] The time-to-digital converter 100A then generates a reference clock signal CLK based on the trigger signal TRG1n. ref and the time digital signal corresponding to the phase difference PD1 between the trigger signal TRG1 and The reference clock signal CLK ref and sampling clock signal CLK samp A time digital value TD1n corresponding to the phase difference PD2 between the two is calculated.

[0185] Therefore, the difference between the time digital value TD1n corresponding to the phase difference PD1 and the time digital value TD1n corresponding to the phase difference PD2 is the difference between the trigger signal TRG1 and the sampling clock signal CLK samp The phase difference between the voltage Vin and the voltage Sinx of the hold signal is Therefore, the digital signal generating section 42 can generate the digital signal DO corresponding to the voltage Vin of the holding signal Sinx, based on the time digital value TD1n.

[0186] In the time-to-digital converter 100A, the state transition unit 110 starts the state transition based on the trigger signal TRG1 and outputs the state value ST1, and the weighting calculation unit 120 calculates the reference clock signal CLK ref In synchronization with this, a value based on the state value ST1 is weighted according to the passage of time. By performing a predetermined calculation using the sampling clock signal CLK, the time digital value TD1n is calculated according to the number of state transitions of the state transition unit 110. samp The state transition is started based on the weighting calculation unit 100, and the state value ST2 is output. 120 is the reference clock signal CLK ref In synchronization with this, the value based on the state value ST2 is changed over time. and performs a predetermined calculation to calculate a time digital value TD1n according to the number of state transitions of the state transition unit 110. This produces a noise shaping effect, shifting noise components caused by variations in the amount of delay of each element constituting the A / D conversion circuit 1 to a high frequency band, and obtaining a time digital value TD1n with a high S / N ratio.

[0187] As described above, according to the A / D conversion circuit 1 of the third embodiment, by using the time-to-digital converter 100A, a time digital value TD1n with a high S / N ratio can be obtained, thereby enabling highly accurate A / D conversion without complicating the circuitry.

[0188] In the A / D conversion circuit 1 of the third embodiment, the sample-and-hold circuit 52 receives the sampling clock signal CLK samp The input signal Sin is sampled and held based on Therefore, according to the A / D conversion circuit 1 of the third embodiment, the voltage of the hold signal Sinx is constant even if the voltage of the input signal Sin fluctuates, so that fluctuations in the sampling timing according to the voltage of the input signal Sin are reduced, enabling A / D conversion to be performed with high accuracy.

[0189] Furthermore, according to the A / D conversion circuit 1 of the third embodiment, A / D conversion is performed using one time-to-digital converter 100A, so the size can be made smaller than the A / D conversion circuit 1 of the first embodiment, which uses two time-to-digital converters 100A and 100B, or the A / D conversion circuit 1 of the second embodiment, which uses three time-to-digital converters 100A, 100B, and 100C.

[0190] 4. Fourth embodiment Below, for the A / D conversion circuit of the fourth embodiment, components similar to those of the first, second or third embodiment will be given the same symbols, and their explanations will be omitted or simplified, and the explanation will mainly focus on the differences from the first, second and third embodiments.

[0191] Fig. 19 is a diagram showing the configuration of an A / D conversion circuit according to the fourth embodiment. As shown in Fig. 19, the A / D conversion circuit 1 according to the fourth embodiment includes a comparison signal generation unit 10, a comparator 20, a timing generation unit 30, a digital signal generation unit 43, a frequency division circuit 50, a sample-and-hold circuit 52, and a time-to-digital converter 100A.

[0192] The frequency divider circuit 50 divides the reference clock signal CLK ref is divided to generate the sampling clock signal CLK samp Therefore, in this embodiment, the sampling clock signal C LK samp is the reference clock signal CLK ref is synchronized with.

[0193] The sample and hold circuit 52 receives the sampling clock signal CLK samp Based on The force signal Sin is sampled and held, and a held signal Sinx is output.

[0194] The comparison signal generating unit 10 generates a sampling clock signal CLK samp Specific to synchronize In the fourth embodiment, similarly to the first, second and third embodiments, the comparison signal generating section 10 generates a comparison signal Sc having a waveform of the sampling clock signal CLK. samp The integrating circuit includes a resistor 11 and a capacitor 12, The comparison signal Sc is generated based on the output signal of the circuit. The division ratio of the frequency divider circuit 50 is set appropriately depending on the time constant of the integrator circuit.

[0195] The comparator 20 generates a trigger signal TRG1 by comparing the voltage of a held signal Sinx, which is the input signal Sin held by the sample-and-hold circuit 52, with the voltage of a comparison target signal Sc.

[0196] The timing generating section 30 generates a trigger signal TRG1n for instructing the operation timing of the time-to-digital converter 100A based on the trigger signal TRG1.

[0197] The time-to-digital converter 100A receives a reference clock signal CLK ref and the trigger signal TRG 1n is input, and the reference clock signal CLK ref and the phase difference between the trigger signal TRG1n Specifically, the time-to-digital converter 100A calculates a time digital value TD1 corresponding to the reference clock signal CLK ref Reference time event and trigger signal TRG1n A time digital value TD1 corresponding to the phase difference PD1 between the time event is calculated.

[0198] In this embodiment, the sampling clock signal CLK samp is the reference clock signal CL K refSince it is synchronized with the reference clock signal CLK ref The time event that is the basis for and the sampling clock signal CLK samp The phase difference PD2 between the time event and the Therefore, the time digital value TD2 corresponding to the phase difference PD2 is also known.

[0199] The digital signal generator 43 generates a digital signal DO corresponding to the voltage of the input signal Sin based on the time digital value TD1 and the known time digital value TD2.

[0200] In FIG. 19, the trigger signal TRG1 corresponds to the "first trigger signal", and the sampling clock signal CLK samp corresponds to the "second trigger signal." The digital value TD1 corresponds to the “first time digital value,” and the digital value TD2 corresponds to the “second time digital value.” Furthermore, the time-to-digital converter 100A corresponds to the “first time-to-digital converter.”

[0201] In this embodiment, the configuration and functions of the time-to-digital converter 100A are as described above with reference to FIGS.

[0202] The state transition unit 110 of the time-to-digital converter 100A corresponds to the "first state transition unit." Moreover, the state value ST1 output from the state transition unit 110 of the time-to-digital converter 100A corresponds to the “first state information.” Moreover, the weighting calculation unit 120 of the time-to-digital converter 100A corresponds to the “first weighting calculation unit.”

[0203] FIG. 20 is a timing chart showing an example of the operation timing of the A / D conversion circuit 1 of the fourth embodiment.

[0204] As shown in FIG. 20, the voltage of the comparison signal Sc is equal to the voltage of the sampling clock signal CLK sa mpIn synchronization with the rising edge of It increases with a time constant determined by RC.

[0205] Sampling clock signal CLK samp The time t elapsed from the rising edge of a To The voltage V of the comparison signal Sc c is the voltage V of the input signal Sin in If it crosses, the voltage V in is expressed by the above-mentioned equation (6). In equation (6), the reference voltage V ref , resistor 11 Since the resistance value R and the capacitance value C of the capacitor 12 are known, their digital values ​​are also known. a Once the digital value of is obtained, the voltage V of the holding signal Sinx in Digital The value is calculated.

[0206] As shown in Figure 20, the voltage V of the input signal Sin in is the voltage V of the comparison signal Sc c twist The trigger signal TRG1 becomes high level when the trigger signal TRG1n is also high. The rising edge of the trigger signal TRG1n occurs at approximately the same timing as the rising edge of the trigger signal TRG1. As described above, the time-to-digital converter 100A generates p pulses of the clock signal CK while the trigger signal TRG1n is at high level, and generates p pulses of the reference clock signal CLK ref The phase difference PD between the reference time event and the time event of the trigger signal TRG1 A time digital value TD1 corresponding to 1 is generated.

[0207] As mentioned above, the sampling clock signal CLK samp is the reference clock signal C LK ref Since it is synchronized with the reference clock signal CLK ref The time event that is the basis for and the sampling clock signal CLKsamp The phase difference PD2 corresponds to the time event The time digital value TD2 is known.

[0208] In the example of FIG. 20, the time required from when the state transition unit 110 of the time-to-digital converter 100A starts the state transition until the time digital value TD1 is obtained is equal to the sampling clock signal CLK samp It is set so that the time does not exceed the half period of the Therefore, even if the time-to-digital converter 100A continuously generates the time digital value TD1, the current state transition can be completed before the state transition unit 110 starts the next state transition.

[0209] As shown in Figure 20, the elapsed time t a is equal to the difference between the phase difference PD1 and the phase difference PD2, the difference between the time digital value TD1 and the time digital value TD2 is equal to the elapsed time t a Therefore, the digital signal generator 43 calculates the elapsed time t based on the time digital value TD1 and the known time digital value TD2. a Then, the digital signal generator 43 calculates a time digital value corresponding to the elapsed time t a A digital value of the voltage of the input signal Sin can be obtained using the time digital value corresponding to the time, and a digital signal DO having the digital value can be generated.

[0210] In addition, the elapsed time t a In order to calculate the time constant RC in equation (6), it is necessary to know the time constant RC. For example, the elapsed time t a Calculate the elapsed time t a Therefore, the time constant RC can be calculated in advance.

[0211] Here, an offset value OF1 caused by delays due to wiring when the trigger signal TRG1 propagates to the time-to-digital converter 100A is superimposed on the time digital value TD1. The offset value OF1 can be calculated in advance from the difference between the time digital value TD1 obtained using an input signal Sin, whose voltage Vin is known, and a theoretical value. The digital signal generator 43 may then subtract the offset value OF1 from the time digital value TD1 and generate the digital signal DO based on the time digital value TD1 from which the offset value OF1 has been subtracted and the known time digital value TD2. This reduces A / D conversion errors caused by the offset value OF1 superimposed on the time digital value TD1, improving A / D conversion accuracy.

[0212] As described above, in the A / D conversion circuit 1 of the fourth embodiment, the sample-and-hold circuit 52 receives the sampling clock signal CLK samp Sampling the input signal Sin based on The comparison signal generating unit 10 generates the sampling clock signal CLK samp Same as The comparison signal Sc having a specific waveform is generated, and the comparator 20 generates the trigger signal TRG1 by comparing the voltage Vin of the hold signal Sinx with the voltage Vc of the comparison signal Sc. Therefore, the sampling clock signal CLK samp The timing at which the trigger signal TRG1 is generated changes. Therefore, the trigger signal TRG1 and the sampling clock signal CLK samp The phase difference with , the voltage Vin of the holding signal Sinx changes according to the voltage.

[0213] The time-to-digital converter 100A then converts the reference clock signal CLK ref and trigger signal A time digital value TD1 corresponding to a phase difference PD1 between the reference clock signal CLK1 and the reference clock signal TRG1 is calculated. ref is divided to generate the sampling clock signal CLKsa mp Therefore, the sampling clock signal CLK samp is the reference clock signal CL K ref Therefore, the reference clock signal CLK ref and sampling Clock signal CLK samp The time digital value TD2 corresponding to the phase difference between Therefore, the difference between the time digital value TD1 and the time digital value TD2 is the difference between the trigger signal TRG1 and the sampling clock signal CLK samp The phase difference between the hold signal S The digital signal generator 43 can generate a digital signal DO corresponding to the voltage Vin of the hold signal Sinx based on the time digital value TD1 and the known time digital value TD2.

[0214] In the time-to-digital converter 100A, the state transition unit 110 starts the state transition based on the trigger signal TRG1 and outputs the state value ST. The weighting calculation unit 120 calculates the reference clock signal CLK. ref In synchronization with this, the value based on the state value ST is weighted according to the passage of time. and performs a predetermined calculation to calculate a time digital value TD1 according to the number of state transitions of the state transition unit 110. This produces a noise shaping effect, shifting noise components caused by variations in the amount of delay of each element constituting the A / D conversion circuit 1 to a high frequency band, and obtaining a time digital value TD1 with a high S / N ratio.

[0215] Thus, according to the A / D conversion circuit 1 of the fourth embodiment, by using the time-to-digital converter 100A, a time digital value TD1 with a high S / N ratio can be obtained, thereby enabling high-precision A / D conversion without complicating the circuitry.

[0216] In the A / D conversion circuit 1 of the fourth embodiment, the sample-and-hold circuit 52 receives the sampling clock signal CLK samp The input signal Sin is sampled and held based on Therefore, according to the A / D conversion circuit 1 of the fourth embodiment, the voltage of the hold signal Sinx is constant even if the voltage of the input signal Sin fluctuates, so that fluctuations in the sampling timing according to the voltage of the input signal Sin are reduced, enabling A / D conversion to be performed with high accuracy.

[0217] Furthermore, according to the A / D conversion circuit 1 of the fourth embodiment, A / D conversion is performed using one time-to-digital converter 100A, so the size can be made smaller than the A / D conversion circuit 1 of the first embodiment, which uses two time-to-digital converters 100A and 100B, or the A / D conversion circuit 1 of the second embodiment, which uses three time-to-digital converters 100A, 100B, and 100C.

[0218] Furthermore, according to the A / D conversion circuit 1 of the fourth embodiment, the sampling clock signal CLK samp A / D conversion can be performed for each cycle of the sampling clock. Clock signal CLK samp This is higher than the A / D conversion circuit 1 of the third embodiment, which requires two periods. A / D conversion can be performed quickly.

[0219] 5. Variations In the A / D conversion circuit 1 of the first, third or fourth embodiment, the digital signal generation units 40, 42 and 43 each generate a sampling clock signal CLK samp of From the rising edge, the voltage V of the comparison signal Sc c is the voltage V of the input signal Sin in Exchange with Time elapsed until the insertion t a The digital value is calculated based on the sampling clock signal CLK samp From the falling edge of cis input Voltage V of signal Sin in The time elapsed until the intersection with b Calculate the time digital value corresponding to The voltage V of the input signal Sin in The lower the elapsed time t b becomes smaller, so The digital signal generators 40, 42, and 43 respectively generate a signal corresponding to the elapsed time t b The voltage V of the input signal Sin is calculated using the digital value corresponding to the time in The digital value of A digital signal DO can be generated.

[0220] Furthermore, similar to the A / D conversion circuit 1 of the second embodiment, in the A / D conversion circuit 1 of the first, third or fourth embodiment, the digital signal generation units 40, 42, 43 may each calculate the fluctuation amount ε of the time constant RC and generate a digital signal DO in which the fluctuation amount ε is compensated.

[0221] Furthermore, in each of the above embodiments, the state transition unit 110 and the transition state acquisition unit 130 may be modified as shown in Fig. 21. In the example of Fig. 21, the state transition unit 110 starts a state transition in which the internal state transitions based on a trigger signal TRG, and outputs state information indicating the internal state. As shown in Fig. 21, the state transition unit 110 includes an exclusive OR circuit 211, an NAND circuit 212, an accumulator 213, a modulo calculator 214, a quantizer 215, a multi-stage delay line 216, and an accumulator 217.

[0222] The exclusive OR circuit 211 outputs an exclusive OR signal EX of the trigger signal TRG and the quantized signal QT output from the quantizer 215. The exclusive OR signal EX goes to a high level when the logical level of the trigger signal TRG and the logical level of the quantized signal QT are different, and goes to a low level when the logical level of the trigger signal TRG and the logical level of the quantized signal QT are the same.

[0223] The NAND circuit 212 outputs a clock signal CK, which is an NAND signal of the exclusive OR signal EX and the signal D[n] output from the multi-stage delay line 216. The clock signal CK is at a low level when both the exclusive OR signal EX and the signal D[n] are at a high level, and is at a high level when at least one of the exclusive OR signal EX and the signal D[n] is at a low level.

[0224] The accumulator 213 adds 1 every time a rising edge of the clock signal CK occurs and outputs an integrated value CE. In other words, the accumulator 213 counts the rising edges of the clock signal CK and outputs an integrated value CE. The accumulator 213 may also count the falling edges of the clock signal CK.

[0225] The modulo calculator 214 performs a modulo operation using the accumulated value CE as the dividend and a predetermined value as the divisor. That is, the modulo calculator 214 outputs a remainder value MD when dividing the accumulated value CE as the dividend and the predetermined value as the divisor. The predetermined value that is the divisor is set appropriately.

[0226] The quantizer 215 compares the remainder value MD with a predetermined threshold value to quantize the remainder value MD and output a quantized signal QT. In other words, the quantizer 215 divides the remainder value MD as the dividend by the threshold value as the divisor, and outputs the quotient as the quantized signal QT.

[0227] Multi-stage delay line 216 has a plurality of delay elements, specifically n+1 delay elements 218-0 to 218-n, where n is an integer equal to or greater than 1. Multi-stage delay line 216 is a delay line in which n+1 delay elements 218-0 to 218-n are connected in a chain shape, and has one input terminal and n output terminals. Such multi-stage delay line 216 is also called a tapped delay line (TDL). Delay elements 218-0 to 218-n are buffer elements or logic inversion elements, respectively. In the following description, it is assumed that delay elements 218-0 to 218-n are all buffer elements.

[0228] The input terminal of the first delay element 218-0 of the multi-stage delay line 216 becomes the input terminal of the multi-stage delay line 216. Furthermore, the output terminals of the delay elements 218-0 to 218-n become n output terminals of the multi-stage delay line 216. Signals D[0] to D[n] are output from the n output terminals of the multi-stage delay line 216 in order from the input terminal side of the multi-stage delay line 216.

[0229] A clock signal CK is input to the input terminal of the multi-stage delay line 216. When the clock signal CK changes from low level to high level, the high-level clock signal CK propagates through the delay element 218-0, causing the signal D[0] to change from low level to high level. When the high-level signal D[i-1] propagates through the delay element 218-i, the signal D[i] changes from low level to high level, where i is an arbitrary integer between 1 and n. In other words, the high-level signal propagates through the delay elements 218-0 to 218-n in order, causing the signals D[0] to D[n] to change from low level to high level in order.

[0230] Similarly, when the clock signal CK changes from high to low, the low-level clock signal CK propagates through delay element 218-0, causing signal D[0] to change from high to low. Then, when the low-level signal D[i-1] propagates through delay element 218-i, signal D[i] changes from high to low, where i is an arbitrary integer between 1 and n. That is, the low-level signal propagates through delay elements 218-0 to 218-n in order, causing signals D[0] to D[n+1] to change from high to low in order.

[0231] The accumulator 217 adds 1 every time a rising edge of the clock signal CK occurs, and outputs an (m+1)-bit signal q[m:0], where m is an integer equal to or greater than 0. In other words, the accumulator 217 counts the rising edges of the clock signal CK and outputs the signal q[m:0]. That is, the signal q[m:0] corresponds to the count information of the edges of the clock signal CK. The accumulator 217 may also count the falling edges of the clock signal CK.

[0232] Fig. 22 is a diagram showing an example of the waveform of each signal in state transition unit 110. Fig. 22 shows an example in which n is 6, m is 2, the divisor in the modulo operation by modulo operator 204 is 16, and the threshold value for quantization by quantizer 205 is 8.

[0233] In the example of Figure 22, when the logic level of the trigger signal TRG changes, the exclusive OR signal EX changes from low to high, and pulses of the clock signal CK are generated continuously while the exclusive OR signal EX is high. The integrated value CE increases by one at each rising edge of the clock signal CK, and the remainder value MD increases as the integrated value CE increases, and is initialized to 0 each time the integrated value CE becomes an integer multiple of 16. The quantized signal QT goes low when the remainder value MD is 7 or less, and goes high when the remainder value MD is 8 or more. When the logic level of the quantized signal QT changes, the exclusive OR signal EX changes from high to low, and the generation of pulses of the clock signal CK stops.

[0234] 22, each time the logic level of the trigger signal TRG changes, the logic level of the clock signal CK is inverted 16 times, generating eight pulses. However, if the divisor in the modulo calculation by the modulo calculator 204 and the threshold value for quantization by the quantizer 205 are changed, the number of pulses of the clock signal CK also changes. For example, if the divisor in the modulo calculation by the modulo calculator 204 is 2p and the threshold value for quantization by the quantizer 205 is p, each time the logic level of the trigger signal TRG changes, the logic level of the clock signal CK is inverted 2p times, generating p pulses. Each time the logic level of the clock signal CK changes, the signal q[2:0] is incremented by 1. Each time the logic level of the clock signal CK changes, each bit of the signal D[6:0] changes in sequence.

[0235] Here, the value of the 10-bit signal composed of the signal q[2:0] and the signal D[6:0] changes over time. Therefore, if the internal state of the state transition unit 110 is defined in association with the value of this 10-bit signal, the state transition unit 110 will start a state transition in which the internal state transitions based on the trigger signal TRG, and will output a state value ST composed of the signal q[2:0] output from the accumulator 217 and the signal D[6:0] output from the multi-stage delay line 216 as state information indicating the internal state.

[0236] 21, the transition state acquisition unit 130 is a latch circuit that latches and holds the state information output by the state transition unit 110 based on a latch signal. The latch signal is a clock signal CLK ref and the state information is composed of the signal q[m:0] and the signal D[n:0]. 21, the transition state acquisition unit 130 includes n+1 D flip-flops 231-0 to 231-n, and an m+1-bit register 232 made up of m+1 D flip-flops.

[0237] Each of the D flip-flops 231-0 to 231-n receives a clock signal CLK ref Standing In synchronization with the rising edge, each of the signals D[0] to D[n] is acquired, and signals S[0] to S[n] corresponding to the logic levels of each of the signals D[0] to D[n] are held.

[0238] The register 232 also receives the clock signal CLK. ref Synchronized with the rising edge of , acquires the signal q[m:0], and holds the signal Q[m:0] according to the value of the signal q[2:0].

[0239] The transition state acquisition unit 130 configured in this manner receives the clock signal CLK ref Standing At the timing of the rising edge, the transition state acquisition unit 130 functions as a latch circuit that latches and holds the state value ST that indicates the internal state of the state transition unit 110. Then, the transition state acquisition unit 130 outputs the state value LST that is composed of the signal Q[m:0] and the signal S[n:0].

[0240] Here, when the value of the signal S[0] is 1, the number of bits whose value is 1 contained in the signal S[m:0] is equal to the number of bits whose value is 1 contained in the signal S[m:0]. ref Multi-stage delay line 2 at the timing of the rising edge of Similarly, if the value of signal S[0] is 0, the number of bits with a value of 0 contained in signal S[m:0] is equal to the number of bits of clock signal CLK ref The low-frequency signal propagating through the multi-stage delay line 216 at the timing of the rising edge of The value of the signal Q[m:0] indicates the position of the clock signal CK at the level. ref Indicates the number of rising edges of

[0241] Therefore, although not shown in the figure, the state transition counting unit 150 subsequent to the transition state acquisition unit 130 calculates the number of state transitions of the state transition unit 110 after the occurrence of a time event of the trigger signal TRG by performing a predetermined calculation on the state value LST, and can calculate the count value CNT by calculating the difference between the calculated values ​​of two consecutive state transitions.

[0242] Furthermore, in each of the above embodiments, the state transition unit 110 and the transition state acquisition unit 130 may be modified as shown in Fig. 23. In the example of Fig. 23, the state transition unit 110 starts a state transition in which the internal state transitions based on a trigger signal TRG, and outputs state information indicating the internal state. As shown in Fig. 23, the state transition unit 110 includes an exclusive OR circuit 211, an NAND circuit 212, an accumulator 213, a modulo calculator 214, a quantizer 215, a multi-stage delay line 216, and a synchronous transition unit 219.

[0243] The functions of the exclusive OR circuit 211 and the NAND circuit 212 are the same as those in FIG. 21, and therefore a description thereof will be omitted.

[0244] The synchronous transition unit 219 counts the edges of the clock signal CK output from the NAND circuit 212. The synchronous transition unit 219 is a state machine whose state transitions in synchronization with the clock signal CK, and the m+1-bit signal q[m:0] output from the synchronous transition unit 219 is a signal indicating the state, where m is an integer greater than or equal to 0. The synchronous transition unit 219 transitions its state every time the logic level of the clock signal CK is inverted, so the signal q[m:0] corresponds to count information of the edges of the clock signal CK. In addition, the synchronous transition unit 219 outputs a signal dout which is supplied to the input terminal of the multi-stage delay line 216.

[0245] When the synchronization transition unit 219 transitions from any state to the next state, only one bit of the m+1 bits of the signal q[m:0] changes. That is, the Hamming distance of the signal q[m:0] before and after the state transition of the synchronization transition unit 219 is 1. For example, the synchronization transition unit 219 may be a Gray code counter.

[0246] FIG. 24 shows a state transition table in which the synchronous transition unit 219 is a Gray code counter and m is 2. In FIG. 24 and the following description, low and high levels are represented as 0 and 1, respectively. In the example in FIG. 24, the synchronous transition unit 219 has eight states, T0 to T7. In state T0 in which the signal q[2:0] is "000," the synchronous transition unit 219 maintains state T0 if the clock signal CK is low; if the clock signal CK is low, bit 0 of the signal q[2:0] changes from 0 to 1, causing the synchronous transition unit 219 to transition to state T1. In state T1 in which the signal q[2:0] is "001," if the clock signal CK is low, bit 1 of the signal q[2:0] changes from 0 to 1, causing the synchronous transition unit 219 to transition to state T2; and if the clock signal CK is high, the synchronous transition unit 219 maintains state T1. Furthermore, in state T2 when signal q[2:0] is "011", if the clock signal CK is at a low level, the synchronous transition unit 219 maintains state T2; if the clock signal CK is at a high level, bit 0 of signal q[2:0] changes from 1 to 0, and the synchronous transition unit 219 transitions to state T3. Furthermore, in state T3 when signal q[2:0] is "010", if the clock signal CK is at a low level, bit 2 of signal q[2:0] changes from 0 to 1, and the synchronous transition unit 219 transitions to state T4; and if the clock signal CK is at a high level, the synchronous transition unit 219 maintains state T3. Furthermore, in state T4 when signal q[2:0] is "110", if the clock signal CK is at a low level, the synchronous transition unit 219 maintains state T4; if the clock signal CK is at a high level, bit 0 of signal q[2:0] changes from 0 to 1, and the synchronous transition unit 219 transitions to state T5. Furthermore, in state T5 when signal q[2:0] is "111", if the clock signal CK is at a low level, the synchronous transition unit 219 changes bit 1 of signal q[2:0] from 1 to 0, causing a transition to state T6, and maintaining state T5 if the clock signal CK is at a high level. Furthermore, in state T6 when signal q[2:0] is "101", if the clock signal CK is at a low level, the synchronous transition unit 219 maintains state T6, and if the clock signal CK is at a high level, the synchronous transition unit 219 changes bit 0 of signal q[2:0] from 1 to 0, causing a transition to state T7. Furthermore, in state T7 when signal q[2:0] is "100", if the clock signal CK is at a low level, the synchronous transition unit 219 changes bit 2 of signal q[2:0] from 1 to 0, causing a transition to state T0, and maintaining state T7 if the clock signal CK is at a high level.

[0247] 24, the synchronization transition unit 219 transitions from state T0 to state T7 and then returns to state T0, but in each state transition, the signal q[2:0] changes by only one bit. Therefore, the Hamming distance of the signal q[2:0] before and after the state transition of the synchronization transition unit 219 is 1.

[0248] 24, the signal dout is 0 in states T0, T2, T4, and T6, and is 1 in states T1, T3, T5, and T7. Therefore, the logic level of the signal dout is inverted every time a state transition occurs.

[0249] 23, the accumulator 213 adds 1 every time a rising edge of the signal dout occurs, and outputs an accumulated value CE. In other words, the accumulator 213 counts the rising edges of the signal dout and outputs an accumulated value CE. The accumulator 213 may also count the falling edges of the signal dout.

[0250] The functions of the modulo calculator 214 and the quantizer 215 are the same as those in Fig. 21, and therefore their description will be omitted. Also, although the input signal is the signal dout rather than the clock signal CK, the configuration and function of the multi-stage delay line 216 are the same as those in Fig. 21, and therefore their description will be omitted.

[0251] Fig. 25 is a diagram showing an example of the waveform of each signal in state transition unit 110. Fig. 25 shows an example in which n is 6, m is 2, the divisor in the modulo operation by modulo operator 204 is 16, and the threshold value for quantization by quantizer 205 is 8.

[0252] In the example of Figure 25, when the logic level of the trigger signal TRG changes, the exclusive OR signal EX changes from low to high, and pulses of the clock signal CK are generated continuously while the exclusive OR signal EX is high. The integrated value CE increases by one at each rising edge of the clock signal CK, and the remainder value MD increases as the integrated value CE increases, and is initialized to 0 each time the integrated value CE becomes an integer multiple of 16. The quantized signal QT goes low when the remainder value MD is 7 or less, and goes high when the remainder value MD is 8 or more. When the logic level of the quantized signal QT changes, the exclusive OR signal EX changes from high to low, and the generation of pulses of the clock signal CK stops.

[0253] 25, each time the logic level of the trigger signal TRG changes, the logic level of the clock signal CK is inverted 16 times, generating eight pulses. However, if the divisor in the modulo calculation by the modulo calculator 204 and the quantization threshold by the quantizer 205 are changed, the number of pulses of the clock signal CK also changes. For example, if the divisor in the modulo calculation by the modulo calculator 204 is 2p and the quantization threshold by the quantizer 205 is p, each time the logic level of the trigger signal TRG changes, the logic level of the clock signal CK is inverted 2p times, generating p pulses. Each time the logic level of the clock signal CK changes, the state of the synchronization transition section 219, i.e., one bit of the signal q[2:0], changes, and the logic level of the signal dout also changes. Furthermore, each time the logic level of the signal dout changes, each bit of the signal D[6:0] changes in sequence.

[0254] Here, the value of the 10-bit signal composed of the signal q[2:0] and the signal D[6:0] changes over time. Therefore, if the internal state of the state transition unit 110 is defined in association with the value of this 10-bit signal, the state transition unit 110 will start a state transition in which the internal state transitions based on the trigger signal TRG, and will output a state value ST composed of the signal q[2:0] output from the synchronous transition unit 219 and the signal D[6:0] output from the multi-stage delay line 216 as state information indicating the internal state.

[0255] Returning to the explanation of FIG. 23, the transition state acquisition unit 130 receives the clock signal CLK ref The rise of At the timing of the falling edge, the state transition acquisition unit 130 functions as a latch circuit that latches and holds the state value ST that indicates the internal state of the state transition unit 110. The transition state acquisition unit 130 then outputs a state value LST that is made up of the signal Q[m:0] and the signal S[n:0]. The function of the transition state acquisition unit 130 is the same as that in FIG. 21, so a detailed description thereof will be omitted.

[0256] Here, when the value of the signal S[0] is 1, the number of bits whose value is 1 contained in the signal S[m:0] is equal to the number of bits whose value is 1 contained in the signal S[m:0]. refMulti-stage delay line 2 at the timing of the rising edge of Similarly, when the value of the signal S[0] is 0, the number of bits with the value 0 contained in the signal S[m:0] is 1 / 2 of the clock signal CLK ref The low-level signal propagating through the multi-stage delay line 216 at the timing of the rising edge of The value of the signal Q[m:0] indicates the position of the signal dout in the loop. ref indicates the number of edges.

[0257] Therefore, although not shown in the figure, the state transition counting unit 150 subsequent to the transition state acquisition unit 130 calculates the number of state transitions of the state transition unit 110 after the occurrence of a time event of the trigger signal TRG by performing a predetermined calculation on the state value LST, and can calculate the count value CNT by calculating the difference between the calculated values ​​of two consecutive state transitions.

[0258] Furthermore, when the internal state of the state transition unit 110 transitions from an arbitrary state to the next state, the state value ST, which is composed of the signal q[m:0] and the signal D[n:0], changes by only one bit. That is, the Hamming distance of the state information before and after the state transition of the state transition unit 110 is 1. Therefore, when the state transition unit 110 transitions from an arbitrary state to the next state, it does not pass through any other state, so the clock signal CLK ref Timing of rising edge and state transition part 1 Even if the timing of the state transition of the current state 10 substantially coincides with the timing of the current state transition of the current state 10, the transition state acquisition unit 130 can latch the state value ST corresponding to either of the two states before and after the state transition. Therefore, the risk that the transition state acquisition unit 130 acquires erroneous state information is reduced.

[0259] The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0260] For example, a part of the first embodiment may be replaced with a part of any one of the second to fourth embodiments, as appropriate. Similarly, a part of the second embodiment may be replaced with a part of any one of the first, third, or fourth embodiments, as appropriate. Similarly, a part of the third embodiment may be replaced with a part of any one of the first, second, or fourth embodiments, as appropriate. Similarly, a part of the fourth embodiment may be replaced with a part of any one of the first to third embodiments, as appropriate.

[0261] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0262] The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects). The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects as the configurations described in the embodiments or that can achieve the same purpose. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments. [Explanation of symbols]

[0263] 1...A / D conversion circuit, 10...comparison signal generation unit, 11...resistor, 12...capacitor, 20...comparator, 30, 31, 32...timing generation unit, 40, 41, 42, 43...digital signal generation unit, 50...frequency divider circuit, 52...sample and hold circuit, 54, 56...logic inversion circuit, 100, 100A, 100B, 100C...time digital converter, 110...state transition unit, 111...oscillator unit, 112...accumulator, 120...weighting calculation unit, 121...accumulator, 130...transition state acquisition unit, 131...register, 140...calculation unit, 141...register, 142...subtractor, 143 ...accumulator, 144...multiplier, 145...accumulator, 150...state transition counter, 160...weighting unit, 170...accumulator, 201...exclusive OR circuit, 202...NAND circuit, 203...accumulator, 204...modulo calculator, 205...quantizer, 206...buffer circuit, 211...exclusive OR circuit, 212...NAND circuit, 213...accumulator, 214...modulo calculator, 215...quantizer, 216...multistage delay line, 217...accumulator, 218-0 to 218-n...delay elements, 219...synchronization transition unit, 231-0 to 231-n...D flip-flop, 232...register

Claims

1. At least one of the rising edge and the falling edge is used as a time event. a trigger signal having the time event is input, and a trigger signal is input to the time event of the trigger signal; an oscillator that starts oscillating based on the time a state transition unit including a first accumulator that accumulates a constant in response to an event and outputs a state value; In response to the time event of the reference clock signal, the state value is accumulated to generate a time digital value. a second integrator that outputs a time-to-digital converter including:

2. the time digital value is a first time digital value; When the trigger signal is a first trigger signal, A time-to-digital converter according to claim 1; a comparison signal generation unit that generates a comparison signal synchronized with a sampling clock signal; The first trigger is generated by comparing the voltage of the input signal with the voltage of the comparison signal. a comparator for generating a signal; a second trigger signal based on the reference clock signal and the sampling clock signal; and the first time digital value, a digital signal generator that generates a digital signal corresponding to the voltage of the input signal; An A / D conversion circuit including:

3. In claim 2, The comparison signal generation unit an integration circuit that integrates the sampling clock signal; an A / D conversion circuit that generates the comparison signal based on the output signal of the integration circuit;

4. In claim 3, The digital signal generation unit the first time digital value, the second time digital value, and the reference clock signal; a third time corresponding to a phase difference between the first trigger signal and a third trigger signal synchronized with the first trigger signal; The amount of fluctuation in the time constant of the integrating circuit is calculated based on the digital value, and the amount of fluctuation is compensated for. an A / D conversion circuit for generating the digital signal.

5. In claim 4, A sampling clock signal is used to sample and hold the input signal. a sample and hold circuit; The comparator The voltage of the input signal held by the sample-and-hold circuit and the comparison signal an A / D conversion circuit that generates the first trigger signal by comparing the voltage of the input signal with the voltage of the output signal;

6. In claim 5, The sampling clock signal is synchronized with the reference clock signal. circuit.

7. In claim 6, The digital signal generation unit subtracting an offset value from the first time digital value; The digital signal is calculated based on the first time digital value from which the offset value has been subtracted. An A / D conversion circuit that generates a signal.

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