Resistive random access memory device and method for manufacturing same

Abstract

To solve defects or faults of the prior arts by providing an improved resistive random access memory (RRAM) device and a fabrication method thereof.SOLUTION: An RRAM device 1 includes a substrate 100; a first inter-layer dielectric (ILD) layer 110 disposed on the substrate; a first interconnect structure M1 disposed in the first ILD layer; a capping layer 120 disposed on the first interconnect structure and the first ILD layer; an intermediate dielectric layer 130 disposed on the capping layer; a conductive via 200 disposed in the capping layer and the intermediate dielectric layer, wherein the conductive via comprises a polishing stop layer 201, a barrier layer 202 on the polishing stop layer, and a tungsten layer 203 on the barrier layer; and a resistive switching structure 300 disposed on the conductive via.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the field of semiconductor technology, and more particularly to resistive random access memory (RRAM) devices and methods for fabricating the same. [Background technology]

[0002] Resistive random access memory (RRAM) is a memory structure that includes an array of RRAM cells, each of which stores bits of data using resistance values ​​rather than using an electric charge. In particular, each of these RRAM cells includes a resistive-switching material layer whose resistance can be adjusted to represent a logic "0" or a logic "1."

[0003] At advanced technology nodes, feature sizes are scaled down, and memory device sizes are reduced accordingly. However, the reduction of RRAM devices is limited by the "forming" operation, in which a high voltage is applied to the RRAM device to create a conductive path in the resistive switching material layer.

[0004] When RRAM devices are integrated into the 12-nm node process, a short via design is usually used. The tungsten metal grinding process consumes more silicon oxide layers, so the step height required for alignment in the lithography process is not sufficient. Adding a photomask can solve the alignment problem, but it increases the cost of the process. Summary of the Invention

[0005] SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved resistive random access memory (RRAM) device and method for fabricating the same, which overcomes the deficiencies or shortcomings of existing technology.

[0006] One aspect of the present invention provides a resistive random access memory device including a substrate, a first inter-layer dielectric (ILD) layer disposed over the substrate, a first interconnect structure disposed in the first ILD layer, a capping layer disposed over the first interconnect structure and the first ILD layer, an intermediate dielectric layer disposed over the capping layer, a conductive via disposed in the capping layer and the intermediate dielectric layer, the conductive via including a polishing stop layer, a barrier layer over the polishing stop layer, and a tungsten layer over the barrier layer, and a resistive switching structure disposed over the conductive via.

[0007] According to some of the embodiments, the conductive via includes an upper portion protruding from a top surface of the intermediate dielectric layer.

[0008] According to some of the embodiments, the resistive random access memory device further includes a sidewall spacer disposed around an upper portion of the conductive via and the resistive switching structure.

[0009] According to some of the embodiments, the sidewall spacers cover the sidewalls of the resistive switching structure, the sidewalls of the top of the conductive via, and the top surface of the intermediate dielectric layer, and the sidewall spacers are in direct contact with the polishing stop layer.

[0010] According to some embodiments, the sidewall spacers include a silicon nitride layer and a silicon oxide layer.

[0011] According to some of the embodiments, the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.

[0012] According to some embodiments, the interlevel dielectric layer comprises a TEOS-based silicon oxide layer.

[0013] According to some embodiments, the polish stop layer comprises tantalum nitride.

[0014] According to some of the embodiments, the barrier layer comprises titanium nitride.

[0015] According to some of the embodiments, the resistive random access memory device further includes a second inter-layer dielectric (ILD) layer covering the sidewall spacers and a second interconnect structure disposed in the second ILD layer.

[0016] Another aspect of the present invention provides a method for forming a resistive random access memory device. A substrate is provided. A first inter-layer dielectric (ILD) layer is formed over the substrate. A first interconnect structure is formed in the first ILD layer. A capping layer is formed over the first interconnect structure and the first ILD layer. An intermediate dielectric layer is formed over the capping layer. A conductive via is formed in the capping layer and the intermediate dielectric layer, the conductive via including a polishing stop layer, a barrier layer over the polishing stop layer, and a tungsten layer over the barrier layer. A resistive switching structure is formed over the conductive via.

[0017] According to some of the embodiments, the conductive via includes an upper portion that protrudes from a top surface of the intermediate dielectric layer.

[0018] According to some of the embodiments, the method further includes forming a sidewall spacer on top of the conductive via and around the resistive switching structure.

[0019] According to some of the embodiments, the sidewall spacers cover the sidewalls of the resistive switching structure, the sidewalls of the top of the conductive via, and the top surface of the intermediate dielectric layer, and the sidewall spacers are in direct contact with the polishing stop layer.

[0020] According to some embodiments, the sidewall spacers include a silicon nitride layer and a silicon oxide layer.

[0021] According to some of the embodiments, the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.

[0022] According to some embodiments, the interlevel dielectric layer comprises a TEOS-based silicon oxide layer.

[0023] According to some embodiments, the polish stop layer comprises tantalum nitride.

[0024] According to some of the embodiments, the barrier layer comprises titanium nitride.

[0025] According to some of the embodiments, the method further includes forming a second inter-layer dielectric (ILD) layer on the sidewall spacers and forming a second interconnect structure in the second ILD layer. [Brief explanation of the drawings]

[0026] These and other objects of the present invention will no doubt become obvious to those skilled in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.

[0027] [Figure 1]2 is a schematic cross-sectional view of a memory device region of a resistive random access memory device according to one embodiment of the present invention. [Figure 2] 1A-1C are schematic diagrams illustrating a method of forming an RRAM device according to one embodiment of the present invention. [Figure 3] 1A-1C are schematic diagrams illustrating a method of forming an RRAM device according to one embodiment of the present invention. [Figure 4] 1A-1C are schematic diagrams illustrating a method of forming an RRAM device according to one embodiment of the present invention. [Figure 5] 1A-1C are schematic diagrams illustrating a method of forming an RRAM device according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0028] In the following detailed description of the present disclosure, reference is made to the accompanying drawings which form a part hereof, and which show by way of illustration specific embodiments in which the invention may be practiced, the embodiments being described in sufficient detail to enable those skilled in the art to practice the invention.

[0029] Other embodiments may be utilized, and structural, logical, and electrical changes may be made, without departing from the scope of the present invention. Therefore, the following detailed description is not to be construed as limiting; rather, the various embodiments contained herein are defined by the scope of the invention as set forth in the appended claims.

[0030] Referring to FIG. 1, FIG. 1 is a schematic cross-sectional view of a memory device region of a resistive random access memory (RRAM) device according to an embodiment of the present invention. As shown in FIG. 1, the RRAM device 1 includes a substrate 100 and a first interlayer dielectric layer 110 disposed on the substrate 100. According to an embodiment of the present invention, the substrate 100 may be a semiconductor substrate such as, but not limited to, a silicon substrate. According to an embodiment of the present invention, the first interlayer dielectric layer 110 may include, for example, a low dielectric constant material layer or an ultra-low dielectric constant material layer. According to an embodiment of the present invention, the thickness of the first interlayer dielectric layer 110 may be, for example, about 800 angstroms to 900 angstroms.

[0031] According to an embodiment of the present invention, a first interconnect structure M1 is formed in the first interlayer dielectric layer 110. According to an embodiment of the present invention, for example, the first interconnect structure M1 may be a copper damascene structure. According to an embodiment of the present invention, a capping layer 120 is formed on the first interconnect structure M1 and the first interlayer dielectric layer 110. According to an embodiment of the present invention, for example, the capping layer 120 may include, but is not limited to, a nitrogen-doped silicon carbide layer. According to an embodiment of the present invention, the thickness of the capping layer 120 may be, for example, about 100 angstroms.

[0032] According to one embodiment of the present invention, an intermediate dielectric layer 130 is formed on the capping layer 120. According to one embodiment of the present invention, for example, the intermediate dielectric layer 130 may include, but is not limited to, a TEOS-based silicon oxide layer. According to one embodiment of the present invention, the thickness of the intermediate dielectric layer 130 may be, for example, about 100 angstroms.

[0033] According to one embodiment of the present invention, the RRAM device 1 further includes conductive vias 200 disposed in the capping layer 120 and the intermediate dielectric layer 130. According to one embodiment of the present invention, for example, the conductive vias 200 include an outermost polishing stop layer 201, a barrier layer 202 located on the polishing stop layer 201, and a tungsten layer 203 located on the barrier layer 202. According to one embodiment of the present invention, the polishing stop layer 201 may include, for example, tantalum nitride or other materials that have high polishing selectivity with respect to the tungsten layer 203. According to one embodiment of the present invention, the barrier layer 202 may include, for example, but is not limited to, titanium nitride.

[0034] According to one embodiment of the present invention, the height of the conductive via 200 may be between approximately 200 angstroms and 600 angstroms, such as between 400 angstroms and 500 angstroms. According to one embodiment of the present invention, the conductive via 200 includes an upper portion 200a, which protrudes from a top surface 130a of the intermediate dielectric layer 130. The RRAM device 1 further includes a resistive switching structure 300 disposed on the conductive via 200. According to one embodiment of the present invention, a sidewall S1 of the resistive switching structure 300 may be flush with a sidewall S2 of the upper portion 200a of the conductive via 200. According to one embodiment of the present invention, the upper surface of the resistive switching structure 300 may be covered by a hard mask layer 310.

[0035] According to one embodiment of the present invention, the resistive switching structure 300 may include a stacked structure, which is composed of a bottom electrode layer, a resistive switching layer, and a top electrode layer. For example, but not limited to, the bottom electrode layer may include TaN, TiN, Pt, Ir, Ru, or W, the resistive switching layer may include hafnium oxide, tantalum oxide, titanium, titanium oxide, or a combination thereof, and the top electrode layer may include TiN, TaN, Pt, Ir, or W.

[0036] According to one embodiment of the present invention, sidewall spacers 400 are provided around the upper portion 200a of the conductive via 200 and the resistive switching structure 300. According to one embodiment of the present invention, for example, the sidewall spacers 400 may include, but are not limited to, a silicon nitride layer 410 and a silicon oxide layer 420. According to one embodiment of the present invention, the silicon nitride layer 410 conformally covers the sidewall S1 of the resistive switching structure 300, the sidewall S2 of the upper portion 200a of the conductive via 200, and the upper surface 130a of the intermediate dielectric layer 130. According to one embodiment of the present invention, the silicon nitride layer 410 directly contacts the polish stop layer 201 but does not directly contact the barrier layer 202 or the tungsten layer 203.

[0037] According to an embodiment of the present invention, the RRAM device 1 further includes a second interlayer dielectric layer 160, which covers the sidewall spacers 400 and the resistive switching structure 300. According to an embodiment of the present invention, a second interconnect structure M2 may be formed in the second interlayer dielectric layer 160. According to an embodiment of the present invention, for example, the second interconnect structure M2 may be disposed between two adjacent resistive switching structures 300. The second interconnect structure M2 may be electrically connected to the first interconnect structure M1 through a conductive via V1.

[0038] 2-5, which are schematic diagrams illustrating a method of forming a resistive random access memory device according to an embodiment of the present invention, in which like layers, materials, or regions are designated by like numbers or labels. As shown in FIG. 2, a substrate 100, such as a silicon substrate, is provided. According to an embodiment of the present invention, the substrate 100 includes a memory cell region MR and an alignment mark region AM. According to an embodiment of the present invention, an etch stop layer 106, a first interlayer dielectric layer 110, a capping layer 120, and an intermediate dielectric layer 130 are formed on the substrate 100.

[0039] For example, the etch stop layer 106 may include, but is not limited to, a nitrogen-doped silicon carbide layer. The first interlayer dielectric layer 110 may include, but is not limited to, a low dielectric constant material layer or an ultra-low dielectric constant material layer. According to one embodiment of the present invention, the first interlayer dielectric layer 110 may have a thickness of, for example, about 800 angstroms to 900 angstroms. According to one embodiment of the present invention, the capping layer 120 may include, but is not limited to, a nitrogen-doped silicon carbide layer. According to one embodiment of the present invention, the capping layer 120 may have a thickness of, for example, about 100 angstroms. According to one embodiment of the present invention, the intermediate dielectric layer 130 may include, but is not limited to, a TEOS-based silicon oxide layer. According to one embodiment of the present invention, the thickness of the intermediate dielectric layer 130 may be, for example, about 300 angstroms.

[0040] According to one embodiment of the present invention, a first interconnect structure M1 is formed in the first interlayer dielectric layer 110 in the memory cell region MR. According to one embodiment of the present invention, for example, the first interconnect structure M1 may be a copper damascene structure. According to one embodiment of the present invention, an alignment trench T is formed in the alignment mark region AM using a photolithography process and an etching process. According to one embodiment of the present invention, the alignment trench T may be recessed into the first interlayer dielectric layer 110, and the bottom of the alignment trench T may expose the etching stop layer 106. For example, the depth of the alignment trench T is approximately 1200 angstroms to 1300 angstroms.

[0041] 3, a photolithography process and an etching process are then performed to form a via hole SV in the interlevel dielectric layer 130 and the capping layer 120 above the first interconnect structure M1 in the memory cell region MR, exposing a portion of the first interconnect structure M1. A chemical vapor deposition (CVD) process is then performed to blanket deposit a polishing stop layer 201, a barrier layer 202, and a tungsten layer 203 on the substrate 100. The polishing stop layer 201 and the barrier layer 202 are conformally filled into the via hole SV. The remaining space in the via hole SV is then filled with the tungsten layer 203. In the alignment mark region AM, the polishing stop layer 201, the barrier layer 202, and the tungsten layer 203 are conformally filled into the alignment trench T.

[0042] Next, a tungsten chemical mechanical polishing (WCMP) process is performed to polish away the barrier layer 202 and the tungsten layer 203 above the polishing stop layer 201 from the memory cell region MR and the alignment mark region AM. Because the polishing stop layer 201 has a high selectivity relative to the tungsten layer 203, polishing will stop at the polishing stop layer 201 and leave the barrier layer 202 and the tungsten layer 203 in the via hole SV to form the conductive via 200. At this point, the barrier layer 202 and the tungsten layer 203 will remain in the alignment trench T. The polishing stop layer 201 allows the thickness of the intermediate dielectric layer 130 in the alignment mark area AM and the thickness of the intermediate dielectric layer 130 in the memory cell area MR to be approximately the same, and the intermediate dielectric layer 130 is not consumed by the WCMP process, so that the trench step height SH in the alignment mark area AM can reach approximately 920 angstroms, which allows the trench step height SH to improve the alignment accuracy of the subsequent lithography process.

[0043] 4, deposition, photolithography, and etching processes are then performed to form a resistive switching structure 300 on the conductive via 200 in the memory cell region MR. During the process of forming the resistive switching structure 300, portions of the polish stop layer 201 and the interlevel dielectric layer 130 that are not covered by the resistive switching structure 300 will be etched away. At that point, the conductive via 200 may include an upper portion 200a that protrudes from the upper surface 130a of the interlevel dielectric layer 130, and the remaining thickness of the interlevel dielectric layer 130 will be approximately 100 angstroms.

[0044] 5, a chemical vapor deposition (CVD) process and an etching process are then performed to form sidewall spacers 400 around the upper portion 200a of the conductive via 200 and the resistive switching structure 300. According to an embodiment of the present invention, for example, the sidewall spacers 400 may include, but are not limited to, a silicon nitride layer 410 and a silicon oxide layer 420. According to an embodiment of the present invention, the silicon nitride layer 410 conformally covers the sidewall S1 of the resistive switching structure 300, the sidewall S2 of the upper portion 200a of the conductive via 200, and the upper surface 130a of the intermediate dielectric layer 130. According to an embodiment of the present invention, the silicon nitride layer 410 directly contacts the polish stop layer 201 but does not directly contact the barrier layer 202 or the tungsten layer 203. According to one embodiment of the present invention, a second interlevel dielectric layer 160 is then formed over the sidewall spacers 400 and the resistive switching structure 300. A metallization process may then continue to form a second interconnect structure M2 in the second interlevel dielectric layer 160.

[0045] Those skilled in the art will readily appreciate that numerous modifications and variations of the devices and methods may be made while keeping in mind the teachings of the present invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims

1. 1. A resistive random access memory device, comprising: A substrate; a first interlevel dielectric (ILD) layer disposed over the substrate; a first interconnect structure disposed in the first interlevel dielectric (ILD) layer; a capping layer disposed over the first interconnect structure and the first inter-level dielectric (ILD) layer; an intermediate dielectric layer including an upper surface and disposed over the capping layer; a via hole formed in the capping layer and the interlevel dielectric layer above the first interconnect structure; a conductive via disposed in the via hole, the conductive via including a polishing stop layer, a barrier layer overlying the polishing stop layer, and a tungsten layer overlying the barrier layer, the polishing stop layer and the barrier layer conformally filling the via hole, the tungsten layer filling the remaining space in the via hole, the polishing stop layer serving as a stop layer in a tungsten chemical mechanical polishing process, and the conductive via including an upper portion protruding from the upper surface of the interlevel dielectric layer; a resistive switching structure disposed over the conductive via. Resistive random access memory device.

2. The resistive random access memory device of claim 1, further comprising sidewall spacers disposed around the top of the conductive via and the resistive switching structure.

3. The resistive random access memory device of claim 2, wherein the sidewall spacers are in direct contact with the polish stop layer.

4. The resistive random access memory device of claim 2 , wherein the sidewall spacers cover sidewalls of the resistive switching structure, sidewalls of the upper portion of the conductive via, and the top surface of the interlevel dielectric layer.

5. The resistive random access memory device of claim 4 , wherein the sidewall spacers are not in direct contact with the tungsten layer and the barrier layer.

6. The resistive random access memory device of claim 1 , wherein the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.

7. The resistive random access memory device of claim 1 , wherein the interlevel dielectric layer comprises a TEOS-based silicon oxide layer.

8. The resistive random access memory device of claim 1 , wherein the polish stop layer comprises tantalum nitride.

9. The resistive random access memory device of claim 1 , wherein the barrier layer comprises titanium nitride.

10. a second inter-level dielectric (ILD) layer covering the sidewall spacers; a second interconnect structure disposed in the second interlevel dielectric (ILD) layer; 4. The resistive random access memory device of claim 3, further comprising:

11. 1. A method for forming a resistive random access memory device, the method comprising: providing a substrate; forming a first inter-layer dielectric (ILD) layer over the substrate; forming a first interconnect structure in the first interlevel dielectric (ILD) layer; forming a capping layer over the first interconnect structure and the first inter-level dielectric (ILD) layer; forming an interlevel dielectric layer over the capping layer, the interlevel dielectric layer including an upper surface; forming a via hole formed in the capping layer and the interlevel dielectric layer above the first interconnect structure; forming a conductive via disposed in the via hole, the conductive via including a polishing stop layer, a barrier layer overlying the polishing stop layer, and a tungsten layer overlying the barrier layer, the polishing stop layer and the barrier layer conformally filling in the via hole, the tungsten layer filling a remaining space in the via hole, the polishing stop layer serving as a stop layer in a tungsten chemical mechanical polishing process, and the conductive via including an upper portion protruding from the upper surface of the interlevel dielectric layer; forming a resistive switching structure over the conductive via. method.

12. The method of claim 11, further comprising forming sidewall spacers disposed around the top of the conductive via and the resistive switching structure.

13. The method of claim 12, wherein the sidewall spacers are in direct contact with the polish stop layer.

14. 13. The method of claim 12, wherein the sidewall spacers cover sidewalls of the resistive switching structure, sidewalls of the upper portion of the conductive via, and the top surface of the intermediate dielectric layer.

15. 15. The method of claim 14, wherein the sidewall spacers are not in direct contact with the tungsten layer and the barrier layer.

16. The method of claim 11 , wherein the capping layer comprises a nitrogen-doped silicon carbide (NDC) layer.

17. The method of claim 11 , wherein the interlevel dielectric layer comprises a TEOS-based silicon oxide layer.

18. The method of claim 11 , wherein the polish stop layer comprises tantalum nitride.

19. The method of claim 11 , wherein the barrier layer comprises titanium nitride.

20. forming a second inter-layer dielectric (ILD) layer over the sidewall spacers; forming a second interconnect structure in the second interlevel dielectric (ILD) layer; 14. The method of claim 13, further comprising:

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