Power Conversion Device

Abstract

To provide a power conversion device capable of reducing energy loss.SOLUTION: A power conversion device according to one embodiment of the disclosure includes a first power terminal, a switching circuit including first and second switching elements connected in series through a connection node, a trans, a rectifier circuit, a filter circuit, a second power terminal, a control circuit, a voltage generation circuit, and a driving unit including a diode, a capacitor, and a driving circuit that drives the first switching element using the voltage between both ends of the capacitor as a power source voltage. The control circuit repeatedly changes the operation state of the switching circuit in the order of a first operation state in which the first and second switching elements are kept off, a second operation state in which the first switching element is kept off and the second switching element performs a switching operation, and a third operation state in which the first and second switching elements perform the switching operation.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to a power conversion device that converts electric power. [Background technology]

[0002] Some power conversion devices generate a drive signal by a bootstrap operation and drive a switching element of a switching circuit using the generated drive signal. For example, Patent Document 1 discloses a technology for maintaining the voltage of a bootstrap capacitor in a burst mode by continuously switching a lower switching element and intermittently switching an upper switching element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-198134 Summary of the Invention [Problem to be solved by the invention]

[0004] In a power conversion device, low energy loss is desired, and further reduction in energy loss is expected.

[0005] It is desirable to provide a power conversion device that can reduce energy losses. [Means for solving the problem]

[0006] A power conversion device according to one embodiment of the present invention includes a first power terminal, a switching circuit, a transformer, a rectifier circuit, a smoothing circuit, a second power terminal, a control circuit, a voltage generation circuit, and a drive unit. The first power terminal includes a first terminal and a second terminal. The switching circuit has a first switching element and a second switching element connected in series via a connection node in a path connecting the first terminal and the second terminal. The transformer has a first winding connected to the switching circuit and a second winding. The rectifier circuit is connected to the second winding. The smoothing circuit is connected to the rectifier circuit. The second power terminal is connected to the smoothing circuit. The control circuit is capable of controlling the operation of the switching circuit. The voltage generation circuit generates a predetermined voltage. The drive unit includes a diode having an anode connected to the output terminal of the voltage generating circuit and a cathode, a capacitor having one end connected to the cathode of the diode and the other end connected to the connection node, and a drive circuit capable of driving the first switching element based on a control signal supplied from the control circuit by using the voltage across the capacitor as a power supply voltage. The control circuit is capable of repeatedly changing the operating state of the switching circuit in the order of a first operating state in which the first switching element and the second switching element both maintain their off states, a second operating state in which the first switching element maintains its off state and the second switching element performs a switching operation, and a third operating state in which the first switching element and the second switching element both perform a switching operation.

[0007] According to the power conversion device according to an embodiment of the present invention, it is possible to reduce energy loss. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram illustrating an example of a configuration of a power conversion device according to an embodiment of the present invention. [Figure 2]2 is a circuit diagram illustrating an example of the configuration of a voltage generating circuit and four driving units in the power conversion device shown in FIG. 1. FIG. [Figure 3] 2 is a timing waveform diagram illustrating an example of an operation of the power conversion device shown in FIG. 1. [Figure 4A] 2 is an explanatory diagram illustrating one operating state of the power conversion device shown in FIG. 1. FIG. [Figure 4B] 1. FIG. 4 is an explanatory diagram illustrating another operating state of the power conversion device shown in FIG. [Figure 5] 2 is an explanatory diagram illustrating an example of an operation at the time of start-up of the power conversion device shown in FIG. 1. FIG. [Figure 6] 2 is a timing chart illustrating an example of an operation at the start-up of the power conversion device shown in FIG. 1. [Figure 7] 2 is a timing waveform diagram illustrating an example of an operation in burst mode of the power conversion device shown in FIG. 1. FIG. [Figure 8] 4 is a flowchart illustrating an example of an operation in a burst mode of the power conversion device shown in FIG. [Figure 9] 2 is a timing chart illustrating an example of an operation in burst mode of the power conversion device shown in FIG. 1. FIG. [Figure 10] 1. FIG. 4 is a timing chart illustrating another example of operation in burst mode of the power conversion device shown in FIG. [Figure 11] FIG. 10 is a circuit diagram illustrating a configuration example of a power conversion device according to a modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] <Embodiment> [Configuration example] 1 shows an example of the configuration of a power conversion device 1 according to an embodiment of the present invention. The power conversion device 1 is a DC / DC converter that converts power by stepping down the voltage supplied from a battery BH and supplies the converted power to a load LD.

[0011] Power conversion device 1 has terminals T11 and T12, a voltage generation circuit 20, a switching circuit 12, insulating units 31A and 31C, drive units 32A to 32D, a transformer 13, a rectifier circuit 14, a smoothing circuit 15, a voltage sensor 18, a control circuit 19, and terminals T21 and T22. Battery BH, voltage generation circuit 20, switching circuit 12, and drive units 32A to 32D form a primary circuit of power conversion device 1, and rectifier circuit 14, smoothing circuit 15, voltage sensor 18, and load LD form a secondary circuit of power conversion device 1.

[0012] Terminals T11 and T12 are power input terminals of the power conversion device 1. In the power conversion device 1, the terminal T11 is connected to the voltage line L11, and the terminal T12 is connected to the reference voltage line L12.

[0013] The voltage generating circuit 20 is configured to generate a predetermined voltage V20 based on the power supplied from the battery BH.

[0014] 2 shows an example of a more specific circuit configuration of the primary side circuit of the power conversion device 1. In this example, the voltage generation circuit 20 is an isolated DC / DC converter, and converts a DC voltage of approximately 200 V to 400 V supplied from the battery BH into a voltage V20 that is a DC voltage of approximately 15 V. The voltage generation circuit 20 has a transformer 21, a transistor 22, a diode 23, a capacitor 24, and a voltage control circuit 25.

[0015] The transformer 21 has windings 21A and 21B. One end of the winding 21A is connected to a voltage line L11, and the other end is connected to the drain of a transistor 22. One end of the winding 21B is connected to a reference voltage line L12, and the other end is connected to the anode of a diode 23.

[0016] The transistor 22 is configured using, for example, an N-type field effect transistor. Although an N-type field effect transistor is used in this example, any switching element may be used. A control signal is supplied from the voltage control circuit 25 to the gate of the transistor 22, the drain is connected to the other end of the winding 21A of the transformer 21, and the source is connected to the reference voltage line L12.

[0017] The anode of the diode 23 is connected to the other end of the winding 21B of the transformer 21, and the cathode is connected to the node N3.

[0018] The capacitor 24 is an electrolytic capacitor, one end of which is connected to the node N3 and the other end of which is connected to the reference voltage line L12.

[0019] The voltage control circuit 25 is configured to control the switching operation of the transistor 22 based on the voltage V20 at the node N3. The voltage control circuit 25 controls the switching operation of the transistor 22 so that the voltage V20 at the node N3 becomes a predetermined voltage (15 V in this example).

[0020] In this example, the voltage generating circuit 20 is configured using an isolated step-down converter circuit having a transformer 21, but this is not limited to this. Instead, for example, the voltage generating circuit 20 may be configured using a non-isolated step-down converter circuit.

[0021] With this configuration, the voltage generating circuit 20 generates a voltage V20, which is a DC voltage. The voltage generating circuit 20 then supplies the generated voltage V20 to the insulating units 31A and 31C and the driving units 32A, 32B, 32C, and 32D.

[0022] The switching circuit 12 (FIG. 1) is configured to convert a DC voltage supplied from the battery BH into an AC voltage. The switching circuit 12 is a full-bridge circuit and includes transistors SA to SD. The transistors SA to SD are switching elements that perform switching operations based on gate signals GA1 to GD1, respectively. The transistors SA to SD are configured using, for example, N-type field effect transistors (FETs). The transistors SA to SD each include body diodes DA to DD. For example, the anode of the body diode DA is connected to the source of the body of the transistor SA, and the cathode is connected to the drain of the body of the transistor SA. The same is true for the body diodes DB to DD. Note that, although an N-type field effect transistor is used in this example, any switching element may be used.

[0023] The transistor SA is provided in a path connecting the voltage line L11 and the node N1, and is configured to connect the node N1 to the voltage line L11 when it is turned on. The drain of the transistor SA is connected to the voltage line L11, the gate is supplied with a gate signal GA1, and the source is connected to the node N1. The transistor SB is provided in a path connecting the node N1 and the reference voltage line L12, and is configured to connect the node N1 to the reference voltage line L12 when it is turned on. The drain of the transistor SB is connected to the node N1, the gate is supplied with a gate signal GB1, and the source is connected to the reference voltage line L12. The node N1 is the connection point between the source of the transistor SA and the drain of the transistor SB.

[0024] The transistor SC is provided in a path connecting the voltage line L11 and the node N2, and is configured to connect the node N2 to the voltage line L11 when it is turned on. The drain of the transistor SC is connected to the voltage line L11, the gate is supplied with a gate signal GC1, and the source is connected to the node N2. The transistor SD is provided in a path connecting the node N2 and the reference voltage line L12, and is configured to connect the node N2 to the reference voltage line L12 when it is turned on. The drain of the transistor SD is connected to the node N2, the gate is supplied with a gate signal GD1, and the source is connected to the reference voltage line L12. The node N2 is the connection point between the source of the transistor SC and the drain of the transistor SD.

[0025] The insulating unit 31A is configured to generate a gate signal GA0 that is electrically isolated from the gate signal GA based on the gate signal GA supplied from the control circuit 19. The insulating unit 31A is configured using an insulating element such as a photocoupler, for example. However, the insulating unit 31A is not limited to this, and various circuits that electrically insulate the gate signals GA and GA0 can be used.

[0026] The driving unit 32A is configured to generate a gate signal GA1 based on the voltage V20 supplied from the voltage generating circuit 20 and the gate signal GA0 supplied from the insulating unit 31A, and to drive the transistor SA using this gate signal GA1.

[0027] As shown in FIG. 2, the driver 32A includes a diode 33, a resistor 34, a capacitor 35, a driver circuit 36, and a resistor 37. The anode of the diode 33 is connected to a node N3, and the cathode is connected to the resistor 34. A voltage V20 is supplied to the anode of the diode 33 from the voltage generating circuit 20. One end of the resistor 34 is connected to the cathode of the diode 33, and the other end is connected to the capacitor 35 and a power supply terminal of the driver circuit 36. One end of the capacitor 35 is connected to the other end of the resistor 34 and a power supply terminal of the driver circuit 36, and the other end is connected to a node N1. A gate signal GA0 is supplied to an input terminal of the driver circuit 36, an output terminal is connected to the resistor 37, a power supply terminal is connected to the other end of the resistor 34 and one end of the capacitor 35, and a reference power supply terminal is connected to the node N1. In this way, the power supply terminal of the drive circuit 36 ​​is connected to one end of the capacitor 35, and the reference power supply terminal is connected to the other end of the capacitor 35, so that the drive circuit 36 ​​operates by using the voltage across the capacitor 35 as a power supply voltage. One end of the resistor element 37 is connected to the output terminal of the drive circuit 36, and the other end is connected to the gate of the transistor SA. With this configuration, the drive unit 32A drives the transistor SA by performing a bootstrap operation.

[0028] The driving unit 32B (FIG. 1) is configured to generate a gate signal GB1 based on the voltage V20 supplied from the voltage generating circuit 20 and the gate signal GB supplied from the control circuit 19, and to drive the transistor SB using this gate signal GB1.

[0029] As shown in FIG. 2, the driver 32B includes a capacitor 45, a driver circuit 46, and a resistor 47. One end of the capacitor 45 is connected to node N3, and the other end is connected to the reference voltage line L12. A voltage V20 is supplied to one end of the capacitor 45 from the voltage generating circuit 20. A gate signal GB is supplied to an input terminal of the driver circuit 46, an output terminal is connected to the resistor 47, a power supply terminal is connected to node N3, and a reference power supply terminal is connected to the reference voltage line L12. Since the power supply terminal of the driver circuit 46 is connected to one end of the capacitor 45 and the reference power supply terminal is connected to the other end of the capacitor 45, the driver circuit 46 operates by using the voltage across the capacitor 45 as a power supply voltage. One end of the resistor 47 is connected to the output terminal of the driver circuit 46, and the other end is connected to the gate of the transistor SB. With this configuration, the driver 32B drives the transistor SB.

[0030] Similar to the insulating unit 31A, the insulating unit 31C is configured to generate, based on the gate signal GC supplied from the control circuit 19, a gate signal GC0 that is electrically insulated from the gate signal GC.

[0031] The driver 32C (FIG. 1) is configured to generate a gate signal GC1 based on the voltage V20 supplied from the voltage generating circuit 20 and the gate signal GC0 supplied from the insulating unit 31C, and to drive the transistor SC using this gate signal GC1. As shown in FIG. 2, the driver 32C, like the driver 32A, includes a diode 33, a resistor 34, a capacitor 35, a driver circuit 36, and a resistor 37. The circuit configuration of the driver 32C is similar to that of the driver 32A. With this configuration, the driver 32C drives the transistor SC by performing a bootstrap operation.

[0032] The driver 32D (FIG. 1) is configured to generate a gate signal GD1 based on the voltage V20 supplied from the voltage generating circuit 20 and the gate signal GD supplied from the control circuit 19, and to drive the transistor SD using this gate signal GD1. As shown in FIG. 2, the driver 32D has a capacitor 45, a driver circuit 46, and a resistor element 47, similar to the driver 32B. The circuit configuration of the driver 32D is similar to that of the driver 32B. With this configuration, the driver 32D drives the transistor SD.

[0033] Transformer 13 (FIG. 1) insulates the primary circuit from the secondary circuit in terms of DC current and connects them in terms of AC current. Transformer 13 converts AC voltage supplied from the primary circuit at a transformation ratio N of transformer 13 and supplies the converted AC voltage to the secondary circuit. Transformer 13 has windings 13A, 13B, and 13C. One end of winding 13A is connected to node N1 in switching circuit 12, and the other end is connected to node N2 in switching circuit 12. One end of winding 13B is connected to the anode of diode D1 (described below) in rectifier circuit 14, and the other end is connected to one end of winding 13C and a reference voltage line L22. One end of winding 13C is connected to the other end of winding 13B and the reference voltage line L22, and the other end is connected to the anode of diode D2 (described below) in rectifier circuit 14.

[0034] Rectifier circuit 14 is configured to rectify the AC voltage output from windings 13B and 13C of transformer 13. Rectifier circuit 14 has diodes D1 and D2. The anode of diode D1 is connected to one end of winding 13B of transformer 13, and the cathode is connected to the cathode of diode D2 and inductor 16 (described later) of smoothing circuit 15. The anode of diode D2 is connected to the other end of winding 13C of transformer 13, and the cathode is connected to the cathode of diode D1 and inductor 16 of smoothing circuit 15.

[0035] The smoothing circuit 15 is configured to smooth the voltage supplied from the rectifier circuit 14. The smoothing circuit 15 has an inductor 16 and a capacitor 17. One end of the inductor 16 is connected to the cathodes of the diodes D1 and D2 of the rectifier circuit 14, and the other end is connected to the voltage line L21. One end of the capacitor 17 is connected to the voltage line L21, and the other end is connected to the reference voltage line L22.

[0036] The voltage sensor 18 is configured to detect the voltage on the voltage line L21. One end of the voltage sensor 18 is connected to the voltage line L21, and the other end is connected to the reference voltage line L22. The voltage sensor 18 detects the voltage on the voltage line L21 relative to the voltage on the reference voltage line L22 as the voltage VL. The voltage sensor 18 then supplies the detection result of the voltage VL to the control circuit 19.

[0037] The control circuit 19 is configured to control the operation of the power conversion device 1 by controlling the operation of the switching circuit 12 based on the voltage VL detected by the voltage sensor 18. Specifically, the control circuit 19 generates gate signals GA to GD based on the voltage VL, and controls the operation of the power conversion device 1 by performing PWM (Pulse Width Modulation) control using the gate signals GA to GD.

[0038] Terminals T21 and T22 are configured to supply to a load LD a voltage generated by the power conversion device 1. In the power conversion device 1, terminal T21 is connected to a voltage line L21, and terminal T22 is connected to a reference voltage line L22.

[0039] As will be described later, when the load is light, the power conversion device 1 operates in burst mode. In this burst mode, the four transistors SA to SD perform intermittent switching operations. For example, when the four transistors SA to SD are in the off state for a long period of time and then the switching operations of the transistors SA to SD start, the transistors SB and SD start switching operations first, causing the power conversion device 1 to charge the capacitors 35 in the drivers 32A and 32C. Then, the switching operations of the transistors SA and SC start. This allows the power conversion device 1 to reduce energy loss when operating in burst mode.

[0040] Here, terminals T11 and T12 correspond to a specific example of a "first power terminal" in the present disclosure. Switching circuit 12 corresponds to a specific example of a "switching circuit" in the present disclosure. Transformer 13 corresponds to a specific example of a "transformer" in the present disclosure. Winding 13A corresponds to a specific example of a "first winding" in the present disclosure. Windings 13B and 13C correspond to a specific example of a "second winding" in the present disclosure. Rectifier circuit 14 corresponds to a specific example of a "rectifier circuit" in the present disclosure. Smoothing circuit 15 corresponds to a specific example of a "smoothing circuit" in the present disclosure. Terminals T21 and T22 correspond to a specific example of a "second power terminal" in the present disclosure. Control circuit 19 corresponds to a specific example of a "control circuit" in the present disclosure. Insulator 31A and driver 32A correspond to a specific example of a "driver" in the present disclosure. Diode 33 of driver 32A corresponds to a specific example of a "diode" in the present disclosure. The capacitor 35 of the drive unit 32A corresponds to a specific example of "capacitor" in the present disclosure. The drive circuit 36 ​​of the drive unit 32A corresponds to a specific example of "drive circuit" in the present disclosure. The terminals T21 and T22 correspond to a specific example of "second power terminal" in the present disclosure.

[0041] [Actions and Actions] Next, the operation and function of the power conversion device 1 of this embodiment will be described.

[0042] (Overview of overall operation) First, referring to FIG. 1, an overview of the overall operation of the power conversion device 1 will be described. The voltage generation circuit 20 generates a predetermined voltage V20 based on power supplied from the battery BH and supplies this voltage V20 to the insulators 31A and 31C and the drivers 32A, 32B, 32C, and 32D. The insulator 31A generates a gate signal GA0 electrically isolated from the gate signal GA based on the gate signal GA supplied from the control circuit 19. The driver 32A generates a gate signal GA1 based on the voltage V20 supplied from the voltage generation circuit 20 and the gate signal GA0 supplied from the insulator 31A, and drives the transistor SA using this gate signal GA1. The driver 32B generates a gate signal GB1 based on the voltage V20 supplied from the voltage generation circuit 20 and the gate signal GB supplied from the control circuit 19, and drives the transistor SB using this gate signal GB1. The insulating unit 31C generates a gate signal GC0 electrically insulated from the gate signal GC based on the gate signal GC supplied from the control circuit 19. The driving unit 32C generates a gate signal GC1 based on the voltage V20 supplied from the voltage generating circuit 20 and the gate signal GC0 supplied from the insulating unit 31C, and drives the transistor SC using this gate signal GC1. The driving unit 32D generates a gate signal GD1 based on the voltage V20 supplied from the voltage generating circuit 20 and the gate signal GD supplied from the control circuit 19, and drives the transistor SD using this gate signal GD1. The transistors SA to SD perform switching operations based on the gate signals GA1 to GD1, respectively. The transformer 13 insulates the primary side circuit from the secondary side circuit in terms of DC and connects them in terms of AC, converts the AC voltage supplied from the primary side circuit at a transformation ratio N of the transformer 13, and supplies the converted AC voltage to the secondary side circuit. Rectifier circuit 14 rectifies the AC voltage output from windings 13B and 13C of transformer 13. Smoothing circuit 15 smoothes the voltage supplied from rectifier circuit 14. Voltage sensor 18 detects the voltage on voltage line L21. Control circuit 19 controls the operation of switching circuit 12 based on voltage VL detected by voltage sensor 18, thereby controlling the operation of power conversion device 1.

[0043] (Detailed operation) 3 shows an example of operation of the power conversion device 1, where (A) to (D) respectively show the waveforms of gate signals GA to GD, and (E) shows the power transfer operation from the primary side circuit to the secondary side circuit in the power conversion device 1. The power conversion device 1 transfers power from the primary side circuit to the secondary side circuit during a period T when the waveform shown in FIG. 3(E) is at a high level.

[0044] At timing t11, the control circuit 19 changes the gate signal GD from low to high (FIG. 3(D)). The drive unit 32D generates a gate signal GD1 based on the gate signal GD, and uses the gate signal GD1 to change the transistor SD from an off state to an on state.

[0045] Next, at timing t12, the control circuit 19 changes the gate signal GB from high to low (FIG. 3B). The drive unit 32B generates a gate signal GB1 based on the gate signal GB, and uses the gate signal GB1 to change the transistor SB from an on state to an off state.

[0046] Next, at timing t13, the control circuit 19 changes the gate signal GA from low to high (FIG. 3(A)). The insulating unit 31A generates a gate signal GA0 based on this gate signal GA. The driving unit 32A generates a gate signal GA1 based on this gate signal GA0, and uses this gate signal GA1 to change the transistor SA from an off state to an on state.

[0047] Next, at timing t14, the control circuit 19 changes the gate signal GD from high to low (FIG. 3(D)). The drive unit 32D generates a gate signal GD1 based on the gate signal GD, and uses the gate signal GD1 to change the transistor SD from an on state to an off state.

[0048] In this way, both the transistors SA and SD are in the ON state during the period T from timing t13 to t14. During this period T, the gate signals GB and GC are at a low level, so that both the transistors SB and SC are in the OFF state.

[0049] Fig. 4A shows one operation state of the power conversion device 1 at a certain timing during a period T from timing t13 to t14. For ease of explanation, Fig. 4A shows a simplified illustration of the power conversion device 1. Furthermore, the transistors SA to SD are shown as switches that indicate an on / off state.

[0050] Because transistors SA and SD are on, current I1 can flow in the primary circuit of power conversion device 1, in the order of voltage line L11, transistor SA, winding 13A, transistor SD, and reference voltage line L12. Correspondingly, current I2 can flow in the secondary circuit of power conversion device 1, in the order of winding 13B, diode D1, inductor 16, capacitor 17, load LD, reference voltage line L22, and winding 13B. In this way, power conversion device 1 transfers power from the primary circuit to the secondary circuit during period T from timing t13 to t14.

[0051] Next, as shown in FIG. 3, at timing t15, the control circuit 19 changes the gate signal GC from low to high (FIG. 3(C)). The insulating unit 31C generates a gate signal GC0 based on this gate signal GC. The driving unit 32C generates a gate signal GC1 based on this gate signal GC0, and uses this gate signal GC1 to change the transistor SC from an off state to an on state.

[0052] Next, at timing t16, the control circuit 19 changes the gate signal GA from high to low (FIG. 3(A)). The insulating unit 31A generates a gate signal GA0 based on this gate signal GA. The driving unit 32A generates a gate signal GA1 based on this gate signal GA0, and uses this gate signal GA1 to change the transistor SA from an on state to an off state.

[0053] Next, at timing t17, the control circuit 19 changes the gate signal GB from low level to high level (FIG. 3B). The drive unit 32B generates a gate signal GB1 based on the gate signal GB, and uses the gate signal GB1 to change the transistor SB from an off state to an on state.

[0054] Next, at timing t18, the control circuit 19 changes the gate signal GC from high to low (FIG. 3(C)). The insulating unit 31A generates a gate signal GC0 based on this gate signal GC. The driving unit 32C generates a gate signal GC1 based on this gate signal GC0, and uses this gate signal GC1 to change the transistor SC from the on state to the off state.

[0055] In this way, both the transistors SB and SC are in the ON state during the period T from timing t17 to t18. During this period T, the gate signals GA and GD are at a low level, so that both the transistors SA and SD are in the OFF state.

[0056] 4B shows one operating state of the power conversion device 1 at a certain timing during the period T from timing t17 to t18. Because the transistors SB and SC are on, a current I1 can flow in the primary circuit of the power conversion device 1, in the order of voltage line L11, transistor SC, winding 13A, transistor SB, and reference voltage line L12. In response to this, a current I2 can flow in the secondary circuit of the power conversion device 1, in the order of winding 13C, diode D2, inductor 16, capacitor 17, load LD, reference voltage line L22, and winding 13B. In this way, the power conversion device 1 transfers power from the primary circuit to the secondary circuit during the period T from timing t17 to t18.

[0057] In this way, the power conversion device 1 transfers power from the primary side circuit to the secondary side circuit during the period T from timing t13 to t14 and the period T from timing t17 to t18.

[0058] The control circuit 19 determines, for example, the ratio of the time lengths of two periods T during which power is transmitted in a cycle period Tsw corresponding to the switching cycle of the gate signals GA to GD (duty ratio DT) based on the voltage VL, which is the output voltage of the power conversion device 1. The control circuit 19 then generates the gate signals GA to GD based on this duty ratio DT. For example, if the voltage VL is lower than the target voltage, the control circuit 19 attempts to increase the voltage VL by increasing the duty ratio DT. For example, if the voltage VL is higher than the target voltage, the control circuit 19 attempts to decrease the voltage VL by decreasing the duty ratio DT. In this way, the control circuit 19 performs feedback control so that the voltage VL becomes the target voltage.

[0059] (About bootstrap operation) As shown in FIG. 3, by switching circuit 12 performing a switching operation, for example, in drive unit 32A (FIG. 2), the voltage across capacitor 35 is maintained at a voltage lower than voltage V20 by the forward voltage of diode 33. Drive circuit 36 ​​operates by using the voltage across capacitor 35 as a power supply voltage to drive transistor SA. In drive unit 32B, drive circuit 46 operates by using voltage V20 as a power supply voltage to drive transistor SB. The operations of drive units 32A and 32B will be described in detail below.

[0060] As shown in FIG. 3, at timing t10, the control circuit 19 changes the gate signal GB from low to high (FIG. 3(B)). The drive circuit 46 of the drive unit 32B operates by using the voltage V20 as a power supply voltage and changes the gate signal GB1 from low to high. This changes the transistor SB from an off state to an on state. With the transistor SB in the on state, the node N1 is connected to the reference voltage line L12. Therefore, the voltage of the node N1 becomes the same as the voltage of the reference voltage line L12. During this period, the capacitor 35 of the drive unit 32A is charged by a current supplied from the voltage generation circuit 20 via the diode 33 and the resistor element 34.

[0061] Next, at timing t12, the control circuit 19 changes the gate signal GB from high to low (FIG. 3(B)). The drive circuit 46 of the drive unit 32B operates by using the voltage V20 as a power supply voltage, and changes the gate signal GB1 from high to low. This causes the transistor SB to change from an ON state to an OFF state. Because the transistors SA and SB are both OFF, the node N1 is in a floating state, and the voltage of this node N1 rises to, for example, an intermediate voltage between the voltage of the voltage line L11 and the voltage of the reference voltage line L12.

[0062] Next, at timing t13, the control circuit 19 changes the gate signal GA from low to high (FIG. 3A). Based on this gate signal GA, the insulating unit 31A changes the gate signal GA0 from low to high. The drive circuit 36 ​​of the drive unit 32A operates by using the voltage across the capacitor 35 as a power supply voltage, and changes the gate signal GA1 from low to high. This changes the transistor SA from off to on. With the transistor SA in on, the node N1 is connected to the voltage line L11. Therefore, the voltage at the node N1 rises to the voltage of the voltage line L11. In the drive unit 32A, the voltage across the capacitor 35 is maintained at a voltage lower than the voltage V20 by the forward voltage of the diode 33. Therefore, when the voltage at the node N1 connected to the other end of the capacitor 35 rises, the voltage at one end of the capacitor 35 also rises. Therefore, the high-level voltage of the gate signal GA1 also rises. Therefore, the transistor SA remains on.

[0063] Next, at timing t16, the control circuit 19 changes the gate signal GA from high to low (FIG. 3A). Based on this gate signal GA, the insulating unit 31A changes the gate signal GA0 from high to low. The driving circuit 36 ​​of the driving unit 32A operates by using the voltage across the capacitor 35 as a power supply voltage and changes the gate signal GA1 from high to low. This changes the transistor SA from on to off. Because both the transistors SA and SB are off, the node N1 is in a floating state, and the voltage at this node N1 drops to, for example, an intermediate voltage between the voltage of the voltage line L11 and the voltage of the reference voltage line L12. In the driving unit 32A, the voltage across the capacitor 35 is maintained at a voltage lower than the voltage V20 by the forward voltage of the diode 33. Therefore, when the voltage at the node N1 connected to the other end of the capacitor 35 drops, the voltage at one end of the capacitor 35 also drops. Therefore, the low-level voltage of the gate signal GA1 also drops, so that the transistor SB remains in the off state.

[0064] In this way, the driver 32A generates the gate signal GA1 by performing a bootstrap operation.

[0065] Although the above description has been given taking the driving units 32A and 32B as an example, the same applies to the driving units 32C and 32D.

[0066] (About startup behavior) At startup, the power conversion device 1 charges the capacitor 35 of the drive unit 32A based on the voltage V20 generated by the voltage generation circuit 20, and sets the voltage of the capacitor 35 to a voltage lower than the voltage V20 by the forward voltage of the diode 33, and also charges the capacitor 35 of the drive unit 32C, and sets the voltage of the capacitor 35 to a voltage lower than the voltage V20 by the forward voltage of the diode 33. This operation will be described in detail below.

[0067] 5 and 6 show an example of the operation of the power conversion device 1 at startup. In Fig. 6, (A) to (D) show gate signals GA to GD, respectively, (E) shows the waveform of the voltage (capacitor voltage V35) across capacitor 35 in driving units 32A and 32C, and (F) shows the waveform of voltage VL, which is the output voltage of power conversion device 1. In Fig. 6(A) to (D), the shading indicates gate signals transitioning between low and high levels.

[0068] At startup, the power conversion device 1 first starts the switching operation of the transistors SB and SD at timing t21, and then starts the switching operation of the transistors SA and SC at timing t23. This operation will be described in detail below.

[0069] First, during a period T1 from timing t21 to t23, the control circuit 19 generates gate signals GB and GD that transition between low and high levels. The pulse widths of the gate signals GB and GD are predetermined. The control circuit 19 also maintains the gate signals GA and GC at low levels.

[0070] For example, during the period when the gate signal GB is at a high level, the transistor SB is turned on, and the voltage at the node N1 becomes the same voltage (0 V) as the voltage at the reference voltage line L12. In the drive unit 32A, a voltage V20 (e.g., 15 V) is supplied to the anode of the diode 33, and the voltage at the node N1 connected to the other end of the capacitor 35 is 0 V, so that the diode 33 is turned on, and the capacitor 35 is charged.

[0071] For example, during the period when the gate signal GB is at a low level, the transistor SB is turned off, and the voltage at the node N1 becomes, for example, an intermediate voltage between the voltage at the voltage line L11 and the voltage at the reference voltage line L12. Therefore, in the drive unit 32A, the diode 33 is turned off, and charging of the capacitor 35 stops.

[0072] In this way, in the driver 32A, the capacitor 35 is charged while the gate signal GB is at a high level, and the charging of the capacitor 35 stops while the gate signal GB is at a low level. As a result, the capacitor voltage V35, which is the voltage across the capacitor 35, gradually increases, as shown in FIG. 6(E). Then, at timing t22, when the capacitor voltage V35 reaches a voltage lower than voltage V20 by the forward voltage of the diode 33, the diode 33 is no longer in an on state, even while the gate signal GB is at a high level, and the increase in the capacitor voltage V35 stops. As a result, the capacitor voltage V35 is maintained at a voltage lower than voltage V20 by the forward voltage of the diode 33.

[0073] Similarly, in the driver 32C, the capacitor 35 is charged while the gate signal GD is at a high level, and the charging of the capacitor 35 stops while the gate signal GD is at a low level. As a result, the capacitor voltage V35, which is the voltage across the capacitor 35, gradually increases, as shown in FIG. 6(E). Then, at timing t22, when the capacitor voltage V35 reaches a voltage lower than voltage V20 by the forward voltage of the diode 33, the diode 33 is no longer in the on state, even while the gate signal GD is at a high level, and the increase in the capacitor voltage V35 stops. As a result, the capacitor voltage V35 is maintained at a voltage lower than voltage V20 by the forward voltage of the diode 33.

[0074] The time length of the period T1 from timing t21 to t23 is a predetermined time length, which is set in advance by estimating the time it takes for the capacitors 35 of the driving units 32A and 32C to be charged.

[0075] During a period T2 from timing t23 to t24, the control circuit 19 generates gate signals GA to GD that transition between a low level and a high level. During this period T2, the control circuit 19 determines a duty ratio DT based on the voltage VL, which is the output voltage of the power conversion device 1, and generates the gate signals GA to GD based on this duty ratio DT. For example, if the voltage VL is lower than the target voltage Vtarget, the control circuit 19 attempts to increase the voltage VL by increasing the duty ratio DT. For example, if the voltage VL is higher than the target voltage Vtarget, the control circuit 19 attempts to decrease the voltage VL by decreasing the duty ratio DT. In this manner, the control circuit 19 performs feedback control so that the voltage VL becomes the target voltage Vtarget. In this example, the voltage VL becomes the target voltage Vtarget at timing t24, and is subsequently controlled to maintain this target voltage Vtarget.

[0076] (Burst mode operation) When the load is light, the power conversion device 1 operates in burst mode. In this burst mode, the four transistors SA to SD perform intermittent switching operations.

[0077] FIG. 7 shows an example of the operation of the power conversion device 1 in burst mode, where (A) to (D) show the waveforms of the gate signals GA to GD, respectively, and (E) shows the power transmission operation from the primary side circuit to the secondary side circuit in the power conversion device 1.

[0078] 7, initially, the control circuit 19 generates gate signals GA to GD that transition between low and high levels (FIGS. 7(A) to (D)). The insulating units 31A, 31C and the driving units 32A to 32D generate gate signals GA1 to GD1 based on the gate signals GA to GD, and the switching circuit 12 performs switching operations based on the gate signals GA1 to GD1. In this example, as the load on the power conversion device 1 becomes lighter, the duty ratio DT gradually decreases, and the duration of the period T during which power is transmitted gradually becomes shorter (FIG. 7(E)).

[0079] Then, the control circuit 19 sets the gate signals GA to GD to low level (FIGS. 7(A) to 7(D)). The insulating units 31A, 31C and the driving units 32A to 32D generate low-level gate signals GA1 to GD1 based on the gate signals GA to GD, and the switching circuit 12 stops switching operation.

[0080] When the switching operation stops in this way, the power conversion device 1 does not transmit power from the primary side circuit to the secondary side circuit, and the voltage VL, which is the output voltage of the power conversion device 1, gradually decreases. When the voltage VL falls below a certain voltage (a threshold VLth1 described later), the control circuit 19 starts to generate gate signals GA to GD again, which transition between low and high levels (FIGS. 7(A) to 7(D)). The driving units 32A to 32D generate gate signals GA1 to GD1 based on the gate signals GA to GD, and the switching circuit 12 performs switching operation based on the gate signals GA1 to GD1.

[0081] Thereafter, as long as the light load state is maintained, the power conversion device 1 repeats this operation. In the burst mode, the power conversion device 1 intermittently operates the four transistors SA to SD in this manner.

[0082] FIG. 8 shows an example of the operation of the power conversion device 1 in the burst mode.

[0083] First, the control circuit 19 checks whether the duty ratio DT is lower than a predetermined threshold value DTth1 (step S101). If the duty ratio DT is not lower than the threshold value DTth1 ("N" in step S101), the control circuit 19 repeats the process of step S101 until the duty ratio DT becomes lower than the threshold value DTth1.

[0084] In step S101, if the duty ratio DT is lower than a predetermined threshold value DTth1 ("Y" in step S101), the control circuit 19 stops the switching operation of the transistors SA to SD (step S102). Specifically, the control circuit 19 sets the gate signals GA to GD to a low level. The insulating units 31A, 31C and the driving units 32A to 32D generate low-level gate signals GA1 to GD1 based on the gate signals GA to GD. This turns off the transistors SA to SD, and the switching circuit 12 stops its switching operation.

[0085] Next, the control circuit 19 starts a counting operation to count the length of the period during which the switching operation is stopped (step S103). The control circuit 19 counts, for example, the number of cycle periods Tsw (FIG. 3) of the switching cycle, and updates the count value CNT.

[0086] During the period when the switching operation is stopped, the power conversion device 1 does not transfer power from the primary side circuit to the secondary side circuit, so that the voltage VL, which is the output voltage of the power conversion device 1, gradually decreases. Furthermore, because the transistors SB and SD are not turned on, the capacitors 35 in the driving units 32A and 32C are not charged. Therefore, the capacitors 35 are gradually discharged naturally over time, and the voltage across the capacitors 35 decreases.

[0087] Next, the control circuit 19 checks whether the voltage VL, which is the output voltage of the power conversion device 1, is lower than a predetermined threshold value VLth1 (step S104). If the voltage VL is not lower than the threshold value VLth1 ("N" in step S104), the control circuit 19 repeats the process of step S104 until the voltage VL becomes lower than the threshold value VLth1.

[0088] In step S104, if the voltage VL is lower than the threshold value VLth1 ("Y" in step S104), it is confirmed whether the count value CNT of the counting operation is smaller than a predetermined threshold value CNTth (step S105).

[0089] In step S105, if the count value CNT is smaller than the predetermined threshold value CNTth ("Y" in step S105), the control circuit 19 starts the switching operation of the transistors SA to SD and performs feedback control (step S106). Specifically, the control circuit 19 determines the duty ratio DT based on the voltage VL that is the output voltage of the power conversion device 1, and generates the gate signals GA to GD based on this duty ratio DT. The insulating units 31A and 31C and the driving units 32A to 32D generate the gate signals GA1 to GD1 based on the gate signals GA to GD. As a result, the transistors SA to SD of the switching circuit 12 start their switching operation. The voltage VL that is the output voltage of the power conversion device 1 is controlled to become the target voltage Vtarget. As a result, the voltage VL increases toward the target voltage Vtarget. Furthermore, when the transistor SB is turned on, the capacitor 35 of the driving unit 32A is charged, and when the transistor SD is turned on, the capacitor 35 of the driving unit 32C is charged. This increases the voltage across the capacitor 35. Then, the process proceeds to step S110.

[0090] In step S105, if the count value CNT is not smaller than the predetermined threshold value CNTth ("N" in step S105), the control circuit 19 starts the switching operation of the transistors SB and SD (step S107). Specifically, the control circuit 19 generates gate signals GB and GD having a predetermined pulse width and maintains the gate signals GA and GC at a low level. The insulating units 31A and 31C and the driving units 32A to 32D generate gate signals GA1 to GD1 based on the gate signals GA to GD. As a result, the transistors SB and SD of the switching circuit 12 start their switching operation.

[0091] Next, the control circuit 19 waits for a predetermined time (step S108).

[0092] During the period when the transistors SB and SD are performing switching operations, when the transistor SB is turned on, the capacitor 35 of the drive unit 32A is charged, and when the transistor SD is turned on, the capacitor 35 of the drive unit 32C is charged, thereby increasing the voltage across the capacitor 35.

[0093] Next, the control circuit 19 starts the switching operation of the transistors SA and SC, and performs feedback control (step S109). Specifically, the control circuit 19 determines the duty ratio DT based on the voltage VL, which is the output voltage of the power conversion device 1, and generates the gate signals GA to GD based on this duty ratio DT. The insulating units 31A and 31C and the driving units 32A to 32D generate the gate signals GA1 to GD1 based on the gate signals GA to GD. As a result, the transistors SA to SD of the switching circuit 12 start their switching operation. The voltage VL, which is the output voltage of the power conversion device 1, is controlled to become the target voltage Vtarget. As a result, the voltage VL rises toward the target voltage Vtarget.

[0094] Next, the control circuit 19 checks whether the voltage VL, which is the output voltage of the power conversion device 1, is higher than a predetermined threshold value VLth2 (step S110). If the voltage VL is not higher than the threshold value VLth2 ("N" in step S110), the control circuit 19 repeats the process of step S110 until the voltage VL becomes higher than the threshold value VLth2.

[0095] Next, the control circuit 19 checks whether the duty ratio DT is greater than a predetermined threshold value DTth2 (step S111). If the duty ratio DT is not greater than the threshold value DTth2 ("N" in step S111), the process returns to step S102, and the control circuit 19 repeats the processes of steps S102 to S110 until the duty ratio DT becomes greater than the predetermined threshold value DTth2.

[0096] In step S111, if the duty ratio DT is greater than the predetermined threshold value DTth2 ("Y" in step S111), this process ends.

[0097] Next, the operation of the power conversion device 1 will be described in detail with reference to the flowchart shown in FIG. 8, using several examples.

[0098] Figure 9 shows an example of operation of the power conversion device 1, where (A) shows the waveform of the load current IL of the power conversion device 1, (B) to (E) show the waveforms of the gate signals GA to GD, respectively, (F) shows the waveform of the voltage (capacitor voltage V35) across the capacitor 35 in the driving units 32A and 32C, and (G) shows the waveform of the voltage VL, which is the output voltage of the power conversion device 1.

[0099] Before timing t21, the load current IL of the power conversion device 1 decreases (FIG. 9(A)). As a result, in the power conversion device 1, the duty ratio DT decreases.

[0100] At timing t21, the control circuit 19 confirms that the duty ratio DT is smaller than the threshold value DTth1 ("Y" in step S101). Then, the control circuit 19 stops the switching operations of the transistors SA to SD by setting the gate signals GA to GD to a low level (FIGS. 9B to 9E, step S102). When the switching operations are stopped in this manner, the power conversion device 1 does not transmit power from the primary side circuit to the secondary side circuit, and the voltage VL, which is the output voltage of the power conversion device 1, gradually decreases (FIG. 9G). Furthermore, because the transistors SB and SD are not turned on, the capacitor 35 in the driving units 32A and 32C is not charged. Therefore, the capacitor 35 gradually discharges naturally over time, and the voltage across the capacitor 35 decreases (FIG. 9F).

[0101] Next, at timing t22, the voltage VL, which is the output voltage of the power conversion device 1, becomes lower than the threshold value VLth1 (FIG. 9(G), step S104: “Y”). In this example, the count value CNT, which corresponds to the time length from timing t21 to t22, is smaller than the threshold value CNTth (step S105: “Y”). As a result, the control circuit 19 determines the duty ratio DT based on the voltage VL, which is the output voltage of the power conversion device 1, and generates gate signals GA to GD based on this duty ratio DT, thereby starting the switching operations of the transistors SA to SD (FIGS. 9(B) to 9(E), step S106). The control circuit 19 determines the duty ratio DT by performing feedback control, so that the voltage VL is controlled to become the target voltage Vtarget. As a result, the voltage VL gradually increases (FIG. 9(G)). Furthermore, when the transistor SB is turned on, the capacitor 35 of the drive unit 32A is charged, and when the transistor SD is turned on, the capacitor 35 of the drive unit 32C is charged. This causes the voltage across the capacitor 35 to rise (FIG. 9(F)).

[0102] Next, at timing t23, voltage VL, which is the output voltage of power conversion device 1, becomes higher than threshold value VLth2 (FIG. 9(G), "Y" in step S110). In this example, since load current IL is still small, duty ratio DT is not higher than threshold value DTth2 ("N" in step S111). Therefore, control circuit 19 stops the switching operation of transistors SA to SD by setting gate signals GA to GD to low level (FIGS. 9(B) to (E), step S102). As a result, voltage VL gradually decreases (FIG. 9(G)), and the voltage across capacitor 35 also gradually decreases (FIG. 9(F)).

[0103] Thereafter, the power conversion device 1 repeats this operation.

[0104] Then, before timing t24, the load current IL of the power conversion device 1 increases (FIG. 9(A)). This causes the duty ratio DT to increase in the power conversion device 1. At timing t24, the control circuit 19 confirms that the duty ratio DT is greater than the threshold value DTth2 ("Y" in step S111). This ends the operation in burst mode.

[0105] Figure 10 shows another example of operation of the power conversion device 1, where (A) shows the waveform of the load current IL of the power conversion device 1, (B) to (E) show the waveforms of the gate signals GA to GD, respectively, (F) shows the waveform of the voltage (capacitor voltage V35) across the capacitor 35 in the driving units 32A and 32C, and (G) shows the waveform of the voltage VL, which is the output voltage of the power conversion device 1.

[0106] Before timing t31, the load current IL of the power conversion device 1 decreases (FIG. 10(A)). The amount of the load current IL is even smaller than in the case of FIG. 9. As a result, the duty ratio DT of the power conversion device 1 decreases.

[0107] At timing t31, the control circuit 19 confirms that the duty ratio DT is smaller than the threshold value DTth1 ("Y" in step S101). Then, the control circuit 19 stops the switching operations of the transistors SA to SD by setting the gate signals GA to GD to a low level (FIGS. 10B to 10E, step S102). When the switching operations are stopped in this manner, the power conversion device 1 does not transmit power from the primary side circuit to the secondary side circuit, and the voltage VL, which is the output voltage of the power conversion device 1, gradually decreases (FIG. 10G). Furthermore, because the transistors SB and SD are not turned on, the capacitor 35 in the driving units 32A and 32C is not charged. Therefore, the capacitor 35 gradually discharges naturally over time, and the voltage across the capacitor 35 decreases (FIG. 10F).

[0108] Next, at timing t32, the voltage VL, which is the output voltage of the power conversion device 1, becomes lower than the threshold value VLth1 (FIG. 10(G), step S104: “Y”). In this example, the count value CNT corresponding to the time length from timing t31 to t32 is greater than the threshold value CNTth (step S105: “N”). That is, in this example, the amount of load current IL is even smaller than in the case of FIG. 9, so the rate of change of voltage VL is gentler than in the example of FIG. 9. As a result, the time length from timing t31 to t32 is longer than the time length from timing t21 to t22 in FIG. 9. This causes the control circuit 19 to generate gate signals GB and GD having a predetermined pulse width, thereby starting the switching operation of the transistors SB and SD (FIGS. 10(C) and 10(E), step S107). When the transistor SB is turned on, the capacitor 35 of the drive unit 32A is charged, and when the transistor SD is turned on, the capacitor 35 of the drive unit 32C is charged. This causes the voltage across the capacitor 35 to rise (FIG. 10(F)).

[0109] Next, at timing t33, when a predetermined time has elapsed since timing t32, the control circuit 19 determines the duty ratio DT based on the voltage VL, which is the output voltage of the power conversion device 1, and generates gate signals GA to GD based on this duty ratio DT, thereby starting the switching operations of the transistors SA to SD (FIGS. 10B to 10E, step S109). The control circuit 19 determines the duty ratio DT by performing feedback control, so that the voltage VL is controlled to become the target voltage Vtarget. As a result, the voltage VL gradually increases (FIG. 10G).

[0110] Next, at timing t34, voltage VL, which is the output voltage of power conversion device 1, becomes higher than threshold value VLth2 (FIG. 10(G), "Y" in step S110). In this example, since load current IL is still small, duty ratio DT is not higher than threshold value DTth2 ("N" in step S111). Therefore, control circuit 19 stops the switching operation of transistors SA to SD by setting gate signals GA to GD to low level (FIGS. 10(B) to (E), step S102). As a result, voltage VL gradually decreases (FIG. 10(G)), and the voltage across capacitor 35 also gradually decreases (FIG. 10(F)).

[0111] Thereafter, the power conversion device 1 repeats this operation.

[0112] Then, before timing t35, the load current IL of the power conversion device 1 increases (FIG. 10(A)). This causes the duty ratio DT to increase in the power conversion device 1. At timing t35, the control circuit 19 confirms that the duty ratio DT is greater than the threshold value DTth2 ("Y" in step S111). This ends the operation in burst mode.

[0113] Here, the threshold value VLth1 corresponds to a specific example of a "first threshold voltage" in the present disclosure, and the threshold value VLth2 corresponds to a specific example of a "second threshold voltage" in the present disclosure.

[0114] In this way, the power conversion device 1 is provided with a switching circuit 12 having a first switching element (e.g., transistor SA) and a second switching element (e.g., transistor SB) connected in series via a connection node in a path connecting the first terminal (terminal T11) and the second terminal (terminal T12), a diode 33 having an anode connected to the output terminal of the voltage generating circuit 20 and a cathode, a capacitor 35 having one end connected to the cathode of the diode 33 and the other end connected to node N1, and a drive unit (e.g., insulating unit 31A and drive unit 32A) having a drive circuit 36 ​​that can drive the first switching element based on a control signal (gate signal GA) supplied from the control circuit 19 by using the voltage across the capacitor 35 as a power supply voltage. The control circuit 19 repeatedly changes the operating state of the switching circuit 12 in the following order: a first operating state in which both the first switching element and the second switching element are maintained in the off state, a second operating state in which the first switching element is maintained in the off state and the second switching element performs a switching operation, and a third operating state in which both the first switching element and the second switching element perform a switching operation. This allows the power conversion device 1 to reduce energy loss.

[0115] That is, for example, as in the technology described in Patent Document 1, in burst mode, when the lower switching element is continuously switched while the upper switching element is intermittently switched, drive loss occurs in the lower switching element, resulting in increased energy loss. Meanwhile, in the power conversion device 1, for example, in FIG. 10, the switching operation of the second switching element (e.g., transistor SB) is stopped during the period from timing t31 to t32, and the second switching element is switched during the period from timing t32 to t33. The length of this period from timing t32 to t33 can be set to a short time that allows the capacitor 35 of the drive unit 32A to be charged. This reduces the drive loss of transistor SB, thereby reducing energy loss.

[0116] 10 , in the power conversion device 1, the control circuit 19 changes the operating state of the switching circuit 12 in the order of the first operating state, the second operating state, and the third operating state if the time from when the switching circuit 12 is changed to the first operating state until the voltage at the second power terminals (terminals T21 and T22) falls below the first threshold voltage (threshold voltage VLth1) is longer than a second predetermined time. That is, if the period of the first operating state in which both the first switching element and the second switching element are maintained in the off state is long, the amount of voltage drop across the capacitor 35 of the drive unit 32A is large. Therefore, in such a case, the control circuit 19 changes the operating state of the switching circuit 12 to the second operating state in which the first switching element is maintained in the off state and the second switching element performs a switching operation, and then to the third operating state in which both the first switching element and the second switching element perform a switching operation. The control circuit 19 can charge the capacitor 35 of the drive unit 32A by setting the operating state of the switching circuit 12 to the second operating state. This allows the power conversion device 1 to charge the capacitor 35 while effectively reducing energy loss.

[0117] Furthermore, in the power conversion device 1, as shown in FIG. 9 , the control circuit 19 changes the operating state of the switching circuit 12 sequentially from the first operating state to the third operating state if the time it takes for the voltage at the second power terminal (terminals T21, T22) to fall below the first threshold voltage (threshold voltage VLth1) is shorter than a second predetermined time after the switching circuit 12 is changed to the first operating state. That is, if the period of the first operating state in which both the first switching element and the second switching element maintain their off states is short, the amount of voltage drop across the capacitor 35 of the drive unit 32A is small. Therefore, in such a case, the control circuit 19 changes the operating state of the switching circuit 12 to the third operating state in which both the first switching element and the second switching element perform their switching operations, rather than to the second operating state in which the first switching element maintains its off state and the second switching element performs its switching operation. This allows the power conversion device 1 to effectively reduce energy loss.

[0118] [effect] As described above, this embodiment provides a driving unit including a switching circuit having a first switching element and a second switching element connected in series via a connection node in a path connecting the first terminal and the second terminal; a diode having an anode connected to the output terminal of the voltage generating circuit and a cathode; a capacitor having one end connected to the cathode of the diode and the other end connected to the connection node; and a driving circuit capable of driving the first switching element based on a control signal supplied from a control circuit by using the voltage across the capacitor as a power supply voltage. The control circuit repeatedly changes the operating state of the switching circuit between a first operating state in which both the first switching element and the second switching element are maintained in an off state, a second operating state in which the first switching element is maintained in an off state and the second switching element performs a switching operation, and a third operating state in which both the first switching element and the second switching element perform a switching operation. This reduces energy loss.

[0119] In this embodiment, if the time from when the operating state of the switching circuit is changed to the first operating state until the voltage at the second power terminal becomes lower than the first threshold voltage is longer than a second predetermined time, the control circuit changes the operating state of the switching circuit in the order of the first operating state, the second operating state, and the third operating state. This makes it possible to charge capacitor 35 while effectively reducing energy loss.

[0120] Furthermore, in the power conversion device 1, as shown in FIG. 9, the control circuit 19 changes the operating state of the switching circuit 12 to the first operating state and then to the third operating state in that order if the time from when the operating state of the switching circuit 12 is changed to the first operating state until the voltage at the second power terminal becomes lower than the first threshold voltage is shorter than the second predetermined time. Therefore, the power conversion device 1 can effectively reduce energy loss.

[0121] [Variations] In the above embodiment, the switching circuit 12 includes four transistors SA to SD. However, this is not limiting. Instead, for example, the power conversion device 1A shown in FIG. 11 may include two transistors. The power conversion device 1A includes terminals T11 and T12, a voltage generating circuit 20, a switching circuit 12A, an insulating unit 31A, driving units 32A and 32B, capacitors 51 and 52, a transformer 13, a rectifier circuit 14, a smoothing circuit 15, a voltage sensor 18, a control circuit 19A, and terminals T21 and T22. The switching circuit 12 is a half-bridge circuit and includes transistors SA and SB. The insulating unit 31A is configured to generate a gate signal GA0 electrically insulated from the gate signal GA based on the gate signal GA supplied from the control circuit 19A. The driver 32A is configured to generate a gate signal GA1 based on the voltage V20 supplied from the voltage generating circuit 20 and the gate signal GA0 supplied from the insulating unit 31A, and to drive the transistor SA using this gate signal GA1. The driver 32B is configured to generate a gate signal GB1 based on the voltage V20 supplied from the voltage generating circuit 20 and the gate signal GB supplied from the control circuit 19A, and to drive the transistor SB using this gate signal GB1. One end of the capacitor 51 is connected to the voltage line L11, and the other end is connected to a node N2. One end of the capacitor 52 is connected to the node N2, and the other end is connected to a reference voltage line L12. The control circuit 19A is configured to control the operation of the switching circuit 12A based on the voltage VL detected by the voltage sensor 18, thereby controlling the operation of the power conversion device 1A.

[0122] Although the present invention has been described above by way of embodiments and modifications, the present invention is not limited to these embodiments and can be modified in various ways.

[0123] For example, in the above embodiment, the voltage step-down operation is performed in the power conversion operation, but this is not limitative, and the voltage step-up operation may also be performed.

[0124] Furthermore, for example, the circuit configuration of the voltage generating circuit 20, the circuit configuration of the switching circuit 12, the circuit configuration of the rectifier circuit 14, the operating waveforms of the gate signals, etc. in the above embodiments are merely examples and may be changed as appropriate.

[0125] The effects described in this specification are merely examples, and the effects of the present disclosure are not limited to the effects described in this specification. Therefore, other effects may be obtained with respect to the present disclosure.

[0126] Furthermore, the present disclosure may take the following aspects.

[0127] (1) a first power terminal including a first terminal and a second terminal; a switching circuit including a first switching element and a second switching element connected in series via a connection node in a path connecting the first terminal and the second terminal; a transformer having a first winding and a second winding connected to the switching circuit; a rectifier circuit connected to the second winding; a smoothing circuit connected to the rectifier circuit; a second power terminal connected to the smoothing circuit; a control circuit capable of controlling the operation of the switching circuit; a voltage generating circuit for generating a predetermined voltage; a drive unit including a diode having an anode connected to the output terminal of the voltage generating circuit and a cathode, a capacitor having one end connected to the cathode of the diode and the other end connected to the connection node, and a drive circuit capable of driving the first switching element based on a control signal supplied from the control circuit by using the voltage across the capacitor as a power supply voltage; Equipped with The control circuit is capable of repeatedly changing the operating state of the switching circuit in the order of a first operating state in which both the first switching element and the second switching element maintain an off state, a second operating state in which the first switching element maintains an off state and the second switching element performs a switching operation, and a third operating state in which both the first switching element and the second switching element perform a switching operation. Power conversion device. (2) The control circuit the operating state of the switching circuit is changeable from the first operating state to the second operating state when the voltage at the second power terminal falls below a first threshold voltage; The operating state of the switching circuit may be changed from the third operating state to the first operating state when the voltage at the second power terminal is greater than a second threshold voltage. The power conversion device according to (1) above. (3) The control circuit is capable of changing the operating state of the switching circuit from the second operating state to the third operating state when a first predetermined time has elapsed after changing the operating state of the switching circuit from the first operating state to the second operating state. The power conversion device according to (2) above. (4) When the operating state of the switching circuit is the second operating state, the control circuit supplies the control signal having a predetermined pulse width to the drive unit, thereby causing the drive unit to drive the second switching element. The power conversion device according to any one of (1) to (3). (5) The control circuit is capable of changing the operating state of the switching circuit in the order of the first operating state, the second operating state, and the third operating state when a time period from when the operating state of the switching circuit is changed to the first operating state until the voltage at the second power terminal becomes lower than a first threshold voltage is longer than a second predetermined time period. The power conversion device according to any one of (1) to (4). (6) The control circuit is capable of changing the operating state of the switching circuit from the first operating state to the third operating state in that order when the time from when the operating state of the switching circuit is changed to the first operating state to when the voltage at the second power terminal becomes lower than the first threshold voltage is shorter than the second predetermined time. The power conversion device according to (5) above. (7) The control circuit is capable of repeatedly changing the operating state of the switching circuit in the order of the first operating state, the second operating state, and the third operating state when the load of the power conversion device is light. The power conversion device according to any one of (1) to (6). [Explanation of symbols]

[0128] 1,1A...power conversion device, 12,12A...switching circuit, 13...transformer, 13A,13B,13C...winding, 14...rectifier circuit, 15...smoothing circuit, 16...inductor, 17...capacitor, 18...voltage sensor, 19,19A...control circuit, 20...voltage generation circuit, 21...transformer, 21A,21B...winding, 22...transistor, 23...diode, 24...capacitor, 25...voltage control circuit, 32A to 32D...drive unit, 33...diode, 34...resistance element, 35...capacitor, 36...drive circuit, 37...resistance element, 45...capacitor, 46...drive circuit, 47...resistance element, BH...battery, CNT...count value, CNTth...threshold value, DA~DD...body diode, DT...duty ratio, DTth1,DTth2...threshold value, D1,D2...diode, GA~GD1,GA1~GD1...gate signal, L11,L21...voltage line, L12,L22...reference voltage line, LD...load, N1~N3...node, SA~SD...transistor, T,T1,T2...period, Tsw...cycle period, T11,T12,T21,T22...terminal, VL...voltage, VLth1,VLth2...threshold value, Vtarget...target voltage, V20...voltage, V35...capacitor voltage.

Claims

1. a first power terminal including a first terminal and a second terminal; a switching circuit including a first switching element and a second switching element connected in series via a connection node in a path connecting the first terminal and the second terminal; a transformer having a first winding and a second winding connected to the switching circuit; a rectifier circuit connected to the second winding; a smoothing circuit connected to the rectifier circuit; a second power terminal connected to the smoothing circuit; a control circuit capable of controlling the operation of the switching circuit; a voltage generating circuit for generating a predetermined voltage; a drive unit including a diode having an anode and a cathode connected to the output terminal of the voltage generating circuit, a capacitor having one end connected to the cathode of the diode and the other end connected to the connection node, and a drive circuit capable of driving the first switching element based on a control signal supplied from the control circuit by using the voltage across the capacitor as a power supply voltage; Equipped with The control circuit is capable of repeatedly changing the operating state of the switching circuit in the order of a first operating state in which both the first switching element and the second switching element maintain an off state, a second operating state in which the first switching element maintains an off state and the second switching element performs a switching operation, and a third operating state in which both the first switching element and the second switching element perform a switching operation. Power conversion device.

2. The control circuit the operating state of the switching circuit is changeable from the first operating state to the second operating state when a voltage at the second power terminal falls below a first threshold voltage; The operating state of the switching circuit may be changed from the third operating state to the first operating state when the voltage at the second power terminal is greater than a second threshold voltage. The power conversion device according to claim 1 .

3. The control circuit is capable of changing the operating state of the switching circuit from the second operating state to the third operating state when a first predetermined time has elapsed after changing the operating state of the switching circuit from the first operating state to the second operating state. The power conversion device according to claim 2 .

4. When the operating state of the switching circuit is the second operating state, the control circuit supplies the control signal having a predetermined pulse width to the drive unit, thereby causing the drive unit to drive the second switching element. The power conversion device according to claim 1 .

5. The control circuit is capable of changing the operating state of the switching circuit in the order of the first operating state, the second operating state, and the third operating state when a time period from when the operating state of the switching circuit is changed to the first operating state until the voltage at the second power terminal becomes lower than a first threshold voltage is longer than a second predetermined time period. The power conversion device according to any one of claims 1 to 4.

6. The control circuit is capable of changing the operating state of the switching circuit from the first operating state to the third operating state in that order when the time from when the operating state of the switching circuit is changed to the first operating state to when the voltage at the second power terminal becomes lower than the first threshold voltage is shorter than the second predetermined time. The power conversion device according to claim 5 .

7. The control circuit is capable of repeatedly changing the operating state of the switching circuit in the order of the first operating state, the second operating state, and the third operating state when the load of the power conversion device is light. The power conversion device according to claim 1 .

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