Semiconductor Devices

Abstract

To improve the performance of an ESD protection circuit while suppressing destruction of a transistor even when an ESD protection circuit is provided with a low withstand voltage type transistor.SOLUTION: A semiconductor device includes an ESD protection circuit having a first n-channel MOS transistor provided between a signal terminal and a ground line, and a control circuit electrically connected to the signal terminal, and the control circuit outputs a first voltage obtained by stepping down the high-level voltage of the signal to the gate of the 1-n channel MOS transistor when a high-level signal is supplied to the signal terminal, and when a surge due to ESD is input, a second voltage lower than the first voltage is output to the gate of the 1-n channel MOS transistor.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Electrostatic discharge (ESD) protection circuits are known that are provided in semiconductor devices to protect the internal circuits of the semiconductor devices from electrostatic discharge (ESD). For example, an ESD protection circuit includes a transistor disposed between an external terminal and a ground line, and a control circuit that increases the gate voltage of the transistor in the ESD protection circuit in response to an ESD event applied to the external terminal. This type of ESD protection circuit may also include an RC circuit that generates a control voltage in response to an ESD event. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent No. 11,056,880 [Patent Document 2] US Patent Application Publication No. 2014 / 0307354 [Patent Document 3] U.S. Patent No. 10,535,647 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, the miniaturization of semiconductor elements such as transistors and the reduction in power consumption of semiconductor devices have led to a decrease in the breakdown voltage of elements such as transistors mounted on semiconductor devices. For example, when using low-voltage transistors in ESD protection circuits, it is necessary to control the gate voltage so as to improve the performance of the ESD protection circuit while suppressing breakdown of the transistors.

[0005] The present invention has been made in view of the above points, and has an object to improve the performance of an ESD protection circuit while suppressing breakdown of a low-voltage transistor even when the transistor is provided in the ESD protection circuit. [Means for solving the problem]

[0006] In one aspect of the present invention, a semiconductor device includes an ESD protection circuit having a first n-channel MOS transistor provided between a signal terminal and a ground line, and a control circuit electrically connected to the signal terminal, wherein when a high-level signal is supplied to the signal terminal, the control circuit outputs a first voltage that is a step-down version of the high-level voltage of the signal to the gate of the first n-channel MOS transistor, and when an ESD surge is input to the signal terminal, the control circuit outputs a second voltage that is lower than the first voltage to the gate of the first n-channel MOS transistor. [Effects of the Invention]

[0007] According to the disclosed technology, even when a low-voltage transistor is provided in an ESD protection circuit, it is possible to improve the performance of the ESD protection circuit while suppressing breakdown of the transistor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 2 is a diagram illustrating an example of a layout of the semiconductor device according to the first embodiment. [Figure 2] 2 is a circuit diagram showing an example of a signal I / O cell unit in FIG. 1; [Figure 3] FIG. 10 is a circuit diagram illustrating an example of an I / O cell unit for signals in a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a circuit diagram illustrating an overview of a semiconductor device according to a third embodiment. [Figure 5] 5 is a circuit diagram showing an example of a signal I / O cell unit and a control circuit shown in FIG. 4. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal value, a signal line, or a signal terminal. A symbol indicating a voltage is also used to indicate a voltage line or a voltage terminal to which a voltage is supplied.

[0010] (First embodiment) Fig. 1 shows an example of the layout of a semiconductor device according to the first embodiment. For example, the semiconductor device SEM shown in Fig. 1 may be a SoC (System on Chip), or may be a standalone CPU (Central Processing Unit), GPU (Graphics Processing Unit), DSP (Digital Signal Processor), FPGA (Field-Programmable Gate Array), memory, or the like.

[0011] The semiconductor device SEM has a plurality of I / O cells IOC1 and IOCP1, each including a pad PAD. The I / O cell IOC1 is an interface circuit for a signal SIG, such as an input signal, an output signal, or an input / output signal. The I / O cell IOCP1 is an interface circuit for a power supply voltage VDD or a ground voltage. The pad PAD provided in the I / O cell IOC1 is an example of a signal terminal.

[0012] Each of the I / O cells IOC1 and IOCP1 is connected to an internal circuit area. For example, the internal circuit area may include a logic circuit or a memory. Furthermore, the internal circuit area may include an analog circuit. In FIG. 1, the semiconductor device SEM has one internal circuit area, but the number of internal circuit areas may be two or more.

[0013] The number of I / O cells IOC1 and IOCP1 is not limited to the example shown in FIG. 2. The number of pads PAD for the signal SIG, the number of pads PAD for the power supply voltage VDD, and the number of pads PAD for the ground voltage VSS, and their ratio are also not limited to the example shown in FIG. 1. In addition, in FIG. 1, for ease of explanation, an example is shown in which the pads PAD are provided on the outer periphery of the semiconductor device SEM, but the pads PAD may be provided at any position on the semiconductor device SEM. Furthermore, the pads PAD may be provided on the opposite side (back side) from the element surface on which the I / O cells IOC1 and IOCP1 are formed. A bonding wire or a bump may be connected to the pad PAD.

[0014] 2 shows an example of the I / O cell section IOC1 for the signal SIG in FIG. 1. In addition to the pad PAD, the I / O cell IOC1 has an ESD protection circuit ESDP, a control circuit CNT1, and an input / output circuit IOBUF. The input / output circuit IOBUF has, for example, an input buffer that receives a signal supplied to the pad PAD, an output buffer that outputs a signal to the pad PAD, or an input buffer and an output buffer. Although not shown, the I / O cell IOCP1 shown in FIG. 1 has an ESD protection circuit provided between the power supply line VDD and the ground line VSS.

[0015] The protection circuit ESDP has n-channel MOS (Metal Oxide Semiconductor) transistors NM11 and NM12 connected in series between the pad PAD and a ground line VSS. The drain of the n-channel MOS transistor NM11 is connected to the pad PAD. The source of the n-channel MOS transistor NM11 is connected to the drain of the n-channel MOS transistor NM12. The source and gate of the n-channel MOS transistor NM12 are connected to the ground line VSS.

[0016] Hereinafter, n-channel MOS transistors and p-channel MOS transistors will also be simply referred to as transistors. The n-channel MOS transistors will be denoted by the symbol "NM," and the p-channel MOS transistors will be denoted by the symbol "PM."

[0017] The gate of the transistor NM11 receives a control signal CNT output from the control circuit CNT1. The back gates (p-type well regions) of the transistors NM11 and NM12 are connected to the ground line VSS.

[0018] For example, the transistors used in the internal circuit area and the I / O cells IOC1 and IOCP1 are low-voltage type. Note that the input and output buffers arranged in the input / output circuit IOBUF are designed to withstand a higher voltage than the low-voltage type, in accordance with the high-level voltage of the signal supplied to the pad PAD.

[0019] For example, the breakdown voltage of a low-voltage transistor is lower than the high-level voltage of the signal input / output to / from the I / O cell IOC1. Therefore, in the protection circuit ESDP, the gate-drain voltage of the n-channel MOS transistor NM11 connected to the pad PAD must be set to a value equal to or lower than the breakdown voltage of the n-channel MOS transistor NM11 while a high-level signal is being supplied to the pad PAD. Although not particularly limited, for example, the high-level voltage of the signal supplied to the pad PAD is 1.8V, and the breakdown voltage of the n-channel MOS transistor NM11 is 1.2V.

[0020] The control circuit CNT1 includes resistive elements R1, R2, R3, and R4, a capacitive element C1, transistors PM21, PM22, and PM23, and transistors NM21, NM22, and NM23. The resistive elements R1 and R2 are connected in series between the pad PAD and the ground line VSS via a node ND2. The resistive elements R3 and R4 are connected in series between the pad PAD and the ground line VSS via a node ND1. Although not particularly limited, the withstand voltage of the transistors PM21-PM23 and NM21-NM23 is, for example, 1.2V.

[0021] A diode may be connected in series instead of the resistor R3. In this case, for example, the anode of the diode is connected to the pad PAD, and the cathode of the diode is connected to the node ND1. Also, multiple diodes may be connected in series between the pad PAD and the node ND1.

[0022] The capacitance element C1 is connected between the node ND2 and the ground line VSS. For example, but not limited to, the capacitance element C1 is formed using the gate insulating film of an n-channel MOS transistor whose gate is connected to the node ND2 and whose source, drain, and back gate are connected to the ground line VSS. The resistance element R1 and the capacitance element C1 function as an RC circuit.

[0023] The transistors PM21, PM22, and NM21 are connected in series between the node ND1 and the ground line VSS and operate as an inverter IV1. The transistors PM23, NM22, and NM23 are connected in series between the node ND1 and the ground line VSS and operate as an inverter IV2. The back gates of the transistors PM21, PM22, and PM23 are connected to the node ND1. The back gates of the transistors NM21, NM22, and NM23 are connected to the ground line VSS.

[0024] The input of inverter IV1 is connected to node ND2, and the output of inverter IV1, node ND3, is connected to the input of inverter IV2. The output of inverter IV2 is connected to the gate of transistor NM11 via control signal line CNT. The output of inverter IV2 is an example of an output terminal.

[0025] The following describes the operation of the I / O cell IOC1 when a high-level signal SIG is supplied to the pad PAD, and the operation of the I / O cell IOC1 when an ESD-induced surge is input to the pad PAD. Here, the high level is used to mean a logic 1 level and a high-level voltage. The low level is used to mean a logic 0 level and a low-level voltage (ground voltage VSS). Hereinafter, the input of an ESD-induced surge to the pad PAD is also referred to as the occurrence of an ESD event.

[0026] A state in which a high-level signal SIG is supplied to the pad PAD occurs, for example, after the semiconductor device SEM is incorporated into the system and during system operation. When a high-level signal SIG is supplied to the pad PAD, the node ND2 is set to a voltage obtained by dividing the high level by the resistor elements R1 and R2. Similarly, the node ND1 is set to a voltage obtained by dividing the high level by the resistor elements R3 and R4.

[0027] For example, if the resistance values ​​of resistor elements R1 and R3 are equal and the resistance values ​​of resistor elements R2 and R4 are equal, the voltages of nodes ND1 and ND2 will be equal. The voltage division ratios of resistor elements R1 and R2 and resistor elements R3 and R4 are designed so that the voltages of nodes ND1 and ND2 when a high-level signal SIG is supplied to pad PAD are equal to or lower than the withstand voltages of each transistor in control circuit CNT1. This makes it possible to prevent breakdown of transistors PM21-PM23 and NM21-NM23 of inverters IV1 and IV2 and transistor NM11 of protection circuit ESDP when a high-level signal SIG is supplied to pad PAD.

[0028] The inverter IV1 outputs a low level to the node ND3 while receiving the high level at the input of the node ND2. The inverter IV2 outputs a high level as the control signal CNT while receiving the low level at the input of the node ND3. The high level control signal CNT is supplied to the gate of the transistor NM11 of the protection circuit ESDP. The high level of the signal SIG is supplied to the drain of the transistor NM11.

[0029] This allows the drain-gate voltage of the transistor NM11 to be set to a value equal to or lower than the breakdown voltage of the low-voltage type transistor NM11, thereby preventing the breakdown voltage of the transistor NM11 from being violated when a high-level signal SIG is supplied to the pad PAD, and thus preventing the transistor NM11 from being destroyed.

[0030] When a control signal CNT corresponding to a high level at node ND1 is supplied to the gate of transistor NM11, the source-drain resistance of transistor NM11 decreases. However, since transistor NM12 is maintained in the off state, when a high-level signal SIG is input to pad PAD, the protection circuit ESDP can prevent a through current from flowing between pad PAD and ground line VSS.

[0031] On the other hand, when a high-level signal SIG is supplied to the pad PAD and the gate of the transistor NM11 is set to a low level, the drain-gate voltage of the transistor NM11 is set to the high-level voltage of the control signal CNT, which exceeds the breakdown voltage of the transistor NM11, and in this case, the transistor NM11 may be destroyed.

[0032] The operation when a high-level signal SIG output from the internal circuit region is output from the pad PAD to the outside of the semiconductor device SEM is the same as the operation when a high-level signal SIG is input to the pad PAD.

[0033] On the other hand, an ESD event occurs, for example, during the manufacturing process of the semiconductor device SEM or the assembly process of a system into which the semiconductor device SEM is incorporated. For example, if the pad PAD comes into contact with a charged jig or the like and a positive surge is input to the pad PAD, the bipolar operation of the transistor NM11 of the protection circuit ESDP causes an ESD current to flow from the pad PAD to the ground line VSS. This makes it possible to prevent the ESD current from flowing into the internal circuit area, and to protect elements such as transistors mounted in the internal circuit area from the surge.

[0034] Furthermore, when a positive surge is input to the pad PAD, the node ND2 is maintained at a low level (ground voltage VSS) due to the time constant of the RC circuit formed by the resistive element R1 and the capacitive element C1. The RC circuit is designed to have a time constant that sets the node ND2 at a low level while a positive surge is input to the pad PAD.

[0035] Node ND1 is set to the same voltage as when a high-level signal SIG is input to pad PAD. Therefore, inverter IV1 outputs a high level to node ND3 in response to node ND1 being low. Inverter IV2 outputs a low-level control signal CNT to the gate of transistor NM11 in response to node ND3 being high. By setting the gate of transistor NM11 to a low level when an ESD event occurs, the bipolar operation capability can be improved compared to when the gate of transistor NM11 is set to a high level.

[0036] Here, since the nodes ND1 and ND2 are electrically isolated via the resistive elements R1 and R3, it is possible to prevent the node ND1 and the node ND2 from going low when an ESD event occurs. Therefore, when an ESD event occurs, the inverters IV1 and IV2 can operate by receiving a normal power supply voltage and can generate a low-level control signal CNT.

[0037] When a low-level signal SIG is supplied to the pad PAD or when the pad PAD is in an open state, the nodes ND1 and ND2 are set to a low level and the control signal CNT is set to a low level, so that the drain-gate voltage of the transistor NM11 of the protection circuit ESDP becomes 0V and the transistor NM11 is not destroyed.

[0038] Furthermore, when a negative surge is input to the pad PAD, a current flows from the back gate (p-type well layer) to the drain (n-type diffusion layer) of the transistor NM11 in the protection circuit ESDP due to a parasitic diode. This prevents ESD current from flowing from the internal circuit area to the pad PAD, protecting elements such as transistors mounted in the internal circuit area. When a negative surge is input to the pad PAD, the control signal CNT1 does not operate.

[0039] As described above, in this embodiment, when a high-level signal SIG is input to the pad PAD, the control circuit CNT1 outputs a high-level control signal CNT to the gate of the transistor NM11 of the protection circuit ESDP. This makes it possible to prevent a breakdown voltage violation in the transistor NM11 when a high-level signal SIG is input to the pad PAD, and to prevent the transistor NM11 from being destroyed. In other words, even when a low-voltage transistor NM11 is provided in the protection circuit ESDP, it is possible to prevent the transistor NM11 from being destroyed.

[0040] In the control circuit CNT, a voltage obtained by lowering the high-level voltage of the signal SIG is supplied to a node ND2, which is the input of the inverter IV1. Similarly, a voltage obtained by lowering the high-level voltage of the signal SIG is supplied to a node ND1, which is the power supply terminal of the inverters IV1 and IV2. This prevents the transistors PM21-PM23 and NM21-NM23 of the inverters IV1 and IV2 from being destroyed when a high-level signal SIG is supplied to the pad PAD.

[0041] Furthermore, when a positive surge is input to the pad PAD, the bipolar operation of the transistor NM11 in the protection circuit ESDP causes an ESD current to flow from the pad PAD to the ground line VSS. This prevents the ESD current from flowing into the internal circuit area, protecting elements such as transistors mounted in the internal circuit area from surges. Furthermore, by setting the gate of the transistor NM11 to a low level during an ESD event, the bipolar operation capability can be improved compared to when the gate of the transistor NM11 is set to a high level.

[0042] (Second embodiment) 3 shows an example of a signal I / O cell section in a semiconductor device according to the second embodiment. Elements similar to those in FIG. 2 are given the same reference numerals, and detailed description thereof will be omitted. The I / O cell IOC2 for the signal SIG shown in FIG. 3 has the same configuration as the I / O cell IOC1 in FIG. 2, except that it has a control circuit CNT2 instead of the control circuit CNT1. The I / O cell IOC2 is mounted on the semiconductor device SEM in place of the I / O cell IOC1 in FIG. 1.

[0043] The I / O cell IOC2 has a configuration similar to that of the control circuit CNT1 in Figure 2, except that it has resistive elements R5, R6, and R7 instead of resistive elements R1-R4. The resistive elements R5, R6, and R7 are connected in series between the pad PAD and the ground line via nodes ND1 and ND2 in that order. The resistive elements R5 and R6 and the capacitive element C1 function as an RC circuit.

[0044] The number of resistor elements R5-R7 included in I / O cell IOC2 is smaller than the number of resistor elements R1-R4 included in I / O cell IOC1 in Figure 2. Therefore, the size of I / O cell IOC2 can be made smaller than the size of I / O cell IOC1.

[0045] When a high-level signal SIG is supplied to pad PAD, the operation of I / O cell IOC2 is the same as that of I / O cell IOC1 in Fig. 2. When a surge due to ESD is input to pad PAD, the operation of I / O cell IOC2 is the same as that of I / O cell IOC1 in Fig. 2.

[0046] As described above, this embodiment can also achieve the same effects as the above-described embodiments. For example, when a high-level signal SIG is input to pad PAD, the control circuit CNT2 outputs a high-level control signal CNT, so that a breakdown voltage violation does not occur in transistor NM11, and it is possible to prevent transistor NM11 from being destroyed. Nodes ND1 and ND2 of the control circuit CNT2 are set to a voltage that is a step-down voltage of the high-level voltage of signal SIG, so it is possible to prevent transistors PM21-PM23 and NM21-NM23 from being destroyed by a high-level signal SIG.

[0047] Furthermore, in this embodiment, the number of resistive elements included in I / O cell IOC2 can be made smaller than the number of resistive elements included in I / O cell IOC1 in Fig. 2. As a result, the size of I / O cell IOC2 can be made smaller than the size of I / O cell IOC1.

[0048] Since the I / O cells IOC2 are provided in the same number as the pads PAD for inputting or outputting the signal SIG, the chip size of the semiconductor device SEM can be significantly reduced. If the chip size of the semiconductor device SEM is not reduced, the number of elements such as transistors that can be mounted in the internal circuit region can be increased.

[0049] (Third embodiment) Fig. 4 shows an outline of a semiconductor device according to the third embodiment. The semiconductor device SEM shown in Fig. 4 has the same configuration as the semiconductor device SEM of Fig. 1, except that it has an I / O cell IOC3 instead of the I / O cell IOC1 and an I / O cell IOCP2 instead of the I / O cell IOCP1. Note that it is sufficient that the I / O cell IOCP2 is placed in place of at least one of the I / O cells IOCP1 of Fig. 1.

[0050] The I / O cell IOC3 has a configuration in which the control circuit CNT1 is removed from the I / O cell IOC1 in Figure 2 and an inverter IV31 and diodes D31 and D32 are added. The diodes D31 and D32 are connected in series between the pad PAD and the node PADIN, with their anodes located on the pad PAD side. The inverter IV31 outputs a control signal CNT, which is an inverted version of the control signal / CNT, to the gate of the transistor NM11 in the protection circuit ESDP.

[0051] The I / O cell IOCP2 has a control circuit CNT3 and an ESD protection circuit ESDV. The I / O cell IOCP2 in FIG. 4 is a power supply I / O cell whose pad PAD is connected to the power supply line VDD. The protection circuit ESDV is provided between the pad PAD connected to the power supply line VDD and the ground line VSS. The I / O cell IOCP2 may also be applied to an I / O cell whose pad PAD is connected to the ground line VSS. In this case, the protection circuit ESDV of the I / O cell IOCP2 is provided between the power supply line VDD and the pad PAD connected to the ground line VSS.

[0052] The control circuit CNT3 is connected to the pad PAD of each I / O cell IOC3 via the node PADIN and the diodes D31 and D32 of the I / O cells IOC3. The control circuit CNT3 is also connected to the gate of the transistor NM11 of each I / O cell IOC3 via the control signal line / CNT and the inverter IV31 of the I / O cells IOC3. An example of the control circuit CNT3 is shown in FIG. 5.

[0053] Fig. 5 shows an example of the signal I / O cell unit IOC3 and control circuit CNT3 of Fig. 4. In addition to the configuration shown in Fig. 4, the I / O cell IOC3 has resistor elements R31 and R32 connected in series between the pad PAD and the ground line VSS. A node ND31 provided between the resistor elements R31 and R32 is connected to the power supply line of the inverter IV31.

[0054] The inverter IV31 has transistors PM31 and NM31 connected in series between the node ND31 and the ground line VSS. The transistors PM31 and NM31 are designed to be low-voltage, similar to the transistors NM11 and NM12.

[0055] The voltage division ratio of the resistor elements R31 and R32 is designed so that the voltage at the node ND31 when a high-level signal SIG is supplied to the pad PAD is equal to or lower than the breakdown voltage of the transistors PM31 and NM31. This makes it possible to prevent the transistors PM31 and NM31 from being destroyed when a high-level signal SIG is supplied to the pad PAD, similar to the inverters IV1 and IV2 in Figure 2.

[0056] The control circuit CNT3 includes resistors R8, R9, and R11, an RC circuit RC1, and an inverter string IVR. The RC circuit RC1 includes a resistor R10 and a capacitor C1 connected in series between the node PADIN and the ground line VSS via a node ND4. For example, the capacitor C1 is formed using the gate insulating film of an n-channel MOS transistor, similar to the capacitor C1 in FIG. 2.

[0057] The inverter row IVR has CMOS (Complementary Metal Oxide Semiconductor) inverters IV4, IV5, and IV6 connected in series. The input and output of inverter IV4 are connected to nodes ND4 and ND5, respectively. The input and output of inverter IV5 are connected to nodes ND5 and ND6, respectively. The input and output of inverter IV6 are connected to node ND6 and the control signal line / CNT, respectively.

[0058] Inverter IV4 has transistors PM24 and NM24 connected in series between node PADIN and ground line VSS, inverter IV5 has transistors PM25 and NM25 connected in series between node PADIN and ground line VSS, and inverter IV6 has transistors PM26 and NM26 connected in series between node PADIN and ground line VSS.

[0059] Resistor elements R8 and R9 are connected in series between node PADIN and the ground line VSS. In other words, diodes D31 and D32 and resistor elements R8 and R9 are connected in series between pad PAD and the ground line VSS. The resistance values ​​of resistor elements R8 and R9 are designed so that the voltage at node PADIN when a high-level signal SIG is supplied to pad PAD is equal to or lower than the breakdown voltage of transistors PM24-PM26 and NM24-NM26 of the inverter string IVR. This prevents breakdown of transistors PM24-PM26 and NM24-NM26 when a high-level signal SIG is supplied to pad PAD, similar to inverters IV1 and IV2 in FIG. 2.

[0060] The resistor R11 is connected between the control signal line / CNT and the ground line VSS, and functions as a pull-down resistor that prevents the level of the control signal / CNT from becoming unstable when the signal SIG supplied to the pad PAD changes from low level to high level.

[0061] The operation of the I / O cell IOC3 and the control circuit CNT3 when a high-level signal SIG is supplied to the pad PAD and when a surge due to ESD is input to the pad PAD is the same as the operation of the I / O cell IOC1 (control circuit CNT1) in FIG.

[0062] For example, when a high-level signal SIG is supplied to the pad PAD, a high-level control signal CNT, which is the same as the voltage of the node ND31 obtained by lowering the high level of the pad PAD, is supplied to the gate of the transistor NM11 of the protection circuit ESDP. This makes it possible to set the drain-gate voltage of the transistor NM11 to a value equal to or lower than the breakdown voltage of the transistor NM11, thereby preventing the transistor NM11 from being destroyed.

[0063] Furthermore, when a positive surge due to ESD is input to pad PAD, the bipolar operation of transistor NM11 in the protection circuit ESDP causes an ESD current to flow from pad PAD to the ground line VSS. This prevents the ESD current from flowing into the internal circuit area, protecting elements such as transistors mounted in the internal circuit area from surges. At this time, the control circuit CNT3 outputs a low-level control signal CNT to the gate of transistor NM11, thereby improving the bipolar operation capability compared to when the gate of transistor NM11 is set to a high level.

[0064] As described above, this embodiment can also achieve the same effects as the above-described embodiments. Furthermore, in this embodiment, the control circuit CNT3 that controls the gate of transistor NM11 of the protection circuit ESDP of I / O cell IOC3 is provided in common to multiple I / O cells IOC3. This allows the single control circuit CNT3 to protect low-voltage transistors of multiple I / O cells IOC3.

[0065] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form. [Explanation of symbols]

[0066] C1 Capacitor element CNT, control signal CNT1, CNT2, CNT3 control circuits D31, D32 diodes ESDP protection circuit IOC1, IOC2, IOC3 I / O cells IOCP1, IOCP2 I / O cells IV, IV1, IV2 inverters IV4, IV5, IV6 inverters IV31 Inverter IVR inverter string ND1, ND2, ND3, ND4, ND5, ND6 nodes ND31 node NM11, NM12 n-channel MOS transistors NM21, NM22, NM23 n-channel MOS transistors NM24, NM25, NM26 n-channel MOS transistors NM31 n-channel MOS transistor PAD PADIN node PM11, PM12 p-channel MOS transistors PM21, PM22, PM23 p-channel MOS transistors PM24, PM25, PM26 p-channel MOS transistors PM31 p-channel MOS transistor R1, R2, R3, R4 Resistive elements R5, R6, R7 resistance elements R8, R9, R10, R11 resistor elements R31, R32 resistor elements RC1 RC circuit SEM semiconductor device SIG signal

Claims

1. an ESD protection circuit having a first n-channel MOS transistor provided between a signal terminal and a ground line; a control circuit electrically connected to the signal terminal; and When a high-level signal is supplied to the signal terminal, the control circuit outputs a first voltage obtained by lowering the high-level voltage of the signal to the gate of the first n-channel MOS transistor, and when a surge due to ESD is input to the signal terminal, outputs a second voltage lower than the first voltage to the gate of the first n-channel MOS transistor. Semiconductor device.

2. The control circuit an RC circuit connected to the signal terminal; a buffer circuit having an input connected to the RC circuit and an output terminal electrically connected to the gate of the first n-channel MOS transistor; a step-down circuit that steps down the voltage received at the signal terminal and supplies the voltage to a power supply terminal of the buffer circuit; The semiconductor device according to claim 1 ,

3. an ESD protection circuit having a first n-channel MOS transistor provided between a signal terminal and a ground line; a control circuit electrically connected to the signal terminal; and The control circuit an RC circuit connected to the signal terminal; a buffer circuit having an input connected to the RC circuit and an output terminal electrically connected to the gate of the first n-channel MOS transistor; a step-down circuit that steps down the voltage received at the signal terminal and supplies the voltage to a power supply terminal of the buffer circuit; A semiconductor device having:

4. the buffer circuit outputs a low level from the output terminal when receiving a high level at the input, and outputs a high level from the output terminal when receiving a low level at the input; The ESD protection circuit has an inverter provided between the output terminal of the buffer circuit and the gate of the first n-channel MOS transistor.

4. The semiconductor device according to claim 2.

5. the step-down circuit has a diode and a resistor connected in series between the signal terminal and a ground line; A connection node between the diode and the resistor element is connected to the power supply terminal of the buffer circuit.

5. The semiconductor device according to claim 2, wherein the first insulating film is a semiconductor substrate.

6. the control circuit is provided in common to the plurality of ESD protection circuits, The output of the buffer circuit is electrically connected to the gates of the first n-channel MOS transistors of the plurality of ESD protection circuits. The semiconductor device according to claim 5 .

7. The specification of the high-level voltage value of the signal input or output via the signal terminal is greater than the withstand voltage value of the transistor provided in the control circuit.

7. The semiconductor device according to claim 1.

8. the signal terminal is connected to the drain of the first n-channel MOS transistor; The ESD protection circuit further includes a second n-channel MOS transistor having a drain connected to the source of the first n-channel MOS transistor and a source and a gate connected to the ground line.

8. The semiconductor device according to claim 1.

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