Low voltage differential signaling device and driver therefor

Abstract

The application discloses a low-voltage differential signal device and a driver thereof, wherein the output circuit of the device comprises a first current source and a differential push-pull output circuit, the first current source is connected between a power supply end and the differential push-pull output circuit, the differential push-pull output circuit is connected with a differential output end of the driver, and is used for generating a first output voltage and a second output voltage according to a first input signal and a second input signal; the turn-off circuit is connected with the differential output end of the driver, and is used for turning off the first current source by using a short-circuit power supply on the differential output end when the driver is in a leakage protection state; the first end of the substrate clamping circuit is connected with the power supply end, the second end provides a substrate potential for a MOS tube in the first current source, and when the driver is in the leakage protection state, the substrate clamping circuit is in a turn-off state from the second end to the first end, so that the low-voltage differential signal driver can also be effectively protected from leakage when the low-voltage differential signal driver is in a power-off state.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular, to a low voltage differential signaling device and a driver thereof. BACKGROUND

[0002] LVDS (Low Voltage Differential Signaling) is a point-to-point high-speed differential electrical interface, which is designed for applications requiring ultra-low power consumption, low noise and high data rate.

[0003] Under normal circumstances, the LVDS interface circuit needs to meet the TIA / EIA-644-A standard issued by the Electronics and Communications Industry Association. The standard stipulates the electrical and switching characteristics that the LVDS interface circuit needs to meet, and also stipulates the self-protection function required by the LVDS device, including the small leakage current that the LVDS device needs to have in the case of open circuit or short circuit at the output node. The LVDS device usually includes an LVDS driver and a receiver. The LVDS driver of the prior art has a large leakage current flowing into the LVDS device if the output node is shorted to the power supply in the power-off state, thereby not meeting the self-protection requirements of the TIA / EIA-644-A standard.

[0004] Therefore, a new low voltage differential signaling device and a driver thereof need to be proposed to solve the above problems. SUMMARY

[0005] In view of the above problems, the purpose of the present application is to provide a low voltage differential signaling device and a driver thereof, so that effective leakage protection can be performed on the low voltage differential signaling driver when the low voltage differential signaling driver is in a power-off state.

[0006] According to an aspect of the present application, a low voltage differential signaling driver is provided, which includes an output circuit including a first current source and a differential push-pull output circuit, the first current source being connected between a power supply end and the differential push-pull output circuit, the differential push-pull output circuit being connected to a differential output end of the driver and being used to generate a first output voltage and a second output voltage according to a first input signal and a second input signal; a shutdown circuit connected to the differential output end of the driver and used to shut down the first current source by a short-circuit power supply on the differential output end when the driver is in a leakage protection state; and a substrate clamping circuit having a first end connected to the power supply end and a second end providing a substrate potential for a MOS tube in the first current source, and the substrate clamping circuit being in a shutdown state in the direction from the second end to the first end when the driver is in the leakage protection state.

[0007] Optionally, the differential push-pull output circuit comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, the first current source comprises a third PMOS transistor and a fourth PMOS transistor connected between the power supply end and the first end of the first PMOS transistor and the second PMOS transistor in sequence, the substrate of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor is connected to the first voltage end, and the substrate of the first NMOS transistor and the second NMOS transistor is connected to the second voltage end.

[0008] Optionally, the second end of the substrate clamping circuit is connected to the first voltage end, and the turn-off circuit is connected to the control end of the fourth PMOS transistor, and is used for turning off the fourth PMOS transistor by the short-circuit power supply on the differential output end to turn off the first current source when the driver is in the leakage protection state.

[0009] Optionally, the output circuit further comprises a second current source, the first current source, the differential push-pull output circuit and the second current source are connected between the power supply end and the ground end in sequence, the second current source comprises a third NMOS transistor, the first end of the third NMOS transistor is connected to the second end of the first NMOS transistor and the second NMOS transistor, and the substrate of the third NMOS transistor is connected to the second voltage end.

[0010] Optionally, the driver further comprises an open circuit protection circuit, which is used for pulling down the power supply end to the ground end when the power supply end is open.

[0011] Optionally, the substrate clamping circuit comprises a first transistor connected between the power supply end and the first voltage end, the control end of the first transistor is connected to the power supply end, and the substrate of the first transistor is connected to the second voltage end, and the second voltage end is the ground end.

[0012] Optionally, the turn-off circuit comprises a second transistor connected between the control end of the fourth PMOS transistor and the positive differential output end, the control end of the second transistor is connected to the power supply end, and the substrate of the second transistor is connected to the first voltage end; and a third transistor connected between the control end of the fourth PMOS transistor and the negative differential output end, the control end of the third transistor is connected to the control end of the second transistor, and the substrate of the third transistor is connected to the first voltage end.

[0013] Optionally, the substrate clamping circuit further comprises a first resistor connected between the power supply end and the control end of the first transistor, and a second resistor connected between the second end of the first transistor and the first voltage end.

[0014] Optionally, the turn-off circuit further comprises a third resistor connected between the power supply end and the control end of the second transistor; a fourth resistor connected between the second end of the second transistor and the positive differential output end; and a fifth resistor connected between the second end of the third transistor and the negative differential output end.

[0015] According to another aspect of the present application, there is provided a low-voltage differential signal device comprising the low-voltage differential signal driver as described above; and a low-voltage differential signal receiving end connected to the low-voltage differential signal driver through a differential signal line.

[0016] The low-voltage differential signal device and its driver provided by the present application, the LVDS driver comprises an output circuit, a turn-off circuit and a substrate clamping circuit, the turn-off circuit is connected to the differential output end of the LVDS driver, the first end of the substrate clamping circuit is connected to the power supply end, and the second end provides a substrate potential for the MOS tube in the first current source, when the LVDS driver is in the leakage protection state, the turn-off circuit turns off the first current source by using the short-circuited power supply on the differential output end, and the substrate clamping circuit is in the turn-off state in the direction from the second end to the first end, so that the LVDS driver can meet the self-protection requirement of the TIA / EIA-644-A standard. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A circuit schematic diagram of a low-voltage differential signal driver is shown;

[0019] Figure 2 A circuit schematic diagram of a low-voltage differential signal driver is shown; Figure 1 A leakage test schematic diagram of the low-voltage differential signal driver shown in the power-off state, in which the differential output end is short-circuited to the second power supply end;

[0020] Figure 3 A leakage test schematic diagram of the low-voltage differential signal driver shown in the power-off state, in which the differential output end is short-circuited to the second power supply end; Figure 1 A leakage test schematic diagram of the low-voltage differential signal driver shown in the power-off state, in which the differential output end is short-circuited to the second power supply end;

[0021] Figure 4 A circuit schematic diagram of a low-voltage differential signal driver according to an embodiment of the present application is shown;

[0022] Figure 5 A circuit schematic diagram of a low-voltage differential signal driver according to an embodiment of the present application is shown; Figure 4 A leakage test schematic diagram of the low-voltage differential signal driver shown in the power-off state, in which the differential output end is short-circuited to the second power supply end. DETAILED DESCRIPTION

[0023] Various embodiments of the present application will be described in detail below with reference to the drawings. In the drawings, like elements or modules are denoted by the same or similar reference numerals to indicate like or similar elements or modules. For the purpose of clarity, not every component or module of the application is shown in each drawing.

[0024] It is to be understood that the terms "circuit" and "circuitry" as used herein can include single or multiple components or hardware circuits, programmable circuits, state machines, and / or elements to store instructions for execution by a programmable circuit. When an element or circuit is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled or connected to the other element or it can be present in intermediate elements, the connection between elements being physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that the two are connected without any intermediate elements.

[0025] Also, it is to be understood that the use of certain terms to describe the application in this specification is not intended to limit the application to the terms. For example, the terms "including", "including", "comprising", and "having" are meant not to be limiting and are meant to encompass the possibility that there are items being added or other items being excluded, not expressly listed or otherwise described.

[0026] In addition, it should also be noted that, in the present context, relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action without necessarily implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by an indefinite article "a" or "an" does not exclude the existence of additional identical elements in the process, method, article, or apparatus including the defined element.

[0027] Figure 1 A circuit schematic of a low voltage differential signal driver is shown.

[0028] Referring to Figure 1The LVDS driver 100 comprises an output circuit and a common-mode feedback circuit. The output circuit comprises transistors M1, M2, M4, M5 and M3 connected in sequence between a first power supply terminal and a ground terminal, and transistors M6 and M7 connected in sequence between the intermediate nodes of the transistors M2 and M4 and the intermediate nodes of the transistors M5 and M3. The transistors M1-M2, M4 and M6 are PMOS transistors, the substrates of which are connected to the first power supply terminal, the transistors M3, M5 and M7 are NMOS transistors, the substrates of which are connected to the ground terminal, the control terminals of the transistors M4 and M5 receive an input signal Vin1, the control terminals of the transistors M6 and M7 receive an input signal Vin2, the control terminal of the transistor M1 receives a bias voltage Vbias1, the control terminal of the transistor M2 receives a bias voltage Vbias2, the intermediate node of the transistors M6 and M7 provides an output voltage Vout+ as a first output node, and the intermediate node of the transistors M4 and M5 provides an output voltage Vout- as a second output node. The input signals Vin1 and Vin2 are complementary signals, and the ground terminal provides a ground voltage GND. The first power supply terminal is a chip power supply terminal, which provides a power supply voltage VDD. The first output node is connected to a positive differential output terminal of the LVDS driver 100, and the second output node is connected to a negative differential output terminal of the LVDS driver 100.

[0029] The common-mode feedback circuit comprises an error amplifier 110 and resistors R1 and R2 connected in sequence between the positive differential output terminal and the negative differential output terminal of the LVDS driver 100. The positive input terminal of the error amplifier 110 is connected to the intermediate node of the resistors R1 and R2, the negative input terminal receives a reference voltage Vref, and the output terminal is connected to the control terminal of the transistor M3.

[0030] Further, the positive differential output terminal and the negative differential output terminal of the LVDS driver 100 are also connected to an LVDS receiving terminal. The LVDS receiving terminal comprises a terminal resistor Rt, capacitors CL1 and CL2. The terminal resistor Rt is connected between the positive differential output terminal and the negative differential output terminal, the capacitor CL1 is connected between the positive differential output terminal and the ground terminal, the capacitor CL2 is connected between the negative differential output terminal and the ground terminal, and the current flowing through the terminal resistor Rt is a driving current Iout.

[0031] The LVDS driver 100 adopts the drain of the PMOS tube M6 and the NMOS tube M7 to provide the output voltage Vout+, and the drain of the PMOS tube M4 and the NMOS tube M5 to provide the output voltage Vout- to meet the requirements of the large output driving current Iout and the fast flip of the output voltage Vout+ and Vout-. When the LVDS driver 100 is in the normal working state, the PMOS tube and the NMOS tube on the opposite side are alternately turned on (i.e. M4 and M7 are turned on, and M5 and M6 are turned off, and M5 and M6 are turned on, and M4 and M7 are turned off), and the output current Is provided by the current source composed of the transistors M1 and M2 flows through the terminal resistor Rt through the transistors M4-M7, so that the differential output voltage Vout+ and Vout- are obtained, and the positive and negative of the differential output voltage Vout+ and Vout- are related to the turn-on and turn-off of the transistors M4-M7.

[0032] Figure 2 It is shown that Figure 1 The leakage test schematic diagram of the low-voltage differential signal driver shown in the power-off state, the differential output end is short-circuited to the second power supply end; Figure 3 It is shown that Figure 1 The leakage schematic diagram of the low-voltage differential signal driver shown in the power-off state, the differential output end is short-circuited to the second power supply end.

[0033] Referring to Figure 2 and Figure 3 When the LVDS driver 100 is in the power-off state, if the differential output end (the positive differential output end and / or the negative differential output end) is short-circuited to the second power supply end, the LVDS driver 100 will appear the leakage. Taking the positive differential output end of the LVDS driver 100 being short-circuited to the second power supply end as an example, at this time, the potential of the positive differential output end of the LVDS driver 100 is lifted to the power supply voltage VDD1 of the second power supply end, and the first power supply end is in the open circuit state or the short circuit state, resulting in the leakage current flowing from the positive differential output end to the first power supply end, and the leakage path of the leakage current is the positive differential output end-M6-M2-M1-the first power supply end. In addition, at this time, the body diode between the drain of the transistor M6 and the substrate of the transistor M2 is also biased, and the leakage current will be injected to the substrate of the transistor M1 and the transistor M2 and the source end of the transistor M1, i.e. the first power supply end. Therefore, the LVDS driver 100 cannot meet the self-protection requirement of the TIA / EIA-644-A standard, and the reliability of the entire LVDS device is affected.

[0034] Figure 4 It is shown that the circuit schematic diagram of the low-voltage differential signal driver according to the embodiment of the application; Figure 5 It is shown that Figure 4The low-voltage differential signal driver in the power-off state is short-circuited to the second power supply terminal.

[0035] Referring to Figure 4 and Figure 5 The LVDS driver 200 comprises an output circuit 210, a common-mode feedback circuit 220, a substrate clamping circuit 230, an off circuit 240 and an open circuit protection circuit 250.

[0036] The output circuit 210 is used to generate output voltages Vout+ and Vout- according to input signals Vin1 and Vin2. The output circuit 210 comprises a first current source, a differential push-pull output circuit and a second current source connected in sequence between a first power supply terminal and a ground terminal, and the differential push-pull output circuit is connected to the differential output terminal of the LVDS driver 200. The first power supply terminal refers to a chip power supply terminal.

[0037] The first end of the substrate clamping circuit 230 is connected to the first power supply terminal, and the second end provides a substrate potential for the MOS tube in the first current source, and when the LVDS driver 200 is in the leakage protection state, the substrate clamping circuit 230 is in the off state in the direction from the second end to the first end. The second end of the substrate clamping circuit 230 is connected to the first voltage terminal A. The leakage protection state refers to the state that the LVDS driver 200 is in the power-off state, and the differential output terminal (positive differential output terminal and / or negative differential output terminal) is short-circuited to the second power supply terminal.

[0038] The off circuit 240 is connected to the differential output terminal of the LVDS driver 200, and is used to turn off the first current source by the short-circuited power supply on the differential output terminal when the LVDS driver 200 is in the leakage protection state.

[0039] The differential push-pull output circuit includes a first PMOS transistor M4, a second PMOS transistor M6, a first NMOS transistor M5, and a second NMOS transistor M7. The first current source includes a third PMOS transistor M1 and a fourth PMOS transistor M2, and the second current source includes a third NMOS transistor M3. The third PMOS transistor M1, the fourth PMOS transistor M2, the first PMOS transistor M4, the first NMOS transistor M5, and the third NMOS transistor M3 are sequentially connected between a first power supply terminal and a ground terminal. The second PMOS transistor M6 and the second NMOS transistor M7 are sequentially connected between the intermediate node of the fourth PMOS transistor M2 and the first PMOS transistor M4 and the intermediate node of the first NMOS transistor M5 and the third NMOS transistor M3. The substrates of the first to fourth PMOS transistors are connected to a first voltage terminal A, and the substrates of the first to third NMOS transistors are connected to a second voltage terminal, such as a ground terminal. The control terminals of the first PMOS transistor M4 and the first NMOS transistor M5 receive the input signal Vin1, and the control terminals of the second PMOS transistor M6 and the second NMOS transistor M7 receive the input signal Vin2. The intermediate node of the second PMOS transistor M6 and the second NMOS transistor M7 serves as the first output node, providing the output voltage Vout+, and the intermediate node of the first PMOS transistor M4 and the first NMOS transistor M5 serves as the second output node, providing the output voltage Vout-. The input signals Vin1 and Vin2 are inverted signals. The first power supply terminal provides the power supply voltage VDD, and the ground terminal provides the ground voltage GND. The first output node is connected to the positive differential output terminal of the LVDS driver 200, and the second output node is connected to the negative differential output terminal of the LVDS driver 200.

[0040] The shutdown circuit 230 is also connected to the control terminal of the fourth PMOS transistor M2, and is used to turn off the fourth PMOS transistor M2 by using the power supply short-circuited on the differential output terminal when the LVDS driver 200 is in the leakage protection state, so as to shut down the first current source.

[0041] The common-mode feedback circuit 220 is used to compare the common-mode feedback voltages of the output voltages Vout+ and Vout- with the reference voltage Vref, and generate a control voltage Vc based on the comparison result, so as to adjust the output voltages Vout+ and Vout- through the control voltage Vc, so that the common-mode feedback voltages of the output voltages Vout+ and Vout- are stabilized near the reference voltage Vref.

[0042] The open circuit protection circuit 250 is configured to pull down the first power supply terminal to the ground terminal when the LVDS driver 200 is in a power-off state and the first power supply terminal is in an open circuit state, so as to enable the shutdown circuit 240 to work normally. It can be understood that the open circuit protection circuit 250 can be implemented by using any existing circuit which can pull down the first power supply terminal to the ground terminal when the LVDS driver 200 is in a power-off state and the first power supply terminal is in an open circuit state. For example, the open circuit protection circuit 250 can be implemented by using a resistor R1 connected between the first power supply terminal and the ground terminal.

[0043] The common-mode feedback circuit 220 includes an error amplifier 221 and resistors R7 and R8 connected in sequence between the positive differential output terminal and the negative differential output terminal. The positive input terminal of the error amplifier 221 is connected to the middle node of the resistors R7 and R8, the negative input terminal receives a reference voltage Vref, and the output terminal is connected to the control terminal of the transistor M3 to provide a control voltage Vc for the control terminal of the transistor M3.

[0044] The substrate clamping circuit 230 includes a transistor M11 connected between the first power supply terminal and the first voltage terminal A, the substrate of the transistor M11 is connected to the ground terminal, and the control terminal of the transistor M11 is connected to the first power supply terminal.

[0045] The substrate clamping circuit 230 further includes a resistor R6 connected between the control terminal of the transistor M11 and the first power supply terminal, and a resistor R5 connected between the second terminal of the transistor M11 and the first voltage terminal A. The resistors R5 and R6 are configured to implement Electrostatic Discharge (ESD) protection.

[0046] The shutdown circuit 240 includes transistors M12 and M13, the control terminals of the transistors M12 and M13 are connected to the first power supply terminal, the first terminal of the transistor M12 and the first terminal of the transistor M13 are connected to the control terminal of the fourth PMOS transistor M2, the substrates of the transistors M12 and M13 are connected to the first voltage terminal A, the second terminal of the transistor M12 is connected to the first output node, and the second terminal of the transistor M13 is connected to the second output node.

[0047] The shutdown circuit 240 further includes resistors R2-R4, the resistor R2 is connected between the first power supply terminal and the control terminal of the transistor M12, the resistor R3 is connected between the second terminal of the transistor M12 and the first output node, and the resistor R4 is connected between the second terminal of the transistor M13 and the second output node. The resistors R2-R4 are configured to implement Electrostatic Discharge (ESD) protection.

[0048] Optionally, the transistors M12-M13 are P-channel Metal-Oxide-Semiconductor (PMOS) transistors, and the transistor M11 is an N-channel Metal-Oxide-Semiconductor (NMOS) transistor. The first terminal of the PMOS transistor is a source terminal, the second terminal is a drain terminal, and the control terminal is a gate terminal. The first terminal of the NMOS transistor is a drain terminal, the second terminal is a source terminal, and the control terminal is a gate terminal.

[0049] When the LVDS driver 200 is in a normal working state, the substrate of the PMOS transistor is connected to the power supply voltage VDD through the transistor M11. At this time, the transistor M11 is used as a forward conducting diode to provide a substrate potential slightly lower than the power supply voltage VDD for the first voltage terminal A, so that the normal working of the LVDS driver 200 is not affected. The gate voltage Vb of the transistors M12 and M13 is pulled up to the power supply voltage VDD, and the transistors M12 and M13 are turned off. At the same time, the gate voltage of the fourth PMOS transistor M2 depends on the bias voltage Vbias2, so that the fourth PMOS transistor M2 works normally, and the current flowing through the resistor R1 is equivalent to a constant static working current, which does not affect the normal working of the LVDS driver 200.

[0050] When the LVDS driver 200 is in the leakage protection state, if the first power supply end is shorted to the ground voltage GND, the gate voltage Vb of the transistors M12 and M13 is pulled to the ground voltage GND, the transistors M12 and M13 are turned on, the gate voltage Va of the fourth PMOS transistor M2 is pulled high by the high voltage of the differential output end, and the fourth PMOS transistor M2 is in the off state, thus the leakage path to the source end of the fourth PMOS transistor M2 is cut off. In addition, at this time, the leakage current introduced by the forward conduction of the drain-sub diodes of the PMOS transistors M2, M4, M6 and M12-M13 flows to the source end of the transistor M11 through the resistor R5, the gate voltage of the transistor M11 is pulled low by the first power supply end, the transistor M11 is in the off state, and the parasitic diode between the source end and the substrate of the transistor M11 is in the reverse bias state, so there is no leakage current flowing into the first power supply end through the transistor M11. Therefore, when the first power supply end is shorted to the ground end, the LVDS driver 200 has no leakage path to the first power supply end, forcing the leakage current to be in a very small state; if the first power supply end is open, since the gate voltage Vb of the transistors M12 and M13 is in an uncertain state at this time, the transistors M12 and M13 can not be turned on, the leakage current flows into the first power supply end through the source end of the transistor M2, thereby causing a large leakage current, therefore, at this time, the resistor R1 needs to be set to pull down the first power supply end to the ground end, so as to turn on the transistors M12 and M13, so that the shutdown circuit 240 can work normally.

[0051] The LVDS driver 200 provided by the embodiments of the present application can meet the self-protection requirement of the TIA / EIA-644-A standard when the LVDS driver 200 is in the leakage protection state, the shutdown circuit 240 turns off the first current source by using the shorted power supply on the differential output end, and the substrate clamping circuit is in the off state in the direction from the second end to the first end, so that the LVDS driver 200 can meet the self-protection requirement of the TIA / EIA-644-A standard.

[0052] It can be understood that the present application also provides an LVDS device, which comprises the LVDS driver 200 and an LVDS receiving end, and the LVDS driver 200 and the LVDS receiving end are connected through a differential data line. The LVDS driver can adopt the LVDS receiving end shown in the Figure 1 .

[0053] According to the embodiments of the present application as described above, these embodiments do not describe all the details, and do not limit the present application to only the specific embodiments. Obviously, according to the above description, many modifications and changes can be made. The present application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well use the present application and make modifications and uses on the basis of the present application. The protection scope of the present application should be defined by the scope of the claims of the present application and the equivalent thereof.

Claims

1. A low-voltage differential signal driver, comprising: The output circuit includes a first current source and a differential push-pull output circuit. The first current source is connected between the power supply terminal and the differential push-pull output circuit. The differential push-pull output circuit is connected to the differential output terminal of the driver and is used to generate a first output voltage and a second output voltage according to the first input signal and the second input signal. A shutdown circuit, which is connected to the differential output terminal of the driver, is used to shut off the first current source by using the short-circuited power supply on the differential output terminal when the driver is in a leakage protection state. A substrate clamping circuit has a first terminal connected to the power supply terminal and a second terminal providing a substrate potential to the MOS transistor in the first current source. When the driver is in a leakage protection state, the substrate clamping circuit is in a turned-off state from the second terminal to the first terminal. The first current source includes a third PMOS transistor and a fourth PMOS transistor connected sequentially between the power supply terminal and the differential push-pull output circuit. The substrates of both the third and fourth PMOS transistors are connected to a first voltage terminal, which is also connected to the second terminal of the substrate clamping circuit. The shutdown circuit includes a second transistor connected between the control terminal and the positive differential output terminal of the fourth PMOS transistor, with its control terminal connected to the power supply terminal and its substrate connected to the first voltage terminal; and a third transistor connected between the control terminal and the negative differential output terminal of the fourth PMOS transistor, with its control terminal connected to the control terminal of the second transistor and its substrate connected to the first voltage terminal.

2. The driver according to claim 1, wherein, The differential push-pull output circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The substrates of the first PMOS transistor and the second PMOS transistor are both connected to the first voltage terminal, and the substrates of the first NMOS transistor and the second NMOS transistor are both connected to the second voltage terminal.

3. The driver according to claim 2, wherein, The output circuit also includes: The second current source, the first current source, the differential push-pull output circuit, and the second current source are sequentially connected between the power supply terminal and the ground terminal. The second current source includes a third NMOS transistor, the first end of which is connected to the first NMOS transistor and the second end of the second NMOS transistor, and the substrate of the third NMOS transistor is connected to the second voltage terminal.

4. The driver according to claim 1, further comprising: An open-circuit protection circuit is used to pull the power supply terminal down to the ground terminal when the power supply terminal is open-circuited.

5. The driver according to claim 2, wherein, The substrate clamping circuit includes: A first transistor is connected between the power supply terminal and the first voltage terminal, with its control terminal connected to the power supply terminal and its substrate connected to the second voltage terminal, which is a ground terminal.

6. The driver according to claim 5, wherein, The substrate clamping circuit further includes: A first resistor is connected between the power supply terminal and the control terminal of the first transistor; The second resistor is connected between the second terminal of the first transistor and the first voltage terminal.

7. The driver according to claim 1, wherein, The shutdown circuit also includes: The third resistor is connected between the power supply terminal and the control terminal of the second transistor; A fourth resistor is connected between the second terminal of the second transistor and the positive differential output terminal; The fifth resistor is connected between the second terminal of the third transistor and the negative differential output terminal.

8. A low-voltage differential signaling device, comprising: The low-voltage differential signal driver as described in any one of claims 1-7; as well as The low-voltage differential signal receiver is connected to the low-voltage differential signal driver via a differential signal line.

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