Gallium nitride monolithic integrated circuit device and gate driver

Abstract

According to an embodiment, provided is a gate driver for driving a gallium nitride element, the gate driver comprising: a first pull-up circuit for raising a gate voltage of the gallium nitride element to the Miller plateau region when a gate signal is applied; and a second pull-up circuit for raising the gate voltage at a high speed after the gate voltage is raised to the Miller plateau region.

Description

Gallium nitride monolithic integrated circuit device and gate driver

[0001] This embodiment relates to gallium nitride semiconductor technology.

[0002] As the demand for high efficiency and miniaturization / lightweighting of power electronic systems increases, power semiconductor device technology capable of simultaneously satisfying high-speed switching and high power density is required in power converters, inverters, electric vehicle drive systems, wireless power transmission devices, and server power supplies.

[0003] Silicon-based power semiconductors have the advantages of mature manufacturing technology and high reliability, but they have limitations such as increased leakage current and switching losses during high-voltage operation due to their narrow bandgap and low breakdown field. Due to these limitations, there are physical constraints on increasing switching frequencies or improving circuit power density.

[0004] As an alternative to address these problems, wide bandgap semiconductor technology is attracting attention. Among them, Gallium Nitride (GaN) devices have recently become the most 주목받는 technology due to their high electron mobility, large bandgap energy, and low on-resistance.

[0005] Gallium nitride-based High Electron Mobility Transistors (HEMTs) possess excellent current density and high-speed switching characteristics even in high voltage regions of 200V or higher, allowing for simultaneous improvement in system efficiency and power density in power converters utilizing them. Due to these advantages, GaN power semiconductors are rapidly expanding into various application fields, including power converters, data center power supplies, communication equipment, and aerospace power systems.

[0006] However, GaN devices differ structurally from silicon-based devices; they lack a body diode, have a very low gate threshold voltage, and possess small gate-drain capacitance. Consequently, the rate of change of drain voltage (dv / dt) during switching can become very large. These characteristics of GaN devices cause instability phenomena, such as false turn-on / turn-off or ringing, during high-speed circuit operation.

[0007] In particular, if the gate voltage rises or falls instantaneously during the switching process due to Miller capacitance, unintended state transitions may occur, which poses a risk of increased power loss or device degradation.

[0008] Conventional gate drivers are structured to apply gate voltage through a single pull-up path. In this structure, when the gate voltage reaches the Miller Plateau region, the gate current fluctuates rapidly due to the interaction between the gate capacitance and the drain capacitance. Consequently, the gate voltage becomes unstable, leading to current spikes. If the gate current flows excessively, stress is applied to the gate insulating layer, causing switching speed imbalances or waveform distortion, which degrades the stability of the entire circuit. As such, conventional driver structures were not suitable for stably controlling the fast switching characteristics of GaN devices.

[0009] In addition, the gate driving voltage required to drive GaN devices differs from that of conventional silicon devices, and because the margin between the on and off voltages is narrow, precise voltage control and fast response are required in the driving circuit. However, conventional gate drivers rely on external power supply, and since a separate bootstrap power circuit must be configured externally for high-speed driving, there was a problem of increased circuit complexity and losses and reduced system reliability.

[0010] On the other hand, when GaN power devices and gate drivers are implemented as separate chips, the wiring inductance and resistance between the driver output and the device gate increase, exacerbating distortion of voltage and current waveforms during switching and deteriorating electromagnetic interference characteristics. This leads to a decrease in the system's power conversion efficiency and necessitates additional compensation circuitry for stable switching control.

[0011] Due to these issues, the importance of designing gate driving circuits capable of stably controlling the high-speed switching characteristics of GaN devices, and monolithic integration technology for integrating them onto the same semiconductor die as the GaN device, is gradually increasing.

[0012] Against this backdrop, the objective of the present embodiment is, in one aspect, to provide a gate driving structure suitable for the fast switching characteristics of a Gallium Nitride (GaN) device. In another aspect, the objective of the present embodiment is to provide a technique for configuring an on-chip bootstrap circuit within a gate driver. In yet another aspect, the objective of the present embodiment is to provide a technique for monolithically integrating a gate driver and a Gallium Nitride power device on the same semiconductor die.

[0013] To achieve the above-mentioned objective, one embodiment provides a gate driver for driving a gallium nitride device, comprising: a first pull-up circuit that raises the gate voltage of the gallium nitride device to a Miller plateau region when a gate signal is applied; and a second pull-up circuit that raises the gate voltage at a high speed after the rise to the Miller plateau region.

[0014] The first pull-up circuit includes a first inverting logic circuit that outputs an inverted gate signal by re-inverting it, and a first pull-up transistor that raises the gate voltage of the gallium nitride device to a Miller Plato section according to the output signal of the first inverting logic circuit, and the second pull-up circuit includes a second inverting logic circuit that outputs an inverted gate signal by re-inverting it, and a second pull-up transistor that raises the gate voltage at high speed according to the output signal of the second inverting logic circuit, and the inverted gate signal can be transmitted with a delay to the second inverting logic circuit.

[0015] The first pull-up transistor and the second pull-up transistor are implemented as N-channel gallium nitride devices, and the gallium nitride devices can be implemented as High Electron Mobility Transistors (HEMTs).

[0016] A first driving voltage is supplied to one side of the first pull-up transistor and the second pull-up transistor, and the other side is connected to the gate electrode of the gallium nitride device, and a pull-down transistor may be connected to the gate electrode of the gallium nitride device.

[0017] A bootstrap circuit for supplying power to the first inverting logic circuit or the second inverting logic circuit may be integrated on a chip on a semiconductor die on which the first inverting logic circuit and the second inverting logic circuit are placed.

[0018] The bootstrap circuit described above includes a first diode that receives a first driving voltage on one side and is connected to a first capacitor on the other side, and a transistor whose gate is connected to the other side of the first diode, whose drain is connected to the first driving voltage, and whose source is connected to a second capacitor, and the voltage of the second capacitor can be supplied as a power source to the first inverting logic circuit or the second inverting logic circuit.

[0019] The first inverting logic circuit and the second inverting logic circuit are each composed of a logic unit cell, and the logic unit cell includes a first transistor and a second transistor that function as a pull-up transistor and a pull-down transistor, respectively, between a driving high voltage and a driving low voltage, a third transistor that operates as a bootstrap diode, a bootstrap capacitor with one side connected to the contact node of the first transistor and the second transistor where the output is formed and charged to a voltage close to the driving high voltage by the bootstrap diode, and a fourth transistor that supplies electrical energy from the bootstrap capacitor to the gate of the first transistor to operate the first transistor at high speed when the output is pulled up, and an input signal can be supplied to the gate of the second transistor, and an inverted signal of the input signal can be supplied to the gate of the fourth transistor.

[0020] The above logic unit cell further includes a fifth transistor that connects the gate of the first transistor to the driving low voltage, and the input signal can be supplied to the gate of the fifth transistor.

[0021] A sixth transistor and a resistor are arranged in series between the third transistor and the fifth transistor, and the fourth transistor can be connected in parallel to the resistor.

[0022] The first to fifth transistors may be composed of enhancement mode gallium nitride devices, and the sixth transistor may be composed of depletion mode gallium nitride devices.

[0023] The on-resistance of the second transistor may be 1 / 4 the level of the first transistor.

[0024] Another embodiment provides a gallium nitride monolithic integrated circuit device, wherein a gate driver for driving the gate of a gallium nitride device is integrated on the same semiconductor die, and the gate driver includes a first pull-up circuit that raises the gate voltage of the gallium nitride device to a Miller plateau region when a gate signal is applied, and a second pull-up circuit that raises the gate voltage at high speed after the Miller plateau region, and the gallium nitride device is composed of a High Electron Mobility Transistor (HEMT).

[0025] The first pull-up circuit includes a first inverting logic circuit that inverts the inverted gate signal again and outputs it, and a first pull-up transistor that raises the gate voltage to a Miller Plato section according to the output signal of the first inverting logic circuit, and the second pull-up circuit includes a second inverting logic circuit that inverts the inverted gate signal again and outputs it, and a second pull-up transistor that raises the gate voltage at high speed according to the output signal of the second inverting logic circuit, and the inverted gate signal can be transmitted with a delay to the second inverting logic circuit.

[0026] The gate driver includes a bootstrap circuit for supplying power to the first inverting logic circuit or the second inverting logic circuit, and the bootstrap circuit may be integrated on a semiconductor die on which the first inverting logic circuit and the second inverting logic circuit are disposed.

[0027] The first inverting logic circuit and the second inverting logic circuit are each composed of a logic unit cell, and the logic unit cell includes a first transistor and a second transistor that function as a pull-up transistor and a pull-down transistor, respectively, between a driving high voltage and a driving low voltage, a third transistor that operates as a bootstrap diode, a bootstrap capacitor with one side connected to the contact node of the first transistor and the second transistor where the output is formed and charged to a voltage close to the driving high voltage by the bootstrap diode, and a fourth transistor that supplies electrical energy from the bootstrap capacitor to the gate of the first transistor to operate the first transistor at high speed when the output is pulled up, and an input signal can be supplied to the gate of the second transistor, and an inverted signal of the input signal can be supplied to the gate of the fourth transistor.

[0028] As described above, according to the present embodiment, switching stability can be improved through a gate driving method with a two-stage pull-up structure suitable for the fast switching characteristics of a Gallium Nitride (GaN) device. Furthermore, according to the present embodiment, by configuring an on-chip bootstrap circuit inside the gate driver, the complexity of the external power supply circuit can be reduced, and the gate driving voltage can be generated internally. Additionally, according to the present embodiment, by monolithically integrating the gate driver and the Gallium Nitride power device on the same semiconductor die, wiring inductance and parasitic resistance are reduced, and an integrated circuit device capable of high-speed and high-efficiency operation can be realized.

[0029] FIG. 1 is a circuit diagram of a power converter to which a gallium nitride monolithic integrated circuit device according to one embodiment can be applied.

[0030] FIG. 2 is a configuration diagram of a first gallium nitride monolithic integrated circuit device according to one embodiment.

[0031] FIG. 3 is a diagram showing the configuration of a first pull-up circuit according to one embodiment.

[0032] FIG. 4 is a configuration diagram of a second pull-up circuit according to one embodiment.

[0033] FIG. 5 is a waveform diagram of the output voltage and output current of a gate driver according to one embodiment.

[0034] FIG. 6 is a configuration diagram of a bootstrap circuit according to one embodiment.

[0035] FIG. 7 is a configuration diagram of a logic unit cell according to one embodiment.

[0036] FIG. 8 is a diagram showing the configuration of an inverter chain according to one embodiment.

[0037] Hereinafter, some embodiments of the present invention will be described in detail with reference to the exemplary drawings. It should be noted that in assigning reference numerals to the components of each drawing, the same components are given the same reference numeral whenever possible, even if they are shown in different drawings. Furthermore, in describing the present invention, if it is determined that a detailed description of related known components or functions could obscure the essence of the invention, such detailed description is omitted.

[0038] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used when describing the components of the present invention. These terms are intended only to distinguish the components from other components, and the essence, order, or sequence of the components is not limited by the terms. Where it is stated that a component is "connected," "combined," or "connected" to another component, it should be understood that the component may be directly connected or connected to the other component, but that another component may also be "connected," "combined," or "connected" between each component.

[0039] FIG. 1 is a circuit diagram of a power converter to which a gallium nitride monolithic integrated circuit device according to one embodiment can be applied.

[0040] Referring to FIG. 1, the power converter (10) may include a plurality of GaN elements (110a, 112b), a gate driver (120a, 120b), an inductor (L), etc.

[0041] A plurality of GaN devices (110a, 110b) and gate drivers (120a, 120b) can be embedded within a single semiconductor package to form a single gallium nitride monolithic integrated circuit device (100).

[0042] Alternatively, a first GaN device (110a) and a first gate driver (120a) may form a first gallium nitride monolithic integrated circuit device (130a), and a second GaN device (110b) and a second gate driver (120b) may form a second gallium nitride monolithic integrated circuit device (130b). In this case, an inductor (L) may be placed outside the semiconductor package and electrically connected to a plurality of GaN devices (110a, 110b) through the terminals of the semiconductor package.

[0043] Alternatively, only multiple GaN devices (110a, 110b) may be embedded within the semiconductor package, and the gate driver (120a, 120b) may be embedded in a separate semiconductor package and electrically connected to the multiple GaN devices (110a, 110b) through a terminal.

[0044] Each GaN device (110a, 110b) can be individually packaged, and according to the embodiment, a plurality of GaN devices (110a, 110b) can be packaged together as a monolithic dual GaN device.

[0045] A plurality of GaN devices (110a, 110b) can form a half-bridge circuit. In the half-bridge circuit, the first GaN device (110a) may be placed on the low side and the second GaN device (110b) may be placed on the high side.

[0046] In a half-bridge circuit, a ground voltage is supplied to the first source electrode (S1) of the first GaN device (110a), and a gate voltage (Vg1) output from the first gate driver (120a) can be supplied to the first gate electrode (G1) of the first GaN device (110a). A power supply voltage (VI) is supplied to the second drain electrode (D2) of the second GaN device (110b), and a different gate voltage (Vg2) output from the second gate driver (120b) can be supplied to the second gate electrode (G2) of the second GaN device (110b). Additionally, the first drain electrode (D1) of the first GaN device (110a) and the second source electrode (S2) of the second GaN device (110b) are electrically connected, and a switching node (Nsw) can be formed at this connection point.

[0047] One side of the inductor (L) is connected to the switching node (Nsw), and an output voltage (VO) can be formed on the other side.

[0048] The turn-on time intervals of each GaN device (110a, 110b) can be controlled so as not to overlap with each other. For example, the second GaN device (110b) may be turned off during the time interval when the first GaN device (110a) is turned on, and the first GaN device (110a) may be turned off during the time interval when the second GaN device (110b) is turned on.

[0049] The second gate driver may have the same circuit configuration as the first gate driver. Additionally, the second gallium nitride monolithic integrated circuit device (130b) may be configured in the same form as the first gallium nitride monolithic integrated circuit device (130a). Depending on whether the ground voltage is connected to the source electrode or the switching node (Nsw) is connected, the gallium nitride monolithic integrated circuit device may operate as the first gallium nitride monolithic integrated circuit device (130a) or as the second gallium nitride monolithic integrated circuit device (130b). For convenience of explanation, the following description focuses on the first gallium nitride monolithic integrated circuit device (130a) and the first gate driver (120a), but this content may also apply to the second gallium nitride monolithic integrated circuit device (130b) and the second gate driver (120b).

[0050] FIG. 2 is a configuration diagram of a first gallium nitride monolithic integrated circuit device according to one embodiment.

[0051] Referring to FIG. 2, the first gallium nitride monolithic integrated circuit device (130a) may include a first GaN device (110a) and a first gate driver (120a), etc. The first gate driver (120a) may include a first pull-up circuit (210), a second pull-up circuit (220), a bootstrap circuit (230), etc.

[0052] The first GaN device (110a) can be implemented as a High Electron Mobility Transistor (HEMT).

[0053] HEMT is generally composed of a buffer layer, a gallium nitride (GaN) channel layer, and an aluminum gallium nitride (AlGaN) barrier layer grown epitaxially on a silicon substrate.

[0054] At this time, the two-dimensional electron gas (2DEG) formed in the AlGaN / GaN heterojunction structure provides high electron mobility and low on-resistance, so a higher current density can be achieved in the same chip area.

[0055] In addition, the wide bandgap (approx. 3.4 eV) of GaN provides a high breakdown field (approx. 3 MV / cm), so the drain-source voltage drop of the device is small and leakage current does not occur even at high voltages.

[0056] Due to these characteristics, HEMTs can minimize power loss even at high switching frequencies, and as a result, significantly improve the power conversion efficiency and power density of the system.

[0057] Other transistors included in the first gallium nitride monolithic integrated circuit device (130a)—e.g., pull-down transistor (Qdn), etc.—can be implemented as N-channel gallium nitride devices.

[0058] These N-channel GaN transistors also share the same GaN-based epitaxial structure as HEMTs, and since the electron transport channels are formed within the same semiconductor layer, it is easy to match the electrical characteristics of each other.

[0059] In other words, HEMTs and N-channel transistors can be integrated together (monolithic integration) on the same GaN semiconductor die, which is realized by forming different gate structures on a common buffer layer and channel layer.

[0060] For example, HEMTs operate as power switching devices using insulated gates or Schottky gates, and N-channel devices can be utilized as transistors for logic circuits or driver circuits by adjusting the gate structure and device area.

[0061] Such an integrated structure has no separate process compatibility issues, and since different components are formed within the same crystal structure, parasitic inductance and resistance can be minimized.

[0062] The first pull-up circuit (210) can raise the gate voltage of the first GaN device (110a) to the Miller Platheau region when a gate signal (PWMa) is applied.

[0063] The Miller Plato region refers to the area where the rise in gate voltage temporarily plateaus due to the interaction between the gate-drain capacitance (Cgd) and the gate-source capacitance (Cgs) of a transistor.

[0064] In this region, the current applied to the gate is mainly used to lower the drain voltage, so the gate voltage remains constant and the drain-source voltage changes rapidly. The Miller Plato region can be described as a region where the drain current increases rapidly and the drain voltage decreases during the transition of the switching device from the off state to the on state.

[0065] At this time, if the gate voltage rises unstably or an excessive gate current is applied, phenomena such as switching overshoot or ringing may occur, which may reduce the stability of the device. To mitigate this problem, the first pull-up circuit (210) controls the rate of rise of the gate voltage in the Miller Plateau region and supplies a constant current to control the gate voltage so that it passes through the Miller Plateau region stably.

[0066] The second pull-up circuit (220) can increase the gate voltage at high speed after rising to the Miller Plateau section.

[0067] In conventional structures where the gate voltage is supplied by a single pull-up circuit, it is difficult to rapidly control the rise rate of the gate voltage because the gate current supply path remains the same once the Miller Plateau region is passed. In this case, the gate voltage rises slowly even after the Miller Plateau, which limits the switching speed and increases switching losses.

[0068] Conversely, if an attempt is made to increase the rise rate by supplying an excessive gate current, the gate voltage becomes unstable in the Miller Plateau region, and overshoot or ringing phenomena may occur, potentially degrading the stability of the device.

[0069] In contrast, in the present structure in which the first pull-up circuit (210) and the second pull-up circuit (220) operate separately, the first pull-up circuit supplies a gentle current during the Miller Plateau section to stably control the gate voltage, and after the Miller Plateau, the second pull-up circuit additionally intervenes to instantaneously supply a high driving current, thereby rapidly increasing the gate voltage.

[0070] By separating the gate current supply into two stages, stability is ensured during the Miller Plato region, while switching speed can be maximized in the subsequent region. Consequently, compared to conventional structures using only a single pull-up circuit, the two-stage pull-up structure reduces switching losses and improves both gate driving stability and response speed.

[0071] The bootstrap circuit (230) is integrated on-chip on the same semiconductor die as the first pull-up circuit (210) and the second pull-up circuit (220), and can stably supply a driving voltage to the first pull-up circuit (210) and / or the second pull-up circuit (220).

[0072] An inverting logic circuit (INV3) may be placed in front of the input node (Ni). Considering the relationship with the terms used in the following description, this inverting logic circuit (INV3) will be referred to as the third inverting logic circuit below.

[0073] The gate signal (PWMa) is input to the third inverting logic circuit (INV3), then inverted and transmitted to the input node (Ni).

[0074] The first pull-up circuit (210) can operate according to the inverted gate signal (PWMb) formed at the input node (Ni) and pull up the gate voltage (Vg) formed at the gate node (Ng) to the first driving voltage (Vcc1). A pull-down transistor (Qdn) may be connected to the gate node (Ng), and the pull-down transistor (Qdn) can pull down the gate voltage (Vg) to a driving low voltage—e.g., ground voltage—according to the inverted gate signal (PWMb).

[0075] The second pull-up circuit (220) can also operate according to the inverted gate signal (PWMb) formed at the input node (Ni) and pull up the gate voltage (Vg) formed at the gate node (Ng) to the first driving voltage (Vcc1). However, unlike the first pull-up circuit (210), the second pull-up circuit (220) operates according to the delayed inverted gate signal (PWMb), so the operation of pulling up the gate voltage (Vg) may be performed later than that of the first pull-up circuit (210).

[0076] The first pull-up circuit (210) can drive the internal circuit by receiving the second driving voltage (Vcc2), and the second pull-up circuit (220) can drive the internal circuit by receiving the third driving voltage (Vcc3). At this time, the second driving voltage (Vcc2) and / or the third driving voltage (Vcc3) can be supplied by the bootstrap circuit (230). The bootstrap circuit (230) can generate the second driving voltage (Vcc2) and / or the third driving voltage (Vcc3) by receiving the first driving voltage (Vcc1). Here, the second driving voltage (Vcc2) and the third driving voltage (Vcc3) may be the same voltage.

[0077] FIG. 3 is a diagram showing the configuration of a first pull-up circuit according to one embodiment.

[0078] Referring to FIG. 3, the first pull-up circuit (210) may include a first inverting logic circuit (INV1) and a first pull-up transistor (Qu1).

[0079] An inverted gate signal (PWMb) is supplied as an input to the first inverting logic circuit (INV1), and the output of the first inverting logic circuit (INV1) can be transmitted to the gate of the first pull-up transistor (Qu1). Additionally, a second driving voltage (Vcc2) can be supplied as the driving voltage of the first inverting logic circuit (INV1).

[0080] The output of the first inverting logic circuit (INV1) can be connected to the gate of the first pull-up transistor (Qu1), the first driving voltage (Vcc1) can be connected to the drain, and the gate node (Ng) can be connected to the source. The gate electrode of the first GaN device (110a) can be connected to the gate node (Ng), and the pull-down transistor (Qdn) can be connected.

[0081] The first inverting logic circuit (INV1) can re-invert the inverted gate signal (PWMb) and output it to the gate of the first pull-up transistor (Qu1). Then, the first pull-up transistor (Qu1) can raise the gate voltage of the first GaN device (110a) to the Miller Plato region according to the output signal of the first inverting logic circuit (INV1).

[0082] FIG. 4 is a configuration diagram of a second pull-up circuit according to one embodiment.

[0083] Referring to FIG. 4, the second pull-up circuit (220) may include a second inverting logic circuit (INV2), a second pull-up transistor (Qu2), and a delay circuit (410), etc.

[0084] An inverted gate signal (PWMb) is supplied as an input to the second inverting logic circuit (INV2), and the output of the second inverting logic circuit (INV2) can be transmitted to the gate of the second pull-up transistor (Qu2). Additionally, a third driving voltage (Vcc3) can be supplied as the driving voltage of the second inverting logic circuit (INV2).

[0085] The output of the second inverting logic circuit (INV2) can be connected to the gate of the second pull-up transistor (Qu2), the first driving voltage (Vcc1) can be connected to the drain, and the gate node (Ng) can be connected to the source. The gate electrode of the first GaN device (110a) can be connected to the gate node (Ng), and the pull-down transistor (Qdn) can be connected.

[0086] Meanwhile, the inverted gate signal (PWMb) can be transmitted to the second inverting logic circuit (INV2) with a delay. A delay circuit (410) may be placed in front of the second inverting logic circuit (INV2), and the delay circuit (410) can delay the inverted gate signal (PWMb) for a certain period of time and transmit it to the second inverting logic circuit (INV2).

[0087] Due to this signal delay, the second pull-up circuit (220) can pull up the gate voltage of the first GaN device (110a) a certain time later than the first pull-up circuit.

[0088] FIG. 5 is a waveform diagram of the output voltage and output current of a gate driver according to one embodiment.

[0089] Referring to FIGS. 3, 4 and 5, first, the first pull-up circuit (210) can supply a gate current (I_CHG) to the gate electrode of the gallium nitride device from the first time point (T1) according to the inverted gate signal (PWMb).

[0090] And, depending on the gate current (I_CHG) supplied by the first pull-up circuit (210), the gate voltage (Vg) can rise steadily and then enter the Miller Plateau section.

[0091] Since the first pull-up circuit (210) is not designed to supply excessive gate current to quickly pass through the Miller Plateau section, it can stably form the gate voltage (Vg) without causing overshooting or ringing (510) like other conventional gate drivers.

[0092] Meanwhile, the second pull-up circuit (220) can be designed to create a time delay of the signal for the time (T2-T1) during which the first pull-up circuit (210) raises the gate voltage (Vg) of the gallium nitride device to the Miller Plato interval.

[0093] Accordingly, the second pull-up circuit (220) additionally supplies gate current (I_CHG) from the second time point (T2), and accordingly, the gate voltage (Vg) can be increased at high speed.

[0094] FIG. 6 is a configuration diagram of a bootstrap circuit according to one embodiment.

[0095] Referring to FIG. 6, the bootstrap circuit (230) may include a first diode (D1), a first capacitor (C1), a second capacitor (C2), and a transistor (Qvcc), etc. This bootstrap circuit (230) supplies power to a first inverting logic circuit or a second inverting logic circuit and may be integrated on a semiconductor die on which the first inverting logic circuit and the second inverting logic circuit are placed.

[0096] A first driving voltage (Vcc1) is supplied to the anode of the first diode (D1), and the cathode can be connected to the first capacitor (C1). One side of the first capacitor (C1) is connected to an input node (Ni) to which an inverted gate signal is supplied, and the other side can be connected to the gate of a transistor (Qvcc). When the input node (Ni) is at a low voltage, the first capacitor (C1) is charged through the first diode (D1), and the voltage of the first capacitor (C1) can be raised to a voltage level similar to the first driving voltage (Vcc1).

[0097] A first driving voltage (Vcc1) may be connected to the drain of a transistor (Qvcc), and a second capacitor (C2) may be connected to the source. One side of the second capacitor (C2) may be connected to the transistor (Qvcc), and the other side may be connected to the gate node (Ng). When the pull-down transistor (Qdn) is turned on and the gate node (Ng) has a driving low voltage, the transistor (Qvcc) may be turned on to charge the second capacitor (C2), and the voltage (Vcc3) of the second capacitor (C2) may have a voltage level equal to or close to the first driving voltage (Vcc1).

[0098] The voltage (Vcc3) of this second capacitor (C2) can be provided as the driving voltage of the first inverting logic circuit and / or the second inverting logic circuit.

[0099] Meanwhile, a gate driver according to one embodiment may use a logic unit cell as a basic unit cell to realize low-power high-speed switching operation.

[0100] FIG. 7 is a configuration diagram of a logic unit cell according to one embodiment.

[0101] Referring to FIG. 7, the logic unit cell (700) may include six transistors (Qa, Qb, Qc, Qd, Qe, Qf), one capacitor (Ca), and one resistor (Ra).

[0102] The logic unit cell (700) is a circuit that inverts and outputs an input signal (Ain), and can be applied to the first inverting logic circuit and the second inverting logic circuit, and can also be applied to the third inverting logic circuit according to the embodiment.

[0103] The logic unit cell (700) may include a first transistor (Qa) and a second transistor (Qb) that function as a pull-up transistor and a pull-down transistor, respectively, between a driving high voltage (Vcc) and a driving low voltage—e.g., ground voltage. And, when the first transistor (Qa) is turned on, the driving high voltage is output as an output signal (Yout) through the output node (Na), and when the second transistor (Qb) is turned on, the driving low voltage is output as an output signal (Yout).

[0104] The logic unit cell (700) may include a third transistor (Qc) that operates as a bootstrap diode.

[0105] Additionally, the logic unit cell (700) may include a bootstrap capacitor (Ca) with one end connected to an output node (Na) corresponding to the junction of the first transistor (Qa) and the second transistor (Qb), and the other end connected to a third transistor (Qc). The bootstrap capacitor (Ca) can be charged to a voltage close to the driving high voltage (Vcc) when the output node (Na) corresponds to the driving low voltage. When the output signal (Yout) is pulled up, the voltage of the bootstrap capacitor (Ca) charged in this way boosts the gate voltage of the first transistor (Qa), which is a pull-up transistor, thereby rapidly raising the output signal (Yout) and consequently causing the logic unit cell (700) to operate at high speed.

[0106] The logic unit cell (700) may include a fourth transistor (Qd) that, when the output is pulled up, supplies electrical energy from a bootstrap capacitor (Ca) to the gate of a first transistor (Qa) to operate the first transistor (Qa) at high speed. The drain of the fourth transistor (Qd) may be connected to the bootstrap capacitor (Ca), and the source may be connected to the gate of the first transistor (Qa). Additionally, an inverted signal (Bin) having a signal level complementary to the input signal (Ain) may be supplied to the gate of the fourth transistor (Qd).

[0107] A fifth transistor (Qe) for lowering the voltage level of the gate of the first transistor (Qa) to a driving low voltage can be placed between the gate of the first transistor (Qa) and the driving low voltage.

[0108] The input signal (Ain) is supplied to the gate of the second transistor (Qb) and the gate of the fifth transistor (Qe), and when the signal level of the input signal (Ain) is high voltage, the fifth transistor (Qe) is turned on to turn off the first transistor (Qa) and the second transistor (Qb) is turned on to make the signal level of the output signal (Yout) low voltage.

[0109] A sixth transistor (Qf) and a resistor (Ra) connected in series between the third transistor (Qc) and the fifth transistor (Qe) may be placed. The resistor (Ra) can reduce power consumption when the input signal (Ain) is high voltage and the inverting signal (Bin) is low voltage, and also has the effect of rapidly lowering the gate voltage of the first transistor (Qa) when the input signal (Ain) is high voltage.

[0110] The fourth transistor (Qd), connected in parallel to the first resistor (Ra), reduces the resistance between the sixth transistor (Qf) and the fifth transistor (Qe) during the initial switching phase when the input signal (Ain) is low voltage and the inversion signal (Bin) is high voltage, thereby supporting a rapid gate voltage rise of the first transistor (Qa).

[0111] The first transistor (Qa) to the fifth transistor (Qe) may be composed of enhancement mode gallium nitride devices, and the sixth transistor (Qf) may be composed of depletion mode gallium nitride devices.

[0112] In addition, considering the balance of pull-up and pull-down, the on-resistance of the second transistor (Qb) can be designed to be small, at 1 / 4 the level of the first transistor (Qa).

[0113] By applying these logic unit cells, the inverting logic circuit can be operated at a high speed while reducing power consumption.

[0114] Multiple logic unit cells can be connected in a chain structure to form an inverter chain, and such inverter chains can be used as inverting logic circuits.

[0115] FIG. 8 is a diagram showing the configuration of an inverter chain according to one embodiment.

[0116] Referring to FIG. 8, the inverter chain (800) may include three logic unit cells (810, 820, 830).

[0117] An input signal (Ain) can be supplied to the first logic unit cell (810). The input signal (Ain) can also be supplied to the inverted signal terminal of the second logic unit cell (820). Additionally, the output signal of the first logic unit cell (810) can be supplied to the input signal terminal of the second logic unit cell (820).

[0118] And, the output signal of the first logic unit cell (810) can be supplied to the inverted signal terminal of the third logic unit cell (830). And, the output signal of the second logic unit cell (820) can be supplied to the input signal terminal of the third logic unit cell (830).

[0119] And, the output signal of the third logic unit cell (830) can become the final output signal (Yout).

[0120] By using an inverter chain composed of logic unit cells that operate at high speed while reducing current consumption to form the internal circuitry of gate drivers, an optimized logic system can be implemented.

[0121] As described above, according to the present embodiment, switching stability can be improved through a gate driving method with a two-stage pull-up structure suitable for the fast switching characteristics of a Gallium Nitride (GaN) device. Furthermore, according to the present embodiment, by configuring an on-chip bootstrap circuit inside the gate driver, the complexity of the external power supply circuit can be reduced, and the gate driving voltage can be generated internally. Additionally, according to the present embodiment, by monolithically integrating the gate driver and the Gallium Nitride power device on the same semiconductor die, wiring inductance and parasitic resistance are reduced, and an integrated circuit device capable of high-speed and high-efficiency operation can be realized.

[0122] Terms such as "include," "compose," or "have" as described above, unless specifically stated otherwise, mean that the relevant component may be inherent; therefore, they should be interpreted as allowing for the inclusion of additional components rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Commonly used terms, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0123] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

Claims

1. A gate driver for driving a gallium nitride device, A first pull-up circuit that raises the gate voltage of the gallium nitride device to a Miller plateau region when a gate signal is applied; and A second pull-up circuit that rapidly increases the gate voltage after rising to the Miller Plato section. A gate driver including 2. In Paragraph 1, The first pull-up circuit includes a first inverting logic circuit that outputs an inverted gate signal by re-inverting it, and a first pull-up transistor that raises the gate voltage of the gallium nitride device to a Miller Plato section according to the output signal of the first inverting logic circuit. The second pull-up circuit includes a second inverting logic circuit that inverts the inverted gate signal again and outputs it, and a second pull-up transistor that rapidly increases the gate voltage according to the output signal of the second inverting logic circuit. A gate driver in which the inverted gate signal is transmitted with a delay to the second inverting logic circuit above.

3. In Paragraph 2, The first pull-up transistor and the second pull-up transistor are implemented as N-channel gallium nitride devices, and The above gallium nitride device is a gate driver implemented as a High Electron Mobility Transistor (HEMT).

4. In Paragraph 2, A first driving voltage is supplied to one side of the first pull-up transistor and the second pull-up transistor, and the other side is connected to the gate electrode of the gallium nitride device. A gate driver in which a pull-down transistor is connected to the gate electrode of the above gallium nitride element.

5. In Paragraph 2, A gate driver in which a bootstrap circuit for supplying power to the first inverting logic circuit or the second inverting logic circuit is integrated on-chip on a semiconductor die on which the first inverting logic circuit and the second inverting logic circuit are disposed.

6. In Paragraph 5, The above bootstrap circuit is, A gate driver comprising a first diode that receives a first driving voltage on one side and is connected to a first capacitor on the other side, and a transistor whose gate is connected to the other side of the first diode, whose drain is connected to the first driving voltage, and whose source is connected to a second capacitor, wherein the voltage of the second capacitor is supplied as a power source to the first inverting logic circuit or the second inverting logic circuit.

7. In Paragraph 2, The first inverting logic circuit and the second inverting logic circuit are each composed of a logic unit cell, and The above logic unit cell is, A first transistor and a second transistor that function as a pull-up transistor and a pull-down transistor, respectively, between a driving high voltage and a driving low voltage, A third transistor operating as a bootstrap diode, A bootstrap capacitor, one end of which is connected to the contact node of the first transistor and the second transistor where the output is formed, and which is charged to a voltage close to the driving high voltage by the bootstrap diode, and It includes a fourth transistor that supplies electrical energy of the bootstrap capacitor to the gate of the first transistor when the above output is pulled up, thereby operating the first transistor at high speed. A gate driver in which an input signal is supplied to the gate of the second transistor and an inverted signal of the input signal is supplied to the gate of the fourth transistor.

8. In Paragraph 7, The above logic unit cell further includes a fifth transistor that connects the gate of the first transistor to the driving low voltage, and A gate driver in which the input signal is supplied to the gate of the fifth transistor.

9. In Paragraph 8, A gate driver having a sixth transistor and a resistor connected in series between the third transistor and the fifth transistor, and the fourth transistor connected in parallel to the resistor.

10. In Paragraph 9, A gate driver in which the first to fifth transistors are composed of enhancement mode gallium nitride devices and the sixth transistor is composed of depletion mode gallium nitride devices.

11. In Paragraph 7, A gate driver in which the on-resistance of the second transistor is 1 / 4 the level of the first transistor.

12. In a gallium nitride monolithic integrated circuit device, A gate driver for driving the gate of a gallium nitride device is integrated on the same semiconductor die, and The gate driver comprises a first pull-up circuit that raises the gate voltage of the gallium nitride device to a Miller plateau region when a gate signal is applied, and It includes a second pull-up circuit that rapidly increases the gate voltage after the Miller Plato section, and The above gallium nitride device is composed of a High Electron Mobility Transistor (HEMT). Gallium nitride monolithic integrated circuit device.

13. In Paragraph 12, The first pull-up circuit includes a first inverting logic circuit that outputs an inverted gate signal by re-inverting it, and a first pull-up transistor that raises the gate voltage to a Miller Plato section according to the output signal of the first inverting logic circuit. The second pull-up circuit includes a second inverting logic circuit that inverts the inverted gate signal again and outputs it, and a second pull-up transistor that rapidly increases the gate voltage according to the output signal of the second inverting logic circuit. A gallium nitride monolithic integrated circuit device in which the inverted gate signal is delayed and transmitted to the second inverting logic circuit.

14. In Paragraph 12, The gate driver includes a bootstrap circuit for supplying power to the first inverting logic circuit or the second inverting logic circuit, and The above bootstrap circuit is a gallium nitride monolithic integrated circuit device that is integrated on-chip on a semiconductor die on which the first inverting logic circuit and the second inverting logic circuit are disposed.

15. In Paragraph 12, The first inverting logic circuit and the second inverting logic circuit are each composed of a logic unit cell, and The above logic unit cell is, A first transistor and a second transistor that function as a pull-up transistor and a pull-down transistor, respectively, between a driving high voltage and a driving low voltage, A third transistor operating as a bootstrap diode, A bootstrap capacitor, one end of which is connected to the contact node of the first transistor and the second transistor where the output is formed, and which is charged to a voltage close to the driving high voltage by the bootstrap diode, and It includes a fourth transistor that supplies electrical energy of the bootstrap capacitor to the gate of the first transistor when the above output is pulled up, thereby operating the first transistor at high speed. A gallium nitride monolithic integrated circuit device in which an input signal is supplied to the gate of the second transistor and an inverted signal of the input signal is supplied to the gate of the fourth transistor.

Images