Non-volatile tunable capacitive processing unit

Abstract

In a method for forming a non-volatile tunable capacitor device, a first electrode layer is formed facing distally from a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection. A dielectric layer is positioned between the first electrode layer and an adjacent second electrode layer. A phase change material (PCM) layer is positioned between the first electrode layer and the second electrode layer adjacent the dielectric layer. An activation component is provided for heating the PCM layer to change a phase of the PCM layer. The activation component may include a heating element or an electrical probe in direct contact with the PCM layer and is configured to apply heat to the PCM layer when activated. The phase of the PCM layer is changeable between an amorphous phase and a crystalline phase.

Description

[Technical Field]

[0001] This application relates to capacitive processing devices and methods of forming capacitive processing devices. More particularly, this application relates to non-volatile tunable capacitive processing unit (CPU) devices and their application in artificial intelligence (AI) hardware. [Background technology]

[0002] Resistive processing units (RPUs) are used in deep neural network (DNN) processing to accelerate the training and inference of machine learning models. RPU elements can be implemented using phase-change materials in the form of resistors, because the resistance of these materials can be tuned and maintains its tuned resistance even when not connected to a power source (non-volatile memory function).

[0003] A common operation in digital signal processing circuits is the multiply-accumulate (MAC), which is performed by a MAC unit that calculates the product of two numbers and adds the product to an accumulator. A MAC unit includes a multiplier implemented in combinational logic, followed by an adder, and an accumulator register that stores the result. As an example, the implementation of a finite impulse response (FIR) filter primarily consists of a MAC operation in which input samples to the filter are multiplied by the filter coefficients and the products are summed. The implementation of a DNN also requires the use of many MAC operations. More specifically, the implementation of each layer of a DNN requires the multiplication of each input (e.g., from the previous layer) by a weight and then the summing of all products. While DNNs can be implemented using digital processors, they can also be realized using analog circuits. Analog implementations of DNNs use tunable resistors (e.g., RPUs) and Ohm's law to calculate the product, followed by Kirchhoff's laws to perform the summation of the products. Tunable resistors are typically implemented using phase change materials (PCMs), which can have high conductance when the PCM is in the crystalline phase and low conductance when the PCM is in the amorphous phase. It is possible to tune the PCM element to intermediate conductance levels between the extremes of the conductance range. When a voltage is applied to the PCM element, the current through the PCM element is the conductance (G) times the voltage (V), or I = V x G. In the case of a DNN, the voltage V k represents the input and the conductance G j represents the synaptic weight. k is the sum of all weights G j where j = (1 to N), and all currents are summed using Kirchhoff's law. Hence, the MAC operation was implemented in analog form.

[0004] One drawback of the analog implementation of the MAC operation described above is that each product calculation requires I 2 / G (i.e., current squared times resistance). When DNNs are large, power consumption can be substantial, and furthermore, when DNNs are part of battery-powered devices, reducing power consumption is important. Therefore, more power-efficient memory-based processing units are needed.

[0005] Therefore, there is a need in the art to address the aforementioned problems. Summary of the Invention

[0006] Viewed from a first aspect, the present invention provides a method of forming a nonvolatile tunable capacitor device, the method comprising: forming a first electrode layer distally opposite a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection; positioning a dielectric layer between the first and second electrode layers; positioning a phase change material (PCM) layer between the first electrode layer and the second electrode layer adjacent the dielectric layer; and providing an energizing component that heats the PCM layer to change a phase of the PCM layer.

[0007] Viewed from a further aspect, the present invention provides a non-volatile tunable capacitor device comprising: an outer cylindrical electrode layer having a first diameter; an inner cylindrical electrode layer axially proximal to the outer cylindrical electrode layer, the inner cylindrical electrode layer having a second diameter that is less than the first diameter; a dielectric layer disposed between the outer cylindrical electrode and the inner cylindrical electrode and over an entire surface of the outer cylindrical electrode facing the inner cylindrical electrode; a phase change material (PCM) layer disposed between the inner cylindrical electrode and the dielectric layer and over an entire surface of the inner cylindrical electrode facing the dielectric layer; and a heating element layer disposed between the outer cylindrical electrode and the inner cylindrical electrode.

[0008] Viewed from a further aspect, the present invention provides a method of performing a multiply-accumulate (MAC) operation for a neural network (NN), the method comprising: providing one or more circuit configurations including a tunable capacitor device of the present invention; a charge transistor including a first charge transistor terminal connected to a voltage line and a second charge transistor terminal connected to the first capacitor terminal of the tunable capacitor, the tunable capacitor including a second capacitor terminal connected to a ground terminal; and a discharge transistor including a first discharge terminal connected to the second charge transistor terminal and the first capacitor terminal and a second discharge terminal connected to a current line; and applying a predetermined amount of heat to the tunable capacitor for a predetermined amount of time, the tunable capacitor having a first capacitance value, the predetermined amount of heat being sufficient to change the first capacitance value to a second capacitance value.

[0009] Viewed from a further aspect, the present invention provides a method of performing a multiply-accumulate (MAC) operation for a neural network (NN), the method comprising: providing one or more circuit configurations including a charge transistor having a first charge transistor terminal connected to a voltage line and a second charge transistor terminal connected to a first capacitor terminal of a tunable capacitor, the tunable capacitor having a second capacitor terminal connected to a ground terminal; and a discharge transistor having a first discharge terminal connected to the second charge transistor terminal and the first capacitor terminal and a second discharge terminal connected to a current line; and applying a predetermined amount of heat to the tunable capacitor for a predetermined amount of time, the tunable capacitor having a first capacitance value, the predetermined amount of heat being sufficient to change the first capacitance value to a second capacitance value.

[0010] A non-volatile tunable capacitive processing unit (CPU) and a method for forming the non-volatile tunable capacitive processing unit are described.

[0011] A method of forming a nonvolatile tunable capacitor device may include forming a first electrode layer distally facing a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection. The method may further include positioning a dielectric layer adjacent to the first inner planar surface and between the first electrode layer adjacent to the second inner planar surface of the second electrode layer. The method may further include positioning a phase change material (PCM) layer between the first electrode layer and the second electrode layer adjacent to the dielectric layer. The method may further include providing an activating component that heats the PCM layer to change the phase of the PCM layer.

[0012] The first electrode layer may include a first inner planar surface distally facing from the second inner planar surface of the second electrode layer. The first electrode layer may include a first outer planar surface configured to make a first electrical connection, and the second electrode layer may include a second outer planar surface configured to make a second electrical connection.

[0013] The activation component may include a heating element coplanar with any one of the first electrode layer and the second electrode layer, the heating element configured to apply heat to the PCM layer when activated.

[0014] The activation component may include a resistive element in direct contact with the PCM layer and is configured to apply heat to the PCM layer when activated.

[0015] The phase of the PCM layer can be selectively changeable between an amorphous phase corresponding to a resistive PCM layer and a crystalline phase corresponding to a conductive PCM layer. The PCM layer can include a composition of Ge2Sb2Te5, GeTe, or Sb2Te3. The dielectric layer can include a composition of HfO2.

[0016] In another embodiment, a nonvolatile tunable capacitor device is described. The device can include an outer cylindrical electrode layer having a first diameter, an inner cylindrical electrode layer axially proximal to the outer cylindrical electrode layer, the inner cylindrical electrode layer having a second diameter less than the first diameter, a dielectric layer disposed between the outer cylindrical electrode and the inner cylindrical electrode and across opposing surfaces of the outer cylindrical electrode and the inner cylindrical electrode, a phase change material (PCM) layer disposed between the inner cylindrical electrode and the dielectric layer and across opposing surfaces of the inner cylindrical electrode and the dielectric layer, and a heating element layer disposed between the outer cylindrical electrode and the inner cylindrical electrode. The heating element layer can be configured to be activated to apply heat to the PCM layer.

[0017] The non-volatile tunable capacitor device may further include a resistive element in direct contact with the PCM layer, the resistive element being configured to apply heat to the PCM layer when activated.

[0018] The nonvolatile tunable capacitor device may further include a PCM layer having a phase configured to change from an amorphous phase corresponding to a resistive PCM layer to a crystalline phase corresponding to a conductive PCM layer based on a predetermined amount of heat applied to the PCM layer.

[0019] In another embodiment, a method for performing a multiply-accumulate (MAC) operation for a neural network (NN) includes providing one or more circuit configurations, where the one or more circuit configurations may include a charge transistor, a discharge transistor, and a tunable capacitor. In the embodiment, the charge transistor includes a first charge transistor terminal connected to a voltage line. The charge transistor further includes a second charge transistor terminal connected to a first capacitor terminal of the tunable capacitor, and the tunable capacitor includes a second capacitor terminal connected to a ground terminal. The one or more circuit configurations may further include a discharge transistor including a first discharge transistor terminal connected to the second charge transistor terminal and the first capacitor terminal. The discharge transistor further includes a second discharge terminal connected to a current line.

[0020] Additionally, a method of performing a MAC operation for a NN may include applying a predetermined amount of heat to a tunable capacitor for a predetermined amount of time, where the tunable capacitor has a first capacitance value, and where the predetermined amount of heat may be sufficient to change the first capacitance value to a second capacitance value.

[0021] A method of performing a MAC operation for a NN may include charging a tunable capacitor for a first predetermined amount of time by applying an input voltage to the tunable capacitor through a closed charge transistor and an open discharge transistor, and discharging the tunable capacitor for a second predetermined amount of time by stopping the input voltage to the tunable capacitor through the open charge transistor and the closed discharge transistor, wherein charge flows from the tunable capacitor through the discharge transistor to an integrator circuit.

[0022] In an embodiment, a method for performing a MAC operation for a neural network is configured to configure a tunable capacitor to a weight of the neural network, represented as a second capacitance value, to provide a predetermined amount of heat.

[0023] In an embodiment, the method of performing a MAC operation for a NN may further include determining a total charge of one or more circuit components including a tunable capacitor by integrating the charge of the one or more circuit components through the discharge transistor using an integrator circuit.

[0024] In an embodiment, a method for performing a MAC operation for a neural network is configured to configure a tunable capacitor to a weight of the neural network, represented as a second capacitance value, to provide a predetermined amount of heat.

[0025] In an embodiment, the phase of the PCM layer may be selectively changeable from an amorphous phase corresponding to a resistive PCM layer to a crystalline phase corresponding to a conductive PCM layer.

[0026] The present invention will now be described, by way of example only, with reference to preferred embodiments thereof, as illustrated in the following drawings: [Brief explanation of the drawings]

[0027] [Figure 1] 1A-1C are cross-sectional views of a tunable capacitor device of the present application during amorphous and crystalline stages of fabrication, according to example embodiments of the present invention. [Figure 2] 1A-1C are cross-sectional views of another tunable capacitor device of the present application during amorphous and crystalline stages of fabrication, in accordance with example embodiments of the present invention. [Figure 3] 10A-10C illustrate various views of another tunable capacitor device of the present application during a tuning phase, in accordance with an example embodiment of the present invention. [Figure 4]1A-1C are cross-sectional views of a cylindrical tunable capacitor device of the present application during amorphous and crystalline stages of fabrication, according to example embodiments of the present invention. [Figure 5] 1 illustrates a cross-sectional view of a cylindrical tunable capacitor device of the present application, according to an example embodiment of the present invention. [Figure 6] 1 is a cross-sectional view of a cylindrical capacitor device and a lumped circuit, also referred to as an equivalent circuit, of the device, according to an example embodiment of the present invention. [Figure 7] 1 is a cross-sectional view of a cylindrical capacitor device in an intermediate capacitance state and an equivalent circuit of the device, according to an example embodiment of the present invention. [Figure 8] FIG. 10 is a circuit array diagram of a neural network for charging a tunable capacitor device (Phase I), according to an example embodiment of the present invention. [Figure 9] 9 illustrates a second time phase of the circuit array diagram of FIG. 8 during discharging of the tunable capacitor device (Phase II), according to an example embodiment of the present invention. [Figure 10] 1 is a flowchart of a method for forming a tunable capacitor device, according to an example embodiment of the present invention. [Figure 11] FIG. 1 is a block diagram of components of a server computer that executes a method for forming a tunable capacitor device, according to an example embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0028] The present application will now be described in more detail by reference to the following description and the drawings that accompany this application. It should be noted that the drawings of the present application are provided for illustrative purposes only, and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0029] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present application. However, it will be understood by those skilled in the art that various embodiments of the present application may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present application.

[0030] When an element, such as a layer, region, or substrate, is referred to as being "on" or "above" another element, it is understood that it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements present. When an element is referred to as being "below" or "below" another element, it is also understood that it can be directly below or directly below the other element, or intermediate elements may also be present. In contrast, when an element is referred to as being "directly below" or "directly below" another element, there are no intervening elements present.

[0031] The embodiments described herein can be implemented and used in many applications to perform analog computations in artificial intelligence (AI) operations. For example, in performing a multiply-accumulate (MAC) operation, the product of two numbers is determined by multiplication, and then the products are added to output a sum. MAC operations can be used in neural networks (NNs). To speed up NN computations, MAC operations need to be performed in parallel. Furthermore, the computations need to be more energy efficient, which can enable large NNs involving millions of weight multiplications. Therefore, a solution is needed to accelerate MAC operations and perform them in a more efficient manner.

[0032] In neural networks, the circuit array architecture consists of input nodes (e.g., V1, V2, V3) configured to receive electrical or vector inputs to each node. n), where the electrical inputs may include weights (e.g., W1, W2, W3) stored in the neural network configured to be trained thereby. n ). For example, in performing a MAC operation in a neural network, tunable capacitor devices may be used in a first portion of the neural network to store weights corresponding to capacitance values ​​for each tunable capacitor device. When an input voltage (e.g., V1) is applied to a first tunable capacitor device (e.g., C1), the electronic charge on the tunable capacitor device is the product of the input voltage and the capacitance of the first tunable capacitor device (e.g., Q1). The tunable capacitor device C k Each of these has a voltage V k ×C k It holds a charge that is the product of

[0033] The power dissipation for any circuit element is I 2 where R is the current flowing through the element, I is the resistance of the element, and R is the resistance of the element. Therefore, an ideal capacitor does not dissipate power when it is charged or discharged. However, there are small parasitic resistances, such as the lead resistance of interconnects in a circuit, which will result in some power dissipation.

[0034] FIG. 1 is a cross-sectional view of a tunable capacitor device 100 of the present application in an amorphous state (110) and a crystalline state (120), according to an example embodiment of the present invention.

[0035] 1 is an example of a plate capacitor including a first electrode layer 112 distally facing a second electrode layer 118, where the first electrode layer 112 is configured to make a first electrical connection (e.g., via a first terminal 111a) and the second electrode layer 118 is configured to make a second electrical connection to an external voltage source (e.g., via a second terminal 111b). The first electrode layer 112 may include a heating element (e.g., a proximity heater) configured to generate heat that is applied to adjacent components of the tunable capacitor device 100. The heating element may be positioned within or adjacent to any other layer within the tunable capacitor device 100 such that the heating element is within sufficient proximity to heat the intended component therein.

[0036] A method of forming the tunable capacitor device 100 may include positioning a dielectric layer 116 between a first electrode layer 112 and a second electrode layer 118, each layer having a planar surface (e.g., a top surface, a bottom surface). The dielectric layer 116 may be positioned directly between the first electrode layer 112 and the second electrode layer 118, or indirectly between the first electrode layer 112 and the second electrode layer 118, or an intervening adjacent layer may be positioned between the dielectric layer 116 and one of the first electrode layer 112 and the second electrode layer 118. The dielectric layer 116 may include a hafnium oxide (HfO2) composition. In an embodiment, the composite dielectric layer may be partitioned into two portions, a first portion including the dielectric layer 116 and a second portion including the phase change material (PCM) layer 114 (e.g., an approximately 3-10 nm thick layer), which may be comprised of a hafnium oxide HfO2 layer (e.g., an approximately 2-5 nm thick layer), as described further below.

[0037] The method of forming the tunable capacitor device 100 may further include positioning a PCM layer 114 between the first electrode layer 112 and the second electrode layer 118 adjacent the dielectric layer 116. In embodiments, the PCM layer 114 may be positioned directly adjacent to the first electrode layer 112, which includes the heating element, such that heat generated from the heating element changes the temperature of the PCM layer 114.

[0038] The method of forming the tunable capacitor device 100 may further include providing an activating component (e.g., to heat the PCM layer 114 to change the phase of the PCM layer 114). The activating component may be a heating element coplanar with either one of the first electrode layer 112 or the second electrode layer 118, the heating element configured to apply heat to the PCM layer 114 when activated. The activating component may be a resistive element in direct contact with the PCM layer 114, the resistive element configured to apply heat to the PCM layer 114 when activated. Other activating components may be used, so long as they are configured to heat the PCM layer 114 sufficiently to change the phase of the PCM layer 114 to the desired phase.

[0039] In an embodiment, the activation component is a proximity heater (not shown) in direct contact with the PCM layer 114, the proximity heater being configured to apply heat to the PCM layer 114 when activated.

[0040] In an embodiment, the tunable capacitor device 100 may include a PCM layer 114 that is in a first phase 110 corresponding to an amorphous phase, where the PCM layer 114 is a highly resistive material similar to a dielectric material. Heat may be applied to the PCM layer 114 to change phase from the first phase 110 (e.g., a completely amorphous phase) to a mixture of amorphous and crystalline, and finally to a second phase 120 (e.g., a crystalline phase), where the PCM layer 124 is a highly conductive material that is a semimetal.

[0041] In embodiments, the tunable capacitor device 100 may be tuned (i.e., heated to change the properties of the PCM layer 114) by various methods. In one embodiment, a melt quenching method may be provided, in which a high-current pulse with an abrupt termination is applied to the PCM layer 114, configured to generate sufficient heat in the PCM layer 114 so that a portion of the PCM layer 114 melts. Once terminated, the PCM layer 114 rapidly cools or returns to ambient temperature, thereby providing little opportunity for the PCM layer 114 to crystallize and remaining in the amorphous phase. In another embodiment, an annealing method may be provided, in which a pulse is provided that heats the PCM layer 114 not enough to melt it, but above the crystallization temperature while still in the amorphous phase to initiate crystal nucleation.

[0042] In embodiments, the PCM layer 114 may be composed of germanium antimony tellurium (Ge2Sb2Te5), which may have a crystallization temperature of approximately 160-170 degrees Celsius (C) and a melting temperature of approximately 600-700 degrees Celsius (C). A PCM layer 114 of this composition may be crystallized by applying a current pulse to a proximity heater that allows the PCM layer 114 to reach the crystallization temperature. For example, for PCM crystallization, the PCM need not be melted; rather, just enough heat may be applied so that the PCM temperature is sufficient to achieve crystallization.

[0043] In an embodiment, the phase of the PCM layer 114 and the capacitance (e.g., C 12), a capacitance versus phase change graph 130 for the tunable capacitor device 100 may be provided to illustrate the relationship between the phase of the PCM layer 114 and the crystallinity of the PCM layer 114. For example, as the phase of the PCM layer 114 transitions from 0% crystallinity (e.g., amorphous PCM or α-PCM) to 100% crystallinity (e.g., crystalline PCM or c-PCM), the capacitance of the tunable capacitor device 100 transitions from a capacitive minimum to a capacitive maximum. Thus, the tunable capacitor device 100 may be tuned to a particular capacitive value by varying the crystallinity of the PCM layer 114, as illustrated in the capacitance versus phase change graph 130.

[0044] It should be noted that although a single first electrode layer 112 and a single second electrode layer 118 are described and shown, the present application may also be used when multiple first electrode layers 112 and multiple second electrode layers 118 are formed.

[0045] In an embodiment, the first electrode layer 112 may include a first outer planar surface (e.g., a top planar surface) configured to make a first electrical connection via a first terminal 111a electrically connected to the first outer planar surface of the first electrode layer 112. The second electrode layer 118 may include a second outer planar surface (e.g., a bottom planar surface) configured to make a second electrical connection via a second terminal 111b electrically connected to the second outer planar surface of the second electrode layer 118.

[0046] The first electrode layer 112 and the second electrode layer 118 may be composed of a conductive metal or metal alloy. Examples of conductive materials that may be used in the present application include titanium nitride (TiN), molybdenum (Mo), tantalum nitride (TaN), or tungsten (W). Other inert materials may be used to reduce potential interactions with the PCM material.

[0047] The first electrode layer 112 may be composed of a conductive metal, such as tantalum (Ta), TaN, titanium (Ti), TiN, ruthenium (Ru), ruthenium nitride (RuN), ruthenium tantalum (RuTa), ruthenium tantalum nitride (RuTaN), cobalt (Co), cobalt tungsten phosphorus (CoWP), cobalt nitride (CoN), W, tungsten nitride (WN), or any combination thereof. The first electrode layer 112 may have a thickness of 2 nm to 100 nm. Other thicknesses are possible and may be used herein as the thickness of the first electrode layer 112. The first electrode layer 112 may be formed by a deposition process, such as evaporation, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). Deposition of the conductive material providing the first electrode layer 112 may be followed by an etch-back process, a planarization process (such as chemical mechanical polishing), or a patterning process (such as lithography and etching).

[0048] The second electrode layer 118 may be composed of one of the conductive materials described above for the first electrode layer 112. In one embodiment, the conductive material providing the second electrode layer 118 is compositionally different from the first electrode layer 112. In another embodiment, the conductive material providing the second electrode layer 118 is compositionally identical to the first electrode layer 112. The second electrode layer 118 may have a thickness within the thickness range described above for the first electrode layer 112. The second electrode layer 118 may be formed using one of the deposition processes described above for providing the first electrode layer 112, followed by a patterning process such as photolithography and etching.

[0049] In embodiments, dielectric layer 116 is typically a dielectric material having a large dielectric constant (relative permittivity). Examples of dielectric materials having a large dielectric constant include hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide, and aluminum oxide. The dielectric constant of Ge2Sb2Te5 is approximately 33. A large dielectric constant is desirable for layer 116 to obtain a large dynamic range for capacitance change (tunability).

[0050] The PCM layer 114 may be formed using a deposition process such as, for example, PECVD, PVD, CVD, or ALD. The PCM layer 114 may have a thickness between 3 nm and 20 nm. Other thicknesses are possible and may be employed for the PCM layer 114. In some embodiments, the PCM layer 114 has a conformal thickness. The term "conformal" indicates that the material layer has a vertical thickness along horizontal planes that is approximately the same (i.e., within ±5%) as its lateral thickness along vertical planes.

[0051] The dielectric layer 116 may be formed before or after forming the second electrode layer 118. In embodiments in which the dielectric layer 116 is formed before the second electrode layer 118, a blanket layer of dielectric capping material is formed, after which openings are formed (by photolithography and etching) in the dielectric capping material. The second electrode layer 118, defined below, is then formed in the openings. In such embodiments, the second electrode layer 118 is formed by deposition, followed by a planarization process. In embodiments in which the second electrode layer 118 is formed before the dielectric layer 116, the second electrode layer 118 may be formed by deposition and patterning, after which the dielectric capping material is deposited and a subsequent planarization process is performed.

[0052] FIG. 2 is a cross-sectional view of another tunable capacitor device of the present application in an amorphous state (e.g., first phase) and a crystalline state (e.g., second phase), according to an example embodiment of the present invention.

[0053] 2 is another example of a plate capacitor including a first electrode layer 218a distally facing a second electrode layer 218b, where the first electrode layer 218a is configured to make first electrical connections 211a, 221a and the second electrode layer 218b is configured to make second electrical connections 211b, 221b to an external voltage source. In this embodiment, the tunable capacitor device 200 may include a heating element 212 (e.g., a proximity heater) configured to generate heat that is applied to adjacent components of the tunable capacitor device 200. The heating element 212 may be positioned within or adjacent to any other layer within the tunable capacitor device 200 such that the heating element is within sufficient proximity to heat the intended component therein. Thus, instead of a heating element adjacent to or embedded in the electrode layer, or instead of using the electrode layer itself as the heater as described in FIG. 1, the heating element 212 is now positioned between the PCM layer 214 and the dielectric layer 216, both of which are between the first electrode layer 218a and the second electrode layer 218b.

[0054] In an embodiment, the tunable capacitor device 200 may include a PCM layer 214 that is in a first phase 210 corresponding to an amorphous phase, where the PCM layer 214 is a highly resistive material similar to a dielectric material. Heat may be applied to the PCM layer 214 to change phase from the first phase 210 (e.g., a fully amorphous phase) to a mixture of amorphous and crystalline, and finally to a second phase 220 (e.g., a fully crystalline phase), where the PCM layer 224 is a highly conductive material that is a semimetal.

[0055] In this embodiment, the phase of the PCM layer 214 and the capacitance (e.g., C 12), a phase change graph 230 for tunable capacitor device 200 is also provided to illustrate the relationship between the crystallinity of PCM layer 214 and the phase change of PCM layer 214. For example, as the phase of PCM layer 214 transitions from 0% crystallinity (e.g., α-PCM) to 100% crystallinity (e.g., c-PCM), the capacitance of tunable capacitor device 200 transitions from a capacitive minimum to a capacitive maximum. Thus, tunable capacitor device 200 can be tuned to a particular capacitive value by varying the crystallinity of PCM layer 214, as shown in capacitance versus phase change graph 230.

[0056] FIG. 3 shows various views of another tunable capacitor device of the present application during a tuning phase, according to an example embodiment of the present invention.

[0057] In an embodiment, the heater 312 may be located below the dielectric layer 316 and in the top plane of the bottom electrode layer 318b and is configured to apply heat to the dielectric layer 316 and the PCM layer 314 when activated. The top electrode layer 318a is configured to make a first electrical connection via a first terminal 311a electrically connected to a first outer plane of the top electrode layer 318a. The bottom electrode layer 318b may include a second outer plane (e.g., a bottom-most plane) configured to make a second electrical connection via a second terminal 311b electrically connected to a second outer plane of the bottom electrode layer 318b.

[0058] In embodiments, the tunable capacitor device 300 may be tuned (i.e., heated to change the properties of the PCM layer 314) by various methods. In one embodiment, a melt quench method may be used, in which a high current pulse with an abrupt termination (e.g., V program301) is applied to the PCM layer 314 and is configured to generate enough heat in the PCM layer 314 to melt a portion of the PCM layer 314. Upon termination, the PCM layer 314 rapidly cools or returns to ambient temperature, thereby leaving the PCM layer 314 in its amorphous phase with little opportunity to crystallize. The region of amorphous material that forms is the amorphous dome shown as part of the PCM layer 324. In another embodiment, an annealing method may be provided in which the heater 312 is activated with pulses that heat the PCM layer 314 to a temperature not sufficient to melt the PCM layer 314, but slightly above the crystallization temperature while still in the amorphous phase to initiate crystal nucleation.

[0059] In embodiments, during tuning of the tunable capacitor device 300, the PCM layer 314 may start out in a crystalline phase because, during fabrication, the material of the PCM layer 314 is typically annealed to fully crystallize it. When the PCM layer 314 is in the crystalline phase, sufficient heat must be applied to melt the PCM material to change it to the amorphous phase.

[0060] FIG. 4 is a cross-sectional view of a cylindrical tunable capacitor device of the present application in an amorphous state (410 and 430) and a crystalline state (420 and 440), according to an example embodiment of the present invention.

[0061] In an embodiment, the cylindrical tunable capacitor device 400 may include an inner electrode core 418b (e.g., a metal core electrode) surrounded by an outer electrode layer 418a. The heating element 412 is adjacent to the inner surface of the outer electrode layer 418a and adjacent to the outer surface of a dielectric layer 416 that is adjacent to a PCM layer 414 having an inner surface adjacent to the inner electrode core 418b, thereby forming a cylindrical composite of all described layers formed around and extending outward from the inner electrode core 418b.

[0062] As described above, the cylindrical tunable capacitor device 400 may be tuned according to the methods described herein by activating the heating element 412 to heat the PCM layer 414 and change the phase of the PCM layer 414 to achieve a desired capacitance. For example, the cylindrical tunable capacitor device 400 may be in a first phase 410, where the PCM layer 414 is in an amorphous phase. Heat may be applied to the PCM layer 414 to change the phase of the PCM layer 414 from the amorphous phase to a semi-amorphous semi-crystalline phase, and ultimately to a second phase 420, where the PCM layer 424 is in a crystalline phase as described herein above.

[0063] In another embodiment, the cylindrical tunable capacitor device 400 may be in a first phase 430 corresponding to the PCM layer 434 in an amorphous phase, and the cylindrical tunable capacitor device 400 includes an inner electrode core 438b (e.g., a metal core electrode) surrounded by the outer electrode layer 438a along with the PCM layer 434 positioned between the inner electrode core 438b and the outer electrode layer 438a, a heating element 432, and a dielectric layer 436. In this example embodiment, the heating element 432 is adjacent to the inner surface of the dielectric layer 436, which is adjacent to the inner surface of the outer electrode layer 438a. Additionally, the heating element 432 may contact the PCM layer 434.

[0064] As described above, cylindrical tunable capacitor device 400 in first phase 430 may be tuned using the methods described herein by activating heating element 432 to heat PCM layer 434 and change the phase of PCM layer 434 to obtain a desired capacitance. For example, cylindrical tunable capacitor device 400 may be in first phase 430, with PCM layer 434 in an amorphous phase. Heat may be applied to PCM layer 434 to change the phase of PCM layer 434 from the amorphous phase to a semi-amorphous, semi-crystalline phase, and ultimately to second phase 440, with PCM layer 444 in a crystalline phase as described herein above.

[0065] FIG. 5 illustrates a cross-sectional view of a cylindrical tunable capacitor device of the present application, according to an example embodiment of the present invention.

[0066] In an embodiment, the cylindrical capacitor device 500 may be in a heating core-electrode configuration of a first phase 510 corresponding to the crystalline phase of the PCM layer 514, with the heating electrodes 512, 522, 538 being at the center of the cylindrical capacitor device 500. In this embodiment, the outer surface of the dielectric layer 516 is directly adjacent to the inner surface of the outer electrode layer 518, and the outer surface of the PCM layer 514 is adjacent to the inner surface of the dielectric layer 516. Further, in this embodiment, the inner surface of the PCM layer 514 is adjacent to the outer surfaces of the heating electrodes 512, 522, 538.

[0067] In an embodiment, cylindrical tunable capacitor device 500 is in a first phase 510, but heating electrodes 512, 522, 538 can be activated to change the phase of PCM layer 514 from first phase 510 to a second phase 520 corresponding to a semi-amorphous, semi-crystalline phase including a surrounding crystalline portion 524a and amorphous portion 524b. The outer surface of crystalline portion 524a is adjacent to the inner surface of dielectric layer 516.

[0068] In another embodiment, cylindrical capacitor device 500 may have an external heating electrode configuration 530 corresponding to a crystalline PCM layer 534, with heating electrode 532 being the outermost electrode of cylindrical capacitor device 500. In this embodiment, the outer surface of dielectric layer 536 is directly adjacent to the inner surface of heating electrode 532, and the outer surface of PCM layer 534 is adjacent to the inner surface of dielectric layer 536.

[0069] FIG. 6 shows a cross-sectional view 600 of a cylindrical capacitor device and a lumped circuit, also called an equivalent circuit, of the device, according to an example embodiment of the present invention.

[0070] In an embodiment, a cylindrical capacitor device 610 is shown having an inner electrode core 618b distally facing an outer electrode layer 618a (e.g., a metal core electrode), with the PCM layer 614, heating element 612, and dielectric layer 616 positioned between the inner electrode core 618b and the outer electrode layer 618a. In this example embodiment, the heating element 612 is sufficiently conductive (e.g., constructed on TiN), so that the equivalent circuit 620 does not require an additional resistive element between capacitors C1 and C2. As shown, the entire volume of the PCM layer 614 is in the amorphous phase. The capacitance per capacitor in this configuration is given by:

[0071]

number

[0072]

number

[0073] a is the radius of the internal electrode core 618b, b is the radius from the center of the internal electrode core 618b to the outer edge of the PCM layer 614, c is the radius from the center of the internal electrode core 618b to the inner surface of the dielectric layer 616, and d is the radius from the center of the internal electrode core 618b to the inner surface of the external electrode layer 618a. α-PCM and ε HfO2 are the respective dielectric constants (i.e., relative permittivity) of the amorphous PCM (α-PCM) and the dielectric layer 616 (e.g., hafnium oxide (HfO2)), and ε is the vacuum permittivity. In this example, the dielectric layer 616 is assumed to be composed of HfO2.

[0074] The total capacitance between C1 and C2 is measured between the first terminal 611a and the second terminal 611b and is given by:

[0075] 1 / C 12 =1 / C1+1 / C2

[0076] The above equation indicates that to obtain a large dynamic range, the tunable capacitor dielectric layer 616 should be kept as thin as possible (i.e., without becoming leaky) and the dielectric constant of the material should be as high as possible.

[0077] FIG. 7 shows a cross-sectional view 700 of a cylindrical capacitor device 710 in an intermediate capacitance state and an equivalent circuit of the device, according to an example embodiment of the present invention.

[0078] In an embodiment, the cylindrical capacitor device 710 is shown in the intermediate state as illustrated in FIG. 5 as a second phase 520 corresponding to a semi-amorphous, semi-crystalline phase including a surrounding crystalline portion 714a of the PCM layer 714 and an amorphous portion 714b of the PCM layer 714, with the outer surface of the crystalline portion 714a adjacent to the outer electrode layer 718 and adjacent to the inner surface of the dielectric layer 716 surrounded by the outer electrode layer 718. In this example embodiment, the heating electrode core 712 is sufficiently electrically conductive (e.g., constructed on TiN), so that the intermediate state equivalent circuit 720 does not require an additional resistive element added in series with capacitors C1 and C2. The capacitance per capacitor in this configuration is expressed as:

[0079]

number

[0080]

number

[0081] a is the radius of the heating electrode core 712, b is the radius from the center of the heating electrode core 712 to the outer edge of the amorphous portion 714b of the PCM layer 714, c is the radius from the center of the heating electrode core 712 to the outer edge of the crystalline portion 714a of the PCM layer 714, and d is the radius from the center of the heating electrode core 712 to the outer edge of the dielectric layer 716.

[0082] The total capacitance between C1 and C2 is measured between the first terminal 711a and the second terminal 711b and is given by:

[0083] 1 / C 12 =1 / C1+1 / C2

[0084] In an embodiment, as the amorphous PCM area increases (i.e., radius b increases), the capacitance decreases. Thus, by varying the energy delivered to the heater, the size of the amorphous portion 714b of the PCM layer 714 increases (or decreases), increasing the total capacitance C 12 can be tuned to a specified value. The phase of the PCM layer 714 (a and b) can be programmed using a RESET pulse, a SET pulse, or both. When a RESET pulse is applied to the electrode core 712 (e.g., a heater), the PCM region adjacent to the heater melts and then cools very quickly (a process called melt quenching). The size of the amorphous region depends on the RESET pulse amplitude, with larger pulses leading to a larger radius b. When a SET pulse is applied to some or all of the amorphous portion 714b, the PCM layer 714 crystallizes. The longer the SET pulse, the more material in the PCM layer 714 crystallizes. As explained previously, the SET pulse does not need to melt the PCM material; it typically releases enough heat to bring the PCM temperature to or above the crystallization temperature.

[0085] FIG. 8 illustrates a circuit array diagram of a neural network (NN) for charging a tunable capacitor device (Phase I) according to an example embodiment of the present invention. As shown, charging circuit array diagram 800 (or "cross point array 800") includes circuit configurations (e.g., 811, 821, 812, 822), each including two transistors (e.g., a charge transistor and a discharge transistor) and a tunable capacitor. For example, circuit configuration 811 includes a first set of transistors, charge transistor 811a, and a second set of transistors, discharge transistor 811b, connected at a first end to voltage line V1 and at a second end to Cap 811c. The remaining circuit configurations 821, 812, and 822 have identical configurations.

[0086] In an embodiment, a method of performing a MAC operation for a NN having a tunable capacitor device 100 may include forming a circuit array representing a circuit array diagram 800; providing one or more circuit configurations including tunable capacitors (e.g., 811c, 821c, 812c, 822c) connected to charging transistors (e.g., 811a, 821a, 812a, 822a), where the circuit array diagram 800 is configured to apply an input voltage to the tunable capacitors; and providing discharge transistors (e.g., 811b, 821b, 812b, 822b) configured to discharge the tunable capacitors, where the circuit array diagram 800 is configured to perform a portion of a multiply-accumulate operation.

[0087] In these configurations, the computation of the MAC operation is completed in two phases of time. In the first phase, the charge transistor is activated to allow current flow through the charge capacitor into the tunable capacitor to charge the capacitor, and the discharge transistor is not activated to prevent current flow from the tunable capacitor. In embodiments, one or more processors may be configured to activate the charge transistor to charge the capacitor. In embodiments, one or more processors may be configured to tune the tunable capacitor to a desired or predetermined capacitance level according to embodiments described herein.

[0088] In an embodiment, a method includes charging two or more tunable capacitors using charging transistors to accumulate a total charge across one or more circuit configurations (Q 11 +Q 21 +Q 12 +Q 22 ) and discharging the two or more tunable capacitors with discharge transistors and integrating the total charge, which may be determined by integrating the total current flowing from the discharge transistors, as shown in FIG.

[0089] 9 illustrates a second time phase of the circuit array diagram of FIG. 8 during discharging (Phase II) of the tunable capacitor device, according to an example embodiment of the present invention. As shown, the discharge circuit array diagram 900 (or "cross point array") has the same configuration as the charge circuit array diagram 800, except that the charge transistors (e.g., 911a, 921a, 912a, 922a) are not activated to prevent current flow into the tunable capacitors (e.g., 911c, 921c, 912c, 922c), and the discharge transistors (e.g., 911b, 921b, 912b, 922b) are activated to allow current flow from the tunable capacitors to discharge them, such that the discharge circuit array diagram 900 is configured to perform a portion of the MAC operation.

[0090] In these configurations, the discharge transistors are activated to allow current flow through them and out to the integrator, and the charge transistors are not activated to prevent current flow through them. In the first phase, each of the tunable capacitors is charged with a charge Q i =C i ×V i In the second phase, the tunable capacitor is discharged and the total charge is integrated to produce Q T =ΣQ i , performs the "accumulate" part of the MAC operation.

[0091] FIG. 10 is a flowchart of a method 1000 of forming a tunable capacitor device, according to an example embodiment of the present invention.

[0092] In an embodiment, a method 1000 of forming a non-volatile tunable capacitor device includes forming 1002 a first electrode layer distally opposite a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection.

[0093] The method 1000 may further include positioning 1004 a dielectric layer adjacent to the first inner planar surface and between the first electrode layer adjacent to the second inner planar surface of the second electrode layer. The first electrode layer may include a first inner planar surface distally facing the second inner planar surface of the second electrode layer. The first electrode layer may include a first outer planar surface configured to make a first electrical connection, and the second electrode layer may include a second outer planar surface configured to make a second electrical connection.

[0094] The method 1000 may further include positioning 1006 a phase change material (PCM) layer between the first electrode layer and a second electrode layer adjacent to the dielectric layer.

[0095] The method 1000 may further include providing 1008 an activation component that heats the PCM layer to change the phase of the PCM layer. The activation component may include a heating element coplanar with either one of the first electrode layer and the second electrode layer, the heating element configured to apply heat to the PCM layer when activated. The activation component may include a resistive element in direct contact with the PCM layer, the resistive element configured to apply heat to the PCM layer when activated. For example, the resistive element may be an electrical probe.

[0096] The phase of the PCM layer may be selectively changeable between at least an amorphous phase corresponding to a resistive PCM layer and a crystalline phase corresponding to a conductive PCM layer. The PCM layer may include a composition of Ge2Sb2Te5, GeTe, or Sb2Te3. The dielectric layer may include a composition of HfO2.

[0097] In another embodiment, a method for performing a multiply-accumulate (MAC) operation for a neural network (NN) includes one or more circuit configurations (e.g., 811, 812, 821, 822), which may include charge transistors (e.g., 811a, 812a, 821a, 822a), discharge transistors (e.g., 811b, 812b, 821b, 822b), and tunable capacitors (e.g., 811c, 812c, 821c, 822c). In the embodiment, the charge transistors include a first charge transistor terminal connected to a voltage line V1. Further, the charge transistors also include a second charge transistor terminal connected to a first capacitor terminal of the tunable capacitor, which includes a second capacitor terminal connected to a ground terminal. Further, the one or more circuit configurations may further include a discharge transistor including a first discharge transistor terminal connected to the second charge transistor terminal and the first capacitor terminal. Additionally, the discharge transistor also includes a second discharge terminal connected to the current line.

[0098] Further, a method of performing a MAC operation for a NN may include applying a predetermined amount of heat to a tunable capacitor (e.g., 811c, 812c, 821c, 822c) for a predetermined amount of time, where the tunable capacitor has a first capacitance value and the predetermined amount of heat may be sufficient to change the first capacitance value to a second capacitance value.

[0099] A method of performing a MAC operation for a NN may include charging tunable capacitors (e.g., 811c, 812c, 821c, 822c) for a first predetermined amount of time by applying an input voltage V1 to the tunable capacitors through closed charge transistors (e.g., 811a, 812a, 821a, 822a) and open discharge transistors (e.g., 811b, 812b, 821b, 822b), and discharging the tunable capacitors for a second predetermined amount of time by stopping the input voltage to the tunable capacitors through the open charge transistors and closed discharge transistors, where charge flows from the tunable capacitors through the discharge transistors to an integrator circuit.

[0100] In an embodiment, a method for performing a MAC operation for a neural network is configured to configure a tunable capacitor to a weight of the neural network, represented as a second capacitance value, to provide a predetermined amount of heat.

[0101] In an embodiment, the method of performing a MAC operation for a NN may further include determining a total charge of one or more circuit components including a tunable capacitor by integrating the charge of the one or more circuit components through the discharge transistor using an integrator circuit.

[0102] In an embodiment, a method for performing a MAC operation for a neural network is configured to configure a tunable capacitor to a weight of the neural network, represented as a second capacitance value, to provide a predetermined amount of heat.

[0103] In embodiments, the phase of the PCM layer of the tunable capacitor may be selectively changeable from an amorphous phase corresponding to a resistive PCM layer to a crystalline phase corresponding to a conductive PCM layer.

[0104] 11 illustrates a block diagram of components of a server computer that may execute a method 1000 for forming a tunable capacitor device in accordance with an example embodiment of the present invention. It should be understood that FIG. 11 is merely provided as an illustration of one implementation and is not intended to suggest any limitation with respect to the environments in which different embodiments may be implemented. Many modifications to the illustrated environments may be made.

[0105] The method 1000 may be performed on a server computer or computing device 1100 that includes a communications fabric 1102 that provides communications between a cache 1116, memory 1106, persistent storage 1108, a communications unit 1110, and an input / output (I / O) interface 1112. The communications fabric 1102 may be implemented with any architecture designed to pass data and / or control information between processors (such as microprocessors, communications and network processors), system memory, peripheral devices, and any other hardware components in a system. For example, the communications fabric 1102 may be implemented with one or more buses or crossbar switches.

[0106] The memory 1106 and the persistent storage 1108 are computer-readable storage media. In this embodiment, the memory 1106 includes random access memory (RAM). Generally, the memory 1106 may include any suitable volatile or non-volatile computer-readable storage medium. The cache 1116 is a high-speed memory that enhances the performance of the computer processor 1104 by retaining recently accessed data and data near recently accessed data from the memory 1106.

[0107] Programs may be stored in persistent storage 1108 and memory 1106 for execution and / or access by one or more of the respective computer processors 1104 via cache 1116. In an embodiment, persistent storage 1108 includes a magnetic hard disk drive. Alternatively, or in addition to a magnetic hard disk drive, persistent storage 1108 may include a solid-state hard drive, a semiconductor storage device, read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, or any other computer-readable storage medium capable of storing program instructions or digital information.

[0108] The media used by persistent storage 1108 may also be removable. For example, a removable hard drive may be used for persistent storage 1108. Other examples include optical and magnetic disks, thumb drives, and smart cards, which are inserted into a drive for transfer onto another computer-readable storage medium that is also part of persistent storage 1108.

[0109] In these examples, communications unit 1110 provides for communication with other data processing systems or devices. In these examples, communications unit 1110 includes one or more network interface cards. Communications unit 1110 may provide communications through the use of either or both physical and wireless communications links. Programs described herein may be downloaded to persistent storage 1108 through communications unit 1110.

[0110] The I / O interface 1112 allows for the input and output of data with other devices that may be connected to the server computer and / or computing device 1100. For example, the I / O interface 1112 may provide connection to external devices 1118, such as an image sensor, a keyboard, a keypad, a touch screen, or any other suitable input device, or a combination thereof. The external devices 1118 may also include portable computer-readable storage media, such as thumb drives, portable optical or magnetic disks, and memory cards. Software and data 1114 used to implement embodiments of the present invention may be stored on such portable computer-readable storage media or loaded onto persistent storage 1108 via the I / O interface 1112. The I / O interface 1112 is also connected to a display 1120.

[0111] Display 1120 provides a mechanism for displaying data to a user and may be, for example, a computer monitor.

[0112] The software and data 1114 described herein are identified based on the application in which they are implemented in a particular embodiment of the invention. However, it should be understood that any particular program terminology herein is used merely for convenience, and thus the invention should not be limited to use only in any particular application identified and / or suggested by such terminology.

[0113] The present invention may be a system, method, or computer program product, or combination thereof, at any possible level of technical detail of integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the present invention.

[0114] A computer-readable storage medium may be a tangible device capable of retaining and storing instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, punch cards, or mechanically encoded devices such as ridge structures in grooves that allow instructions to be recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as being ephemeral signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through fiber optic cable), or electrical signals transmitted through electrical wires.

[0115] The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage in a computer-readable storage medium within the respective computing / processing device.

[0116] Computer-readable program instructions for carrying out the operations of the present invention may be either source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or object-oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer-readable program instructions by individualizing the electronic circuitry using state information of the computer-readable program instructions to perform aspects of the present invention.

[0117] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0118] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, when executed by the processor of the computer or other programmable data processing apparatus, create means for performing the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions may also be stored on a computer-readable storage medium that may direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium having the instructions stored therein comprises an article of manufacture containing instructions that perform aspects of the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0119] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operational steps to create a computer-implemented process, such that the instructions executing on the computer, other programmable apparatus, or other device perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams.

[0120] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may actually be implemented as a single step, executed concurrently, substantially concurrently, partially, or fully overlapping in time, or the blocks may be executed in the reverse order depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0121] While the present application has been particularly shown and described with respect to its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the scope of the present application. It is therefore intended that the present application not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

Claims

1. 1. A method of forming a nonvolatile tunable capacitor device, comprising: forming a first electrode layer distally opposite a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection; positioning a dielectric layer between the first electrode layer and the second electrode layer; positioning a phase change material (PCM) layer between the first electrode layer and the second electrode layer adjacent the dielectric layer; providing an activation component for heating the phase change material (PCM) layer to change the phase of the PCM layer, the activation component being a heating element coplanar with one of the first electrode layer and the second electrode layer; A method comprising:

2. 1. A method of forming a nonvolatile tunable capacitor device, comprising: forming a first electrode layer distally opposite a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection; positioning a dielectric layer between the first electrode layer and the second electrode layer; positioning a phase change material (PCM) layer between the first electrode layer and the second electrode layer adjacent the dielectric layer; providing an activation component for heating the phase change material (PCM) layer to change the phase of the PCM layer, the activation component being a resistive element in direct contact with the phase change material (PCM) layer, the resistive element being configured to apply heat to the PCM layer when activated; A method comprising:

3. 3. The method of claim 1 or 2, wherein the phase of the phase change material (PCM) layer is selectively changeable between at least an amorphous phase corresponding to a resistive phase change material (PCM) layer and a crystalline phase corresponding to a conductive phase change material (PCM) layer.

4. 1. A non-volatile tunable capacitor device comprising: an outer cylindrical electrode layer having a first diameter; an inner cylindrical electrode layer axially proximal to the outer cylindrical electrode layer, the inner cylindrical electrode layer having a second diameter less than the first diameter; a dielectric layer disposed between the outer cylindrical electrode layer and the inner cylindrical electrode layer and over the entire surface of the outer cylindrical electrode layer facing the inner cylindrical electrode layer; a phase change material (PCM) layer disposed between the inner cylindrical electrode layer and the dielectric layer and over the entire surface of the inner cylindrical electrode layer facing the dielectric layer; a heating element layer disposed between the dielectric layer and the phase change material (PCM) layer and configured to apply heat to the phase change material (PCM) layer when activated; 1. A nonvolatile tunable capacitor device comprising:

5. A nonvolatile tunable capacitor device, comprising: an outer cylindrical electrode layer having a first diameter; an inner cylindrical electrode layer axially proximal to the outer cylindrical electrode layer, the inner cylindrical electrode layer having a second diameter less than the first diameter; a phase change material (PCM) layer disposed between the outer cylindrical electrode layer and the inner cylindrical electrode layer and over the entire surface of the inner cylindrical electrode layer facing the outer cylindrical electrode layer; a dielectric layer disposed between the external cylindrical electrode layer and the phase change material (PCM) layer and over the entire surface of the phase change material (PCM) layer facing the external cylindrical electrode layer; a heating element layer disposed between the outer cylindrical electrode layer and the dielectric layer, the heating element layer being configured to apply heat to the phase change material (PCM) layer when activated; 1. A nonvolatile tunable capacitor device comprising:

6. 6. The non-volatile tunable capacitor device of claim 4 or 5, further comprising a resistive element in direct contact with the phase change material (PCM) layer, the resistive element being configured to apply heat to the phase change material (PCM) layer when activated.

7. 7. The nonvolatile tunable capacitor device of claim 4, wherein the phase change material (PCM) layer has a phase configured to change from an amorphous phase corresponding to a resistive phase change material (PCM) layer to a crystalline phase corresponding to a conductive phase change material (PCM) layer based on a predetermined amount of heat applied to the phase change material (PCM) layer.

8. 8. The nonvolatile tunable capacitor device of claim 4, wherein the phase change material (PCM) layer comprises one of the following compositions: Ge2Sb2Te5, GeTe, and Sb2Te3.

9. 9. The nonvolatile tunable capacitor device of claim 4, wherein the dielectric layer comprises a composition of HfO2.

10. 1. A method for performing a multiply-accumulate (MAC) operation for a neural network (NN), comprising: providing one or more circuit configurations, the one or more circuit configurations comprising: A tunable capacitor device according to any one of claims 4 to 9; a charge transistor including a first charge transistor terminal connected to a voltage line and a second charge transistor terminal connected to a first capacitor terminal of the tunable capacitor, the tunable capacitor including a second capacitor terminal connected to a ground terminal; a discharge transistor including a first discharge terminal connected to the second charge transistor terminal and the first capacitor terminal and a second discharge terminal connected to a current line; providing; applying a predetermined amount of heat to the tunable capacitor for a predetermined amount of time, the tunable capacitor having a first capacitance value, the predetermined amount of heat being sufficient to change the first capacitance value to a second capacitance value; A method comprising:

11. charging the tunable capacitor for a first predetermined amount of time by applying an input voltage to the tunable capacitor through the charge transistor in a closed state and the discharge transistor in an open state; discharging the tunable capacitor for a second predetermined amount of time by stopping the input voltage to the tunable capacitor through the open state of the charge transistor and the closed state of the discharge transistor, wherein charge flows from the tunable capacitor through the discharge transistor to an integrating circuit; The method of claim 10 further comprising:

12. 12. The method of claim 11, wherein applying the predetermined amount of heat is configured to set the tunable capacitor to a weight of the neural network (NN) represented as the second capacitance value.

13. 13. The method of claim 11 or 12, further comprising determining a total charge of the one or more circuit configurations including the tunable capacitor by integrating the charge of the one or more circuit configurations through the discharge transistor using the integrating circuit.

14. 14. The method of claim 10, further comprising determining the predetermined amount of heat as a change in temperature sufficient to achieve a desired weight corresponding to the second capacitance value.

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