Decoding method, processor, chip and electronic device

Abstract

The embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device, the method including: generating a fetch request carrying at least one switching mark indicating an instruction position where at least a decoder group switching is performed; in response to the decoder group decoding to obtain a microinstruction, obtaining an instruction stream fetched by the fetch request, and determining an instruction position where the decoder group switching is performed according to the switching mark carried by the fetch request; in response to the instruction position, assigning the instruction stream to a plurality of decoder groups for parallel decoding, and attaching a switching mark to a target microinstruction obtained by decoding a target instruction, which is an instruction corresponding to the instruction position; in response to the microinstruction being obtained by searching a microinstruction cache, if the fetch request hits in the microinstruction cache, obtaining the corresponding microinstruction from the microinstruction cache. The embodiments of the present disclosure can improve the decoding performance of a processor.

Description

[Technical Field]

[0001] This application claims priority from Chinese Patent Application No. 202211350246.2 filed on October 31, 2022, and the contents disclosed in the above Chinese patent application are hereby incorporated by reference in their entirety as part of this application.

[0002] SUMMARY OF THE INVENTION The embodiments of the present disclosure relate to a decoding method, a processor, a chip, and an electronic device. [Background technology]

[0003] In modern processors, instructions must go through a process of fetching, decoding, and execution, where decoding is the process of analyzing and translating a fetched instruction to obtain a micro-instruction (Uop). Decoding is an important operation of a processor, and how to improve the decoding performance of a processor has been a topic of research for those skilled in the art. Summary of the Invention [Means for solving the problem]

[0004] In view of this, embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device for achieving parallel decoding of instructions and obtaining a microinstruction sequence that matches the fetch order, thereby improving the decoding performance of the processor.

[0005] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions.

[0006] An embodiment of the present disclosure is a decoding method applied to a processor, comprising: generating a fetch request carrying at least one switching mark indicating an instruction position where at least a switching of decoder groups is to occur; In response to a microinstruction being obtained by decoding a decoder group, acquiring the instruction stream fetched by the fetch request, determining an instruction position in the instruction stream where a decoder group is to be switched in accordance with a switching mark carried by the fetch request, allocating the instruction stream to a plurality of decoder groups in accordance with the instruction position for parallel decoding, and attaching a switching mark to a target microinstruction obtained by decoding a target instruction, which is an instruction corresponding to the instruction position; In response to the microinstruction being obtained by searching the microinstruction cache, if the fetch request hits in the microinstruction cache, a microinstruction corresponding to the fetch request and not marked with a switching mark is obtained from the microinstruction cache.

[0007] An embodiment of the present disclosure includes: a branch prediction unit for generating a fetch request carrying at least one switching mark indicating an instruction position where at least a decoder group switching occurs; an instruction cache for responsively obtaining microinstructions by decoding the decoder groups to obtain the instruction stream fetched by said fetch request and for determining, in response to a switch mark carried by said fetch request, the instruction position in said instruction stream at which a switch of decoder groups is to be made; an instruction allocation unit for allocating the instruction stream to a plurality of decoder groups for parallel decoding according to the instruction position; a decoder group for decoding the assigned instruction to obtain a microinstruction, the number of said decoder groups being plural, wherein when said decoder group decodes a target instruction, a switching mark is attached to a target microinstruction obtained by decoding said target instruction, and said target instruction is an instruction corresponding to said instruction position; The processor further includes a microinstruction cache for, in response to a microinstruction being obtained by searching the microinstruction cache, if the fetch request hits in the microinstruction cache, obtaining from the microinstruction cache a microinstruction corresponding to the fetch request and not marked for switching.

[0008] An embodiment of the present disclosure further provides a chip including the above-described processor.

[0009] An embodiment of the present disclosure further provides an electronic device including the above-described chip.

[0010] The decoding method provided by the embodiments of the present disclosure may be applied to a processor, and may include a fetch request carrying at least one switching mark indicating an instruction position where at least a decoder group switching occurs. Thus, when the processor responds to a microinstruction being obtained by decoding a decoder group, it may obtain the instruction stream fetched by the fetch request, determine the instruction position in the instruction stream where the decoder group switching occurs according to the switching mark carried by the fetch request, assign the instruction stream to multiple decoder groups for parallel decoding according to the instruction position, decode a target instruction corresponding to the instruction position, and add a switching mark to the target microinstruction obtained by decoding the target instruction, and subsequently combine the microinstructions decoded by the multiple decoder groups according to the switching mark added to the target microinstruction to obtain a microinstruction corresponding to the fetch order. When the processor responds to a microinstruction being obtained by searching a microinstruction cache, if the fetch request hits in the microinstruction cache, the embodiments of the present disclosure may obtain the microinstruction corresponding to the fetch request from the microinstruction cache without decoding the instruction using a decoder group.

[0011] In an embodiment of the present disclosure, in a processor having a microinstruction cache and a decoder, a fetch request may carry a switching mark, which indicates at least the instruction position where the decoder group switching occurs. In a decoder mode in which a microinstruction is obtained by decoding a decoder group, the switching mark is transparently transmitted through the target instruction and the target microinstruction, thereby supporting parallel decoding of multiple decoder groups. The decoded microinstructions can be fused according to the instruction fetch order, improving decoding efficiency. In a microinstruction cache mode in which a processor obtains microinstructions by searching a microinstruction cache, the embodiment of the present disclosure does not need to perform processing based on the switching mark carried in the fetch request, thereby being compatible with the microinstruction cache mode of the processor. In a processor that supports both a decoder mode and a microinstruction cache mode, the embodiment of the present disclosure supports parallel decoding and improves decoding performance. [Brief explanation of the drawings]

[0012] In order to more clearly describe the embodiments of the present disclosure, the following briefly introduces the drawings required to be used in the embodiments. Obviously, the drawings in the following description are only embodiments of the present disclosure, and those skilled in the art can obtain other drawings from the provided drawings without paying creative labor. [Figure 1A] FIG. 1A is an architectural block diagram of a processor. [Figure 1B] FIG. 1B is another architecture block diagram of a processor. [Figure 2A] FIG. 2A is an architectural block diagram of one of the processors provided in accordance with at least one embodiment of the present disclosure. [Figure 2B] FIG. 2B is a flowchart of an optional decoding method provided by at least one embodiment of the present disclosure. [Figure 2C]FIG. 2C is yet another architectural block diagram of a processor provided in accordance with at least one embodiment of the present disclosure. [Figure 3A] FIG. 3A is a schematic diagram of instruction stream segmentation provided by at least one embodiment of the present disclosure. [Figure 3B] FIG. 3B is a schematic diagram of microinstruction fusion provided in accordance with at least one embodiment of the present disclosure. [Figure 4A] FIG. 4A is an architectural block diagram of a processor with a microinstruction cache. [Figure 4B] FIG. 4B is yet another architectural block diagram of a processor provided in accordance with at least one embodiment of the present disclosure. [Figure 5A] FIG. 5A is a schematic diagram of options for retaining microinstructions in a microinstruction cache mode provided by at least one embodiment of the present disclosure. [Figure 5B] FIG. 5B is a schematic diagram of another option for retaining microinstructions in a microinstruction cache mode provided by at least one embodiment of the present disclosure. [Figure 6] FIG. 6 is a flowchart of another optional decoding method provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013] The following clearly and completely describes the technical solutions in the embodiments of the present disclosure, combining the accompanying drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only some embodiments of the present disclosure, not all embodiments, and all other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without paying creative labor belong to the scope of protection of the present disclosure.

[0014] An instruction is a command that controls a computer to perform an operation, and is also called a machine instruction. The role of an instruction is to coordinate the operational relationships between each hardware component, reflect the basic functions of a computer, and is the smallest functional unit at which a computer operates. When a computer executes an operation command, the processor must process the instruction and convert it into machine language that the machine can understand. In a processor, instruction processing is generally achieved using pipeline technology.

[0015] In a processor's pipeline operation, instructions must undergo processing processes such as instruction fetch, decode, and execute. Fetching refers to fetching an instruction corresponding to program execution from the processor's cache or main memory. Decoding refers to decoding the fetched instruction to determine the instruction's opcode and / or address code, etc. Executing refers to executing the instruction according to the obtained opcode and / or address code, etc., to execute the program. Since some instructions contain branch instructions that change the flow of a program, a branch prediction unit may be provided at the beginning of the processor's instruction processing pipeline to realize instruction branch prediction, thereby eliminating pipeline delays caused by the processor waiting for the execution result of the branch instruction before deciding on the next fetch.

[0016] FIG. 1A shows an exemplary architecture block diagram of a processor including a branch prediction unit 101, an instruction cache 102, and a decoder group 103.

[0017] The branch prediction unit 101 is a digital circuit that can predict the branching of instructions and generate a fetch request based on the branch prediction result. The branch prediction result may be, for example, whether the current instruction is a branch instruction or not, the branching result (direction, address, destination address, etc.) of the branch instruction, etc. In one implementation, the branch prediction unit may perform branch prediction of instructions based on historical execution information and results of the branch instruction, thereby obtaining a fetch address range of the instructions and generating a fetch request. The fetch request generated by the branch prediction unit includes fetch addresses of several instructions for reading corresponding instructions from the instruction cache 102.

[0018] Instructions are stored in the instruction cache 102, primarily via instruction cache blocks. In the instruction cache, each instruction cache block corresponds to a Tag that identifies the instruction cache block in the instruction cache, so that the instruction cache can find the corresponding instruction cache block based on the Tag when fetching in response to a fetch request. A fetch address generated by the branch prediction unit may correspond to multiple instructions forming an instruction stream. Optionally, the instruction cache 102 may be a cache portion for storing instructions located in a level 1 cache of the processor.

[0019] The fetch address generated by the branch prediction unit has a tag area (address identification area) and an index area (address index area). The index area in the fetch address allows the tags of multiple instruction cache blocks in the instruction cache to be read out. Furthermore, a match is determined between the tags of the multiple instruction cache blocks in the read instruction cache and the tag of the fetch address, and the storage location in the instruction cache of the instruction corresponding to the fetch address (i.e., the location of the instruction cache block) is obtained, and the corresponding instruction is then read out.

[0020] The decoder group 103 can analyze and translate the instruction, and the decoder group can decode the instruction to obtain the decoded instruction. The decoded instruction can be machine-executable operation information obtained by translating the instruction, such as a machine-executable UOP (micro-op) formed by a control field, that is, the decoder can decode the instruction to obtain a micro-op.

[0021] The processor architecture shown in FIG. 1A decodes instructions using a single decoder group, which is limited by the decoder group's throughput, making it difficult to effectively improve instruction decoding efficiency. Based on this, processors that use multiple decoder groups to decode instructions in parallel have emerged. FIG. 1B is an exemplary block diagram of another processor architecture. As shown by combining FIGS. 1A and 1B, the processor shown in FIG. 1B has multiple decoder groups 1031-103n, where the specific value of n may depend on the specific design of the processor and is not limited to the embodiments of the present disclosure. Based on the multiple decoder groups 1031-103n provided by the processor, the instruction cache 102 may assign and decode an instruction stream fetched based on a fetch request to the multiple decoder groups. The multiple decoder groups may decode instructions in parallel and output the decoded microinstructions, thereby improving instruction decoding efficiency.

[0022] In one example, the multiple decoder groups may be, for example, two decoder groups, decoder group 0 and decoder group 1. Here, decoder group 0 may decode instructions while decoder group 1 may also decode instructions. For example, in one clock cycle of the processor, decoder group 0 and decoder group 1 can simultaneously perform decode operations on instructions to obtain microinstructions, thereby realizing parallel instruction decoding. At the same time, decoder group 0 and decoder group 1 do not need to decode instructions in order and can support parallel instruction decoding. Note that in actual applications, a processor may have two or more decoder groups as needed. For ease of understanding, the embodiments of the present disclosure only illustrate two decoder groups.

[0023] However, parallel instruction decoding by multiple decoder groups differs from sequential instruction decoding by a single decoder group, and parallel instruction decoding by multiple decoder groups requires more complex issues, such as how to allocate instruction streams fetched from an instruction cache to multiple decoder groups, and how to fuse microinstructions decoded by the multiple decoder groups so that the microinstructions that are ultimately executed correspond to the instruction fetch order. To solve the above problems, an embodiment of the present disclosure provides a further improved processor architecture, and FIG. 2A exemplarily illustrates an architecture block diagram of a processor provided by at least one embodiment of the present disclosure. 1B and 2A, the processor shown in FIG. 2A further includes an instruction allocation unit 201 for dividing the instruction stream fetched by the instruction cache 102, thereby obtaining multiple instruction groups to be assigned to decoder groups and decoded in parallel. To provide a basis for dividing the instruction stream, the embodiment of the present disclosure carries a switching mark in the fetch request, which indicates at least the instruction position where the decoder group switching occurs. The switching mark is then transparently transmitted to the process of the instruction cache fetching the instruction stream in response to the fetch request, allowing the instruction allocation unit 201 to divide the instruction stream according to the instruction position where the decoder group switching occurs, and assign the divided instruction groups of the instruction stream to multiple decoder groups for parallel decoding, thereby technically supporting parallel decoding of instructions in multiple decoder groups. Furthermore, the switching mark may be transparently transmitted to the microinstruction through an instruction corresponding to the instruction position. This technically supports that, after each decoder group decodes to obtain a microinstruction, microinstruction fusion can be performed based on the switching mark in the microinstruction, and the fused microinstruction results can be associated with the fetch order.

[0024] As an optional implementation, Figure 2B exemplarily illustrates an optional flowchart of a decoding method provided by at least one embodiment of the present disclosure. This decoding method may be considered as a method flow when a processor decodes using a decoder group, i.e., a method flow in which a microinstruction is obtained by decoding the decoder group. Referring to Figure 2B, this method flow may include the following steps:

[0025] In step S21, a fetch request is generated which carries at least one switching mark indicating the instruction position where at least a switching of decoder groups is to occur.

[0026] In some embodiments, a fetch request generated by a branch prediction unit may include a portable switching mark. When the branch prediction unit performs branch prediction, the branch prediction direction is mainly divided into two types: a jump branch instruction and a non-jump branch instruction. Accordingly, the fetch addresses generated by the branch prediction unit may be divided into two types: a fetch address corresponding to the predicted jump branch direction and a fetch address corresponding to the predicted non-jump branch direction. As an optional implementation, embodiments of the present disclosure may set a switching mark according to an address location corresponding to the predicted jump branch direction, and generate a fetch request carrying at least one switching mark.

[0027] In some embodiments, the switch mark is not limited to being set in the fetch request based on the branch prediction status by the branch prediction unit, but may be set by other mechanisms. As an optional implementation, after the branch prediction unit generates the fetch request (without carrying the switch mark), embodiments of the present disclosure may utilize another device in the processor (e.g., an instruction cache) to set the switch mark in the fetch request. In one implementation, after obtaining the fetch request from the branch prediction unit, the instruction cache may set the switch mark in the fetch request based on an instruction boundary that can represent the end location of the instruction.

[0028] In step S22, the instruction stream fetched by the fetch request is obtained, and the instruction position in the instruction stream where the decoder group is to be switched is determined according to the switching mark carried in the fetch request.

[0029] The instruction cache receives a fetch request from the branch prediction unit, fetches instructions according to the fetch address in the fetch request, and thereby obtains an instruction stream corresponding to the fetch request. If the fetch request carries a switching mark and the switching mark indicates at least an instruction position where a decoder group switching occurs, the instruction position in the instruction stream where a decoder group switching occurs may be determined according to the switching mark carried in the fetch request.

[0030] It will be understood that an instruction stream is a set of instruction sequences containing several instructions, and if there is no clear boundary in the instruction sequence, it is impossible to determine the end position of an instruction in the instruction sequence. In an embodiment of the present disclosure, if the boundary of the instruction stream can be determined by determining an instruction position in the instruction stream where a decoder group switch occurs in accordance with a switching mark carried in a fetch request, the instruction position may be considered as the end position. If the instruction corresponding to the instruction position is designated as the target instruction, the instruction position becomes the end position of the target instruction, and thereby the end position of the target instruction in the instruction stream can be determined according to the instruction position indicated by the switching mark carried in the fetch request.

[0031] Since the switching mark is used to indicate at least the instruction position where the decoder group switching is performed, the setting position of the switching mark in the fetch request does not affect the instruction stream fetched by the instruction cache and does not destroy the structure of the fetched instruction stream. In the embodiment of the present disclosure, the setting position and expression format of the switching mark are not limited to a specific one, and may be, for example, an indication area existing outside the instruction stream fetched by the instruction cache, or may be represented by a switching mark indication bit.

[0032] In step S23, the instruction stream is assigned to a plurality of decoder groups according to the instruction position and decoded in parallel, and a switching mark is attached to the target microinstruction obtained by decoding the target instruction, which is the instruction corresponding to the instruction position.

[0033] In some embodiments, based on the instruction stream fetched by the instruction cache, the instruction allocation unit may allocate the instruction stream to multiple decoder groups for parallel decoding according to the instruction position (i.e., the instruction position at which the decoder group switching occurs). In one optional example, the instruction allocation unit may divide the instruction stream according to the instruction position to obtain multiple instruction groups, and further allocate the multiple instruction groups to multiple decoder groups for parallel decoding by the multiple decoder groups.

[0034] Furthermore, in some embodiments, dividing the instruction stream according to the instruction position by the instruction allocation unit may involve dividing the instruction stream into a plurality of instruction groups using the instruction position in the instruction stream as a boundary, where a target instruction that is a boundary between two adjacent instruction groups is divided as if it were in the previous instruction group. Thus, when allocating the instruction stream to a plurality of decoder groups for parallel decoding, the instruction allocation unit may allocate a decoder group different from the decoder group allocated to the previous instruction group to the next instruction group according to a switching mark corresponding to the target instruction divided as if it were in the previous instruction group, where the switching mark corresponding to the target instruction may be a switching mark corresponding to indicating the end position of the target instruction.

[0035] In addition, after the multiple decoder groups perform the decoding operations on the instruction groups assigned thereto to obtain microinstructions, in order to enable the microinstructions decoded by the multiple decoder groups to be merged in accordance with the fetch order, the embodiment of the present disclosure may analyze and translate the target instruction corresponding to the instruction position, and then mark the target microinstruction obtained by decoding the target instruction with a switching mark. As an optional implementation, the target microinstruction obtained by decoding the target instruction may be a combination of two microinstructions, one of which is a microinstruction without a switching mark and the other is a microinstruction with a switching mark.

[0036] In some embodiments, the embodiments of the present disclosure may, after obtaining microinstructions decoded by multiple decoder groups, fuse the microinstructions decoded by the multiple decoder groups according to the switching marks attached to the target microinstructions to obtain microinstructions corresponding to the fetch order. It will be understood that in order to achieve complete operation on the program, the microinstructions decoded by the multiple decoder groups need to be fuse, and the order of the microinstruction sequence obtained by fusing the microinstructions also needs to correspond to the fetch order.

[0037] In an embodiment of the present disclosure, when a switching mark is carried in a fetch request, the switching mark indicates at least an instruction position where a decoder group switching will occur. Accordingly, a fetch request may acquire a fetched instruction stream, determine an instruction position in the instruction stream where a decoder group switching will occur according to the switching mark carried in the fetch request, and further assign the instruction stream to multiple decoder groups according to the instruction position for parallel decoding, and attach a switching mark to a target microinstruction obtained by decoding a target instruction corresponding to the instruction position. In an embodiment of the present disclosure, the switching mark may indicate an instruction position where a decoder group switching will occur, and the fetch request may transparently transmit the switching mark to an instruction position in the fetched instruction stream, thereby dividing the fetched instruction stream based on the instruction position and assigning it to multiple decoder groups for parallel decoding, thereby effectively improving the decoding efficiency of the processor. Furthermore, the embodiments of the present disclosure may transmit the switching mark to the target microinstruction transparently by analyzing and translating the boundary target instruction, and after the microinstructions decoded by the multiple decoder groups are obtained, the microinstructions decoded by the multiple decoder groups may be merged according to the switching mark to obtain the microinstruction corresponding to the fetch order, in order to facilitate accurate execution of the microinstructions.

[0038] In some embodiments, Figure 2C shows yet another architecture block diagram of a processor provided in accordance with at least one embodiment of the present disclosure. As shown by combining Figures 2A and 2C, in the processor shown in Figure 2C, each decoder group is provided with a corresponding instruction queue and microinstruction queue, for example, decoder groups 1031 to 103n are provided with instruction queues 2021 to 202n and microinstruction queues 2031 to 203n, respectively, and one decoder group corresponds to one instruction queue and one microinstruction queue. Here, the instruction queue of the decoder group is for holding the instruction group assigned by the instruction allocation unit to the decoder group, i.e., the instruction queue may hold the instructions to be decoded by the decoder group, for example, instruction queue 2021 holds the instructions to be decoded by decoder group 1031, and similarly, instruction queue 202n holds the instructions to be decoded by decoder group 103n, where, when realizing parallel decoding of multiple decoder groups, as long as the speed at which the instruction queue of each decoder group holds the instructions to be decoded is faster than the decoding speed of the decoder group, the decoder group can continuously obtain and decode instructions from the instruction queue, thereby realizing parallel decoding of multiple decoder groups. The microinstruction queue of the decoder group is for holding microinstructions obtained by decoding the decoder group, for example, microinstruction queue 2031 holds the microinstructions decoded by decoder group 1031, and similarly, microinstruction queue 203n holds the microinstructions decoded by decoder group 103n. In order to fuse the microinstructions decoded by each decoder group, the processor is further provided with a fusion unit 204 that can read and fuse instructions from multiple microinstruction queues so that the order of the fused microinstructions corresponds to the fetch order.

[0039] Based on the principle of the method flow shown in Figure 2B, the processor architecture shown in Figure 2C, in the decoding process, the switching mark in the fetch request is transmitted transparently to the microinstruction by the corresponding instruction, to realize parallel decoding of multiple decoder groups, and the microinstructions may be merged according to the fetch order, and the optional specific process is as follows:

[0040] The branch prediction unit 101 generates a fetch request carrying a switching mark, issues the fetch request to the instruction cache 102, and reads the corresponding instruction stream in response to the fetch request from the instruction cache 102. Here, the switching mark in the fetch request indicates the instruction position where the decoder group switching is performed, and does not affect the fetch address's search for the instruction corresponding to the instruction position in the instruction cache.

[0041] The instruction cache 102 reads the instruction stream according to the fetch address of the fetch request, where the switching mark carried in the fetch request does not affect the fetching of instructions in the instruction cache. After reading the instruction stream, the instruction cache 102 can determine the instruction position in the instruction stream where the decoder group switching occurs according to the switching mark carried in the fetch request.

[0042] The instruction allocation unit 201 divides the instruction stream according to the instruction position, obtains a plurality of instruction groups, and assigns the plurality of instruction groups to instruction queues 2021-202n corresponding to decoder groups 1031-103n. As one optional implementation, the switching marks may indicate a plurality of instruction positions, thereby determining a plurality of instruction positions in the instruction stream. When the instruction allocation unit divides the instruction stream, it may perform division once when one of the instruction positions is recognized in the instruction stream, dividing the target instruction corresponding to the instruction position into a previous instruction group, and assigning a decoder group different from the decoder group assigned to the previous instruction group to the next instruction group according to the switching mark corresponding to the target instruction divided into a previous instruction group. In this way, the instruction stream is divided into a plurality of instruction groups using the instruction positions as boundaries, and the plurality of instruction groups are assigned to a plurality of decoder groups for parallel decoding.

[0043] In some embodiments, the instruction allocation unit 201 may hold the first instruction group of the multiple instruction groups in an instruction queue corresponding to a default decoder group based on the instruction queues for holding instructions to be decoded that are set corresponding to the decoder groups, but for an instruction group that is not the first instruction group of the multiple instruction groups, the instruction allocation unit 201 may determine a decoder group from the multiple decoder groups that is different from the decoder group assigned to the previous instruction group according to a switching mark corresponding to a target instruction in the previous instruction group, and further hold this non-first instruction group in the instruction queue corresponding to the determined decoder group.

[0044] In realizing the option of assigning a decoder group to a non-first instruction group of the plurality of instruction groups, a decoder group to be assigned to each of the non-first instruction groups may be determined from the plurality of decoder groups in sequence according to the order of the plurality of decoder groups, depending on a switching mark corresponding to a target instruction in an instruction group preceding the non-first instruction group. For example, if the first decoder group 1031 is a default decoder group, the first instruction group after the instruction stream is divided is assigned to decoder group 1031, and then, according to the order of the decoder groups, each of the non-first instruction groups is assigned to a decoder group following decoder group 1031 up to decoder group 103n in sequence.

[0045] In addition, the allocation principle by which the instruction allocation unit allocates decoder groups to instruction groups may be to allocate them according to the order of the decoder groups, and allocate a decoder group to the next instruction group that is different from the decoder group allocated to the previous instruction group according to the switching mark corresponding to the target instruction in the previous instruction group, thereby realizing a rational allocation of instruction groups in the instruction queues corresponding to the decoder groups, ensuring that multiple decoder groups can read instructions to be decoded in the corresponding instruction queues, and realizing parallel decoding of multiple decoder groups.

[0046] In another embodiment, the switching mark may further include information about a decoder group to be switched to, in order to specifically indicate the decoder group to be switched to. This allows the instruction allocation unit to assign a specific decoder group to the next instruction group based on the switching mark corresponding to the target instruction in the previous instruction group, thereby realizing the allocation of decoder groups to instruction groups regardless of the order of the decoder groups. For example, for decoder groups 1031 to 103n, if the first switching mark records information about decoder group 103n, the first instruction group is assigned to the default decoder group, and the next instruction group is assigned to decoder group 103n, which is specifically indicated by the first switching mark, and decoding is performed by decoder group 103n. If the next switching mark specifically indicates decoder group 1031, the decoder group assigned to the next instruction group is 1031, and decoding is performed by decoder group 1031. In this way, the instruction allocation unit assigns corresponding decoder groups to instruction groups according to the decoder groups to be switched to, which are specifically indicated by the switching mark, until the assignment of instruction groups is completed.

[0047] Furthermore, the default decoder group may be the first decoder group assigned according to the order, or may be a decoder group designated and assigned by the processor, and this disclosure does not place excessive restrictions on this.

[0048] Next, referring to FIG. 2C, the decoder groups 1031 to 103n store the decoded microinstructions in the microinstruction queues 2031 to 203n, and if the instruction to be decoded is a target instruction, the decoder groups 1031 to 103n may decode and obtain a target microinstruction corresponding to the target instruction, and may attach a switching mark to the target microinstruction according to the instruction position in the target instruction corresponding to the switching mark.

[0049] The fusion unit 204 reads microinstructions from the microinstruction queues 2031-203n and fuses the read microinstructions to obtain a sequence of microinstructions that can be executed. When the fusion unit 204 realizes the fusion of microinstructions in the microinstruction queues 2031-203n, the fusion unit 204 may sequentially read and fuse the microinstructions from the microinstruction queues 2031-203n based on the switching marks attached to the target microinstructions. For example, the fusion unit reads microinstructions from the microinstruction queue 2031 according to the order of the microinstruction queues. When a target microinstruction marked with a switching mark is read from the microinstruction queue 2031, the fusion unit switches to the next microinstruction queue in the microinstruction queue 2031 in order and reads a microinstruction from that microinstruction queue. When a target microinstruction marked with a switching mark is read from this microinstruction queue, the fusion unit similarly switches to the next microinstruction queue and continues reading microinstructions until the reading of the microinstruction is completed.

[0050] In some embodiments, the first microinstruction queue read by the fusion unit may correspond to the instruction queue that is assigned first in the instruction group (e.g., a microinstruction queue and an instruction queue that belong to the same decoder group), and in one example, if the instruction allocation unit assigns the first instruction group to the instruction queue 2021 corresponding to the decoder group 1031, the fusion unit will first read the microinstructions in the microinstruction queue 2031 when fusing the microinstructions, so as to support the fused microinstruction queues being assigned to the fetch order.

[0051] In some other embodiments, a switch mark corresponding to a target instruction may specifically indicate a decoder group to switch to, or a switch mark attached to a target microinstruction obtained by decoding the target instruction may specifically indicate a microinstruction queue to switch to. Thus, when fusing microinstructions, the fusion unit realizes out-of-order reading of the microinstruction queue based on a read microinstruction queue that can be switched based on the switch mark attached to the target microinstruction. In one example, assuming that a target microinstruction exists in the microinstruction queue 2031 and the switch mark attached to the target microinstruction specifically indicates the microinstruction queue 203n to switch to, when the fusion unit reads the switch mark attached to the target microinstruction in the microinstruction queue 2031, the fusion unit may switch to the microinstruction queue 203n to continue reading the microinstruction. When the fusion unit reads that the switch mark attached to the target microinstruction in the microinstruction queue 203n specifically indicates the microinstruction queue 2031 to switch to, the fusion unit may switch to the microinstruction queue 2031 to read the microinstruction.

[0052] To facilitate understanding of the principle of dividing an instruction stream based on the position of an instruction in the instruction stream where decoder group switching occurs, two decoder groups are introduced below as an example. FIG. 3A illustrates a schematic diagram of instruction stream division. As shown in FIG. 3A, the instruction stream includes instructions 310-31m, where m is the number of instructions in the instruction stream. This number may be determined based on actual circumstances, and the embodiments of the present disclosure are not limited thereto. If the instruction position where decoder group switching occurs, indicated by a switching mark in instructions 310-31m, is indicated by a dashed arrow in the figure, instruction 31k corresponding to the instruction position may be the target instruction, and the instruction position may be the end position of target instruction 31k. Here, the switching mark may be set by, for example, a branch predictor.

[0053] As shown in FIG. 3A, an embodiment of the present disclosure may separate instruction streams 310-31m using the instruction position as a boundary for separating the instruction stream. Here, target instruction 31k is adjacent to instruction 31k+1. When separating the instruction stream according to the instruction position, target instruction 31k is separated into the previous instruction group (i.e., instructions 310-31k are one group), and instruction 31k+1 is separated into the next instruction group (i.e., instructions 31k+1-31m are one group), resulting in two adjacent, different instruction groups. When there are multiple switching marks, there are multiple instruction positions in the instruction stream and multiple corresponding target instructions. This method may be used to separate the instruction stream and obtain multiple instruction groups.

[0054] 3A , an embodiment of the present disclosure may allocate the first group of separated instructions (i.e., instruction 310 through target instruction 31k) to an instruction queue corresponding to decoder group 0 according to the order of decoder group 0 and decoder group 1, and perform a decode operation on instructions 310 through target instruction 31k by decoder group 0. Because target instruction 31k is the instruction corresponding to the instruction position where decoder group switching occurs, it is necessary to allocate a decoder group other than decoder group 0 to instructions after target instruction 31k. Based on this, the instruction group of instructions 31k+1 through 31m is allocated to an instruction queue corresponding to decoder group 1, and perform a decode operation on instructions 31k+1 through 31m by decoder group 1.

[0055] To facilitate understanding of the principle of microinstruction fusion based on the microinstruction marked with a switch mark, two decoder groups are introduced below as examples. Figure 3B exemplarily shows a schematic diagram of microinstruction fusion.

[0056] Decoder group 0 decodes the instruction group of instruction 310 to target instruction 31k to obtain microinstruction 320 to target microinstruction 32k (not shown). Here, decoder group 0 analyzes and translates target instruction 31k, and the obtained target microinstruction 32k is a combination of microinstruction 32k' and microinstruction 32k'', where microinstruction 32k' is a microinstruction without a switching mark and microinstruction 32k'' is a microinstruction with a switching mark. Decoder group 1 decodes the instruction group of instruction 31k+1 to instruction 31m to obtain microinstruction 32k+1 to microinstruction 32m. Microinstruction 320 to target microinstruction 32k are stored in the microinstruction queue of decoder group 0, and microinstruction 32k+1 to microinstruction 32m are stored in the microinstruction queue of decoder group 1.

[0057] When fusing microinstructions, microinstructions may be read first from the microinstruction queue of decoder group 0 in accordance with the order of the decoder groups. When a microinstruction 32k'' marked with a switch mark is read out of the target microinstruction 32k, the microinstruction queue of decoder group 1 is switched to read the microinstruction. In other words, when a microinstruction marked with a switch mark is read out from the microinstruction queue currently being read out, the microinstruction queue is switched to the next microinstruction queue to read the microinstruction until the reading of the microinstruction is completed. The fetched instruction stream is divided according to the instruction position corresponding to the instruction indicated by the switch mark in the target instruction, and assigned to multiple decoder groups for parallel decode. Therefore, when the decoded microinstructions are read out, the microinstructions may be read out by switching among the microinstruction queues of the multiple decoder groups in accordance with the switch mark marked in the target instruction, and the read microinstructions can be associated with the fetch order.

[0058] As described above, when a processor has multiple decoder groups, a switching mark in a fetch request indicates the instruction position where the decoder group switching occurs, and the switching mark is transmitted transparently to the microinstruction obtained by decoding the decoder group according to the target instruction in the instruction stream in response to the fetch request, thereby supporting parallel decoding of multiple decoder groups and sequential fusion of microinstructions, and effectively improving the decoding efficiency of the processor. Although multiple decoder groups in a processor can realize parallel instruction decoding, obtaining microinstructions requires a fetch and decode process, which makes the process of obtaining microinstructions more complicated. Based on this, an embodiment of the present disclosure further provides a high-performance processor with a Micro-Op Cache (OC) to improve the speed of obtaining microinstructions.

[0059] 4A is an architectural block diagram of a processor having a microinstruction cache. As shown in FIG. 4A, branch prediction unit 101 issues generated fetch requests to microinstruction cache 104, which may be used to cache microinstructions. In some embodiments, microinstruction cache 104 may include multiple table entries, each capable of accommodating multiple microinstructions. A fetch request generated by branch prediction unit 101 may correspond to multiple microinstruction cache table entries.

[0060] When a fetch request generated by the branch prediction unit retrieves a microinstruction from the microinstruction cache, the microinstruction cache may perform a hit check between the start address of the fetch request and the addresses of the first microinstruction of all table entries. If a hit occurs, the microinstruction in the first table entry is obtained. If the end address of the last microinstruction in the table entry of the microinstruction cache is less than the end address of the address range of the fetch request, the end address of the address range corresponding to the last microinstruction must be used to further perform a hit check with the addresses of the first microinstruction of all table entries. If a hit occurs, the microinstruction in the second table entry is obtained. By repeating the above process until the end address of the address range in the fetch request is less than the end address of the last microinstruction in the table entry, microinstructions can be read from the microinstruction cache based on the fetch request.

[0061] In some embodiments, if all of the addresses in the fetch request generated by the branch prediction unit can hit in the microinstruction cache, the microinstruction cache can output the corresponding microinstruction, and if the starting address in the fetch request generated by the branch prediction unit does not hit a table entry in the microinstruction cache, the microinstruction cache cannot output the microinstruction.

[0062] Based on a processor having a microinstruction cache and a decoder group, the processor may include multiple decoding modes, including a decoder mode in which a microinstruction is obtained by decoding the decoder group, and a microinstruction cache mode in which a microinstruction is obtained by searching the microinstruction cache. Figure 4B illustrates an exemplary architecture block diagram of a processor provided in accordance with at least one embodiment of the present disclosure.

[0063] As shown in FIG. 4B, the processor of the embodiment of the present disclosure is compatible with a decoder mode and a microinstruction cache mode, and a fetch request carrying a switching mark generated by the branch prediction unit 101 can obtain a microinstruction through two paths, which may be a path (corresponding to the decoder mode) in which the microinstruction is obtained by decoding the decoder group, and a path (corresponding to the microinstruction cache mode) in which the microinstruction is obtained by searching the microinstruction cache.

[0064] In response to obtaining a microinstruction by decoding a decoder group, i.e., in decoder mode, the branch prediction unit 101 issues a fetch request carrying a switching mark to the instruction cache 102, which fetches an instruction stream according to the address in the fetch request, divides the instruction stream according to the instruction position in the instruction stream via the instruction allocation unit 201, obtains a plurality of instruction groups, and assigns the obtained plurality of instruction groups to instruction queues 2021-202n corresponding to the plurality of decoder groups. The plurality of decoder groups 1031-103n reads instructions to be decoded in their corresponding instruction queues 2021-202n, performs decoding operations, obtains microinstructions, and further stores the decoded microinstructions in the corresponding microinstruction queues, and may further cache the decoded microinstructions in the microinstruction cache 104 based on the existence of the microinstruction cache 104.

[0065] In response to obtaining a microinstruction by searching the microinstruction cache, i.e., in the microinstruction cache mode, the branch prediction unit 101 issues a fetch request carrying a switching mark to the instruction cache 102, so that in response to a hit of the fetch request in the microinstruction cache, the microinstruction can be output correspondingly by the microinstruction cache, and based on the existence of a microinstruction queue, the obtained microinstruction can be stored in a microinstruction queue corresponding to the default decoder group.

[0066] In some embodiments, if the fetch request hits the microinstruction cache, the retrieved microinstruction is stored in a microinstruction queue corresponding to a default decoder group, where the microinstruction queue corresponding to the default decoder group may be the microinstruction queue corresponding to the first decoder group determined according to the order, or the microinstruction queue corresponding to a decoder group specified by the processor, or the microinstruction queue corresponding to the decoder group determined by the last instruction decoded by the decoder group before the decode mode was switched to the microinstruction cache mode, depending on whether there is an instruction position corresponding to the indication of the switching mark.

[0067] In one optional implementation, if the last instruction decoded by a decoder group before the processor's decode mode is switched from decoder mode to microinstruction cache mode does not have an instruction position corresponding to the indication of the switching mark, the microinstruction read in the microinstruction cache is held in the microinstruction queue corresponding to the decoder group that decoded the last instruction before the decode mode was switched. 5A is a schematic diagram of an option for switching to a microinstruction cache mode and holding microinstructions in at least one embodiment of the present disclosure. As shown in FIG. 5A, in decoder mode, an instruction stream (i.e., instruction 510 to instruction 51m) is read from the instruction cache in response to a fetch request. Here, if the instruction position where the decoder group is switched, as indicated by the switching mark, is as shown by the dashed line in the figure, instruction 51k corresponding to this instruction position is the target instruction, and there is no instruction position where the decoder group is switched at the end position of the instruction stream. The instruction stream is divided according to the instruction position to obtain two adjacent different instruction groups (i.e., instruction 510 to instruction 51k and instruction 51k+1 to instruction 51m), and the corresponding decoder groups are assigned. Then, the last instruction 51m is decoded by decoder group 1 to obtain microinstruction 52m, which does not have a switching mark, and is held in the corresponding microinstruction queue 1. After the decode mode is switched to the microinstruction cache mode, when the fetch address is searched for and hit in the microinstruction cache and a microinstruction (i.e., microinstruction 530 to microinstruction 53m) is read, the read microinstruction 530 to microinstruction 53m is correspondingly stored in the microinstruction queue 1.

[0068] As another optional implementation, if the last instruction decoded by the decoder group before the processor's decode mode switches from decoder mode to microinstruction cache mode corresponds to the instruction position where the decoder group is switched, as indicated by the switching mark, the microinstruction read in the microinstruction cache is held in the microinstruction queue corresponding to the decoder group after the switch indicated by the switching mark, according to the switching mark corresponding to the last instruction. 5B is a schematic diagram of another option for switching to a microinstruction cache mode and holding microinstructions in at least one embodiment of the present disclosure. As shown in FIG. 5B, in decoder mode, an instruction stream (i.e., instruction 510 to instruction 51m) is read from the instruction cache in response to a fetch request. Here, the last instruction 51m corresponds to the instruction position where the decoder group is switched (the instruction position indicated by switching mark 2 in the figure), as indicated by a switching mark. After dividing the instruction stream and assigning decoder groups, instructions 510 to 51k are decoded by decoder group 0, and instructions 51k+1 to 51m are decoded by decoder group 1. Of the microinstructions 52m' and 52m'' obtained by decoding the last instruction 51m by decoder group 1, microinstruction 52m'' is marked with a switching mark, and the microinstruction obtained by decoder group 1 is held in the corresponding microinstruction queue 1. After the decode mode switches to the microinstruction cache mode, when the fetch address is searched for and hit in the microinstruction cache and a microinstruction (i.e., microinstruction 530 to microinstruction 53m) is read, the read microinstruction 530 to microinstruction 53m is stored in the microinstruction queue (i.e., microinstruction queue 0) corresponding to the destination decoder group (i.e., decoder group 0) indicated by the switching mark corresponding to the last instruction 51m before the decode mode switches.

[0069] It will be appreciated that the switching mark carried in the fetch request indicates at least the instruction location where the decoder group switching occurs, but since the microinstruction cache mode does not decode instructions via decoder groups, the microinstruction cache may not respond to the switching mark carried in the fetch request, and the microinstructions retrieved may not be marked with the switching mark.

[0070] In some other embodiments, if a fetch request does not hit the microinstruction cache in the microinstruction cache mode, the decoder mode is entered, and instructions corresponding to the fetch request are decoded in parallel by multiple decoder groups in the decoder mode to obtain microinstructions, and the microinstructions decoded in the decoder mode may be stored in the microinstruction cache. Here, when switching to the decoder mode, the instruction stream fetched by the fetch request is divided according to the instruction position indicated by the switching mark, and the first instruction group of the obtained multiple instruction groups is assigned to an instruction queue corresponding to a default decoder group, and the instruction queue corresponding to the default decoder group may be the instruction queue corresponding to the first decoder group determined in order, or may be the instruction queue corresponding to a decoder group specified by the processor, or may be the instruction queue corresponding to the corresponding decoder group determined according to whether or not the last instruction decoded by the decoder group before entering the microinstruction cache mode exists in the instruction position corresponding to the instruction indicated by the switching mark.

[0071] In one optional implementation, if the last instruction decoded by a decoder group before the processor's decode mode switches to microinstruction cache mode does not have an instruction position corresponding to the indication of the switching mark, then after switching from microinstruction cache mode to decoder mode, the first instruction group of multiple instruction groups obtained by segmenting the instruction stream is assigned to the instruction queue corresponding to the decoder group that decoded the last instruction before switching from microinstruction cache mode. Continuing with Figure 5A, if the last instruction 51m decoded by decoder group 1 before the processor's decode mode switches to microinstruction cache mode does not have an instruction position corresponding to the indication of the switching mark, and therefore the fetch address in the fetch request does not hit in the microinstruction cache when switching to microinstruction cache mode, then the decode mode switches back to decoder group mode, and the first instruction group obtained by segmenting the instruction stream (i.e., instructions 510 through 51k) is assigned to instruction queue 1 corresponding to decoder group 1 in accordance with the instruction position indicated by the switching mark carried in the fetch request (the position indicated by the dashed line in Figure 5A).

[0072] In another optional implementation, if the last instruction decoded by the decoder group before the processor's decode mode is switched to the microinstruction cache mode contains an instruction position corresponding to the indication of the switching mark, then after switching from the microinstruction cache mode to the decoder mode, the first instruction group of the multiple instruction groups obtained by dividing the instruction stream is assigned to the instruction queue corresponding to the decoder group to which the switch is to be made, as indicated by the switching mark corresponding to the last instruction, before switching from the microinstruction cache mode. Continuing to refer to Figure 5B, before the processor's decode mode switches to microinstruction cache mode, the last instruction 51m decoded by decoder group 1 contains an instruction position corresponding to the indication of the switching mark. Therefore, when switching to microinstruction cache mode, if the fetch address in the fetch request does not hit in the microinstruction cache, the decode mode switches back to decoder group mode, and the first instruction group (i.e., instructions 510 to 51k) obtained by dividing the instruction stream according to the instruction position indicated by the switching mark carried in the fetch request (the position indicated by switching mark 2 in Figure 5B) is assigned to instruction queue 0 corresponding to decoder group 0 after switching, as indicated by the switching mark corresponding to last instruction 51m, before switching from microinstruction cache mode.

[0073] In an embodiment of the present disclosure, in a processor having a microinstruction cache and a decoder, a fetch request may carry a switching mark, which may indicate at least an instruction position where a decoder group switching occurs. In this way, in decoder mode (corresponding to a microinstruction being obtained by decoding a decoder group), the switching mark may be transmitted transparently through the target instruction and the microinstruction, thereby supporting parallel decoding of multiple decoder groups and improving decoding efficiency. Meanwhile, in the processor's microinstruction cache mode (corresponding to a microinstruction being obtained by searching the microinstruction cache), the embodiment of the present disclosure does not need to perform processing based on the switching mark carried in the fetch request, thereby being compatible with the processor's microinstruction cache mode. The embodiment of the present disclosure supports parallel decoding in a processor that supports both a decoder mode and a microinstruction cache mode, thereby improving decoding performance. That is, the embodiment of the present disclosure supports parallel decoding in decoder mode when the processor is compatible with the microinstruction cache mode, thereby improving decoding performance.

[0074] As an optional example, Figure 6 shows a flowchart of another optional decoding method provided by an embodiment of the present disclosure, which can be executed by the processor shown in Figure 4B, where the contents described below can be referenced correspondingly to the contents described above. Referring to Figure 6, this method may include the following steps:

[0075] Step S60: A fetch request is generated.

[0076] Optionally, step S60 may be performed by a branch prediction unit, which may set a switch mark in the fetch request to indicate the instruction position where the decoder group switch occurs depending on the branch prediction jump result.

[0077] Step S61: Determine whether the current processor is in the microinstruction cache mode. If NO, execute step S62; if YES, execute step S69.

[0078] Here, in the microinstruction cache mode, a microinstruction is obtained by searching the microinstruction cache.

[0079] Step S62: The instruction cache is accessed and the instruction stream is fetched in response to the fetch request.

[0080] Furthermore, when an instruction caches an instruction stream read in response to a fetch request, the switching mark carried in the fetch request is transmitted transparently outside the fetched instruction stream, and based on the switching mark indicating at least the instruction position where the decoder group switching occurs, the instruction position in the instruction stream where the decoder group switching occurs can be determined, and further, the target instruction corresponding to the instruction position can be determined.

[0081] Step S63: Determine whether or not a switching mark exists in the fetch request. If NO, execute step S64; if YES, execute step S65.

[0082] Step S64: Send the instruction stream to the default decoder group, decode the instructions by the default decoder group, and store the obtained microinstructions in the corresponding microinstruction queue.

[0083] It will be understood that the switching mark carried in the fetch request is used to indicate at least the instruction position where the decoder group switching is performed, and when the switching mark is not present in the fetch request, there is no need to switch the decoder group, and the instruction stream is decoded by the default decoder group, and the obtained microinstructions are stored in the microinstruction queue corresponding to the default decoder group. Here, the default decoder group may be the first decoder group assigned in order, or may be a decoder group designated and assigned by the processor, and in the instruction processing process, for each fetch request, the default decoder group may be the decoder group to which the current switch is made. The default decoder group in the embodiments of the present disclosure is not designated as a fixed decoder group, but may be selected according to actual needs.

[0084] Step S65: The instruction stream is divided according to the switching mark, and the target instruction and the instruction before the target instruction are assigned to an instruction queue corresponding to the default decoder group, and are decoded by the first decoder group, and the obtained microinstruction is stored in the corresponding microinstruction queue, where a switching mark is attached to the target microinstruction obtained by decoding the target instruction.

[0085] Step S66: It is determined whether or not there is a target command corresponding to the switching mark among the remaining commands. If NO, step S67 is executed; if YES, step S68 is executed.

[0086] Step S67: The remaining instructions are assigned to an instruction queue corresponding to a next decoder group different from the previous decoder group, and are decoded by this next decoder group, and the obtained microinstructions are stored in the corresponding microinstruction queue.

[0087] Step S68: The target instruction and the instruction preceding the target instruction are assigned to an instruction queue corresponding to a next decoder group different from the previous decoder group, and are decoded by this next decoder group. The microinstruction obtained is stored in the corresponding microinstruction queue. Here, a switch mark is attached to the microinstruction obtained by decoding the target instruction, and the process returns to step S66 for execution.

[0088] Since instructions are assigned to the instruction queue of a decoder group, and the decoder group reads and decodes the instructions from the instruction queue, when the rate at which instructions are assigned to the instruction queue is faster than the decoding rate of the decoder group, the embodiment of the present disclosure can realize dividing the instruction stream and assigning them to the instruction queues of multiple decoder groups, and having the multiple decoder groups perform parallel decoding based on the instructions assigned to the instruction queues. Furthermore, steps S65 to S68 are an optional realization method according to the embodiment of the present disclosure, in which the instruction stream is divided based on the switching mark corresponding to the target instruction, to obtain multiple instruction groups, and the multiple instruction groups are assigned to multiple decoder groups for parallel decoding.

[0089] Step S69: Fetch a microinstruction from the microinstruction cache, and store the obtained microinstruction in the corresponding microinstruction queue.

[0090] The selection of the microinstruction queue is as described above and will not be described here.

[0091] The premise for fetching a microinstruction from the microinstruction cache based on a fetch request is that the fetch request hits the microinstruction cache. If the fetch request does not hit the microinstruction cache, the decoder mode is entered and step S62 is executed.

[0092] Here, in the decoder mode, a microinstruction is obtained by decoding by a decoder group.

[0093] Step S70: A microinstruction is read from the microinstruction queue corresponding to the first decoder group.

[0094] Step S71: Determine whether the read microinstruction has a switch mark attached, and if YES, execute step S72; if NO, return to step S70 and execute until the reading of the microinstruction is completed.

[0095] Step S72: Switch to the microinstruction queue corresponding to the next decoder group and read out a microinstruction, then return to step S71.

[0096] After the microinstruction has been read, the embodiments of the present disclosure may further execute the microinstruction.

[0097] The embodiments of the present disclosure can realize support for parallel decoding in a processor that supports a decoder mode and a microinstruction cache mode, thereby improving decoding performance.

[0098] The embodiment of the present disclosure further provides a processor, the configuration of which may refer to FIG. 4B, where the contents described below may be considered as a decoding method provided by the processor to realize the embodiment of the present disclosure, and functional modules configured as needed, and the contents described below may be referred to in correspondence with the contents described above. This processor includes at least: a branch prediction unit for generating a fetch request carrying at least one switching mark indicating an instruction position where at least a decoder group switching occurs; an instruction cache for responsively obtaining microinstructions by decoding the decoder groups to obtain the instruction stream fetched by said fetch request and for determining, in response to a switch mark carried by said fetch request, the instruction position in said instruction stream at which a switch of decoder groups is to be made; an instruction allocation unit for allocating the instruction stream to a plurality of decoder groups for parallel decoding according to the instruction position; a decoder group for decoding the assigned instruction to obtain a microinstruction, the number of said decoder groups being plural, wherein when said decoder group decodes a target instruction, a switching mark is attached to the target microinstruction obtained by decoding the target instruction, and said target instruction is an instruction corresponding to said instruction position; and a microinstruction cache for acquiring, in response to a microinstruction being obtained by searching the microinstruction cache, a microinstruction corresponding to the fetch request and not having a switching mark attached thereto, from the microinstruction cache if the fetch request hits in the microinstruction cache.

[0099] Optionally, the instruction location is an end location of a target instruction, and the step of determining, by the instruction cache, the instruction location in the instruction stream at which a decoder group switch occurs in response to a switch mark carried in the fetch request comprises: The method may further include determining an end position of the target instruction in the instruction stream according to an instruction position indicated by a switching mark carried in the fetch request.

[0100] Optionally, the step by the instruction allocation unit for allocating the instruction stream to a plurality of decoder groups for parallel decoding according to the instruction position comprises: The method may include dividing the instruction stream into a plurality of instruction groups according to the instruction position, and allocating the plurality of instruction groups to a plurality of decoder groups for parallel decoding.

[0101] Optionally, the instruction allocation unit's step of dividing the instruction stream into a plurality of instruction groups according to the instruction position comprises: dividing the instruction stream into a plurality of instruction groups using the instruction positions in the instruction stream as boundaries, wherein a target instruction that is a boundary between two adjacent instruction groups is divided into two instruction groups so that it is in a previous instruction group; The step of the instruction allocation unit allocating the plurality of instruction groups to a plurality of decoder groups for parallel decoding includes: and assigning a decoder group to the next instruction group that is different from the decoder group assigned to the previous instruction group in response to a switching mark corresponding to the target instruction that was carved out as being in the previous instruction group.

[0102] optionally configuring an instruction queue corresponding to one decoder group to hold instructions to be decoded; the instruction allocation unit assigning a decoder group to a next instruction group that is different from the decoder group assigned to the previous instruction group in accordance with a switching mark corresponding to a target instruction that has been carved out as being in the previous instruction group, retaining a first instruction group of the plurality of instruction groups in an instruction queue corresponding to a default decoder group; For an instruction group that is not the first of the plurality of instruction groups, determining a decoder group from the plurality of decoder groups that is different from the decoder group assigned to the previous instruction group in accordance with a switching mark corresponding to a target instruction in the previous instruction group, and storing this non-first instruction group in an instruction queue corresponding to the determined decoder group.

[0103] Optionally, the step of the instruction allocation unit determining, for an instruction group that is not the first of the plurality of instruction groups, a decoder group different from a decoder group assigned to a previous instruction group from the plurality of decoder groups in response to a switching mark corresponding to a target instruction in the previous instruction group, comprises: For a non-first instruction group of the plurality of instruction groups, determining a decoder group to be assigned to each of the non-first instruction groups sequentially from the plurality of decoder groups in accordance with an order of the plurality of decoder groups, in accordance with a switching mark corresponding to a target instruction in an instruction group preceding the non-first instruction group.

[0104] Optionally, the step of the instruction allocation unit retaining a first instruction group of the plurality of instruction groups in an instruction queue corresponding to a default decoder group comprises: After exiting a microinstruction cache mode and entering a decoder mode, assigning a first instruction group of the plurality of instruction groups to an instruction queue corresponding to a default decoder group, wherein in the decoder mode, microinstructions are obtained by decoding the decoder group, and in the microinstruction cache mode, microinstructions are obtained by searching a microinstruction cache; where, if there is no instruction position corresponding to the instruction indicated by the switching mark in the last instruction decoded by the decoder group before the decode mode is switched to the microinstruction cache mode, after the decode mode is subsequently switched to the decoder mode, the first instruction group is assigned to the instruction queue corresponding to the decoder group that decoded this last instruction; If an instruction position corresponding to the instruction indicated by the switching mark exists in the last instruction decoded by the decoder group before the decode mode is switched to the microinstruction cache mode, after the decode mode is subsequently switched to the decoder mode, the first instruction group is assigned to an instruction queue corresponding to the decoder group indicated by the switching mark corresponding to this last instruction.

[0105] Optionally, the processor further includes a fusion unit for, in decoder mode, merging the microinstructions decoded by the multiple decoder groups in accordance with a switching mark attached to the target microinstruction to obtain a microinstruction corresponding to the fetch order.

[0106] Optionally, one microinstruction queue is configured for each decoder group, the decoder group is also used to store the decoded microinstructions in a corresponding microinstruction queue; The step of the fusion unit fusing the microinstructions decoded by the plurality of decoder groups in accordance with the switching marks attached to the target microinstructions to obtain microinstructions corresponding to the fetch order includes: According to the switching marks attached to the target microinstructions, switching and fusing microinstructions in the microinstruction queues corresponding to each decoder group is included to obtain microinstructions corresponding to the fetch order.

[0107] Optionally, the step of the fusion unit switching and fusing microinstructions in the microinstruction queues corresponding to each decoder group according to the switching marks attached to the target microinstructions to obtain microinstructions corresponding to the fetch order comprises: The method includes starting to read microinstructions from a microinstruction queue corresponding to a default decoder group, and if a switching mark is attached to the read microinstruction, determining the next microinstruction queue from which to switch and read microinstructions according to the switching mark attached to the microinstruction until reading of microinstructions in the microinstruction queues corresponding to each decoder group is completed.

[0108] Optionally, if a switching mark is attached to the read microinstruction, the step of determining a next microinstruction queue from which to switch and read a microinstruction in accordance with the switching mark attached to the microinstruction by the fusion unit includes: If a switching mark is attached to the read microinstruction, the microinstruction queue for reading the microinstruction is switched in order from the microinstruction queue of each decoder group according to the order of the microinstruction queues in accordance with the switching mark attached to the microinstruction.

[0109] Optionally, the microinstruction cache is also used in microinstruction cache mode to hold fetched microinstructions in a microinstruction queue corresponding to the default decoder group; the decoder group is also used to store the decoded microinstructions in a microinstruction cache; Here, in the microinstruction cache mode, if the fetch request does not hit in the microinstruction cache, the decoder mode is entered.

[0110] In an embodiment of the present disclosure, a chip is also provided that can include the above-described processor.

[0111] An embodiment of the present disclosure further provides an electronic device that can include the above chip.

[0112] Although multiple embodiments of the present disclosure have been described above, the optional features introduced by each embodiment may be combined and cross-referenced with each other without contradiction, thereby expanding the range of possible embodiments, all of which may be considered to be disclosures of embodiments of the present disclosure.

[0113] Although the embodiments of the present disclosure have been disclosed as above, the present disclosure is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the scope of protection of the present disclosure shall be limited by the scope defined by the claims.

Claims

1. A decoding method applied to a processor, comprising: generating a fetch request carrying at least one switching mark indicating an instruction position where at least a decoder group switching is to occur; in response to a microinstruction being obtained by decoding a decoder group, obtaining the instruction stream fetched by the fetch request, determining an instruction position in the instruction stream where decoder group switching is to be performed according to the switching mark carried by the fetch request, allocating the instruction stream to a plurality of decoder groups for parallel decoding according to the instruction position, and attaching the switching mark to a target microinstruction obtained by decoding a target instruction which is an instruction corresponding to the instruction position, wherein the microinstruction obtained by decoding the decoder group is configured to be held in a microinstruction cache; The decoding method includes: In response to a microinstruction being obtained by searching the microinstruction cache, if the fetch request is a hit in the microinstruction cache, obtaining the microinstruction corresponding to the fetch request from the microinstruction cache.

2. The instruction position is an end position of the target instruction, and determining the instruction position in the instruction stream where decoder group switching is performed in accordance with the switching mark carried in the fetch request comprises:

2. The decoding method according to claim 1, further comprising: determining an end position of the target instruction in the instruction stream according to the instruction position indicated by the switching mark carried in the fetch request.

3. The above-mentioned assigning the instruction stream to a plurality of decoder groups according to the instruction position and decoding the instruction stream in parallel includes:

2. The decoding method according to claim 1, further comprising: dividing the instruction stream into a plurality of instruction groups according to the instruction position; and allocating the plurality of instruction groups to a plurality of decoder groups for parallel decoding.

4. The above-mentioned dividing the instruction stream into a plurality of instruction groups according to the instruction position includes: dividing the instruction stream into a plurality of instruction groups using the instruction positions in the instruction stream as boundaries, wherein a target instruction that is a boundary between two adjacent instruction groups is divided into two instruction groups so that it is in a previous instruction group; The above-mentioned assigning the plurality of instruction groups to the plurality of decoder groups for parallel decoding includes:

4. The decoding method of claim 3, further comprising: assigning a decoder group to a next instruction group that is different from the decoder group assigned to the previous instruction group in response to a switching mark corresponding to a target instruction that has been carved out as being in the previous instruction group.

5. setting up one instruction queue corresponding to one decoder group to hold instructions to be decoded, and allocating a decoder group different from the decoder group allocated to the previous instruction group to the next instruction group in accordance with the switching mark corresponding to the target instruction allocated to the previous instruction group as described above; retaining a first instruction group of the plurality of instruction groups in an instruction queue corresponding to a default decoder group; 5. The decoding method according to claim 4, further comprising: for an instruction group that is not the first of the plurality of instruction groups, determining a decoder group from the plurality of decoder groups that is different from a decoder group assigned to the previous instruction group in accordance with a switching mark corresponding to a target instruction in the previous instruction group, and storing the non-first instruction group in an instruction queue corresponding to the determined decoder group.

6. determining, for the instruction group that is not the first of the plurality of instruction groups, a decoder group different from the decoder group assigned to the previous instruction group from the plurality of decoder groups in accordance with a switching mark corresponding to a target instruction in the previous instruction group, 6. The decoding method of claim 5, further comprising: for the non-first instruction groups of the plurality of instruction groups, determining a decoder group to be assigned to each of the non-first instruction groups in sequence from the plurality of decoder groups in accordance with an order of the plurality of decoder groups in response to a switching mark corresponding to a target instruction in an instruction group preceding the non-first instruction group.

7. The step of storing the first instruction group of the plurality of instruction groups in an instruction queue corresponding to a default decoder group includes: after exiting a microinstruction cache mode and entering a decoder mode, assigning the first instruction group of the plurality of instruction groups to an instruction queue corresponding to a default decoder group, wherein in the decoder mode, microinstructions are obtained by decoding a decoder group, and in the microinstruction cache mode, microinstructions are obtained by searching the microinstruction cache; where, if the instruction position corresponding to the indication of the switching mark does not exist in the last instruction decoded by the decoder group before the decode mode is switched to the microinstruction cache mode, after the decode mode is subsequently switched to the decoder mode, the first instruction group is assigned to an instruction queue corresponding to the decoder group that decoded the last instruction; 6. The decoding method according to claim 5, further comprising: if the instruction position corresponding to the indication of the switching mark is present in the last instruction decoded by a decoder group before the decode mode is switched to the microinstruction cache mode, after the decode mode is subsequently switched to the decoder mode, allocating the first instruction group to an instruction queue corresponding to the decoder group indicated by the switching mark corresponding to the last instruction.

8. 2. The decoding method of claim 1, wherein the processor includes a plurality of decoding modes, including a decoder mode in which a microinstruction is obtained by decoding a decoder group, and a microinstruction cache mode in which a microinstruction is obtained by searching a microinstruction cache.

9. 9. The decoding method according to claim 8, further comprising: in the decoder mode, fusing the microinstructions decoded by the plurality of decoder groups according to the switching mark attached to the target microinstruction to obtain a microinstruction corresponding to a fetch order.

10. One microinstruction queue is set corresponding to one decoder group, and the decoding method includes: The method further includes storing the microinstructions decoded by each decoder group in a corresponding microinstruction queue; The above-mentioned method of fusing the microinstructions obtained by decoding the plurality of decoder groups in accordance with the switching mark attached to the target microinstruction to obtain a microinstruction corresponding to the fetch order includes:

10. The decoding method of claim 9, further comprising: switching and fusing microinstructions in a microinstruction queue corresponding to each decoder group according to the switching mark attached to the target microinstruction to obtain a microinstruction corresponding to a fetch order.

11. The above-mentioned switching and fusing of microinstructions in the microinstruction queues corresponding to each decoder group according to the switching marks attached to the target microinstructions to obtain microinstructions corresponding to the fetch order is performed by:

11. The decoding method according to claim 10, further comprising: starting to read microinstructions from a microinstruction queue corresponding to a default decoder group; and, if the read microinstruction has the switching mark attached, determining the next microinstruction queue from which to switch and read microinstructions in accordance with the switching mark attached to the microinstruction until reading of microinstructions in the microinstruction queues corresponding to each decoder group is completed.

12. If a switching mark is attached to the read microinstruction, the next microinstruction queue from which the microinstruction is to be switched and read is determined in accordance with the switching mark attached to the microinstruction.

12. The decoding method according to claim 11, further comprising: if the switching mark is attached to the read microinstruction, switching the microinstruction queue from which the microinstruction is read in order from the microinstruction queue of each decoder group in accordance with the switching mark attached to the microinstruction, in accordance with the order of the microinstruction queues.

13. 11. The decoding method according to claim 10, wherein in said microinstruction cache mode, the acquired microinstruction is held in a microinstruction queue corresponding to a default decoder group.

14. in the microinstruction cache mode, if the fetch request does not hit in the microinstruction cache, entering the decoder mode; 14. The decoding method according to claim 8, further comprising: in said decoder mode, storing the microinstructions decoded by said decoder group in said microinstruction cache.

15. a branch prediction unit configured to generate a fetch request carrying at least one switching mark indicating an instruction position where at least a decoder group switching occurs; an instruction cache configured to, in response to a microinstruction being obtained by decoding a decoder group, obtain the instruction stream fetched by said fetch request, and determine, in response to said switch mark carried by said fetch request, an instruction position in said instruction stream at which a decoder group switch will occur; an instruction allocation unit configured to allocate the instruction stream to a plurality of decoder groups for parallel decoding according to the instruction position; a decoder group configured to decode an assigned instruction to obtain a microinstruction, the number of the decoder groups being plural, wherein when the decoder group decodes a target instruction, the target microinstruction obtained by decoding the target instruction is marked with the switching mark, and the target instruction is an instruction corresponding to the instruction position; a microinstruction cache configured to hold microinstructions obtained by decoding of the decoder group, and configured to, in response to a microinstruction being obtained by searching the microinstruction cache, obtain from the microinstruction cache a microinstruction corresponding to the fetch request that does not have the switching mark if the fetch request hits in the microinstruction cache.

16. the instruction position is an end position of the target instruction, and the instruction cache determines the instruction position in the instruction stream where decoder group switching occurs in response to the switching mark carried in the fetch request, 16. The processor of claim 15, further comprising: determining an end position of the target instruction in the instruction stream in response to the instruction position indicated by the switching mark carried in the fetch request.

17. The instruction allocation unit allocates the instruction stream to a plurality of decoder groups according to the instruction position for parallel decoding, 16. The processor of claim 15, further comprising: the instruction allocation unit dividing the instruction stream into a plurality of instruction groups according to the instruction position, and allocating the plurality of instruction groups to a plurality of decoder groups for parallel decoding.

18. The instruction allocation unit divides the instruction stream according to the instruction position to obtain a plurality of instruction groups, the instruction allocation unit dividing the instruction stream into a plurality of instruction groups using the instruction positions in the instruction stream as boundaries, wherein a target instruction that is a boundary between two adjacent instruction groups is divided into two instruction groups so that it is in a previous instruction group; and assigning a decoder group to the next instruction group that is different from the decoder group assigned to the previous instruction group in response to a switching mark corresponding to the target instruction that was carved out as being in the previous instruction group.

19. setting up an instruction queue corresponding to one decoder group to hold instructions to be decoded; the instruction allocation unit assigning a decoder group to a next instruction group that is different from the decoder group assigned to the previous instruction group in accordance with a switching mark corresponding to a target instruction that has been carved out as being in the previous instruction group; the instruction allocation unit retaining a first instruction group of the plurality of instruction groups in an instruction queue corresponding to a default decoder group; 19. The processor of claim 18, further comprising: for an instruction group that is not a first instruction group of the plurality of instruction groups, determining a decoder group from the plurality of decoder groups that is different from a decoder group assigned to the previous instruction group in accordance with a switching mark corresponding to a target instruction in the previous instruction group, and storing the non-first instruction group in an instruction queue corresponding to the determined decoder group.

20. 16. The processor of claim 15, further comprising a fusion unit configured to fuse, in a decoder mode, microinstructions decoded by the plurality of decoder groups according to the switching mark attached to the target microinstruction to obtain a microinstruction corresponding to a fetch order, wherein the decoder mode is characterized by the fusion unit obtaining a microinstruction by decoding the decoder groups.

21. one instruction queue is set corresponding to one decoder group, and the decoder group is also configured to hold the microinstructions obtained by decoding in the corresponding microinstruction queue; The fusion unit fuses the microinstructions decoded by the plurality of decoder groups according to the switching mark attached to the target microinstruction to obtain a microinstruction corresponding to the fetch order, 21. The processor of claim 20, further comprising: switching in a microinstruction queue corresponding to each decoder group to fuse microinstructions in accordance with the switching mark attached to the target microinstruction to obtain a microinstruction corresponding to a fetch order.

22. The microinstruction cache is also configured to, in a microinstruction cache mode, hold retrieved microinstructions in a microinstruction queue corresponding to a default decoder group, the microinstruction cache mode being configured such that a microinstruction is obtained by searching the microinstruction cache; the decoder group is also configured to store the decoded microinstructions in the microinstruction cache; 22. The processor of claim 21, wherein in said microinstruction cache mode, if said fetch request does not hit in said microinstruction cache, said decoder mode is entered.

23. A chip comprising a processor according to any one of claims 15 to 22.

24. 24. An electronic device comprising the chip of claim 23.

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