Integrated circuit, processing method, electronic device and medium for memory access

Abstract

To provide an integrated circuit, a processing method, an electronic apparatus, and a medium for memory access.SOLUTION: An integrated circuit comprises: a first memory module, a second memory module, and an access signal determination module respectively connected to the first memory module and the second memory module, where the access signal determination module comprises: an interface circuit configured to transmit a first memory access signal of a processor to the first memory module; an address filtering circuit configured to determine a target security level corresponding to an access address of the first memory access signal; and an access signal processing circuit configured to, in response to the target safety level being a preset level, perform address shifting on an access address of the first memory access signal, obtain a second memory access signal based on the shifted address, and transmit the second memory access signal to the second memory module.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor technology, and more particularly to integrated circuits, processing methods, electronic devices, and media for memory access. [Background technology]

[0002] In the field of smart driving, the DDR (Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory)) of smart driving chips is mainly used for smart driving perception prediction functions, which currently require a functional safety level of ASILB (Automotive Safety Integrity Level B). However, as the control and decision-making function algorithms for smart driving functions, which require a safety level of ASILD (Automotive Safety Integrity Level D), evolve, the control and decision-making function algorithms require increasingly higher computing power and memory capacity. When developing control and decision-making algorithms using processors (or cores within processors) and RAM, there is a problem of insufficient memory capacity. Currently, the functional safety level of DDR controllers is all ASILB, which cannot meet the access needs of ASILD processors (or processor cores), resulting in a lack of memory capacity for relatively high safety levels corresponding to relatively high safety level functions. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure is provided to solve technical problems such as a lack of relatively high-security level memory capacity required for relatively high-security level functions. Embodiments of the present disclosure provide an integrated circuit, a processing method, an electronic device, and a medium for memory access. [Means for solving the problem]

[0004] According to one aspect of the embodiment of the present disclosure, there is provided an integrated circuit for memory access, including a first memory module, a second memory module, and an access signal determination module, wherein the access signal determination module is respectively connected to the first memory module and the second memory module, and the access signal determination module includes: an interface circuit used to transmit a first memory access signal to the first memory module, which is used by a processor to access the first memory module; an address filtering circuit connected to the interface circuit and used to determine a target safety level corresponding to an access address of the first memory access signal; and an access signal processing circuit connected to the address filtering circuit and used to perform address shifting on the access address of the first memory access signal when the target safety level is a predetermined level, obtain a second memory access signal based on the shifted address, and transmit the second memory access signal to the second memory module.

[0005] According to another aspect of an embodiment of the present disclosure, there is provided a processing method for memory access, including a step of a processor transmitting a first memory access signal to a first memory module to access the first memory module, determining a target safety level corresponding to an access address of the first memory access signal, performing an address shift on the access address of the first memory access signal in response to the target safety level being a preset level, and obtaining a second memory access signal based on the shifted address, and transmitting the second memory access signal to a second memory module.

[0006] According to yet another aspect of an embodiment of the present disclosure, there is provided a computer-readable storage medium having a computer program stored therein, the computer program being for executing a processing method for memory access as described in any of the embodiments of the present disclosure.

[0007] According to another aspect of an embodiment of the present disclosure, there is provided an electronic device, the electronic device including a processor and a memory used to store executable instructions for the processor, wherein the processor is used to realize a processing method for memory access described in any of the embodiments of the present disclosure by reading the executable instructions from the memory and executing the instructions, or the electronic device includes an integrated circuit for memory access described in any of the embodiments of the present disclosure. [Effects of the Invention]

[0008] The integrated circuit, processing method, electronic device, and medium for memory access provided in the above embodiments of the present disclosure realize a memory access operation of a predetermined level of a relatively high security level using two memory access operations of a relatively low security level, so that data to be written with a relatively high security level can be written to two memory modules. Correspondingly, when reading the data with a relatively high security level, the same data is read from the two memory modules. The consistency of the access results of the two memory modules ensures the functional safety of the relatively high security level function. Even when the memory controller only satisfies the relatively low security level, the access operation of the relatively high security level function can be completed. This allows a memory with a relatively low security level to be used for a relatively high security level function, and the relatively high security level function can access the memory with a relatively low security level, providing greater memory performance for the relatively high security level function while ensuring functional safety, effectively meeting the memory requirements of the relatively high security level function, and solving problems such as insufficient memory capacity for the relatively high security level.

[0009] The technical solutions of the present disclosure are described in more detail below with reference to figures and examples. [Brief explanation of the drawings]

[0010] The above and other objects, features, and advantages of the present disclosure will become more apparent by describing the embodiments of the present disclosure in more detail with reference to the drawings. The drawings are provided to provide a further understanding of the embodiments of the present disclosure, and are part of the specification, intended to interpret the present disclosure together with the embodiments of the present disclosure, and are not intended to limit the present disclosure. In the drawings, the same reference numerals generally represent the same components or steps. [Figure 1] 1 is an exemplary application scenario of an integrated circuit for memory access provided by the present disclosure. [Figure 2] FIG. 2 is a structural schematic diagram of an integrated circuit for memory access provided by an exemplary embodiment of the present disclosure. [Figure 3] FIG. 10 is a structural schematic diagram of an integrated circuit for memory access provided by another exemplary embodiment of the present disclosure. [Figure 4] 2 is a structural schematic diagram of a read channel module 24 provided by an exemplary embodiment of the present disclosure. [Figure 5] 2 is a structural schematic diagram of a read channel module 24 provided by another exemplary embodiment of the present disclosure. [Figure 6] FIG. 2 is a structural schematic diagram of a read channel module 24 provided according to yet another exemplary embodiment of the present disclosure. [Figure 7] 2 is a structural schematic diagram of a data comparison module 25 provided by an exemplary embodiment of the present disclosure. FIG. [Figure 8] 2 is a structural schematic diagram of a read channel module 24 provided by another exemplary embodiment of the present disclosure. [Figure 9] 2 is a structural schematic diagram of an access signal determination module 23 provided by an exemplary embodiment of the present disclosure. FIG. [Figure 10]2 is a structural schematic diagram of an access signal processing circuit 233 provided by an exemplary embodiment of the present disclosure. FIG. [Figure 11] FIG. 2 is a structural schematic diagram of an access signal determination module 23 provided by another exemplary embodiment of the present disclosure. [Figure 12] FIG. 10 is a structural schematic diagram of a combined implementation of an integrated circuit for memory access provided by yet another exemplary embodiment of the present disclosure. [Figure 13] 4 is a flowchart of a processing method for memory access provided by an exemplary embodiment of the present disclosure. [Figure 14] 10 is a flowchart of a processing method for memory access provided by another exemplary embodiment of the present disclosure. [Figure 15] 10 is a flowchart of a processing method for memory access provided by yet another exemplary embodiment of the present disclosure. [Figure 16] 10 is a flowchart of a processing method for memory access provided by another exemplary embodiment of the present disclosure. [Figure 17] 10 is a flowchart of a processing method for memory access provided by yet another exemplary embodiment of the present disclosure. [Figure 18] 1A and 1B are structural schematic diagrams of application examples of electronic devices according to the present disclosure. [Figure 19] FIG. 10 is a structural schematic diagram of another application example of the electronic device of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. It is obvious that the described embodiments are only some of the embodiments of the present disclosure, and do not include all of the embodiments of the present disclosure. It should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0012] Unless otherwise specifically stated, the relative arrangement of components and steps, formulas, and numerical values ​​described in these examples do not limit the scope of the present disclosure.

[0013] Those skilled in the art will understand that the terms "first", "second", etc. in the embodiments of the present disclosure are used to distinguish between different steps, devices, modules, etc., and do not have any specific technical meaning and do not represent a logical order therebetween.

[0014] It should also be understood that in the embodiments of the present disclosure, "plurality" can refer to two or more, and "at least one" can refer to one, two, or more.

[0015] Embodiments of the present disclosure may be employed in electronic devices such as terminal devices, computer systems, servers, and the like, which may operate with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of numerous well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, and the like include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, networked personal computers, small computer systems, large computer systems, distributed cloud computing technology environments that include any of the above systems, and the like.

[0016] Summary of this disclosure: In the process of realizing the present disclosure, the inventors have found that in the field of smart driving, DDR (Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory)) in smart driving chips is mainly used for smart driving perception prediction functions, which currently require a functional safety level of ASILB (Automotive Safety Integrity Level B). However, with the evolution of control and decision-making function algorithms for smart driving functions with a safety level of ASILD (Automotive Safety Integrity Level D), the control and decision-making function algorithms require increasingly higher computing power and memory capacity. Therefore, when developing control and decision-making algorithms using processors (or cores within processors) and RAM, there is a problem of insufficient memory capacity. Currently, the functional safety levels of DDR controllers are all ASILB, which cannot meet the access needs of ASILD processors (or processor cores), resulting in insufficient memory capacity for relatively high-safety functions such as control and decision-making function algorithms.

[0017] Illustrative explanation: 1 illustrates an exemplary application scenario of the integrated circuit for memory access provided by the present disclosure. In a functional scenario with a predetermined safety level (ASILD level), such as smart driving control and decision-making, by utilizing the integrated circuit for memory access of the present disclosure, a processor executing the corresponding control and decision-making function algorithm can access a DDR with its functional safety level ASILD guaranteed, thereby providing powerful memory capacity through the DDR to meet its ever-increasing memory requirements. The processor may be any possible processor or processor core within a smart driving chip, such as a central processing unit (CPU) or a graphics processing unit (GPU), but is not limited thereto. Specifically, the integrated circuit for memory access of the present disclosure may include a first memory module, a second memory module, and an access signal determination module, and the access signal determination module is respectively connected to the first memory module and the second memory module. The first memory module and the second memory module may be any two memory devices in the smart driving chip or two memory areas in one memory device, for example, two memory areas partitioned by address codes in the DDR in the smart driving chip, and specifically can be configured according to actual needs.The access signal determination module may include transmitting a first memory access signal to the first memory module, causing a processor to access the first memory module; determining a target safety level corresponding to an access address of the first memory access signal; and, if the target safety level is a predetermined level (ASILD level), performing an address shift on the access address of the first memory access signal, obtaining a second memory access signal based on the shifted address, and transmitting the second memory access signal to the second memory module. In this way, in the case of memory access at the predetermined level, two memory modules are accessed simultaneously, and the predetermined level of memory access safety is achieved based on the consistency of the access results of the two modules. This allows a memory device with large memory capacity at the ASILB level to provide memory capacity in ASILD level functional scenarios, effectively resolving the problem of insufficient memory capacity in ASILD level functional scenarios in the prior art.

[0018] It should be noted that the integrated circuit of the present disclosure is not limited to use in the control and decision-making scenarios of smart driving, but can be used in any scenario requiring a relatively high level of safety according to actual needs, and is not specifically limited.

[0019] Exemplary devices: 2 is a structural schematic diagram of an integrated circuit for memory access provided by an exemplary embodiment of the present disclosure. This embodiment is applicable to a predetermined level of functional scenario and can meet the large memory requirements of the predetermined level of functional scenario. As shown in FIG. 2, the integrated circuit for memory access 20 of the present disclosure includes a first memory module 21, a second memory module 22, and an access signal determination module 23, and the access signal determination module 23 is connected to the first memory module 21 and the second memory module 22 respectively.

[0020] The access signal determination module 23 includes an interface circuit 231, an address filtering circuit 232, and an access signal processing circuit 233. The interface circuit 231 is used to transmit a first memory access signal, which is used by a processor to access the first memory module 21, to the first memory module 21. The address filtering circuit 232 is connected to the interface circuit 231 and is used to determine a target safety level corresponding to the access address of the first memory access signal. The access signal processing circuit 233 is connected to the address filtering circuit 232 and is used to perform an address shift on the access address of the first memory access signal according to the target safety level being a predetermined level, obtain a second memory access signal based on the shifted address, and transmit the second memory access signal to the second memory module 22.

[0021] The processor may be any possible processor or processor core within the smart driving chip, such as, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor, etc. The first memory module 21 and the second memory module 22 may be any two memory devices within the smart driving chip or two memory areas of a single memory device, such as two memory areas partitioned by address codes in a DDR within the smart driving chip, and may be configured according to actual needs. The first memory access signal may be a read access signal or a write access signal, and the preset level may be the ASILD level. The interface circuit 231 may be any feasible bus interface circuit, supporting bus protocols such as AXI (Advanced eXtensible Interface), AHB (Advanced High Performance Bus), APB (Advanced Peripheral Bus), and CHI (Coherent Hub Interface), and may be configured according to actual needs. The interface circuit 231 is connected to the processor by a corresponding bus to realize communication with the processor.The interface circuit 231 receives a first memory access signal from the processor, transmits the first memory access signal to the first memory module 21 corresponding to the access address, and transmits the first memory access signal to the address filtering circuit 232. The address filtering circuit 232 determines the target safety level of the access address of the first memory access signal. Specifically, the address filtering circuit 232 may determine the target safety level of the access address of the first memory access signal based on a predetermined address safety level determination method. For example, an address range with an ASILD level and / or an ASILB level is predetermined, and the target safety level of the access address is determined by comparing the access address with the predetermined address range. The specific implementation of the address filtering circuit 232 can be set according to actual needs, as long as it can determine the target safety level of the access address. The access signal processing circuit 233 is used to access a memory corresponding to a corresponding address in the second memory module by performing an address shift on the access address, determining a second memory access signal based on the address after the shift, and transmitting the second memory access signal to the second memory module corresponding to the address after the shift, when the target safety level corresponding to the access address of the first memory access signal is at a predetermined level (e.g., ASILD level).The address ranges of the first memory module 21 and the second memory module 22 are shifted in advance according to the address code. For example, the address range of the first memory module 21 is 0 to 2000, and the address range of the second memory module 22 is 2001 to 3000. Here, address 0 in the first memory module 21 corresponds to address 2001 in the second memory module 22, and address 1 in the first memory module 21 corresponds to address 2002 in the second memory module 22. By analogy, the access address for accessing the first memory module 21 is 200 By shifting by 1, the corresponding post-shift address in the second memory module 22 can be determined. The address range of 1001 to 2000 in the first memory module 21 can be used to store a relatively low security level, such as ASILB. If the access address in the first memory access signal does not belong to a predetermined level (e.g., ASILD level), there is no need to perform address shifting, and the memory corresponding to the access address in the first memory module 21 can be directly accessed, thereby realizing the access needs of memory devices with relatively low security levels to meet different security levels.

[0022] For example, if the first memory access signal is a write access signal, and the access address is at a predetermined level, the target data to be written can be simultaneously written to the first memory module 21 and the second memory module 22 by the first memory access signal and the second memory access signal, respectively. If the first memory access signal is a read access signal and the target data is to be read, similarly, the first memory access signal reads one target data from the corresponding address of the first memory module 21, and the second memory access signal reads one target data from the second memory module 22. The two target data can then be compared, and if the two target data are consistent, it can be determined that the data is correct; if not, corresponding measures can be taken, such as reporting a data error signal as described above, which can be specifically configured according to actual needs.

[0023] In each embodiment of the present disclosure, the integrated circuit 20 for memory access can be abbreviated as the integrated circuit 20 .

[0024] Optionally, the integrated circuit of the present disclosure may be connected to the processor by any operable bus, such as an AXI, AHB, APB, CHI, etc., such that the processor can access the first memory module 21 and the second memory module 22 via the bus.

[0025] The memory access integrated circuit provided in this embodiment realizes a memory access operation of a predetermined level with a relatively high security level using memory access operations of two relatively low security levels, so that data to be written with a relatively high security level can be written to two memory modules. Correspondingly, when reading data with a relatively high security level, the same data is read from the two memory modules. The consistency of the access results of the two memory modules ensures the functional safety of functions with a relatively high security level. Even when the memory controller only satisfies a relatively low security level, access operations with a relatively high security level can be completed. This allows memories with a relatively low security level to be used for functions with a relatively high security level, and functions with a relatively high security level to access memories with a relatively low security level, providing large memory capacity for functions with a relatively high security level while ensuring functional safety, effectively meeting the memory requirements of functions with a relatively high security level, and solving problems such as insufficient memory capacity for functions with a relatively high security level.

[0026] FIG. 3 is a structural schematic diagram of an integrated circuit for memory access provided by another exemplary embodiment of the present disclosure.

[0027] In an optional example, the integrated circuit 20 of the present disclosure further includes a read channel module 24 and a data comparison module 25 .

[0028] The read channel module 24 is used to read first data from the first memory module 21 and read second data from the second memory module 22, and the data comparison module 25 is used to compare the first data with the second data and determine a data error signal based on the comparison result.

[0029] The read channel module 24 is connected to the first memory module 21 and the second memory module 22, respectively. When the first memory access signal is a read access signal, it transmits it to the first memory module 21, and the first memory module 21 communicates with the read channel module 24, so that the read channel module 24 can read the first data at the access address of the first memory access signal from the first memory module 21. Similarly, the second memory module 22 responds to the second memory access signal, so that the read channel module 24 can read the second data at the address after the shift of the access address from the second memory module 22. After the read channel module 24 reads the first data and the second data, it transmits them to the data comparison module 25, respectively. The data comparison module 25 compares the first data with the second data to obtain a comparison result. The comparison result may include two results: the first data and the second data are the same or different. If the first data and the second data are different, it indicates that an error has occurred in the data, and a data error signal should be issued. The read channel module 24 may be connected to the processor, for example, by a bus, and after reading the first data, the read channel module 24 may transmit the first data to the processor via the bus for use by the processor. The data comparison module 25 may be connected to an error processing module that handles error processing within the chip, so as to transmit a data error signal to the error processing module, which may promptly perform corresponding error processing, such as corresponding error diagnosis and error reporting, and the details of which are omitted here.

[0030] Optionally, data is read from the first memory module 21 and the second memory module 22 only when the access address of the first memory access signal belongs to a predetermined level. If the access address does not belong to the predetermined level, only the first memory access signal is transmitted to the first memory module 21, and the second memory access signal is not transmitted to the second memory module 22. Therefore, only the first memory module 21 responds to the first memory access signal, and the read channel module 24 reads the first data from the first memory module 21 and transmits it to the processor, achieving access with a relatively low security level (e.g., ASILB). In this case, the first memory module 21 has both an address range with a relatively high security level and an address range with a relatively low security level. In actual applications, the first memory module 21 and the second memory module 22 may be configured to access only with a relatively high security level according to actual needs, in which case the address range of the first memory module 21 and the address range of the second memory module 22 correspond one-to-one. Specifically, this can be configured according to actual needs.

[0031] The present disclosure compares the first data read from the first memory module 21 with the second data read from the second memory module 22, and determines a data error signal based on the comparison result, thereby ensuring the consistency of the first data and the second data, and promptly reporting any mismatch to the higher level, thereby achieving a relatively high level of access security.

[0032] FIG. 4 is a structural schematic diagram of a read channel module 24 provided by an exemplary embodiment of the present disclosure.

[0033] In an optional example, the read channel module 24 includes a first bus interface circuit 241 and a second bus interface circuit 242 .

[0034] The first bus interface circuit 241 is connected to the first memory module 21 and is used to receive the first data read from the first memory module 21 and transmit the first data to the processor and the data comparison module 25, and the second bus interface circuit 242 is connected to the second memory module 22 and is used to receive the second data read from the second memory module 22 and transmit the second data to the data comparison module 25.

[0035] The first bus interface circuit 241 and the second bus interface circuit 242 may be any available bus interface circuit, and may be configured according to actual needs. For example, the first bus interface circuit 241 and the second bus interface circuit 242 may be bus interface circuits supporting bus protocols such as AXI, AHB, APB, and CHI.

[0036] 5 is a structural schematic diagram of a read channel module 24 provided by another exemplary embodiment of the present disclosure. In this example, a first bus interface circuit 241 and a second bus interface circuit 242 are respectively connected to the first memory module 21 and the second memory module 22 by a bus to realize reading of the first data and the second data.

[0037] The present disclosure realizes parallel processing of two access operations by having two bus interface circuits read data from two memory modules respectively, thereby improving access efficiency.

[0038] FIG. 6 is a structural schematic diagram of a read channel module 24 provided according to yet another exemplary embodiment of the present disclosure.

[0039] In an optional example, the read channel module 24 further includes a first read cache unit 243 and a second read cache unit 244.

[0040] The first read cache unit 243 is connected to the processor, the first bus interface circuit 241, and the data comparison module 25, respectively, and is used to cache the first data received by the first bus interface circuit 241 and output the first data to the processor and the data comparison module 25. The second read cache unit 244 is connected to the second bus interface circuit 242 and the data comparison module 25, respectively, and is used to cache the second data received by the second bus interface circuit 242 and output the second data to the data comparison module 25.

[0041] The first read cache unit 243 and the second read cache unit 244 may be any available cache memory, such as a static random-access memory (SRAM), and may be configured according to actual needs. The first bus interface circuit 241 reads first data from the first memory module 21 and caches it in the first read cache unit 243, which then transmits the first data to the processor and data comparison module 25. The second bus interface circuit 242 reads second data from the second memory module 22 and caches it in the second read cache unit 244, which then transmits the second data to the data comparison module 25 for comparison with the first data.

[0042] Optionally, the first read cache unit 243 may be connected to the processor by a bus, and the processor obtains the first data from the first read cache unit 243 by the bus.

[0043] The present disclosure uses two read cache units to cache data read from two memory modules respectively, which can effectively ensure the synchronization of the first data and the second data input to the data comparison module 25, and helps to deal with bus backpressure. For example, because the bus is busy, the first data may be read but the second data may not yet be read. At this time, data comparison cannot be performed, and the cache may cache the first data that has already been read. After the second data is cached, the operation of the data comparison module 25 is triggered.

[0044] FIG. 7 is a structural schematic diagram of the data comparison module 25 provided by an exemplary embodiment of the present disclosure.

[0045] In an optional example, the data comparison module 25 includes an exclusive OR circuit unit 251 , and the exclusive OR circuit unit 251 includes a first input terminal 2511 , a second input terminal 2512 and an output terminal 2513 .

[0046] The first input terminal 2511 is connected to the first read cache unit 243 and is used to input the first data, the second input terminal 2512 is connected to the second read cache unit 244 and is used to input the second data, and the output terminal 2513 is connected to the error processing module 30 and is used to output the data error signal to the error processing module 30.

[0047] The exclusive OR circuit unit 251 performs exclusive OR logic processing based on the first data input from the first input terminal 2511 and the second data input from the second input terminal 2512, that is, if the first data and the second data are different, the output result is 1, which is a data error signal. The specific implementation of the exclusive OR logic will not be described here.

[0048] The present disclosure realizes the comparison between the first data and the second data by an exclusive OR logic unit, and issues a data error signal when the first data and the second data are different, thereby ensuring the safety of memory access.

[0049] FIG. 8 is a structural schematic diagram of a read channel module 24 provided according to another exemplary embodiment of the present disclosure.

[0050] In an optional example, the read channel module 24 further includes a logical OR circuit 245 .

[0051] The first bus interface circuit 241 is also connected to the OR circuit 245, and is used to receive a bus backpressure signal and output a first ready signal to the OR circuit 245; the second bus interface circuit 242 is also connected to the OR circuit 245, and is used to receive a bus backpressure signal and output a second ready signal to the OR circuit; the OR circuit 245 is used to output a third ready signal to the processor in response to the first ready signal and / or the second ready signal, and the third ready signal is for notifying the processor not to start a read / write operation.

[0052] The bus enables communication between the first bus interface circuit 241 and the second bus interface circuit 242 and the first memory module 21 and the second memory module 22. The backpressure signal indicates that the ingress traffic of the bus is greater than the egress traffic. After receiving the bus backpressure signal, the first bus interface circuit 241 outputs a first ready signal to the OR circuit 245 to indicate that a read / write operation will not be initiated. For example, the first ready signal can be represented by a low level or "0." The second ready signal of the second bus interface circuit 242 is similar and will not be described again. After receiving the first ready signal from the first bus interface circuit 241 and / or the second ready signal from the second bus interface circuit 242, the OR circuit 245 outputs a third ready signal to the processor. The third ready signal notifies the processor that a read / write operation will not be initiated. The third ready signal can also be represented by a low level or "0." That is, the function realized by the OR circuit 245 is to output 0 if either of the two input terminals is 0.

[0053] In practical applications, the ready signal (including the first ready signal, the second ready signal, and the third ready signal) is realized by the ready signal in the handshake protocol, and when the ready signal is set high (1), it indicates that a read or write operation may be started, and when the ready signal is set low (0), it indicates that a read or write operation is not started. Of course, the handshake protocol also includes a valid signal, and the specific principles of the handshake are not described here. In practical applications, different representation methods may be used depending on the protocol, as long as the corresponding purpose is achieved, and this disclosure is not limited to these.

[0054] The present disclosure uses a logical OR circuit to enable either bus interface circuit (first bus interface circuit 241 and / or second bus interface circuit 242) to notify the processor when it receives a bus backpressure signal, thereby alleviating the load on the bus by notifying the processor not to initiate a read or write operation.

[0055] FIG. 9 is a structural schematic diagram of the access signal determination module 23 provided by an exemplary embodiment of the present disclosure.

[0056] In an optional example, the access signal determination module 23 further includes a first address register 234 and a second address register 235 .

[0057] The first address register 234 is used to store the upper limit value of the address range corresponding to the preset level, and the second address register 235 is used to store the lower limit value of the address range corresponding to the preset level, and the address filtering circuit 232 includes a first comparison unit 2321, a second comparison unit 2322, and a judgment unit 2323.

[0058] The first comparison unit 2321 is connected to the interface circuit 231 and the first address register 234, respectively, and is used to compare the access address of the first memory access signal received by the interface circuit 231 with the upper limit value in the first address register 234 to obtain a first comparison result; the second comparison unit 2322 is connected to the interface circuit 231 and the second address register 235, respectively, and is used to compare the access address of the first memory access signal received by the interface circuit 231 with the lower limit value in the second address register 235 to obtain a second comparison result; the judgment unit 2323 is connected to the first comparison unit 2321, the second comparison unit 2322, and the access signal processing circuit 233, respectively, and is used to output a safety level compliance status to the access signal processing circuit 233 based on the first comparison result and the second comparison result, and the safety level compliance status includes two states: whether the target safety level meets or does not meet the preset level.

[0059] The upper and lower limits of the address range corresponding to the preset level may be pre-configured in the first address register 234 and the second address register 235, respectively. The specific configuration method is not limited, and may be configured by the chip's main processor. For example, the address range corresponding to the preset level is 0 to 1000. A binary value corresponding to the upper limit value 0 may be written to the first address register 234, and a binary value corresponding to 1000 may be written to the second address register 235. A detailed description is omitted. The first comparison unit 2321 and the second comparison unit 2322 can realize the comparison function using a comparator and may be configured according to actual needs. The first comparison result may include three cases: the access address is less than the upper limit value, equal to the upper limit value, or greater than the upper limit value. The second comparison result may include three cases: the access address is greater than the lower limit value, equal to the lower limit value, or less than the lower limit value. Alternatively, according to actual needs, the first comparison result of being less than the upper limit value and equal to the upper limit value may be combined into one, i.e., less than or equal to the upper limit value, and the second comparison result of the access address being greater than the lower limit value and equal to the lower limit value may be combined into one, i.e., greater than or equal to the lower limit value, etc. Specific configurations may be made according to actual needs. Different cases can be represented by different outputs, for example, for the first comparing unit 2321, if it is determined that the access address is less than or equal to the upper limit value, the first comparing result is output as 1, otherwise the first comparing result is output as 0; and for the second comparing unit 2322, if it is determined that the access address is greater than or equal to the lower limit value, the second comparing result is output as 1, otherwise the second comparing result is output as 0.Thus, the judgment unit 2323 can determine the safety level compliance state according to different cases of the first comparison result and the second comparison result, and the safety level compliance state may include two states: compliance and non-compliance, and different states can be represented by different codes, for example, compliance is represented by 1 and non-compliance is represented by 0. If the first comparison result is 1 and the second comparison result is 1, it indicates that the access address is within the address range corresponding to the preset level, and the safety level compliance state is 1. In this case, the judgment unit 2323 can be implemented by a logical AND circuit, that is, it outputs 1 when both inputs are 1. In actual application, the specific implementation manner of the first comparison unit 2321, the second comparison unit 2322, and the judgment unit 2323 can be set according to actual needs and is not limited to the above exemplary manner.

[0060] In the present disclosure, the first address register 234 and the second address register 235, in which an address range corresponding to a preset level is pre-configured, provide the first comparison unit 2321 and the second comparison unit 2322 with a comparison basis, respectively, thereby realizing recognition of access addresses with a relatively high level of security, thereby providing memory access that meets security requirements with a relatively high level of security, and further ensuring functional security.

[0061] In an optional example, the access signal processing circuit 233 includes a finite state machine 2331 connected to the judgment unit 2323, which is used to add preset shift information to the access address of the first memory access signal to obtain the shifted address when the safety level compliance state is compliance, obtain the second memory access signal based on the shifted address, and transmit the second memory access signal to the second memory module 22.

[0062] The finite state machine 2331 can be abbreviated as FSM (Finite-State Machine), and its role is to describe the state sequence an object experiences in its life cycle and how it responds to external events. In the present disclosure, the finite state machine 2331 responds differently depending on the different safety level compliance states output by the judgment unit 2323. If the safety level compliance state is compliance (e.g., 1), the finite state machine 2331 adds preset shift information to the access address of the first memory access signal to obtain a shifted address, and then determines a second memory access signal based on the shifted address and transmits the second memory access signal to the second memory module 22. The first memory access signal may be obtained from the address filtering circuit 232 or the interface circuit 231, and can be specifically set according to actual needs. The preset shift information may be pre-stored in a register, and the finite state machine 2331 can obtain the preset shift information from the register and perform address shifting on the access address in the first memory access signal to obtain a shifted address, and then determine a second memory access signal based on the shifted address and transmit it to the second memory module 22.

[0063] In an optional example, the access signal processing circuit 233 may be realized in other ways, and is not limited to the realization of the finite state machine 2331 .

[0064] FIG. 10 is a structural schematic diagram of the access signal processing circuit 233 provided by an exemplary embodiment of the present disclosure.

[0065] In an optional example, the access signal processing circuit 233 further includes a first register 2332 connected to the finite state machine 2331 and used for storing the preset shift information.

[0066] The preset shift information may be placed in the first register 2332 at any possible timing, for example, by the main processor of the chip every time the chip is started up, and specifically may be set according to actual needs, and is not limited in this disclosure.

[0067] In an optional example, the preset shift information may be constantly updated according to actual needs. For example, when setting new address ranges for the first memory module 21 and the second memory module 22 by updating the memory address code, new preset shift information is written to the first register 2332 based on the shift relationship of the new address range, and specifically, can be set according to actual needs.

[0068] The present disclosure provides that the first register 2332 stores preset shift information, allowing users to configure the preset shift information according to their actual needs, thereby improving versatility and user experience.

[0069] FIG. 11 is a structural schematic diagram of the access signal determination module 23 provided by another exemplary embodiment of the present disclosure.

[0070] In an optional example, the access signal determination module 23 further includes a channel selection circuit 236 respectively connected to the interface circuit 231 and the access signal processing circuit 233, and used to select a channel to transmit the first memory access signal and the second memory access signal.

[0071] The channel selection circuit 236 is connected to the first memory module 21 and the second memory module 22 via a bus, and the channel selection circuit 236 can select a channel in any feasible manner, for example, it can use a data selector (MUX) to switch channels and transmit the first memory access signal and the second memory access signal to the first memory module 21 and the second memory module 22. A detailed description will be omitted.

[0072] Optionally, if a channel selection circuit 236 is provided, the channel selection circuit 236 can determine whether to send the signal once or twice according to the output of the finite state machine 2331. Sending once refers to the fact that if the access address does not fall within a predetermined address range, the second memory access signal is not generated by address shifting, and the channel selection circuit 236 directly switches to the interface circuit 231 channel to transmit the first memory access signal to the first memory module 21. Sending twice refers to the fact that if the access address falls within a predetermined address range, both the first and second memory access signals need to be sent, so the channel selection circuit 236 needs to send the signal twice, and may first transmit the first memory access signal to the first memory module 21 on the channel of the interface circuit 231, and then switch to the channel of the access signal processing circuit 233 to transmit the second memory access signal to the second memory module 22.

[0073] The present disclosure realizes the transmission of the first memory access signal and the second memory access signal by the channel selection circuit 236, and compared to the interface circuit 231 and the access signal processing circuit 233 being connected to the first memory module 21 and the second memory module 22, respectively, by buses (i.e., the interface circuit 231 needs to be connected to the bus by one bus interface, and the bus is connected to the first memory module 21 by one bus interface, and the access signal processing circuit 233 needs to be connected to the bus by one bus interface, and the bus is connected to the second memory module 22 by one bus interface, requiring a total of four bus interfaces), it realizes the transmission of two memory access signals by one bus interface (i.e., the channel selection circuit is connected to the bus by one bus interface, and the bus is connected to the first memory module 21 and the second memory module 22, respectively, by two bus interfaces, requiring a total of three bus interfaces), thereby reducing the number of bus interfaces by one.

[0074] The above-described embodiments or optional examples of the present disclosure may be implemented alone or in any combination as long as there is no contradiction, and the description thereof will be omitted here.

[0075] 12 is a structural schematic diagram of a combined implementation of an integrated circuit for memory access provided by yet another exemplary embodiment of the present disclosure. In this embodiment, the integrated circuit 20 includes a first memory module 21, a second memory module 22, an access signal determination module 23, a read channel module 24, and a data comparison module 25. The specific implementation and functions of each module may refer to the above embodiment or optional example, and further description will be omitted here.

[0076] The structural diagrams in the drawings of this disclosure are all connection schematic diagrams, and when actually implemented, the layout of each part of the integrated circuit can be set according to actual needs and is not limited by this disclosure.

[0077] By logically realizing all or part of each component of the integrated circuit of the present disclosure by hardware, real-time performance can be guaranteed, and specifically, it can be set according to actual needs.

[0078] The integrated circuit for memory access provided by this embodiment can realize processor access operations without software intervention through hardware address shifting, and simultaneously controls two memory controllers (e.g., DDR controllers) to decompose access with a relatively high security level (e.g., ASILD level) into two independent data access paths with a relatively low security level (e.g., ASILB level), thereby providing memory capacity for a relatively high security level scenario using a memory device with a relatively low security level, and effectively meeting the memory requirements of a relatively high security level scenario.

[0079] Exemplary methods: 13 is a flowchart of a processing method for memory access provided by an exemplary embodiment of the present disclosure. This embodiment may be applied to any electronic device that requires a relatively high level of security for memory access, specifically, for example, used in a chip. As shown in FIG. 13, the method of the present disclosure includes the following steps: In step 501, the processor transmits a first memory access signal to the first memory module to access the first memory module, and determines a target security level corresponding to the access address of the first memory access signal.

[0080] In step 502, if the target safety level is equal to a preset level, an address shift is performed on the access address of the first memory access signal, and a second memory access signal is obtained based on the address after the shift.

[0081] In step 503, a second memory access signal is transmitted to a second memory module.

[0082] The specific operations of each step in this embodiment can be referred to in the previous embodiment, and further description will be omitted here.

[0083] FIG. 14 is a flowchart of a processing method for memory access provided by another exemplary embodiment of the present disclosure.

[0084] In an optional example, the method of the present disclosure further includes: In step 504, first data is read from the first memory module and second data is read from the second memory module; In step 505, the first data and the second data are compared, and a data error signal is determined based on the comparison result.

[0085] In an optional example, after reading the first data from the first memory module in step 504, further includes: In step 506, the first data is transmitted to a processor.

[0086] FIG. 15 is a flowchart of a processing method for memory access provided by yet another exemplary embodiment of the present disclosure.

[0087] In an optional example, after reading the first data from the first memory module and the second data from the second memory module in step 504, further includes: In step 507, the first data is cached in a first read cache unit, which then transmits the first data to the processor for comparison with the second data.

[0088] In step 508, the second data is cached in the second read cache unit for comparison with the first data.

[0089] In an optional example, after comparing the first data and the second data in step 505 and determining a data error signal based on the comparison result, further including: In step 509, a data error signal is output to the error processing module.

[0090] FIG. 16 is a flowchart of a processing method for memory access provided by another exemplary embodiment of the present disclosure.

[0091] In an optional example, the method of the present disclosure further includes: In step 601, receive a backpressure signal on the bus, and output a third ready signal to the processor in response to the backpressure signal, where the third ready signal is for notifying the processor not to start a read or write operation.

[0092] Step 601 and the other steps described above are not ordered.

[0093] FIG. 17 is a flowchart of a processing method for memory access provided by yet another exemplary embodiment of the present disclosure.

[0094] In an optional example, the method of the present disclosure further includes: In step 602, the upper limit value of the address range corresponding to the preset level is stored in a first address register.

[0095] Specifically, the upper limit value of the address range corresponding to the preset level may be stored in the first address register in response to a first write command from the processor. The first write command may be triggered by a user via a terminal device, and the specific layout of the register is not limited.

[0096] In step 603, the lower limit value of the address range corresponding to the preset level is stored in a second address register.

[0097] For the specific layout of the registers, please refer to the first address register, and the description will be omitted.

[0098] Step 501 of the processor transmitting a first memory access signal to the first memory module for accessing the first memory module and determining a target security level corresponding to the access address of the first memory access signal includes: In step 5011, the processor transmits a first memory access signal to the first memory module to access the first memory module.

[0099] In step 5012, the access address of the first memory access signal is compared with the upper limit value in the first address register to obtain a first comparison result; In step 5013, the access address of the first memory access signal is compared with the lower limit value in the second address register to obtain a second comparison result; In step 5014, a safety level compliance state is determined based on the first comparison result and the second comparison result, and the safety level compliance state includes two states: whether the target safety level complies with or does not comply with a preset level.

[0100] Here, there is no order between step 5011 and step 5012.

[0101] In an optional example, step 502 of performing an address shift on the access address of the first memory access signal in response to the target safety level being a preset level and obtaining a second memory access signal based on the shifted address includes: In step 5021, if the safety level compliance state is compliance, add preset shift information to the access address of the first memory access signal to obtain a shifted address, obtain a second memory access signal based on the shifted address, and transmit the second memory access signal to the second memory module.

[0102] In an optional example, the method of the present disclosure further includes: In step 604, the preset shift information is stored in a first register.

[0103] The layout principle of the first register is similar to that of the first address register, and the description is omitted here.

[0104] In an optional example, the method of the present disclosure further includes realizing transmission of the first memory access signal and the second memory access signal by selecting a channel.

[0105] The specific operations of each step in the method embodiment of the present disclosure may be referred to the integrated circuit embodiment, and the description thereof will be omitted here.

[0106] Any processing method for memory access provided by the embodiments of the present disclosure may be executed by any suitable device having data processing capabilities, including, but not limited to, a terminal device, a server, etc. Alternatively, any processing method for memory access provided by the embodiments of the present disclosure may be executed by a processor, for example, the processor executes any processing method for memory access mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in a memory. Further description is omitted below.

[0107] Exemplary electronic devices: An embodiment of the present disclosure also includes a memory used to store a computer program; and a processor used to execute a computer program stored in the memory, and which, when the computer program is executed, realizes the processing method for memory access described in any of the embodiments of the present disclosure.

[0108] 18 is a structural schematic diagram of an application example of an electronic device of the present disclosure. In this example, the electronic device 10 includes one or more processors 11 and a memory 12.

[0109] The processor 11 may be a central processing unit (CPU) or other type of processing unit with data processing and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0110] The memory 12 may include one or more computer program products, which may include various types of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache. The non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored in the computer-readable storage media, and the processor 11 may execute the program instructions to implement the methods of the embodiments of the present disclosure described above and / or other desired functions. The computer-readable storage media may also store various contents, such as an input signal, a signal component, and a noise component.

[0111] In one example, electronic device 10 may further include input devices 13 and output devices 14, these components being connected together by a bus system and / or other type of connection mechanism (not shown).

[0112] For example, the input device 13 may be a microphone or a microphone array used to capture an input signal of a sound source.

[0113] The input device 13 may further include, for example, a keyboard, a mouse, and the like.

[0114] The output device 14 can output various information such as determined distance information, direction information, etc. The output device 14 may include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, etc.

[0115] 18 shows only some of the components of the electronic device 10 that are relevant to the present disclosure, and omits components such as a bus, an input / output interface, etc. Depending on a specific application scenario, the electronic device 10 may further include any other appropriate components.

[0116] 19 is a structural schematic diagram of another application embodiment of the electronic device of the present disclosure, in which the electronic device 10 includes an integrated circuit 20 for memory access provided by any of the above embodiments or optional embodiments.

[0117] Exemplary computer program products and computer-readable storage media: In addition to the methods and apparatus described above, embodiments of the present disclosure may also be a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods according to various embodiments of the present disclosure described in the "Exemplary Methods" section herein.

[0118] Although the basic principles of the present disclosure have been described above using specific embodiments, the advantages, benefits, and effects mentioned in the present disclosure are examples rather than limitations, and it cannot be assumed that each embodiment of the present disclosure must possess these advantages, benefits, and effects. Furthermore, the details disclosed above are provided for illustration and understanding rather than limitations, and the details described above do not limit the present disclosure to the specific details that must be implemented.

[0119] In this specification, each embodiment is described in a chain-like manner, and the description of each embodiment focuses on the differences from other embodiments, and reference can be made to the same or similar parts between the embodiments. The system embodiments are described briefly because they basically correspond to the method embodiments, but reference can be made to the description of the method embodiments for related points.

[0120] Block diagrams of devices, apparatus, instruments, and systems according to the present disclosure are merely exemplary and are not intended to require or imply that the devices, apparatus, instruments, and systems must be connected, arranged, or configured in the manner shown in the block diagrams. Those skilled in the art will appreciate that these devices, apparatus, instruments, and systems may be connected, arranged, or configured in any manner.

[0121] The methods and apparatuses of the present disclosure can be implemented in many ways. For example, the methods and apparatuses of the present disclosure can be implemented using software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of the steps of the methods is for illustrative purposes only, and the steps of the methods of the present disclosure are not limited to the order specifically described above, unless otherwise specifically described. In addition, in some embodiments, the present disclosure may be implemented as a program recorded on a recording medium, which program includes machine-readable instructions for implementing the methods of the present disclosure. Therefore, the present disclosure covers a recording medium storing a program for executing the methods of the present disclosure.

[0122] In the devices, apparatuses, and methods of the present disclosure, each component or each step may be disassembled and / or recombined, and such disassembly and / or combination should be considered as an equivalent configuration to the present disclosure.

Claims

1. 1. An integrated circuit for memory access, comprising: The access signal determining module includes a first memory module, a second memory module, and an access signal determining module, the access signal determining module being connected to the first memory module and the second memory module respectively, and the access signal determining module is configured to: an interface circuit for transmitting a first memory access signal to the first memory module, the first memory module having a predetermined address range corresponding to a predetermined level; an address filtering circuit connected to the interface circuit, the address filtering circuit being used to determine a target security level corresponding to the access address of the first memory access signal by comparing the access address with the predetermined address range; an access signal processing circuit connected to the address filtering circuit, for performing address shifting on the access address of the first memory access signal based on preset shift information to obtain a shifted address when the target safety level is the preset level, determining a second memory access signal based on the shifted address, and transmitting the second memory access signal to the second memory module; the integrated circuit further includes a read channel module used to read first data from the first memory module and second data from the second memory module when the target safety level is the preset level, and to read first data only from the first memory module when the target safety level is not the preset level; the read channel module includes a logical OR circuit, a first bus interface circuit, and a second bus interface circuit; the first bus interface circuit is connected to the OR circuit, and the first bus interface circuit is also used to receive a bus backpressure signal and output a first preparation signal to the OR circuit; the second bus interface circuit is connected to the OR circuit, and the second bus interface circuit is also used to receive a bus backpressure signal and output a second preparation signal to the OR circuit; An integrated circuit for memory access, wherein the logical OR circuit is used to output a third preparation signal to the processor in response to the first preparation signal and / or the second preparation signal, and the third preparation signal is for notifying the processor not to start a read / write operation.

2. 2. The integrated circuit of claim 1, further comprising: a data comparison module adapted to compare the first data with the second data and determine a data error signal based on a comparison result.

3. The first bus interface circuit is connected to the first memory module and is used to receive the first data read from the first memory module and transmit the first data to the processor and the data comparison module; 3. The integrated circuit of claim 2, wherein the second bus interface circuit is connected to the second memory module and is used to receive the second data read from the second memory module and transmit the second data to the data comparison module.

4. The read channel module includes: a first read cache unit respectively connected to the processor, the first bus interface circuit, and the data comparison module, the first read cache unit being used to cache the first data received by the first bus interface circuit and output the first data to the processor and the data comparison module; 4. The integrated circuit of claim 3, further comprising: a second read cache unit connected to the second bus interface circuit and the data comparison module, respectively, for caching the second data received by the second bus interface circuit and outputting the second data to the data comparison module.

5. The data comparison module includes an exclusive OR circuit unit, the exclusive OR circuit unit including a first input terminal, a second input terminal, and an output terminal; the first input terminal is connected to the first read cache unit and is used to input the first data; the second input terminal is connected to the second read cache unit and is used to input the second data; 5. The integrated circuit according to claim 4, wherein the output terminal is connected to an error processing module and is used to output the data error signal to the error processing module.

6. The access signal determination module: a first address register used to store an upper limit value of an address range corresponding to the preset level; a second address register used to store a lower limit value of an address range corresponding to the preset level; The address filtering circuit a first comparison unit respectively connected to the interface circuit and the first address register, the first comparison unit being used to compare the access address of the first memory access signal received by the interface circuit with the upper limit value in the first address register to obtain a first comparison result; a second comparison unit respectively connected to the interface circuit and the second address register, for comparing the access address of the first memory access signal received by the interface circuit with the lower limit value in the second address register to obtain a second comparison result; 2. The integrated circuit of claim 1, further comprising: a judgment unit connected to the first comparison unit, the second comparison unit, and the access signal processing circuit, respectively, and used to output a safety level compliance state to the access signal processing circuit based on the first comparison result and the second comparison result, wherein the safety level compliance state includes two states that the target safety level complies with or does not comply with the preset level.

7. The access signal processing circuit 7. The integrated circuit of claim 6, further comprising: a finite state machine connected to the judgment unit, the finite state machine being used to, when the safety level compliance state is compliance, add preset shift information to the access address of the first memory access signal to obtain the shifted address, obtain the second memory access signal based on the shifted address, and transmit the second memory access signal to the second memory module.

8. The access signal processing circuit 8. The integrated circuit of claim 7, further comprising a first register coupled to said finite state machine and used to store said preset shift information.

9. The access signal determination module:

2. The integrated circuit according to claim 1, further comprising a channel selection circuit connected to the interface circuit and the access signal processing circuit, respectively, and used to realize transmission of the first memory access signal and the second memory access signal by selecting a channel.

10. A processing method for memory access, comprising: a step of transmitting a first memory access signal to a first memory module by a processor, and determining a target safety level corresponding to the access address of the first memory access signal by comparing the access address of the first memory access signal with a predetermined address range, wherein the address range of the first memory module includes the predetermined address range corresponding to the predetermined level; a step of performing an address shift on the access address of the first memory access signal based on preset shift information in response to the target safety level being the preset level, to obtain a shifted address, and determining a second memory access signal based on the shifted address; transmitting the second memory access signal to a second memory module; generating a third ready signal to notify the processor not to start a read or write operation in response to the first ready signal transmitted by the first bus interface circuit based on a backpressure signal on the bus and / or the second ready signal transmitted by the second bus interface circuit based on the backpressure signal on the bus; If the target safety level is the preset level, reading first data from the first memory module and reading second data from the second memory module, and if the target safety level is not the preset level, reading the first data only from the first memory module.

11. A computer-readable storage medium having a computer program stored thereon, the computer program being for executing the processing method for memory access according to claim 10.

12. a processor; a memory adapted to store instructions executable by the processor, The processor is adapted to implement the processing method for memory access according to claim 10 by reading the executable instructions from the memory and executing the instructions; or The electronic device includes an integrated circuit for memory access according to any one of claims 1 to 9. electronic equipment.

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