Power Conversion Device

Abstract

This power conversion device drives a semiconductor switching element by using PWM control to perform the conversion between DC and AC, wherein: the pulse width of the PWM control is set using a PWM carrier wave; for a carrier frequency, the gate voltage of the semiconductor switching element, and the gate resistance which are the drive condition of the semiconductor switching element, the loss of the semiconductor switching element in a predetermined loss calculation period is obtained by calculation on the basis of a present drive condition at a predetermined update timing; and a process for obtaining the loss in the loss calculation period by calculation is repeated predetermined times while changing the drive condition, thereby determining the drive condition under which the loss becomes minimum and driving the semiconductor switching element under the determined drive condition.

Description

[Technical Field]

[0001] The present application relates to a power conversion device. [Background technology]

[0002] As a power conversion device equipped with an inverter composed of multiple semiconductor switching elements, there is a power conversion device that converts direct current into alternating current by turning on / off the multiple semiconductor switching elements using a pulse width modulation method to supply power to a three-phase AC motor. In this power conversion device, the total loss amount per predetermined time of the semiconductor switching elements is calculated as the sum of the switching loss and the steady-state loss, and the loss is reduced by switching the method of reducing the total loss amount depending on the magnitude relationship between the amount of reduction in switching loss and the amount of increase in steady-state loss (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-020418 Summary of the Invention [Problem to be solved by the invention]

[0004] The gate voltage and gate resistance, which are driving variables of the semiconductor switching element, are fixed so as to satisfy the constraints under the current and voltage conditions that maximize the surge voltage or noise. Therefore, in a power conversion device such as that described in Patent Document 1, it is not possible to adjust the gate voltage and gate resistance to reduce losses when the current and voltage conditions change.

[0005] The present application is intended to solve the above-mentioned problems, and has as its object to provide a power conversion device that can further reduce losses when current and voltage conditions change. [Means for solving the problem]

[0006] The power conversion device disclosed in the present application is a power conversion device that includes a drive controller that controls semiconductor switching elements by PWM control and performs conversion between direct current and alternating current, wherein the drive controller sets a pulse width of the PWM control using a PWM carrier wave, and calculates, at a predetermined update timing, the drive conditions of the semiconductor switching elements, namely, a carrier frequency as the frequency of the PWM carrier wave, a gate voltage of the semiconductor switching element, and a gate resistance of the semiconductor switching element, to determine a current loss of the semiconductor switching element during a predetermined loss calculation period based on the current drive conditions, changes the drive conditions, and repeats the process of calculating the loss during the loss calculation period a predetermined number of times to determine drive conditions that minimize loss, and controls the semiconductor switching elements under the determined drive conditions.

[0007] Furthermore, in a power conversion device that performs conversion between DC and AC and includes a drive controller that controls semiconductor switching elements by PWM control, the drive controller sets a pulse width of the PWM control using a PWM carrier wave, and calculates a loss of the semiconductor switching element during a predetermined loss calculation period based on the current drive conditions at a predetermined update timing for the drive conditions of the semiconductor switching element, namely, a carrier frequency as the frequency of the PWM carrier wave, a gate voltage of the semiconductor switching element, and a gate resistance of the semiconductor switching element, and if the loss is greater than a predetermined value, changes the drive conditions and repeats the process of calculating the loss during the loss calculation period a predetermined number of times to determine drive conditions that minimize the loss, and controls the semiconductor switching element under the determined drive conditions. [Effects of the Invention]

[0008] According to the power conversion device disclosed in the present application, it is possible to provide a power conversion device that can set the gate resistance and gate voltage of a semiconductor switching element to appropriate values ​​when current and voltage conditions change, thereby further reducing losses. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic block diagram showing a configuration of a power conversion device according to a first embodiment. [Figure 2] 2 is a block diagram showing the configuration of a drive controller of the power conversion device according to the first embodiment. FIG. [Figure 3] 1 is a block diagram showing a configuration of a gate driver of a power conversion device according to a first embodiment. [Figure 4] 3 is a block diagram showing the configuration of a drive condition setting unit of the power conversion device according to the first embodiment. FIG. [Figure 5] 4 is a diagram for explaining the timing of updating the drive conditions in the drive condition setting unit of the power conversion device according to the first embodiment. FIG. [Figure 6] 4 is a diagram showing a processing flow for updating a drive condition in a drive condition setting unit of the power conversion device according to the first embodiment. FIG. [Figure 7] 4 is a diagram showing an example of a range of change for each drive condition in a drive condition setting unit of the power conversion device according to the first embodiment. FIG. [Figure 8] 8A and 8B are diagrams showing examples of setting functions of the carrier frequency in the drive condition setting unit of the power conversion device according to the first embodiment. [Figure 9] 9A and 9B are diagrams showing examples of setting functions of gate voltages in the drive condition setting unit of the power conversion device according to the first embodiment. [Figure 10] 10A and 10B are diagrams showing examples of setting functions for gate resistance in the drive condition setting unit of the power conversion device according to the first embodiment. [Figure 11] 3 is a diagram illustrating a carrier wave of the power conversion device according to the first embodiment and timings for changing each driving condition. FIG. [Figure 12] 5 is a diagram illustrating whether or not each setting function is updated in a drive condition setting unit of the power conversion device according to the first embodiment. FIG. [Figure 13]FIG. 10 is a block diagram showing the configuration of a drive condition setting unit of a power conversion device according to a second embodiment. [Figure 14] FIG. 10 is a diagram showing the flow of step ST4 in the processing flow for updating the working conditions in the working condition setting unit of the power conversion device according to the second embodiment. [Figure 15] FIG. 10 is a diagram showing the flow of step ST43 in the processing flow for updating the working conditions in the working condition setting unit of the power conversion device according to the second embodiment. [Figure 16] FIG. 10 is a diagram for explaining the flow of step ST436 in the processing flow for updating the working conditions in the working condition setting unit of the power conversion device according to the second embodiment. [Figure 17] FIG. 10 is a diagram showing an example of a range of change in gate resistance in a drive condition setting unit of the power conversion device according to the second embodiment. [Figure 18] FIG. 11 is a diagram showing a processing flow for updating a drive condition in a drive condition setting unit of a power conversion device according to the third embodiment. [Figure 19] FIG. 2 is a diagram illustrating an example of a hardware configuration of a drive controller. DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiment 1 FIG. 1 is a block diagram showing the configuration of a power conversion device according to a first embodiment. Power conversion device 10 converts DC from DC power supply 20 into three-phase AC and supplies the power to motor 21. Conversely, AC power generated by motor 21 can be converted into DC power and regenerated to DC power supply 20. Power conversion device 10 includes a drive controller 11 shown in FIG. 2, which controls semiconductor switching elements 41 to 46 that constitute power conversion device 10. The DC side of power conversion device 10 is usually provided with a smoothing capacitor 31 that smoothes power pulsation. Here, motor 21 is connected to the AC side of power conversion device 10, but what is connected to the AC side is not limited to a motor and can be any device that can operate on AC.

[0011] The drive controller 11 determines gate signals 8i1 (i = 1 to 6), gate voltage command values ​​8i2 (i = 1 to 6), and gate resistance command values ​​8i3 (i = 1 to 6) for the semiconductor switching elements 41 to 46 (also referred to as 4i (i = 1 to 6). The numbers of the values ​​and signals corresponding to each semiconductor switching element 4i may also be expressed in the same manner), and outputs them to gate drivers 8i (i = 1 to 6) for each semiconductor switching element 4i (i = 1 to 6). The gate drivers 8i (i = 1 to 6) generate gate voltage signals 8i4 (i = 1 to 6) that control the semiconductor switching elements 4i (i = 1 to 6) based on commands from the drive controller 11. The power conversion device 10 also includes a voltage sensor 51 that detects the DC voltage of the DC power supply, a current sensor 61 that detects the AC current supplied to the motor 21, and a temperature sensor 7i (i = 1 to 6) that detects the temperature of each semiconductor switching element 4i (i = 1 to 6).

[0012] With the above configuration, the power conversion device 10 converts DC power from the DC power supply 20 into AC power by turning on and off the semiconductor switching elements 4i (i = 1 to 6) in accordance with the gate signal 8i1 (i = 1 to 6), thereby driving the motor 21. Conversely, by turning on and off the semiconductor switching elements 4i (i = 1 to 6) in accordance with the gate signal 8i1 (i = 1 to 6), the power conversion device 10 can convert AC power generated by the motor 21 into DC power and regenerate it into the DC power supply 20. Here, the on / off control of the semiconductor switching elements is PWM control, in which the pulse width is controlled using a PWM (Pulse Width Modulation) carrier wave as shown in FIG. 11 (described later). While FIG. 1 shows a power conversion device with a three-phase full-bridge circuit in which the AC side is three-phase AC, the technology disclosed herein can be applied to DC-AC conversion circuits using PWM control, whether the AC side is single-phase or multi-phase other than three-phase.

[0013] As shown in FIG. 2, the drive controller 11 includes an AD conversion unit 111, a drive condition setting unit 112, a duty calculation unit 113, and a gate signal output unit 114. The AD conversion unit 111 converts a DC voltage detection value 511 from the voltage sensor 51, an AC current detection value 611 from the current sensor 61, and temperature detection values ​​7i1 (i = 1 to 6) from the temperature sensors 7i (i = 1 to 6) into digital signals, such as a DC voltage detection signal 5112, a current detection signal 6112, and temperature detection signals 7i11 (i = 1 to 6), by sampling or the like. The drive condition setting unit 112 determines drive conditions for the semiconductor switching elements using signals from the AD conversion unit 111 and the like. The drive conditions to be determined here include a carrier frequency, a gate voltage, and a gate resistance. Duty calculation unit 113 generates a voltage peak command value 921 using current detection signal 6112 and DC voltage detection signal 5112, and also adjusts a ratio duty D of the on-period of each semiconductor switching element 4i (i = 1 to 6) using a carrier frequency command value 911, which is the repetition frequency of the PWM carrier wave determined by drive condition setting unit 112, to output duty D, carrier frequency command value 911, and voltage peak command value 921. Note that voltage peak command value 921 generated by duty calculation unit 113 is also used by an operation waveform estimation unit 1121 in drive condition setting unit 112, which will be described later. Gate signal output unit 114 uses carrier frequency command value 911 and voltage peak command value 921 from duty calculation unit 113 to output gate signals 8i1 (i = 1 to 6) for driving each semiconductor switching element to satisfy duty D.

[0014] FIG. 3 is a block diagram showing the configuration of gate drivers 8i (i = 1 to 6) that drive the gates of the semiconductor switching elements 4i (i = 1 to 6). Each gate driver 8i (i = 1 to 6) has the same configuration. Each gate driver 8i (i = 1 to 6) receives a gate signal 8i1 (i = 1 to 6), a gate voltage command value 8i2 (i = 1 to 6), and a gate resistance command value 8i3 (i = 1 to 6) as inputs, outputs a gate voltage signal 8i4 (i = 1 to 6), and drives the semiconductor switching element 4i (i = 1 to 6). A voltage adjustment circuit 810i (i = 1 to 6) receives a gate voltage command value 8i2 (i = 1 to 6) and the current gate voltage value as inputs, and outputs a gate voltage value that matches the command value, for example, through feedback control. The gate driving circuit 811i (i = 1 to 6) amplifies the gate signal 8i1 (i = 1 to 6) to a gate voltage command value set in the voltage adjusting circuit 810i (i = 1 to 6) and outputs the amplified signal to the gate resistance switching circuit. The gate resistance switching circuit 812i (i = 1 to 6) is a circuit that selects a gate resistance value from predetermined gate resistance candidates in accordance with a gate resistance command value 8i3 (i = 1 to 6). By setting the gate resistance to the selected gate resistance value, the circuit outputs a gate voltage signal 8i4 (i = 1 to 6) based on the gate voltage command value 8i2 (i = 1 to 6) input from the gate driving circuit 811i (i = 1 to 6). Note that, although FIG. 1 shows a configuration in which each gate driving unit 8i (i = 1 to 6) is provided outside the drive controller 11, some of the functions of each gate driving unit 8i (i = 1 to 6) or each gate driving unit 8i (i = 1 to 6) may be provided in the drive controller 11.

[0015] 4 is a block diagram showing the configuration of drive condition setting unit 112. Within drive condition setting unit 112, the drive conditions, that is, carrier frequency, gate voltage, and gate resistance, are set as functions for one AC cycle. This function will be referred to as the setting function. Drive condition setting unit 112 receives a current carrier frequency setting function 911f (hereinafter, when a parameter is a function, the symbol f is added), gate voltage setting function 8i2f (i = 1 to 6) and gate resistance setting function 8i3f (i = 1 to 6) of each semiconductor switching element, voltage peak command value 921, voltage frequency command value 931, static characteristics 941 of semiconductor switching elements and dynamic characteristics 942 of semiconductor switching elements stored in memory, as well as DC voltage detection signal 5112 converted by AD conversion unit 111 and temperature detection signal 7i11 (i = 1 to 6) of each semiconductor switching element.

[0016] A set value reading unit 1125 reads a current carrier frequency setting function 911f, a gate voltage setting function 8i2f (i = 1 to 6) and a gate resistance setting function 8i3f (i = 1 to 6) for each semiconductor switching element, a voltage peak command value 921, and a voltage frequency command value 931. An operating waveform estimation unit 1121 estimates a gate signal pattern 951 and an operating current waveform 961 for one period of the voltage frequency command value 931. A semiconductor characteristic derivation unit 1124 reads static characteristics 941 and dynamic characteristics 942 of the semiconductor switching element that are stored in advance as data in memory. From these stored static characteristics and dynamic characteristics of the semiconductor switching element, a conduction loss characteristic 9411 and a switching loss characteristic 9421 of the semiconductor switching element are generated as approximate expressions or approximate data that depend on five variables for each semiconductor switching element: applied voltage, current flow, gate resistance, gate voltage, and temperature.

[0017] Here, static characteristics 941 of the semiconductor switching element on the input side of semiconductor characteristics derivation unit 1124 are given as characteristic data of the forward voltage drop and reverse voltage drop of the target semiconductor switching element, with the flow current, temperature, and gate voltage as parameters. Also, dynamic characteristics 942 of the semiconductor switching element are given as characteristic data of the turn-on loss (loss when the semiconductor switching element is turned on) and turn-off loss (loss when the semiconductor switching element is turned off) of the target semiconductor switching element, with the flow current, temperature, gate voltage, gate resistance, and applied DC voltage as parameters.

[0018] The semiconductor characteristic derivation unit 1124 uses the input static characteristic 941 of the semiconductor switching element to generate a conduction loss characteristic 9411 of the semiconductor switching element as an approximate expression or approximate data with the gate voltage, junction temperature, and conduction current as parameters. The semiconductor characteristic derivation unit 1124 also uses the input dynamic characteristic 942 of the semiconductor switching element to generate a switching loss characteristic 9421 of the semiconductor switching element as an approximate expression or approximate data with the gate voltage, gate resistance, junction temperature, applied DC voltage, and conduction current as parameters. The semiconductor characteristic derivation unit 1124 can be omitted if the conduction loss characteristic 9411 of the semiconductor switching element and the switching loss characteristic 9421 of the semiconductor switching element generated as the approximate expression or approximate data are generated externally and stored in memory.

[0019] Then, in loss calculation unit 1122, gate signal pattern 951 and operating current waveform 961 output from operating waveform estimation unit 1121, DC voltage detection signal 5112 and temperature detection signal 7i11 (i = 1 to 6) of each semiconductor switching element output from AD conversion unit 111, each gate voltage setting function 8i2f (i = 1 to 6), and each gate resistance setting function 8i3f (i = 1 to 6) are applied to semiconductor switching element conduction loss characteristic 9411 and semiconductor switching element switching loss characteristic 9421 output from semiconductor characteristic derivation unit 1124, thereby calculating loss 97i as the sum of the conduction loss and switching loss of each semiconductor switching element 4i (i = 1 to 6) in one period of voltage frequency command value 931, i.e., one AC period. Note that junction temperature is one of the parameters set in the characteristics of the semiconductor switching elements, and the junction temperature of each semiconductor switching element can be estimated from each temperature detection signal 7i11 (i = 1 to 6). In the above, the loss for one AC cycle is calculated, but the loss for, for example, two AC cycles may be calculated, or the loss for a predetermined loss calculation period may be calculated. This loss calculation period is preferably at least one AC cycle.

[0020] The drive condition update unit 1123 updates the setting functions of the carrier frequency, gate voltage, and gate resistance to setting functions that reduce loss. To this end, the loss calculation unit 1122 repeats the process of changing the setting functions of the carrier frequency, gate voltage, and gate resistance, and calculating the loss based on the changed setting functions of the carrier frequency, gate voltage, and gate resistance, thereby determining the setting functions of the carrier frequency, gate voltage, and gate resistance that reduce the loss of the semiconductor switching element. The drive condition update unit 1123 outputs a carrier frequency command value 911, gate voltage command values ​​8i2 (i = 1 to 6), and gate resistance command values ​​8i3 (i = 1 to 6) based on the determined setting functions. These command values ​​are output, for example, for each Tsw (described later) as the value of the setting function corresponding to the phase of the AC at that time.

[0021] 5 shows the update timing for updating each setting function of the carrier frequency, gate voltage, and gate resistance, which are the drive conditions, in drive condition setting unit 112, in relation to the AC period. As shown in FIG. 5, in this embodiment, one period of the sinusoidal current per phase flowing through motor 21 connected to the AC side of the inverter is the period Trot that forms the basis for updating, and processing for updating the drive conditions is executed at a period that is an integer multiple (n times) of Trot. After the processing for updating the drive conditions is executed, the semiconductor switching elements are driven and operated under the updated drive conditions for a period that is n times Trot (also referred to as a predetermined drive period).

[0022] FIG. 6 is a flow diagram showing the processing in the drive condition setting unit 112 described in FIG. 4. The processing in FIG. 6 is executed at the update timing shown in FIG. 5. That is, the processing in FIG. 6 is executed at the update timing to determine and update the setting functions of the carrier frequency, gate voltage, and gate resistance within one AC cycle Trot. Note that each setting function only needs to be set as a function for a period of at least one AC cycle, and may be set as a function for a period of, for example, two AC cycles, or may be set as a function for an even longer period. In the following, an example will be described in which each setting function is set as a function for a period of one AC cycle.

[0023] First, the setting functions for the current carrier frequency, gate voltage, and gate resistance are read (step ST1). Using these setting functions, the loss of one AC cycle of the semiconductor switching elements 41 to 46 is calculated as the loss of the current semiconductor switching elements (step ST2).

[0024] The loss of the semiconductor switching element is found by calculation by applying the current gate voltage setting function 8i2f (i = 1 to 6) and gate resistance setting function 8i3f (i = 1 to 6) stored in memory, the gate signal pattern 951 and operating current waveform 961 output from the operating waveform estimation unit 1121, the temperature detection signal 7i11 (i = 1 to 6) of each semiconductor switching element, and the DC voltage detection signal 5112 to the conduction loss characteristic 9411 of the semiconductor switching element and the switching loss characteristic 9421 of the semiconductor switching element.

[0025] Next, in step ST4, the ranges of change for the carrier frequency, gate voltage, and gate resistance are determined to determine the setting functions to be updated for the carrier frequency, gate voltage, and gate resistance. Each of these ranges of change is determined as a function of the upper and lower limits over one AC cycle, so that the setting functions for each parameter fall within that range. Figure 7 shows examples of the ranges of change for the carrier frequency fsw, gate resistance Rg, and gate voltage Vg.

[0026] The upper limit value fswu and lower limit value fswl of the range of change of the carrier frequency fsw are determined by constraints different from those of loss calculations, such as control characteristics or the processing speed of the control CPU. The upper limit value Rgu of the gate resistance Rg is determined mainly by the withstand voltage of the element, while the lower limit value Rgl is determined mainly by constraints different from those of losses, such as the surge voltage of the semiconductor switching element. The upper limit value Vgu of the gate voltage Vg is determined by constraints due to surge voltage, while the lower limit value Vgl is determined by constraints different from those of losses, such as the saturation characteristics of the semiconductor switching element.

[0027] Next, the setting functions for the carrier frequency, gate voltage, and gate resistance are set within the ranges of the carrier frequency (fswu - fswl), gate voltage (Vgu - Vgl), and gate resistance (Rgu - Rgl) (ST5).

[0028] Examples of the setting function fsws for the carrier frequency fsw are shown in Figures 8A and 8B. The thick line represents the setting function fsws. Figure 8A shows an example of a setting function fsws that reduces switching loss by linearly lowering the frequency toward the phase (Trot / 4, 3Trot / 4) where the output current peaks. Figure 8B shows an example of a setting function fsws that does not change the set value, making it a function with a constant value. The set value can be left unchanged even when updating, or the carrier frequency can be changed when updating and held constant at that set value for one AC cycle (during Trot). It is also possible to change the carrier frequency in steps within one AC cycle.

[0029] Examples of gate voltage Vg setting functions are shown in Figures 9A and 9B. The bold line represents the setting function Vgs. Figure 9A shows an example in which a setting function Vgs is determined to lower the gate voltage near the phases (Trot / 4, 3Trot / 4) where the output current peaks. This setting takes into account the fact that surge voltage increases as the switching current increases, and aims to maintain the surge voltage below the allowable voltage value by lowering the gate voltage over a predetermined period. Figure 9B also shows an example in which a function is set to a constant value. The setting value can be left unchanged even when updating, or the gate voltage can be changed only when updating and maintained at that setting for one AC cycle (Trot). Because switching the gate voltage requires a response time via the capacitor load, a step change is used rather than a ramp change.

[0030] Examples of the setting function Rgs for gate resistance Rg are shown in Figures 10A and 10B. Figure 10A shows an example of a setting function Rgs that changes depending on the phase. In this example, the gate resistance is set to increase near the phases (Trot / 4, 3Trot / 4) where the output current peaks. This setting aims to maintain the surge voltage below the allowable voltage value by increasing the gate resistance at predetermined intervals, taking into account that surge voltage increases as the switching current increases. However, because increasing the gate resistance increases switching loss, the gate resistance is set to be as small as possible within the constraints of the surge voltage. Figure 10B also shows an example of setting the function to a constant value. It is also possible to set the setting function Rgs to a value that does not change even when updated, or to change the gate resistance value when updated and maintain that value constant for one AC cycle (during Trot). The gate resistance switching circuit 812i (i = 1 to 6) is configured to switch a fixed resistance value using a switch or other device. Therefore, the gate resistance value is switched in a stepwise manner rather than a ramp-like manner.

[0031] The losses of the semiconductor switching elements 41 to 46 are calculated and stored using the setting functions of the carrier frequency, gate voltage, and gate resistance determined as described above (step ST6). Steps ST5 and ST6 are repeated a predetermined number of times (N times). That is, N+1 combinations of the setting functions of the carrier frequency, gate voltage, and gate resistance, including the current settings, and the losses of the semiconductor switching elements are stored. A combination of the setting functions of the carrier frequency, gate voltage, and gate resistance that minimizes the loss among the N+1 losses is determined (step ST 7 ), and drives the semiconductor switching elements 41 to 46 based on these set functions.

[0032] In this way, it is possible to find the combination of setting functions that minimizes loss from a wide range of combinations of setting functions set within the ranges of change of the carrier frequency, gate voltage, and gate resistance determined in step ST4. Therefore, even if the current and voltage conditions on the AC side or the voltage on the DC side change, it is possible to set drive conditions, including the gate voltage and gate resistance, that minimize loss in the semiconductor switching elements, resulting in a power conversion device with reduced loss.

[0033] As described above, the carrier frequency, gate voltage, and gate resistance are set as a setting function for one AC cycle, i.e., a function of the AC phase. The output of the drive controller 11, i.e., each gate signal 8i1 (i = 1 to 6), gate voltage command value 8i2 (i = 1 to 6), and each gate resistance command value 8i3 (i = 1 to 6), is output as a value based on each setting function for each AC phase. For example, each gate signal 8i1 (i = 1 to 6), each gate voltage command value 8i2 (i = 1 to 6), and each gate resistance command value 8i3 (i = 1 to 6) are output from the drive controller 11 for each cycle of the carrier frequency, i.e., for each basic pulse of PWM control. Gate voltage signals 8i4 (i = 1 to 6) based on these values ​​are applied from the gate driver 8i (i = 1 to 6) to the gate of each semiconductor switching element 4i (i = 1 to 6), thereby driving each semiconductor switching element 4i (i = 1 to 6).

[0034] When changing the value in steps over one AC cycle, as with the gate voltage setting function Vgs in Fig. 9A or the gate resistance setting function Rgs in Fig. 10A, the timing of the change is set to the peak or valley of the PWM carrier wave (the points indicated by ●) shown in Fig. 11. In other words, the period for changing the value in steps should be longer than one cycle of the PWM carrier wave (Tsw in Fig. 11), and the timing of the change should be set to coincide with the peak or valley of the carrier wave.

[0035] 11 shows a case where the timing of the change is synchronized with the peak or valley of the PWM carrier wave, but the timing of the change may be set to any phase of the PWM carrier wave. The change period is determined by the performance of the controller, but the change period of the carrier frequency, gate voltage, and gate resistance should be set to a period longer than one period of the PWM carrier wave, and the change timing should be set to coincide with the same phase of the carrier wave.

[0036] Regarding the step-like change period of the gate voltage, gate resistance, and carrier frequency, when the gate voltage command value is changed, the gate voltage value of the gate driver shown in Figure 1 changes. However, a smoothing capacitor is always provided in the part to which the gate voltage is applied. Due to the capacitance of this smoothing capacitor, there is a delay in the change in gate voltage relative to the step change in the command value. In particular, if the capacitance of the capacitor is increased, there is a risk that the change in gate voltage will be longer than the period of change in the carrier period. On the other hand, changes in carrier frequency and gate resistance are changes without a time constant. Therefore, when changing the gate voltage step-wise, it is possible to change it in an AC period, i.e., a slow period, while it is also possible to change the carrier frequency and gate resistance in the carrier period, i.e., a fast period.

[0037] As shown in the table in Fig. 12, there are eight combinations for whether or not to update the setting functions of the carrier frequency, gate resistance, and gate voltage shown in Figs. 8A to 10B. Combination 1 is an operating mode in which no updates are made. When the setting function is set in step ST4, combinations 2 to 8 apply. When the setting function is changed at the update timing and then maintained until the next update timing, this is classified as "yes."

[0038] For example, in combination 2, only the setting function of the carrier frequency is updated. That is, in step ST5, only the setting function of the carrier frequency is changed, while the setting function of the gate voltage and the setting function of the gate resistance are not changed, and the loss is calculated in step ST6. This process is repeated N times to determine the setting function of the carrier frequency that minimizes the loss.

[0039] The carrier frequency is set from the perspective of the control quality of the inverter's sinusoidal current, while the gate voltage and gate resistance are set from the perspective of the loss in one switching operation. In this way, by selecting a combination of parameters to be updated from the combinations in Figure 12 in drive condition update unit 1123 based on the difference in perspective between setting the carrier frequency and setting the gate voltage and gate resistance, it is possible to search for drive conditions with smaller losses than when the parameters to be updated are only the carrier frequency alone, or only the gate resistance and gate voltage.

[0040] Embodiment 2 In the first embodiment, the lower limit of the gate resistance is set (1) within one AC cycle, (2) according to the current value, and (3) subject to the withstand voltage of the semiconductor switching elements. For example, if a storage battery is used as the DC power source, it is expected that the DC voltage will change over a period of time much longer than the AC cycle. It is preferable to set the lower limit of the gate resistance according to this changing DC voltage, taking into account surge voltage on the motor side, noise, and false firing of the semiconductor switching elements.

[0041] When considering surge voltages on the motor side, it's important not only to consider the withstand voltage of the semiconductor switching elements themselves, but also to ensure that the surge voltage, superimposed on the inverter's output voltage via the output cable, is applied to the motor's input terminals. Therefore, the surge voltage must meet the upper limit of withstand voltage determined by the motor's dielectric strength. Furthermore, increasing the switching speed by reducing the gate resistance can lead to increased noise and false firing (a condition in which the semiconductor switching element turns on without following the gate signal's "off" signal), which can degrade reliability. Therefore, the switching speed must be kept below a certain level. The switching speed, determined by the surge voltages at the input terminals of the semiconductor switching elements and motor, as well as the switching speed determined by suppressing noise and false firing of the semiconductor switching elements, depends not only on the inverter's sinusoidal current but also on the DC voltage.

[0042] Therefore, in the second embodiment, when determining the setting function for gate resistance Rg described in the first embodiment, the DC voltage and output current are used as input information, and the lower limit Rgl of the gate resistance is determined taking into consideration an upper limit of the switching speed determined in advance to suppress noise and false firing of the semiconductor switching elements, in addition to the upper limit of the switching speed determined by the allowable value of surge voltage determined by the withstand voltage of the semiconductor switching elements and the allowable value of surge voltage determined by the withstand voltage of the input terminals of the motor.

[0043] The setting function of the gate resistance Rg is updated in the drive condition update unit 1123. Therefore, a DC voltage detection signal 5112 and a current detection signal 6112 are input to the drive condition update unit 1123, as shown in FIG.

[0044] 14 and 15 are flowcharts illustrating the determination of the gate resistance change range in step ST4 in the drive condition update unit 1123 in the flowchart illustrating the process in the drive condition setting unit 112 described in FIG. 6. Here, the lower limit of the gate resistance change range is determined by taking into account the upper limit of the switching speed, which is determined by the surge voltage tolerance determined by the breakdown voltage of the semiconductor switching element and the surge voltage tolerance determined by the breakdown voltage of the motor input terminal, as well as a predetermined upper limit of the switching speed to prevent noise and false firing. Other than ST4, steps ST1, ST2, ST5, ST6, and ST7 are the same as those in FIG. 6. Therefore, the process is executed at the update timing shown in FIG. 5. That is, at the update timing, the process shown in FIG. 6, including the process in step ST4 shown in FIGS. 14 and 15, is executed to determine and update the setting functions for the carrier frequency, gate voltage, and gate resistance within one AC cycle Trot.

[0045] Step ST4, as in the first embodiment, is a step for determining the carrier frequency change range, the gate voltage change range, and the gate resistance change range. Step ST41 for determining the carrier frequency and gate voltage change ranges shown in FIG. 14 is the same as in the first embodiment. In the second embodiment, in step ST42 for determining the gate resistance change range, an additional condition is added to the conditions described in the first embodiment. Each of these change ranges is determined as a function of the upper and lower limits over at least one AC cycle, so that the setting function of each parameter falls within that change range. As described in the first embodiment, each setting function and each change range is not limited to one AC cycle, and may be set as a function over a period longer than one AC cycle. Below, as an example, a case will be described in which each setting function and each change range is set as a function over a period of one AC cycle.

[0046] As shown in FIG. 14, in step ST42, which determines the upper limit Rgu and lower limit Rgl of the gate resistance Rg, the upper limit Rgu is determined mainly from the element withstand voltage of the semiconductor switching element (step ST421). FIG. 15 shows a detailed processing flow of step ST43, which determines the lower limit Rgl of the gate resistance shown in FIG. 14. First, the current DC voltage and the output current for one AC cycle are read (step ST431). The output current for one AC cycle is stored as a function using, for example, the phase as a parameter. Next, the allowable value of the surge voltage, which takes into account the DC voltage, the withstand voltage of the semiconductor switching element, and the output current, is expressed as a function of one AC cycle (step ST432). Furthermore, the allowable value of the surge voltage, which takes into account the DC voltage, the withstand voltage of the input terminal of the motor, and the output current, is expressed as a function of one AC cycle (step ST433).

[0047] From these surge voltage tolerance functions, the lower surge voltage tolerance value is selected for each phase of one AC cycle to determine the function of the surge voltage tolerance during one AC cycle.The switching speed of the semiconductor switching element corresponding to that surge voltage tolerance is the upper limit of the switching speed, and this switching speed is determined as a function of one AC cycle (step ST434).Here, the switching speed di / dt1 allowed from the surge voltage tolerance is calculated using the following formula.The surge voltage absolute value (the value obtained by superimposing the surge voltage on the DC voltage) is Vsurge, the DC voltage is Vdc, and the parasitic inductance is L.The parasitic inductance L is a constant that is measured in advance during implementation. di / dt1 = (Vsurge - Vdc) / L Equation (1)

[0048] On the other hand, the upper limit of the switching speed di / dt2 is determined based on the constraints of noise and erroneous firing of the semiconductor switching elements (step ST435). This upper limit of the switching speed is determined, for example, based on the constraints of noise and erroneous firing of the semiconductor switching elements corresponding to the peak values ​​of the DC voltage and current at that time.

[0049] Then, the gate resistance corresponding to the switching speed function di / dt1 determined in step ST434 and the upper limit of the switching speed di / dt2 determined in step ST435 is calculated, and the two values ​​are compared for each phase of one AC cycle, and the larger value is selected to determine the lower limit value Rgl of the gate resistance as a function of one AC cycle (step ST436).

[0050] Here, in step ST434, a function of the upper limit of the switching speed for each function may be determined from the functions of the allowable value of each surge voltage, and in step ST436, these two functions of the upper limit of the switching speed and the switching speed determined in step ST435 may be compared for each phase to determine the lower limit of the gate resistance. By determining the switching speed function by setting the smallest (slowest) switching speed for each phase as the upper limit of the switching speed, and then determining the gate resistance function corresponding to that switching speed function, the lower limit of the gate resistance can be determined as a function of one AC cycle. Alternatively, a function of the gate resistance corresponding to each upper limit of the switching speed may first be determined, and the largest gate resistance value for each phase may be set as the lower limit of the gate resistance for that phase to determine the function of the lower limit of the gate resistance for one AC cycle.

[0051] In any case, the lower limit of the range of change in gate resistance can be determined as a function of one AC cycle by determining as a lower limit the gate resistance corresponding to the upper limit of the slowest switching speed for each AC phase from the upper limit of the switching speed of the semiconductor switching element, which is determined by the allowable value of the surge voltage of the semiconductor switching element, the upper limit of the switching speed of the semiconductor switching element, which is determined by the allowable value of the surge voltage of the motor, and the upper limit of the switching speed of the semiconductor switching element, which is determined by the constraints of noise generated by the power conversion device and false firing of the semiconductor switching element.

[0052] FIG. 16 shows the upper limit Rgu and lower limit Rgl (Rgl1 and Rgl2) of the gate resistance. The lower limit Rgl shows its relationship with the switching speed di / dt. The upper limit Rgu of the gate resistance Rg is determined in step ST421 mainly based on the device breakdown voltage. Rgl1 is the gate resistance value corresponding to di / dt1 calculated in step ST434. As shown in FIG. 16, the switching speed di / dt1, determined based on the allowable surge voltage, varies between the value at which the DC voltage is maximum and the output current is at its peak value and the value at which the DC voltage is minimum and the output current is 0 A. Rgl2 is the gate resistance value corresponding to the switching speed di / dt2 determined in step ST435 based on the constraints on noise and false firing of switching. Since DC voltage does not change significantly over one AC cycle, Rgl2 is compared with Rgl1, which corresponds to the output current that changes over one AC cycle, for each phase, and the larger value for that phase is determined as Rgl for that phase. By determining Rgl over one AC cycle, the function of Rgl for one AC cycle can be determined. Figure 17 shows an example of the function of the upper limit value Rgu and lower limit value Rgl of the gate resistance over one AC cycle. The example in Figure 17 shows an example in which Rgl2 is larger than Rgl1 in phases where the output current is small, and Rgl1 is larger than Rgl2 in phases where the output current is large. This function uses Rgl2 as the Rgl value in phases where the output current is small, and Rgl1 as the Rgl value in phases where the output current is large.

[0053] The upper limit value Rgu of the gate resistance determined in step ST421 and the lower limit value Rgl of the gate resistance determined in step ST436 are set as the variation range of the gate resistance Rg (step ST422). A setting function for the gate resistance is set so that the value falls within this variation range (step ST5 in FIG. 6).

[0054] According to the second embodiment, it is possible to suppress the dielectric breakdown of the motor, noise, and false firing of the semiconductor switching elements, and to achieve low loss in the inverter. Furthermore, by taking the DC voltage into consideration, the lower limit Rgl can be further increased when the DC voltage is lower than the maximum value (worst condition), thereby achieving further low loss. That is, if the DC voltage is not taken into consideration, the lower limit Rgl of the gate resistance is fixed under the condition where the DC voltage is maximum. However, by taking the DC voltage into consideration, Rgl can be made smaller than the Rgl under the condition where the DC voltage is maximum, when the DC voltage is low. This makes it possible to reduce the switching loss below the switching loss under the condition where the DC voltage is maximum, thereby achieving further low loss in the power conversion device.

[0055] Embodiment 3 figure 18 is an embodiment of the present invention. 3 1 is a flowchart showing the processing in the drive condition setting unit 112 of the power conversion device according to the present invention. 18 In this processing flow, the determination processing of step ST3 is added between step ST2 and step ST4 of the processing flow of Fig. 6. That is, if the loss calculated as the current loss of the semiconductor switching element is equal to or less than a predetermined value (no in step ST3), the driving conditions are not updated and driving continues with the current setting function. If the calculated loss is greater than the predetermined value (yes in step ST3), steps ST4 to ST7 are executed.

[0056] In this way, when the current loss is small, no extra processing is performed, and the load on the processing device can be reduced.

[0057] Specifically, the drive controller 11 shown in FIG. 19As shown in the figure, the system includes a processing unit 11p such as a CPU (Central Processing Unit), a storage device 11m that exchanges data with the processing unit 11p, and an input / output interface 11f that inputs and outputs signals between the processing unit 11p and the outside. The processing unit 11p may include an application-specific integrated circuit (ASIC), an integrated circuit (IC), a digital signal processor (DSP), a field programmable gate array (FPGA), and various signal processing circuits. Furthermore, the processing unit 11p may include a plurality of processing units of the same or different types, each performing a different process. The storage device 11m may include a random access memory (RAM) that can read and write data from the processing unit 11p, a read-only memory (ROM) that can read data from the processing unit 11p, and the like. The input / output interface 11f is configured from, for example, an A / D converter (corresponding to the AD conversion unit in FIG. 2) that inputs sensor signals output from the voltage sensor 51, current sensor 61, temperature sensor 7i (i = 1 to 6) and the like to the arithmetic processing device 11p, an interface for outputting gate signals 8i1 (i = 1 to 6) and the like to each gate driving unit 8i (i = 1 to 6), etc. Note that each gate driving unit 8i (i = 1 to 6) may be provided in the drive controller 11.

[0058] Although various exemplary embodiments and examples are described in this application, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are contemplated within the scope of the technology disclosed in this specification. For example, this includes cases where at least one component is modified, added, or omitted, and even cases where at least one component is extracted and combined with components of other embodiments. [Explanation of symbols]

[0059] 10 power conversion device, 11 drive controller, 20 DC power supply, 4i (i = 1 to 6) semiconductor switching element, 8i (i = 1 to 6) gate drive unit, 8i2 (i = 1 to 6) gate voltage command value, 8i3 (i = 1 to 6) gate resistance command value, 51 voltage sensor, 511 DC voltage detection value, 61 current sensor, 611 current detection value, 7i (i = 1 to 6) temperature sensor, 7i1 (i = 1 to 6) temperature detection value, 112 drive condition setting unit, 911 carrier frequency command value, 9411 conduction loss characteristics of semiconductor switching element, 9421 switching loss characteristics of semiconductor switching element, 951 gate signal pattern, 1122 loss calculation unit, 1123 drive condition update unit

Claims

1. A power conversion device that converts between direct current and alternating current and includes a drive controller that controls semiconductor switching elements by PWM control, the drive controller sets a pulse width of the PWM control using a PWM carrier wave, and calculates a current loss of the semiconductor switching element during a predetermined loss calculation period based on current drive conditions, which are drive conditions of the semiconductor switching element, at a predetermined update timing, for a carrier frequency as a frequency of the PWM carrier wave, a gate voltage of the semiconductor switching element, and a gate resistance of the semiconductor switching element; changing the drive conditions and repeating a process of calculating the loss during the loss calculation period a predetermined number of times to determine the drive conditions that minimize the loss, and controlling the semiconductor switching element under the determined drive conditions; Power conversion device.

2. A power conversion device that converts between direct current and alternating current and includes a drive controller that controls semiconductor switching elements by PWM control, The drive controller sets a pulse width of the PWM control using a PWM carrier wave, and calculates a loss of the semiconductor switching element during a predetermined loss calculation period based on the current drive conditions, which are the carrier frequency as the frequency of the PWM carrier wave, the gate voltage of the semiconductor switching element, and the gate resistance of the semiconductor switching element, at a predetermined update timing, and if the loss is larger than a predetermined value, changing the drive conditions and repeating a process of calculating the loss during the loss calculation period a predetermined number of times to determine the drive conditions that minimize the loss, and controlling the semiconductor switching element under the determined drive conditions; Power conversion device.

3. 3. The power conversion device according to claim 1, wherein a range of change of the carrier frequency, a range of change of the gate voltage, and a range of change of the gate resistance are set with respect to the drive conditions, and the carrier frequency, the gate voltage, and the gate resistance are each set as a function of a period of at least one cycle of the AC so as to fall within each of the set ranges of change.

4. 3. The power conversion device according to claim 1 or 2, wherein the loss is determined by applying the temperature of the semiconductor switching element, the DC voltage on the DC side of the power conversion device, the AC current on the AC side of the power conversion device, and the driving conditions to a conduction loss characteristic which is a loss in voltage drop due to a current flowing through the semiconductor switching element, given as parameters of the gate voltage, the junction temperature of the semiconductor switching element, and the current flowing through the semiconductor switching element, and a switching loss characteristic which is a loss during switching of the semiconductor switching element, given as parameters of the gate voltage, the gate resistance, the junction temperature of the semiconductor switching element, a DC applied voltage to the semiconductor switching element, and the current flowing through the semiconductor switching element.

5. The power conversion device according to claim 1 or 2, wherein the loss calculation period is at least one cycle of the AC current.

6. The power conversion device according to claim 1 or 2, wherein the update timing is set at every period that is an integral multiple of one cycle of the AC current.

7. 3. The power conversion device according to claim 1, wherein the driving condition parameters for changing the driving condition are at least one of a gate voltage of the semiconductor switching element and a gate resistance of the semiconductor switching element, and the carrier frequency.

8. 4. The power conversion device according to claim 3, wherein a motor is connected to the AC side, and the lower limit of the range of change of the gate resistance is determined as a function of at least one cycle of the AC by determining, as a lower limit, a gate resistance corresponding to the upper limit of the slowest switching speed for each phase of the AC from an upper limit of the switching speed of the semiconductor switching element determined by an allowable value of a surge voltage of the semiconductor switching element, an upper limit of the switching speed of the semiconductor switching element determined by an allowable value of a surge voltage of the motor, and an upper limit of the switching speed of the semiconductor switching element determined by constraints of noise generated by the power conversion device and false firing of the semiconductor switching element.

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