Examples of high density plasma CVD encapsulation applications for displays

Abstract

FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to moisture barrier films utilized in organic light emitting diode devices. The moisture barrier films are resistant to temperatures below about 250 degrees Celsius, inductively coupled plasma power frequencies of about 2 MHz to about 13.56 MHz or microwave power frequencies of about 2.45 GHz, and temperatures below about 10 11 cm 3 from about 10 12 cm 3 The moisture barrier film is deposited in a high-density plasma chemical vapor deposition chamber at a plasma density of 1000 nm. The moisture barrier film comprises a material selected from the group consisting of silicon oxynitride, silicon nitride, and silicon oxide. The moisture barrier film has a thickness of less than about 3,000 angstroms, a refractive index between about 1.45 and 1.95, and an absorption coefficient of about zero at UV wavelengths. The moisture barrier film may be utilized in thin film encapsulation structures or thin film transistors.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to organic light emitting diode (OLED) devices, and more particularly to moisture barrier films utilized within OLED devices. [Background technology]

[0002] In the manufacture of flat panel displays, many processes are utilized to deposit thin films, such as moisture-proof films, on substrates, such as semiconductor substrates, solar cell substrates, liquid crystal display (LCD) substrates, and / or OLED substrates, to form electronic devices thereon. Deposition of such thin films is generally accomplished by introducing precursor gases into a vacuum chamber having a substrate disposed on a temperature-controlled substrate support. The precursor gases are typically directed through a gas distribution plate located near the top of the vacuum chamber. The precursor gases in the vacuum chamber may be energized (e.g., excited) into a plasma by applying RF power from one or more radio frequency (RF) sources coupled to the chamber to a conductive showerhead disposed within the chamber. The excited gases react to form a material layer on the surface of the substrate.

[0003] Capacitively coupled plasma (CCP) equipment is often used to deposit barrier films on OLED and LCD substrates. Traditionally, plasma is formed in a conventional chamber utilizing CCP equipment to ionize gas atoms and form radicals of the deposition gas that are useful for depositing film layers on the substrate. However, barrier films deposited using CCP equipment are generally quite thick, having thicknesses of about 7,000 angstroms to about 10,000 angstroms, have non-zero absorption coefficients at ultraviolet (UV) wavelengths, and have refractive indices greater than 1.7.

[0004] Therefore, there is a need for improved methods of depositing barrier films for OLED and LCD substrates. Summary of the Invention

[0005] FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to moisture barrier films utilized in organic light emitting diode devices. The moisture barrier films are resistant to temperatures below about 250 degrees Celsius, inductively coupled plasma power frequencies of about 2 MHz to about 13.56 MHz or microwave power frequencies of about 2.45 GHz, and temperatures below about 10 11 cm -3 from about 10 12 cm -3 The moisture barrier film is deposited in a high-density plasma chemical vapor deposition chamber at a plasma density of 1000 nm. The moisture barrier film comprises a material selected from the group consisting of silicon oxynitride, silicon nitride, and silicon oxide. The moisture barrier film has a thickness of less than about 3,000 angstroms, a refractive index between about 1.45 and 1.95, and an absorption coefficient of about zero at UV wavelengths. The moisture barrier film may be utilized in thin film encapsulation structures or thin film transistors.

[0006] A method for depositing a barrier layer includes placing a substrate in a chemical vapor deposition (CVD) chamber equipped with a high density plasma arrangement, a temperature of less than about 250 degrees Celsius, a power frequency of about 2 MHz to about 13.56 MHz, and a temperature of about 10 11 cm -3 from about 10 12 cm -3 and depositing a barrier layer over the substrate using a high-density plasma arrangement at a plasma density of

[0007] The thin film encapsulation structure comprises: a first barrier layer deposited using a high-density plasma CVD chamber, wherein the first barrier layer comprises a material selected from the group consisting of silicon oxynitride, silicon nitride, and silicon oxide, and wherein the first barrier layer has a thickness of less than about 3,000 angstroms, a refractive index between about 1.45 and 1.95, and an absorption coefficient of about zero; a buffer layer disposed on the first barrier layer; and a second barrier layer deposited on the buffer layer.

[0008] A method for depositing a barrier layer includes placing a substrate in a CVD chamber equipped with a high-density plasma arrangement, and applying a temperature of less than about 250 degrees Celsius, a power frequency of about 2 MHz to about 13.56 MHz, and a frequency of about 10 11 cm -3 from about 10 12 cm -3 depositing a barrier layer above the substrate using a high-density plasma arrangement at a plasma density of about 1.45 to 1.95, wherein the barrier layer has a thickness of less than about 3,000 angstroms, a refractive index of between about 1.45 and 1.95, and an absorption coefficient of about zero.

[0009] In order that the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only exemplary embodiments and therefore should not be considered as limiting its scope, as other equally effective embodiments may be recognized. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a schematic cross-sectional view of a chemical vapor deposition apparatus, according to one embodiment. [Figure 2] FIG. 1 illustrates a high-density plasma arrangement, according to one embodiment. [Figure 3] 1 is a schematic cross-sectional view of a display device having a thin film encapsulation structure disposed thereon, according to one embodiment. [Figure 4] 1 is a schematic cross-sectional view of a thin film transistor utilized in a display device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] For ease of understanding, identical reference numerals have been used, where possible, to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0012] FIELD OF THE DISCLOSURE Embodiments of the present disclosure generally relate to moisture barrier films utilized in organic light emitting diode devices. The moisture barrier films are resistant to temperatures below about 250 degrees Celsius, inductively coupled plasma power frequencies of about 2 MHz to about 13.56 MHz or microwave power frequencies of about 2.45 GHz, and temperatures below about 10 11 cm -3 from about 10 12 cm -3 The moisture barrier film is deposited in a high-density plasma chemical vapor deposition chamber at a plasma density of 1000 nm. The moisture barrier film comprises a material selected from the group consisting of silicon oxynitride, silicon nitride, and silicon oxide. The moisture barrier film has a thickness of less than about 3,000 angstroms, a refractive index between about 1.45 and 1.95, and an absorption coefficient of about zero at UV wavelengths. The moisture barrier film may be utilized in thin film encapsulation structures or thin film transistors.

[0013] FIG. 1 is a schematic cross-sectional view of a chemical vapor deposition (CVD) apparatus 101 that can be used to perform the operations described herein. The CVD apparatus 101 may be a plasma-enhanced CVD apparatus. The CVD apparatus 101 includes a chamber 100 in which one or more films may be deposited on a substrate 120. The chamber 100 generally includes walls 102, a bottom 104, and a showerhead 106, which collectively define a process volume. The process volume may be a vacuum environment. A substrate support 118 is disposed within the process volume. The process volume is accessed through a slit valve opening 108 so that the substrate 120 can be moved in and out of the chamber 100. The substrate support 118 may be coupled to an actuator 116 to raise and lower the substrate support 118. Lift pins 122 are movably disposed through the substrate support 118 to move the substrate 120 to and from a substrate receiving surface. The substrate support 118 also includes a heating and / or cooling element 124 to maintain the substrate support 118 at a desired temperature. The substrate support 118 also includes an RF return strap 126 to provide an RF return path around the periphery of the substrate support 118 .

[0014] The showerhead 106 is coupled to the backing plate 112 by a fastening mechanism 150. The showerhead 106 is coupled to the backing plate 112 by one or more fastening mechanisms 150 to prevent subsidence and / or help control the straightness / curvature of the showerhead 106.

[0015] A gas source 132 is coupled to the backing plate 112 to supply gas through gas passages in the showerhead 106 to the processing area between the showerhead 106 and the substrate 120. A vacuum pump 110 is coupled to the chamber 100 to maintain the process volume at a desired pressure. An RF source 128 is coupled to the backing plate 112 and / or the showerhead 106 through a matching network 190 to supply RF current to the showerhead 106. The RF current creates an electric field between the showerhead 106 and the substrate support 118, which may result in plasma being generated from the gas between the showerhead 106 and the substrate support 118.

[0016] A remote plasma source 130, such as an inductively coupled remote plasma source 130, may also be coupled between the gas source 132 and the backing plate 112. During substrate processing, a cleaning gas may be supplied to the remote plasma source 130, resulting in the generation of a remote plasma. Radicals from the remote plasma may be supplied to the chamber 100 to clean components of the chamber 100. The cleaning gas may be further excited by an RF source 128 supplied to the showerhead 106.

[0017] The showerhead 106 is further coupled to the backing plate 112 by a showerhead suspension 134. In one embodiment, the showerhead suspension 134 is a flexible metal skirt. The showerhead suspension 134 has a lip 136 on which the showerhead 106 can rest. The backing plate 112 can rest on top of a ledge 114 coupled to the chamber wall 102 to seal the chamber 100 and form a vacuum environment.

[0018] 2 illustrates a high-density plasma (HDP) system 200 according to one embodiment. The HDP system 200 may be utilized with the CVD apparatus 101 of FIG. 1 to form an HDP CVD chamber (i.e., the CVD apparatus 101 includes the HDP system 200). The HDP system 200 may be an inductively coupled plasma (ICP) system or a microwave (MW) system. The HDP system 200 includes a substrate support 204 disposed within a plasma chamber 202. A gas diffuser 206 is disposed above the plasma chamber 202, and a dielectric plate 208 is disposed above the gas diffuser 206.

[0019] One or more HDP antenna coils 210 are disposed on or above the dielectric plate 208. A terminal capacitor 212 and an intermediate capacitor 214 are coupled to the one or more HDP antenna coils 210. The terminal capacitor 212 may be grounded. The intermediate capacitor 214 is coupled to a power source 218, such as an RF source. The power source 218 includes a matching circuit 216 or tuning capability for adjusting the electrical characteristics of the one or more HDP antenna coils 210. For ICP installations, the power frequency can be from about 2 MHz to about 13.56 MHz. For MW installations, the power frequency can be between about 2.4 GHz and about 2.5 GHz, such as about 2.45 GHz.

[0020] The gas diffuser 206 is configured to deliver process gas to the plasma chamber 202. Each of the one or more HDP antenna coils 210 is configured to produce an electromagnetic field that energizes the process gas into a plasma in the plasma chamber 202 below the gas diffuser 206 as the gas flows into the volume of the plasma chamber 202 below. The plasma then forms one or more films or layers on a substrate disposed on the substrate support 204.

[0021] The HDP facility 200 generates approximately 10 11 cm -3 from about 10 12 cm -3The HDP system 200 is configured to deposit or form HDP CVD films, such as moisture barrier films, on substrates by using a high plasma density of 100 Å or less and a low ion bombardment energy of less than about 10 eV. The HDP system 200 can be utilized to form high-quality films at low temperatures, such as less than about 250 degrees Celsius, and has a high deposition rate with low arcing probability. The ion / radical flux and energy of the HDP system 200 are separately controlled by source power and bias power. Moreover, utilizing the HDP system 200 to deposit a moisture barrier layer allows the moisture barrier layer to have a low RI with a wide range of RI control.

[0022] In contrast, CVD films formed or deposited by CCP equipment typically have a film thickness of about 10 9 cm -3 from about 10 10 cm -3 low plasma density of about 10 2 CCP equipment has high ion bombardment energies (> 100 eV), resulting in low ionization efficiency and high plasma damage. Furthermore, films formed by CCP equipment have poor quality when deposited at low temperatures (below about 250°C), and CCP equipment has a low deposition rate with high arcing probability. The ion / radical flux and energy of CCP equipment are controlled solely by the source power.

[0023] 3 is a schematic cross-sectional view of a display device 300 having a thin film encapsulation (TFE) structure 314 disposed thereon, according to one embodiment. The display device 300 includes a substrate 302. The substrate 302 may be made of a silicon-containing material, glass, polyimide, or a plastic such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). A light-emitting device 304 is disposed on the substrate 302. The light-emitting device 304 may be an OLED structure or a quantum dot structure. A contact layer (not shown) may be disposed between the light-emitting device 304 and the substrate 302, the contact layer being in contact with the substrate 302 and the light-emitting device 304.

[0024] A capping layer 306 is disposed above the light-emitting device 304 and the substrate 302. The capping layer 306 may have a refractive index of about 1.7 to about 1.8. A thin metal layer (not shown) may be disposed above the capping layer 306. A first barrier layer 308 is disposed on the capping layer 306 or the thin metal layer. A buffer layer 310 is disposed on the first barrier layer 308. A second barrier layer 312 is disposed on the buffer layer 310. The first barrier layer 308, the buffer layer 310, and the second barrier layer 312 constitute a TFE structure 314. The first barrier layer 308 and the second barrier layer 312 are moisture-proof films or layers.

[0025] The buffer layer 310 may include an organic material having a refractive index of about 1.5. The buffer layer 310 may include an organosilicon compound such as plasma polymerized hexamethyldisiloxane (pp-HMDSO), fluorinated plasma polymerized hexamethyldisiloxane (pp-HMDSO:F), and hexamethyldisilazane (HMDSN). Alternatively, the buffer layer 310 may be a polymer material composed of a hydrocarbon compound. The polymer material has the chemical formula C x H y O z where x, y, and z are integers. In one embodiment, the buffer layer 310 may be selected from the group consisting of polyacrylate, parylene, polyimide, polytetrafluoroethylene, fluorinated ethylene propylene copolymer, perfluoroalkoxy copolymer resin, ethylene and tetrafluoroethylene copolymer, and parylene. In one specific example, the buffer layer 310 is polyacrylate or parylene.

[0026] First barrier layer 308 may be deposited in an HDP CVD chamber, such as CVD apparatus 101 of FIG. 1, using HDP equipment such as HDP equipment 200 of FIG. 2. First barrier layer 308 is composed of a material selected from the group consisting of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). Furthermore, each layer of TFE structure 314 may be deposited in an HDP CVD chamber, such as CVD apparatus 101 of FIG. 1, using HDP equipment such as HDP equipment 200 of FIG. 2. Purging of the CVD chamber may be performed between cycles to minimize the risk of contamination.

[0027] To deposit the first barrier layer 308 using ICP HDP equipment, the power frequency can be from about 2 MHz to about 13.56 MHz. To deposit the first barrier layer 308 using MW HPD equipment, the power frequency can be between about 2.4 GHz and about 2.5 GHz, such as about 2.45 GHz. The first barrier layer can be deposited at a frequency of about 10 GHz, which results in high ionization efficiency and low plasma damage. 11 cm -3 from about 10 12 cm -3 high plasma density of about 10 2 The first barrier layer 308 is deposited using low ion bombardment energies of less than 10 eV. The first barrier layer 308 is deposited as a high-quality film at a low temperature, such as less than about 250 degrees Celsius, and at a high deposition rate with low arcing probability. In one embodiment in which the first barrier layer 308 comprises SiO, the first barrier layer 308 may be deposited at a temperature of about 100 degrees Celsius and at a rate of about 2000 angstroms per minute. In another embodiment in which the first barrier layer 308 comprises SiN, the first barrier layer 308 may be deposited at a temperature of about 100 degrees Celsius and at a rate of about 1,000 angstroms per minute.

[0028] Moreover, depositing the first barrier layer 308 using HDP equipment allows the first barrier layer 308 to have a refractive index (RI) of about 1.4 to 2.1 and a low absorption coefficient (k) of about zero, thereby allowing the first barrier layer 308 to have zero or less absorption at UV wavelengths. Near The result is zero absorption. The first barrier layer 308 deposited using HDP equipment further has a thickness of less than about 3,000 angstroms, such as less than about 2,000 angstroms, which reduces the barrier thickness requirement, reduces bending / folding stress, and reduces the time required to deposit the first barrier layer 308. Moreover, the HDP equipment allows the first barrier layer 308 to be easily deposited on the sidewall or as a sidewall barrier without causing oxidation, reducing the thickness requirement of the sidewall barrier.

[0029] In one embodiment, the first barrier layer 308 comprises SiN, and SiH4 and NH3 gases are introduced into the chamber to deposit the SiN first barrier layer 308. For example, about 100 sccm of SiH4 and about 600 sccm of NH3 may be used. A chamber pressure of about 120 mTorr, an ICP power frequency of about 2 MHz, a power of about 3,000 W, and a fluence of about 1.725 W / cm 2 may be applied for about 300 seconds.

[0030] When utilizing HDP equipment, the first barrier layer 308 comprising SiN has a wet etch rate (WER) of about 325 Angstroms per minute and a wet etch rate (WER) of about 2.52 g / cm 3 film density of about 1.91 to about 1.95, RI of about 150 GPa to about 160 GPa, and a modulus of about 1×10 to a depth of about 500 Angstroms at 40 degrees Celsius and 100% humidity. -4 g / m 2 / day is about 3 × 10 -4 g / m 2 / day water vapor transmission rate (WVTR), as well as a dense XTEM structure with fewer voids. In comparison, when using CCP equipment, a first barrier layer comprising SiN has a WER of about 13,660 Å per minute and a WVTR of about 2.10 g / cm. 3 film density of about 100 GPa, modulus of about 1×10 to a depth of about 5,000 Angstroms at 40 degrees Celsius and 100% humidity. -4 g / m 2They may have a WVTR of less than 1 / day, as well as an XTEM structure with some spherical voids.

[0031] In another embodiment, the first barrier layer 308 comprises SiON, and SiH4, N2O, and NH3 gases are introduced into the chamber to deposit the SiON first barrier layer 308. For example, about 100 sccm of SiH4, about 200 sccm to about 500 sccm of NH3, and about 100 sccm to about 400 sccm of N2O may be used. A chamber pressure of about 120 mTorr, an ICP power frequency of about 2 MHz, a power of about 3,000 W, and a fluence of about 1.725 W / cm 2 may be applied for about 300 seconds.

[0032] When using HDP equipment, the first barrier layer 308 comprising SiON has a WER of about 3,000 Angstroms per minute and a WER of about 2.13 g / cm 3 to approximately 2.26 g / cm 3 film density of about 1.47 to about 1.84, and a film density of about 1×10 to a depth of about 2,000 Angstroms at 40 degrees Celsius and 100% humidity. -4 g / m 2 / day is about 7 × 10 -4 g / m 2 In comparison, when utilizing CCP equipment, a first barrier layer comprising SiON may have a WVTR of about 20,000 Angstroms per minute, or about 2.04 g / cm. 3 and a film density of about 1×10 to a depth of about 10,000 Angstroms at 40 degrees Celsius and 100% humidity. -4 g / m 2 May have a WVTR of less than 1 / day.

[0033] In yet another embodiment, the first barrier layer 308 comprises SiO, and SiH4 and N2O gases are introduced into the chamber to deposit the SiO first barrier layer 308. For example, about 30 sccm of SiH4 and about 1,000 sccm of N2O may be used. A chamber pressure of about 120 mTorr, an ICP power frequency of about 2 MHz, a power of about 4,000 W, and a fluence of about 2,300 W / cm 2 may be applied for approximately 130 seconds.

[0034] When utilizing HDP equipment, the first barrier layer 308 comprising SiO has a WER of about 3,400 Angstroms per minute and a WER of about 2.09 g / cm 3 film density of about 1.46, an RI of about 1×10 to a depth of about 2,000 Angstroms at 40 degrees Celsius and 100% humidity. -3 g / m 2 In comparison, when using CCP equipment, a first barrier layer comprising SiO may have a WER of about 20,000 Angstroms per minute and may not have moisture barrier properties.

[0035] The second barrier layer 312 is composed of a material selected from the group consisting of SiN, SiO, and SiON. The second barrier layer 312 may comprise the same or a different material as the first barrier layer 308. In some embodiments, the second barrier layer 312 is deposited using the same processes and parameters described above using the CVD apparatus 101 of FIG. 1 and the HDP equipment 200 of FIG. 2. As such, the first barrier layer 308 and / or the second barrier layer 312 deposited using the HDP equipment at low temperatures are high-quality, thin, and dense moisture barrier layers with low RI and a low absorption coefficient of about zero.

[0036] In one embodiment, the TFE structure 314 is formed by placing the substrate 302 including the light-emitting device 304 in an HDP CVD chamber. The capping layer 306 may be deposited on the light-emitting device 304 in the CVD chamber, or the capping layer 306 may already be deposited on the light-emitting device when placed in the chamber. The first barrier layer 308 is deposited on the capping layer 306 in the chamber by the process described above.

[0037] A buffer layer 310 is then deposited in the chamber by a CVD process over the first barrier layer 308. Because different precursors are used in the deposition process, a purge step is performed after depositing the first barrier layer 308 before depositing the buffer layer 310. After the buffer layer 310 is deposited, another purge step is performed. A second barrier layer 312 is deposited over the buffer layer 310, and the second barrier layer 312 may be deposited under the same process conditions as the first barrier layer 308.

[0038] 4 is a schematic cross-sectional view of a thin film transistor (TFT) 400 utilized in a display device, according to various embodiments. The TFT 400 can be a metal oxide TFT. The TFT 400 includes a substrate 402. The substrate 402 may be made of a silicon-containing material, glass, polyimide, or a plastic such as PET or PEN. A gate electrode 404 is disposed on the substrate 402. The gate electrode 404 may include copper, tungsten, tantalum, or aluminum, among others. A gate insulating layer 406 is disposed above the gate electrode 404 and the substrate 402.

[0039] A semiconductor layer 408 is disposed above the gate insulating layer 406. The semiconductor layer 408 may include, among other things, a metal oxide semiconductor material, a metal oxynitride semiconductor material such as indium gallium zinc oxide (IGZO), or silicon such as amorphous silicon, crystalline silicon, and polysilicon. A drain electrode 412 and a source electrode 414 are disposed above the semiconductor layer 408. The drain electrode 412 is adjacent to the source electrode 414 and spaced apart from it. The drain electrode 412 and the source electrode 414 may each include, among other things, copper, tungsten, tantalum, or aluminum. A passivation layer 410 is disposed above the semiconductor layer 408, the drain electrode 412, and the source electrode 414. The passivation layer 410 and the gate insulating layer 406 are moisture-proof films or layers.

[0040] The passivation layer 410 and the gate insulating layer 406 may each be deposited in an HDP CVD chamber, such as the CVD apparatus 101 of FIG. 1, using HDP equipment, such as the HDP equipment 200 of FIG. 2. The gate insulating layer 406 is deposited first, followed by the semiconductor layer 408, followed by the passivation layer 410. The passivation layer 410 and the gate insulating layer 406 each separately comprise the same material as the first barrier layer 308 of FIG. 3. The passivation layer 410 and the gate insulating layer 406 may each be composed of a material selected from the group consisting of SiN, SiO, and SiON. The chamber may be purged between depositions of each layer.

[0041] The passivation layer 410 and the gate insulating layer 406 each have a thickness of about 10 Å, which results in high ionization efficiency and low plasma damage. 11 cm -3 from about 10 12 cm -3 high plasma density of about 10 2The passivation layer 410 and the gate insulating layer 406 may be deposited on the substrate using low ion bombardment energies of less than 100 eV. For ICP HPD equipment, the power frequency may be between about 2 MHz and about 13.56 MHz. For MW HPD equipment, the power frequency may be between about 2.4 GHz and about 2.5 GHz, such as about 2.45 GHz. The passivation layer 410 and the gate insulating layer 406 are each deposited as high-quality, dense films at low temperatures, such as below about 250 degrees Celsius. In one embodiment in which the passivation layer 410 and / or the gate insulating layer 406 comprise SiO, the passivation layer 410 and / or the gate insulating layer 406 may be deposited at a temperature of about 130 degrees Celsius and at a rate of about 2,000 angstroms per minute. In another embodiment in which the passivation layer 410 and / or the gate insulation layer 406 comprise SiN, the passivation layer 410 and / or the gate insulation layer 406 may be deposited at a temperature of about 130 degrees Celsius and at a rate of about 1000 angstroms per minute.

[0042] Moreover, depositing the passivation layer 410 and / or the gate insulating layer 406 using HDP equipment allows the passivation layer 410 and / or the gate insulating layer 406 to have a refractive index of about 1.4 to 2.1 and a low absorption coefficient (k) of about zero, thereby allowing the passivation layer 410 and / or the gate insulating layer 406 to have zero or less absorption at UV wavelengths. Near The result is zero absorption. The passivation layer 410 and / or gate insulation layer 406 deposited using HDP equipment each have a thickness of less than about 3,000 angstroms, such as less than about 2,000 angstroms, thereby reducing barrier thickness requirements, reducing bending / folding stress, and reducing the time required to deposit the passivation layer 410 and / or gate insulation layer 406. Moreover, the HDP equipment allows the passivation layer 410 and / or gate insulation layer 406 to be easily deposited on the sidewall or as a sidewall barrier without causing oxidation, reducing the thickness requirement for the sidewall barrier.

[0043] In one embodiment, the passivation layer 410 and / or the gate insulation layer 406 comprise SiN, and SiH4 and NH3 gases are introduced into the chamber to deposit the SiN passivation layer 410 and / or the SiN gate insulation layer 406. For example, about 100 sccm of SiH4 and about 600 sccm of NH3 may be used. A chamber pressure of about 120 mTorr, an ICP power frequency of about 3,000 MHz, and a power density of about 1.725 W / cm 2 may be applied for about 300 seconds.

[0044] When utilizing HDP equipment, the passivation layer 410 and / or gate insulation layer 406 comprising SiN can achieve a WER of approximately 325 Angstroms per minute and a WER of approximately 2.52 g / cm. 3 film density of about 1.91 to about 1.95, RI of about 150 GPa to about 160 GPa, and a modulus of about 1×10 to a depth of about 500 Angstroms at 40 degrees Celsius and 100% humidity. -4 g / m 2 / day is about 3 × 10 -4 g / m 2 / day WVTR and a dense XTEM structure with fewer voids. In comparison, when utilizing CCP equipment, a passivation layer and / or gate insulator layer comprising SiN can have a WER of about 13,660 Å per minute and a WVTR of about 2.10 g / cm. 3 film density of about 100 GPa, modulus of about 1×10 to a depth of about 5000 Angstroms at 40°C and 100% humidity. -4 g / m 2 They may have a WVTR of less than 1 / day, as well as an XTEM structure with some spherical voids.

[0045] In another embodiment, the passivation layer 410 and / or the gate insulation layer 406 comprise SiON, and SiH4, N2O, and NH3 gases are introduced into the chamber to deposit the SiON passivation layer 410 and / or the SiON gate insulation layer 406. For example, about 100 sccm of SiH4, about 200 sccm to about 500 sccm of NH3, and about 100 sccm to about 400 sccm of N2O may be used. A chamber pressure of about 120 mTorr, an ICP power frequency of about 3,000 MHz, and a power density of about 1.725 W / cm 2 may be applied for about 300 seconds.

[0046] When utilizing HDP equipment, the passivation layer 410 and / or gate insulating layer 406 comprising SiON can achieve a WER of approximately 3,000 angstroms per minute and a WER of approximately 2.13 g / cm. 3 to approximately 2.26 g / cm 3 film density of about 1.47 to about 1.84, and a film density of about 1×10 to a depth of about 2,000 Angstroms at 40 degrees Celsius and 100% humidity. -4 g / m 2 / day is about 7 × 10 -4 g / m 2 In comparison, when utilizing CCP equipment, a passivation layer and / or gate insulating layer comprising SiON may have a WVTR of about 20,000 Angstroms per minute, or about 2.04 g / cm. 3 and a film density of approximately 1×10 to a depth of 10,000 Angstroms at 40 degrees Celsius and 100% humidity. -4 g / m 2 May have a WVTR of less than 1 / day.

[0047] In yet another embodiment, the passivation layer 410 and / or the gate insulation layer 406 comprise SiO, and SiH4 gas and N2O gas are introduced into the chamber to deposit the SiO passivation layer 410 and / or the SiO gate insulation layer 406. For example, about 30 sccm of SiH4 and about 1,000 sccm of N2O may be used. A chamber pressure of about 120 mTorr, an ICP power frequency of about 4,000 MHz, and a fluence of about 2,300 W / cm 2 may be applied for approximately 130 seconds.

[0048] When utilizing HDP equipment, the passivation layer 410 and / or gate insulating layer 406 containing SiO can achieve a WER of approximately 3,400 Angstroms per minute and a WER of approximately 2.09 g / cm. 3 film density of about 1.46, an RI of about 1×10 to a depth of about 2,000 Angstroms at 40 degrees Celsius and 100% humidity. -3 g / m 2 In comparison, when utilizing CCP equipment, passivation layers and / or gate insulating layers containing SiO may have a WER of approximately 20,000 Angstroms per minute and may not have moisture barrier properties.

[0049] The TFE structure 314 and the TFT 400 are two example applications for depositing high-quality, thin, and dense moisture barrier films at low temperatures using HDP equipment. Other applications include moisture barrier layers for touchscreen panels, touch sensors, polyimide / colorless polyimide (PI / CPI), hole-in-active-area (HIAA), and low-temperature polysilicon (LTPS), among others. Therefore, high-quality, thin, and dense barrier films with low RI and low or zero absorption coefficient at UV wavelengths can be deposited at low temperatures using HDP equipment. Thinner barrier films reduce barrier thickness requirements, reduce bending / folding stress, and reduce the time required to deposit the barrier layer. Low light absorption and low RI barrier layers with wide RI control can improve the luminous efficiency of displays.

[0050] While the forgoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which scope is determined by the claims that follow.

Claims

1. 1. A method for depositing a barrier layer, comprising: placing the substrate in a chemical vapor deposition (CVD) chamber equipped with a high-density plasma arrangement; Temperatures below 250 degrees Celsius, power frequencies between 2 MHz and 13.56 MHz, and １１ cm-3 to 10 １２ The high density plasma arrangement is at a plasma density of 10 cm ２ depositing the barrier layer on the substrate using low ion bombardment energy of less than 1 eV; A method comprising:

2. The method of claim 1 , wherein the barrier layer is a first barrier layer or a second barrier layer of a thin film encapsulation structure.

3. The method of claim 1 , wherein the barrier layer is a passivation layer of a thin film transistor.

4. The method of claim 1 , wherein the barrier layer is a gate insulating layer of a thin film transistor.

5. The method of claim 1 , wherein the barrier layer is deposited using an inductively coupled plasma power frequency of 2 MHz to 13.56 MHz.

6. 10. The method of claim 1, wherein the barrier layer has a thickness of less than 3,000 angstroms and a refractive index between 1.45 and 1.

95.

7. 1. A method for manufacturing a thin film encapsulation structure, comprising: forming a first barrier layer deposited using a high density plasma CVD chamber, said first barrier layer comprising silicon oxynitride, said first barrier layer having a thickness of less than 3,000 angstroms and a refractive index between 1.47 and 1.84; forming a buffer layer disposed on the first barrier layer; forming a second barrier layer disposed over the buffer layer; A method comprising:

8. A method for manufacturing a thin film encapsulation structure, comprising: forming a first barrier layer deposited using a high density plasma CVD chamber, the first barrier layer comprising silicon oxide, the first barrier layer having a thickness of less than 3,000 angstroms and a refractive index of 1.46; forming a buffer layer disposed on the first barrier layer; forming a second barrier layer disposed over the buffer layer; A method comprising:

9. 9. The method of claim 7 or 8, wherein the second barrier layer comprises silicon nitride and has a refractive index between 1.91 and 1.

95.

10. The method of claim 7 or 8, wherein the second barrier layer comprises silicon oxynitride and has a refractive index between 1.47 and 1.

84.

11. The method described in claim 7 or 8, wherein the second barrier layer comprises silicon oxide and has a refractive index of 1.

46.

12. 9. The method of claim 7 or 8, wherein the second barrier layer is deposited using a high-density plasma CVD chamber, and the second barrier layer comprises a material selected from the group consisting of silicon oxynitride, silicon nitride, and silicon oxide.

13. 13. The method of claim 12, wherein the second barrier layer has a thickness of less than 3,000 angstroms and a refractive index between 1.45 and 1.

95.

14. 1. A method for depositing a barrier layer, comprising: placing the substrate in a CVD chamber equipped with a high density plasma arrangement; Temperatures below 250 degrees Celsius, inductively coupled plasma power frequencies between 2 MHz and 13.56 MHz, and １１ cm-3 to 10 １２ The high density plasma arrangement is at a plasma density of 10 cm ２ depositing the barrier layer on the substrate using low ion bombardment energy of less than 100 eV, wherein the barrier layer has a thickness of less than 3,000 angstroms and a refractive index between 1.45 and 1.95; A method comprising:

15. 15. The method of claim 14, wherein the barrier layer comprises a material selected from the group consisting of silicon oxynitride, silicon nitride, and silicon oxide.

16. The method of claim 14 , wherein the barrier layer is deposited over a light-emitting device.

17. The method of claim 14 , wherein the barrier layer is a first barrier layer or a second barrier layer of a thin film encapsulation structure.

18. The method of claim 14 , wherein the barrier layer is a passivation layer of a thin film transistor.

19. The method of claim 14 , wherein the barrier layer is a gate insulating layer of a thin film transistor.

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