Substrate for semiconductor device, method for manufacturing substrate for semiconductor device, and bonding material

Abstract

To provide a semiconductor device substrate which improves reliability and productivity, a manufacturing method of the semiconductor device substrate and a joint material.SOLUTION: A semiconductor device substrate comprises a cooler, a plate part, a stress relaxing layer, a first joint layer and a second joint layer. The cooler includes a first principal surface. The plate part includes a second principal surface. The second principal surface is opposed to the first principal surface. The stress relaxing layer is positioned between the first principal surface and the second principal surface. The first joint layer joins the cooler and the stress relaxing layer. The second joint layer joins the stress relaxing layer and the plate part. The second joint layer includes a first alloy layer and a nickel containing layer. In a direction from the first principal surface to the second principal surface, the nickel containing layer is positioned between the first alloy layer and the plate part. The nickel containing layer is in contact with the plate part on the second principal surface. The cooler consists of a material containing aluminum. The plate part consists of a material containing copper.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a substrate for a semiconductor device, a method for manufacturing a substrate for a semiconductor device, and a bonding material. [Background technology]

[0002] International Publication No. 2018 / 181417 (Patent Document 1) discloses a power module having a copper substrate and an aluminum cooler, which are joined by soldering. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 181417 Summary of the Invention [Problem to be solved by the invention]

[0004] In the power module, the difference in the linear expansion coefficient between the copper substrate and the aluminum cooler causes large thermal stress, resulting in low reliability. Furthermore, adding a component to relieve the thermal stress reduces the productivity of the power module.

[0005] The present disclosure has been made in view of the above, and an object thereof is to provide a substrate for a semiconductor device, a method for manufacturing a substrate for a semiconductor device, and a bonding material that are highly reliable and highly productive. [Means for solving the problem]

[0006] The substrate for a semiconductor device according to the present disclosure comprises a cooler, a plate portion, a stress relaxation layer, a first bonding layer, and a second bonding layer. The cooler includes a first main surface. The plate portion includes a second main surface. The second main surface faces the first main surface. The stress relaxation layer is located between the first main surface and the second main surface. The first bonding layer bonds the cooler and the stress relaxation layer. The second bonding layer bonds the stress relaxation layer and the plate portion. The second bonding layer includes a first alloy layer and a nickel-containing layer. In a direction from the first main surface to the second main surface, the nickel-containing layer is located between the first alloy layer and the plate portion. The nickel-containing layer is in contact with the plate portion at the second main surface. The cooler is made of a material containing aluminum. The plate portion is made of a material containing copper. [Effects of the Invention]

[0007] The substrate for a semiconductor device according to the present disclosure has a stress relaxation layer, which can relieve thermal stress. This can increase the reliability of the substrate for a semiconductor device. Furthermore, the cooler is bonded to the stress relaxation layer by a first bonding layer, and the plate portion is bonded to the stress relaxation layer by a second bonding layer. This allows for easy bonding of the cooler, the plate portion, and the stress relaxation layer. This makes it possible to provide a substrate for a semiconductor device, a method for manufacturing a substrate for a semiconductor device, and a bonding material that are highly reliable and highly productive. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic vertical cross-sectional view showing the configuration of a substrate for a semiconductor device according to a first embodiment. [Figure 2] 1 is a flow chart schematically showing a method for manufacturing a substrate for a semiconductor device according to a first embodiment. [Figure 3] 1A to 1C are schematic vertical cross-sectional views showing a step of forming a plating layer on a copper substrate. [Figure 4] FIG. 4 is a schematic vertical cross-sectional view showing a step of forming a plating layer on the second brazing material layer. [Figure 5] 3 is a schematic vertical cross-sectional view showing a state in which a bonding material is disposed between a first main surface and a second main surface. FIG. [Figure 6] 1 is a schematic vertical cross-sectional view showing the configuration of a bonding material according to a first embodiment. [Figure 7] 10 is a schematic vertical cross-sectional view showing a step of heating the bonding material in a state where the bonding material is disposed between the first main surface and the second main surface. FIG. [Figure 8] 10 is a schematic vertical cross-sectional view showing the configuration of a substrate for a semiconductor device according to a second embodiment. FIG. [Figure 9] 10 is a flow chart schematically showing a method for manufacturing a substrate for a semiconductor device according to a second embodiment. [Figure 10] 10 is a schematic vertical cross-sectional view showing the configuration of a bonding material according to a second embodiment. FIG. [Figure 11] 10 is a schematic vertical cross-sectional view showing a state in which a bonding material is disposed between a first main surface and a second main surface in a manufacturing method of a substrate for a semiconductor device according to a second embodiment. FIG. [Figure 12] 10 is a schematic vertical cross-sectional view showing the configuration of a bonding material according to a modified example of the second embodiment. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and description thereof will not be repeated.

[0010] Embodiment 1 The configuration of a substrate 100 for a semiconductor device according to the first embodiment will be described. Fig. 1 is a schematic vertical cross-sectional view showing the configuration of the substrate 100 for a semiconductor device according to the first embodiment. As shown in Fig. 1, the substrate 100 for a semiconductor device mainly includes a cooler 2, a copper substrate 1, a stress relaxation layer 6, a first bonding layer 8, and a second bonding layer 7. The substrate 100 for a semiconductor device is configured such that the first bonding layer 8, the stress relaxation layer 6, and the second bonding layer 7 are stacked in this order from the cooler 2 side between the cooler 2 and the copper substrate 1.

[0011] The cooler 2 is made of a material containing aluminum. The cooler 2 has a main body 20 and a plurality of protrusions 24. The main body 20 is plate-shaped. The main body 20 has a first main surface 21 and a third main surface 23. The third main surface 23 is on the opposite side of the first main surface 21. Each of the plurality of protrusions 24 is continuous with the third main surface 23. Each of the plurality of protrusions 24 extends on the side opposite the first main surface 21 with respect to the third main surface 23. Each of the plurality of protrusions 24 may be plate-shaped extending in a direction perpendicular to the paper surface. Each of the plurality of protrusions 24 may be rod-shaped.

[0012] The copper substrate 1 has a first plate portion 3, an insulating plate 4, and a second plate portion 5. The first plate portion 3 is made of a material containing copper. The first plate portion 3 has a second main surface 32 and a fourth main surface 34. The second main surface 32 faces the first main surface 21 of the cooler 2. The second main surface 32 is spaced apart from the first main surface 21. The fourth main surface 34 is on the opposite side of the second main surface 32.

[0013] The insulating plate 4 is located above the first plate portion 3. In this specification, above refers to the direction from the first main surface 21 of the cooler 2 toward the second main surface 32 of the first plate portion 3. The insulating plate 4 is joined to the first plate portion 3 by a joining method such as brazing or solid-state diffusion bonding. The insulating plate 4 is made of a ceramic such as alumina, aluminum nitride, or silicon nitride.

[0014] The insulating plate 4 has a fifth main surface 35, a sixth main surface 36, and an outer peripheral side surface 33. The fifth main surface 35 is in contact with the fourth main surface 34 of the first plate portion 3. The sixth main surface 36 is on the opposite side of the fifth main surface 35. The outer peripheral side surface 33 is continuous with each of the fifth main surface 35 and the sixth main surface 36. In a cross-sectional view, the outer peripheral side surface 33 may be located outward from the second main surface 32 of the first plate portion 3. The cross section shown in FIG. 1 is perpendicular to the first main surface 21 of the cooler 2 and intersects with each of the first main surface 21 and the second main surface 32. In this specification, the term "outward" refers to the direction from the inside to the outside of the area surrounded by the outer peripheral side surface 33.

[0015] The second plate portion 5 is located on the opposite side of the insulating plate 4 from the first plate portion 3. In other words, the insulating plate 4 is located between the first plate portion 3 and the second plate portion 5. The second plate portion 5 is joined to the insulating plate 4 by a joining method such as brazing or solid-state diffusion bonding. The first plate portion 3 and the second plate portion 5 are insulated from each other by the insulating plate 4. The second plate portion 5 is made of a material containing copper. The second plate portion 5 has a seventh main surface 37 and an eighth main surface 38. The seventh main surface 37 is in contact with the sixth main surface 36 of the insulating plate 4. The eighth main surface 38 is located opposite the seventh main surface 37.

[0016] In the vertical direction, the stress relaxation layer 6 is located between the first main surface 21 of the cooler 2 and the second main surface 32 of the first plate portion 3. In this specification, the vertical direction is the direction from the first main surface 21 to the second main surface 32. The stress relaxation layer 6 is spaced apart from the cooler 2. The stress relaxation layer 6 is spaced apart from the first plate portion 3. The stress relaxation layer 6 is, for example, plate-shaped. The stress relaxation layer 6 is made of, for example, a material containing aluminum. The weight content of aluminum in the stress relaxation layer 6 is higher than the weight content of aluminum in the cooler 2. Specifically, the stress relaxation layer 6 is made of, for example, pure aluminum. The weight content of aluminum in the stress relaxation layer 6 is, for example, 99.5 wt % or more. The thickness of the stress relaxation layer 6 in the vertical direction is, for example, 50 μm or more and 3 mm or less.

[0017] The first bonding layer 8 is located between the cooler 2 and the stress relief layer 6 in the vertical direction. The first bonding layer 8 bonds the cooler 2 and the stress relief layer 6 together. The first bonding layer 8 is in contact with the cooler 2 at the first main surface 21. The first bonding layer 8 is plate-shaped. The first bonding layer 8 is made of a material containing aluminum, silicon, and magnesium. The weight content of silicon in the first bonding layer 8 is, for example, 5% by weight or more and 12% by weight or less. The weight content of magnesium in the first bonding layer 8 is, for example, 1% by weight. The weight content of magnesium in the first bonding layer 8 may be, for example, 0.2% by weight or more and 5% by weight or less. The remainder of the first bonding layer 8, excluding the silicon and magnesium, is made of, for example, aluminum. The thickness of the first bonding layer 8 in the vertical direction is, for example, 10 μm or more and 0.2 mm or less.

[0018] In the vertical direction, the second bonding layer 7 is located between the stress relief layer 6 and the first plate portion 3. The second bonding layer 7 bonds the stress relief layer 6 and the first plate portion 3. The second bonding layer 7 is in contact with the first plate portion 3 at the second main surface 32. The second bonding layer 7 is configured by stacking multiple layers. The second bonding layer 7 has a third compound layer 11, a first alloy layer 12, a first compound layer 13, a second alloy layer 14, a second compound layer 15, and a first nickel-containing layer 16.

[0019] In the vertical direction, the second bonding layer 7 is configured by stacking the third compound layer 11, the first alloy layer 12, the first compound layer 13, the second alloy layer 14, the second compound layer 15, and the first nickel-containing layer 16 in this order from the stress relief layer 6 side. In other words, the first alloy layer 12 is located on the third compound layer 11. The first alloy layer 12 is in contact with the third compound layer 11. The first compound layer 13 is located on the first alloy layer 12. The first compound layer 13 is in contact with the first alloy layer 12.

[0020] The second alloy layer 14 is located on the first compound layer 13. The second alloy layer 14 is in contact with the first compound layer 13. The second compound layer 15 is located on the second alloy layer 14. The second compound layer 15 is in contact with the second alloy layer 14. The first nickel-containing layer 16 is located on the second compound layer 15. The first nickel-containing layer 16 is in contact with the second compound layer 15. In the vertical direction, the first nickel-containing layer 16 is located between the first alloy layer 12 and the first plate portion 3. In the vertical direction, the first compound layer 13, the second alloy layer 14, and the second compound layer 15 are each located between the first alloy layer 12 and the first nickel-containing layer 16. In the vertical direction, the third compound layer 11 is located between the stress relaxation layer 6 and the first alloy layer 12.

[0021] The third compound layer 11 is in contact with the stress relief layer 6. The third compound layer 11 is made of a material containing aluminum and nickel. The third compound layer 11 is, for example, a compound of aluminum and nickel. The weight content of nickel in the third compound layer 11 is, for example, 25 wt %. The weight content of nickel in the third compound layer 11 may be, for example, 15 wt % or more and 35 wt % or less. The remainder of the third compound layer 11 excluding nickel is made of, for example, aluminum. The thickness of the third compound layer 11 in the vertical direction is, for example, 10 μm or more and 30 μm or less.

[0022] The first alloy layer 12 is made of a material containing aluminum, silicon, and magnesium. The weight content of silicon in the first alloy layer 12 is, for example, 5% by weight or more and 12% by weight or less. The weight content of magnesium in the first alloy layer 12 is, for example, 1% by weight. The weight content of magnesium in the first alloy layer 12 may be, for example, 0.2% by weight or more and 5% by weight or less. The remainder of the first alloy layer 12, excluding silicon and magnesium, is made of, for example, aluminum. The thickness of the first alloy layer 12 in the vertical direction is, for example, 10 μm or more and 0.2 mm or less.

[0023] The first compound layer 13 is made of a material containing aluminum and nickel. The first compound layer 13 is, for example, a compound of aluminum and nickel. The weight content of nickel in the first compound layer 13 is, for example, 25 wt %. The weight content of nickel in the first compound layer 13 may be, for example, 15 wt % or more and 35 wt % or less. The remainder of the first compound layer 13 excluding nickel is made of, for example, aluminum. The thickness of the first compound layer 13 in the vertical direction is, for example, 10 μm or more and 30 μm or less.

[0024] The second alloy layer 14 is made of a material containing aluminum, silicon, and magnesium. The weight content of silicon in the second alloy layer 14 is, for example, 5% by weight or more and 12% by weight or less. The weight content of magnesium in the second alloy layer 14 is, for example, 1% by weight. The weight content of magnesium in the second alloy layer 14 may be, for example, 0.2% by weight or more and 5% by weight or less. The remainder of the second alloy layer 14, excluding silicon and magnesium, is made of, for example, aluminum. The thickness of the second alloy layer 14 in the vertical direction is, for example, 10 μm or more and 30 μm or less.

[0025] The second compound layer 15 is made of a material containing aluminum and nickel. The second compound layer 15 is, for example, a compound of aluminum and nickel. The weight content of nickel in the second compound layer 15 is, for example, 25% by weight. The weight content of nickel in the second compound layer 15 may be, for example, 15% by weight or more and 35% by weight or less. The remainder of the second compound layer 15 excluding nickel is made of, for example, aluminum. The thickness of the second compound layer 15 in the vertical direction is, for example, 10 μm or more and 30 μm or less.

[0026] The first nickel-containing layer 16 contacts the first plate portion 3 at the second main surface 32 of the first plate portion 3. The weight content of nickel in the first nickel-containing layer 16 is, for example, 85% by weight or more. The thickness of the first nickel-containing layer 16 in the vertical direction is, for example, 15 μm or more and 30 μm or less. The composition of each portion of the substrate 100 for a semiconductor device can be measured using energy dispersive X-ray analysis.

[0027] Next, a method for manufacturing the substrate 100 for a semiconductor device according to the first embodiment will be described. Fig. 2 is a flow diagram that schematically shows the method for manufacturing the substrate 100 for a semiconductor device according to the first embodiment. As shown in Fig. 2, the method for manufacturing the substrate 100 for a semiconductor device according to the first embodiment mainly includes a step (S10) of preparing a cooler and a copper substrate, a step (S20) of forming a plating layer on the copper substrate, a step (S30) of forming a plating layer on the second brazing material layer, and a step (S40) of heating the bonding material while the bonding material is disposed between the first main surface and the second main surface.

[0028] First, a step (S10) of preparing a cooler and a copper substrate is carried out. The cooler and the copper substrate are prepared in a state where they are not bonded to each other.

[0029] Next, a step (S20) of forming a plating layer on the copper substrate is carried out. Fig. 3 is a schematic vertical cross-sectional view showing the step of forming a plating layer on the copper substrate. The cross section shown in Fig. 3 is perpendicular to the second main surface 32 of the first plate portion 3 and intersects with the second main surface 32.

[0030] As shown in FIG. 3 , a first layer 45 is formed on the second main surface 32 of the first plate portion 3 by plating. The first layer 45 is a nickel plating layer. The first layer 45 is formed by, for example, electrolytic plating. The first layer 45 contacts the first plate portion 3 on the second main surface 32. The thickness of the first layer 45 in the direction perpendicular to the second main surface 32 is, for example, 15 μm or more and 30 μm or less.

[0031] Next, a step (S30) of forming a plating layer on the second brazing filler metal layer is performed. Fig. 4 is a schematic vertical cross-sectional view showing the step of forming a plating layer on the second brazing filler metal layer. The cross section shown in Fig. 4 is parallel to the thickness direction of the second brazing filler metal layer 43 and intersects with the second brazing filler metal layer 43.

[0032] As shown in FIG. 4 , a second brazing filler metal layer 43 is prepared. The second brazing filler metal layer 43 is produced, for example, by rolling an aluminum alloy. Next, a second layer 44 and a fourth nickel-containing layer 42 are each formed on the second brazing filler metal layer 43 by plating. The second layer 44 and the fourth nickel-containing layer 42 are each a nickel-plated layer. The second layer 44 and the fourth nickel-containing layer 42 are each formed, for example, by electrolytic plating. The thickness of the second layer 44 in the direction from the second layer 44 to the fourth nickel-containing layer 42 is, for example, 1 μm or more and 3 μm or less. The thickness of the fourth nickel-containing layer 42 in the direction from the second layer 44 to the fourth nickel-containing layer 42 is, for example, 1 μm or more and 3 μm or less.

[0033] The second brazing filler metal layer 43 is located between the second layer 44 and the fourth nickel-containing layer 42. The second brazing filler metal layer 43 is made of a material containing aluminum, silicon, and magnesium. Specifically, the second brazing filler metal layer 43 is made of, for example, an aluminum alloy to which silicon and magnesium are added. The weight content of silicon in the second brazing filler metal layer 43 is, for example, 5% by weight or more and 12% by weight or less. The weight content of magnesium in the second brazing filler metal layer 43 is, for example, 0.2% by weight or more and 5% by weight or less. The remainder of the second brazing filler metal layer 43, excluding silicon and magnesium, is made of, for example, aluminum. The thickness of the second brazing filler metal layer 43 in the direction from the second layer 44 toward the fourth nickel-containing layer 42 is, for example, 20 μm or more and 0.2 mm or less.

[0034] FIG. 5 is a schematic vertical cross-sectional view showing a state in which a bonding material is disposed between the first main surface 21 and the second main surface 32. The schematic vertical cross-sectional view shown in FIG. 5 corresponds to the schematic vertical cross-sectional view shown in FIG. 1. As shown in FIG. 5, a first brazing filler metal layer 41, a stress relief layer 6, and a second brazing filler metal layer 43 on which the second layer 44 and the fourth nickel-containing layer 42 shown in FIG. 4 are formed are disposed between the copper substrate 1 on which the first layer 45 is formed and the cooler 2. The first brazing filler metal layer 41 is disposed so as to contact the cooler 2 at the first main surface 21. The second layer 44 is disposed so as to contact the first layer 45. From another perspective, a bonding material 200 is disposed between the first main surface 21 of the cooler 2 and the second main surface 32 of the first plate portion 3. The bonding material 200 has a first brazing filler metal layer 41 , a stress relaxation layer 6 , a fourth nickel-containing layer 42 , a second brazing filler metal layer 43 , and a second nickel-containing layer 17 .

[0035] Next, a description will be given of the configuration of the bonding material 200. Fig. 6 is a schematic vertical cross-sectional view showing the configuration of the bonding material 200 according to embodiment 1. As shown in Fig. 6, the bonding material 200 is configured by stacking a plurality of layers.

[0036] In the vertical direction, the bonding material 200 is configured by stacking a first brazing filler metal layer 41, a stress relaxation layer 6, a fourth nickel-containing layer 42, a second brazing filler metal layer 43, and a second nickel-containing layer 17 in this order. In other words, the stress relaxation layer 6 is located on the first brazing filler metal layer 41. The stress relaxation layer 6 is in contact with the first brazing filler metal layer 41. The fourth nickel-containing layer 42 is located on the stress relaxation layer 6. The fourth nickel-containing layer 42 is in contact with the stress relaxation layer 6.

[0037] The second brazing filler metal layer 43 is located on the fourth nickel-containing layer 42. The second brazing filler metal layer 43 is in contact with the fourth nickel-containing layer 42. The second nickel-containing layer 17 is located on the second brazing filler metal layer 43. The second nickel-containing layer 17 is in contact with the second brazing filler metal layer 43. From another perspective, the second brazing filler metal layer 43 is located on the stress relief layer 6. The cross section shown in FIG. 6 is parallel to the direction from the first brazing filler metal layer 41 to the second brazing filler metal layer 43, and intersects with each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43.

[0038] The first brazing filler metal layer 41 is made of a material containing aluminum, silicon, and magnesium. Specifically, the first brazing filler metal layer 41 is made of, for example, an aluminum alloy to which silicon and magnesium are added. The weight content of silicon in the first brazing filler metal layer 41 is, for example, 5% by weight or more and 12% by weight or less. The weight content of magnesium in the first brazing filler metal layer 41 is, for example, 0.2% by weight or more and 5% by weight or less. The remainder of the first brazing filler metal layer 41, excluding silicon and magnesium, is made of, for example, aluminum. The thickness of the first brazing filler metal layer 41 in the vertical direction is, for example, 20 μm or more and 0.2 mm or less. The second nickel-containing layer 17 is made of a first layer 45 and a second layer 44. In other words, the second nickel-containing layer 17 has the first layer 45 and the second layer 44.

[0039] Next, a step (S40) of heating the bonding material with the bonding material disposed between the first and second main surfaces is performed. In a furnace (not shown), the bonding material 200 is heated with the bonding material disposed between the first and second main surfaces 21 and 32. The furnace is filled with an inert atmosphere, such as a nitrogen atmosphere. The first brazing filler metal layer 41 and the second brazing filler metal layer 43 are heated so that their respective temperatures are equal to or higher than their respective melting points and equal to or lower than the melting point of the cooler 2. During heating, the maximum temperature of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is, for example, 600°C. The maximum temperature of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 may be, for example, 530°C or higher and 640°C or lower. As a result, the first brazing filler metal layer 41 and the second brazing filler metal layer 43 are each melted.

[0040] 7 is a schematic vertical cross-sectional view showing a process of heating the bonding material disposed between the first and second main surfaces. The schematic vertical cross-sectional view shown in FIG. 7 corresponds to the schematic vertical cross-sectional view shown in FIG. 5.

[0041] As shown in FIGS. 5 and 7 , during heating, the melted first brazing filler metal layer 41 forms a first molten brazing filler metal layer 57. A portion of the melted second brazing filler metal layer 43 forms a second molten brazing filler metal layer 52. As the second brazing filler metal layer 43 melts, a portion of the second nickel-containing layer 17 dissolves into the second brazing filler metal layer 43. A portion of the melted second nickel-containing layer 17 diffuses in a direction from the second main surface 32 toward the first main surface 21. This forms a first nickel-enriched layer 53. The remaining portion of the melted second nickel-containing layer 17 forms a second nickel-enriched layer 55. The unmelted portion of the second nickel-containing layer 17 forms the first nickel-containing layer 16. A third molten brazing filler metal layer 54 with a low nickel concentration is formed between the first nickel-enriched layer 53 and the second nickel-enriched layer 55. The fourth nickel-containing layer 42 dissolves into the second brazing filler metal layer 43. As a result, a third nickel-enriched layer 51 is formed.

[0042] Each of the first nickel-enriched layer 53, the second nickel-enriched layer 55, and the third nickel-enriched layer 51 is a layer in which nickel has diffused into the molten brazing filler metal. The weight content of nickel in each of the first nickel-enriched layer 53, the second nickel-enriched layer 55, and the third nickel-enriched layer 51 is greater than the weight content of the surrounding molten brazing filler metal layer.

[0043] Specifically, the nickel weight content in the first nickel-enriched layer 53 is greater than the nickel weight content in each of the second molten brazing filler metal layer 52 and the third molten brazing filler metal layer 54, but is less than the nickel weight content in the first nickel-containing layer 16. The nickel weight content in the second nickel-enriched layer 55 is greater than the nickel weight content in the third molten brazing filler metal layer 54, but is less than the nickel weight content in the first nickel-containing layer 16. The nickel weight content in the third nickel-enriched layer 51 is greater than the nickel weight content in the second molten brazing filler metal layer 52, but is less than the nickel weight content in the first nickel-containing layer 16.

[0044] The heated bonding material 200 is cooled to room temperature. In this way, the semiconductor device substrate 100 shown in FIG. 1 is manufactured. As shown in FIGS. 1 and 7, upon cooling, the first molten brazing material layer 57 becomes the first bonding layer 8. The third nickel-enriched layer 51 becomes the third compound layer 11. The second molten brazing material layer 52 becomes the first alloy layer 12. The first nickel-enriched layer 53 becomes the first compound layer 13. The third molten brazing material layer 54 becomes the second alloy layer 14. The second nickel-enriched layer 55 becomes the second compound layer 15.

[0045] The correspondence between each part before and after the step (S40) of heating the bonding material while the bonding material is disposed between the first and second main surfaces will be described. As shown in FIGS. 1 and 5, the first bonding layer 8 is composed of a first brazing filler metal layer 41. The third compound layer 11 is composed of a second brazing filler metal layer 43 and a fourth nickel-containing layer 42. The first alloy layer 12 and the second alloy layer 14 are each composed of the second brazing filler metal layer 43. The first compound layer 13 and the second compound layer 15 are each composed of the second brazing filler metal layer 43 and a second nickel-containing layer 17.

[0046] Next, the effects of the semiconductor device substrate 100 according to the first embodiment will be described.

[0047] The substrate 100 for a semiconductor device according to the first embodiment is used with a semiconductor chip bonded to the second plate portion 5 on the eighth main surface 38. The semiconductor chip is bonded by, for example, soldering. When the semiconductor chip generates heat, the heat is transferred to the cooler 2 via the copper substrate 1, the second bonding layer 7, the stress relaxation layer 6, and the first bonding layer 8. The cooler 2 transfers the heat to the air or a coolant to dissipate the heat, thereby cooling the semiconductor chip.

[0048] When a copper substrate and an aluminum cooler are joined by brazing, the copper substrate and the aluminum cooler each expand during heating and contract during cooling. During cooling, the brazing material solidifies, joining the copper substrate and the aluminum cooler. Cooling continues even after the copper substrate and the aluminum cooler are joined. Therefore, the copper substrate and the aluminum cooler each continue to contract. At this time, thermal stress occurs due to the difference in the linear expansion coefficients of the copper substrate and the aluminum cooler. This thermal stress may cause warping and cracking of the copper substrate and damage to the joint. In particular, when the copper substrate includes a ceramic insulating plate, the difference in the linear expansion coefficients of ceramic and aluminum is greater than the difference in the linear expansion coefficients of copper and aluminum, so the effect of thermal stress becomes more pronounced.

[0049] Furthermore, when the semiconductor chip generates heat, the temperature of the copper substrate and the aluminum cooler rises due to heat transfer, and in this case, thermal stress occurs between the copper substrate and the aluminum cooler, as in the case described above.

[0050] In the substrate 100 for a semiconductor device according to the first embodiment, the stress relaxation layer 6 is located between the first main surface 21 of the cooler 2 and the second main surface 32 of the first plate portion 3. This allows for the relaxation of thermal stress occurring between the cooler 2 and the copper substrate 1. Specifically, for example, the weight content of aluminum in the stress relaxation layer 6 is greater than the weight content of aluminum in the cooler 2. This makes the stress relaxation layer 6 highly ductile and allows for easy plastic deformation. Therefore, the thermal stress occurring between the cooler 2 and the copper substrate 1 is converted into energy for deformation of the stress relaxation layer 6. As a result, the stress relaxation layer 6 can reduce the thermal stress. This prevents warping and cracking of the copper substrate 1 and damage to the bonding layer. As a result, the reliability of the substrate 100 for a semiconductor device can be improved.

[0051] According to the manufacturing method of the substrate 100 for a semiconductor device according to the first embodiment, the cooler 2 is joined to the stress relaxation layer 6 by the first bonding layer 8, and the first plate portion 3 is joined to the stress relaxation layer 6 by the second bonding layer 7. Therefore, in the manufacturing process of the substrate 100 for a semiconductor device, the cooler, the plate portion, and the stress relaxation layer can be easily joined by only one brazing step. This makes it possible to increase productivity while maintaining the high reliability of the substrate 100 for a semiconductor device.

[0052] Generally, brazing aluminum and copper uses a brazing material containing aluminum. Therefore, during the brazing process, the aluminum and copper in the brazing material come into contact with each other. This causes a eutectic structure of aluminum and copper to form between the brazing material and the copper. The eutectic structure of aluminum and copper is brittle. This may result in a decrease in the strength of the joint. According to the manufacturing method of the semiconductor device substrate 100 of the first embodiment, the second nickel-containing layer 17 of the bonding material 200 contacts the first plate portion 3. During the heating process, the second nickel-containing layer 17 becomes the first nickel-containing layer 16. The first nickel-containing layer 16 contacts the first plate portion 3. Therefore, the first plate portion 3 does not contact aluminum. In other words, the first nickel-containing layer 16 of the first plate portion 3 functions as a barrier layer against aluminum. This prevents the formation of a eutectic structure of aluminum and copper between the first plate portion 3 and the bonding material 200. This improves the reliability of the semiconductor device substrate 100.

[0053] According to the method for manufacturing the substrate 100 for a semiconductor device according to the first embodiment, the thickness of the second nickel-containing layer 17 in the vertical direction is 15 μm or more. This prevents the second nickel-containing layer 17 from becoming excessively thin. This further increases the reliability of the substrate 100 for a semiconductor device.

[0054] If the thickness of the first layer 45 of the second nickel-containing layer 17 is excessively large, the time required to form the first layer 45 becomes enormous. According to the substrate 100 for a semiconductor device according to the first embodiment, the thickness of the first layer 45 in the vertical direction is 30 μm or less. This prevents the thickness of the first layer 45 from becoming excessively large. This prevents the time required to form the first layer 45 from becoming enormous.

[0055] According to the substrate 100 for a semiconductor device according to the first embodiment, the thickness of the second layer 44 in the vertical direction is 3 μm or less. This prevents the second layer 44 from becoming excessively thick. Therefore, in the heating step, the second layer 44 can be more reliably dissolved into the second brazing material layer 43. This more reliably achieves bonding between the copper substrate 1 and the stress relaxation layer 6. As a result, the reliability of the substrate 100 for a semiconductor device can be further improved.

[0056] According to the manufacturing method of the semiconductor device substrate 100 of the first embodiment, the bonding material 200 has the second layer 44 of the second nickel-containing layer 17. During the heating process, the second layer 44 becomes the second nickel-enriched layer 55. When a solid dissolves in a liquid, the higher the concentration of the solid in the liquid, the less the solid dissolves in the liquid. Therefore, the second nickel-enriched layer 55 suppresses the dissolution of the first nickel-containing layer 16 into the brazing material layer. This prevents the first nickel-containing layer 16 from dissolving excessively into the brazing material layer. As a result, the first nickel-containing layer 16 can be prevented from functioning as a barrier layer.

[0057] The first layer 45 and the second layer 44 of the second nickel-containing layer 17 are each a nickel-plated layer. That is, the first layer 45 and the second layer 44 are made of the same material. Therefore, the first layer 45 and the second layer 44 are easily bonded together in the heating process. This can increase the reliability of the substrate 100 for a semiconductor device.

[0058] According to the semiconductor device substrate 100 of the first embodiment, the second bonding layer 7 has a first compound layer 13, a second compound layer 15, and a third compound layer 11. Each of the first compound layer 13, the second compound layer 15, and the third compound layer 11 is made of a material containing aluminum and nickel. Each of the first compound layer 13, the second compound layer 15, and the third compound layer 11 is a compound of aluminum and nickel. The compound of aluminum and nickel has high strength. Therefore, cracks are less likely to occur in the second bonding layer 7. This further increases the reliability of the semiconductor device substrate 100.

[0059] If the aluminum weight content of the stress relaxation layer 6 is excessively low, the stress relaxation layer 6 becomes hard. As a result, the stress relaxation layer 6 is less effective in relaxing thermal stress. According to the substrate 100 for a semiconductor device according to the first embodiment, the aluminum weight content of the stress relaxation layer 6 is, for example, 99.5% by weight or more. This prevents the aluminum weight content of the stress relaxation layer 6 from becoming excessively low. This further increases the reliability of the substrate 100 for a semiconductor device.

[0060] According to the substrate 100 for a semiconductor device according to the first embodiment, the thickness of the stress relaxation layer 6 in the vertical direction is 50 μm or more. This prevents the thickness of the stress relaxation layer 6 from becoming excessively thin. This further increases the reliability of the substrate 100 for a semiconductor device.

[0061] If the thickness of the stress relaxation layer 6 is excessively thick, the thermal resistance between the semiconductor chip and the cooler 2 increases. This reduces the heat dissipation performance of the substrate 100 for a semiconductor device. According to the substrate 100 for a semiconductor device according to the first embodiment, the thickness of the stress relaxation layer 6 in the vertical direction is 3 mm or less. This prevents the thickness of the stress relaxation layer 6 from becoming excessively thick. This prevents the heat dissipation performance of the substrate 100 for a semiconductor device from decreasing.

[0062] When brazing to aluminum, the aluminum oxide film inhibits brazing. For this reason, flux is sometimes used to remove the aluminum oxide film. When flux is used in brazing the substrate 100 for a semiconductor device, the flux melts and spreads over the surface of the copper substrate 1, thereby reducing the insulation between the first plate portion 3 and the second plate portion 5 of the copper substrate 1.

[0063] According to the manufacturing method of the semiconductor device substrate 100 of the first embodiment, each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is made of a material containing aluminum, silicon, and magnesium. The bonding strength of magnesium with oxygen is stronger than the bonding strength of aluminum with oxygen. Therefore, during the brazing process, magnesium removes oxygen from aluminum. As a result, magnesium removes the oxide film on aluminum. Therefore, according to the manufacturing method of the semiconductor device substrate 100 of the first embodiment, brazing can be performed without using flux. As a result, deterioration of the insulating properties of the semiconductor device substrate 100 can be prevented.

[0064] When brazing is performed using flux, the flux spreads. This promotes diffusion of the first nickel-containing layer 16 into the molten brazing material layer during the heating process. This may reduce the effectiveness of the first nickel-containing layer 16 as a barrier layer. However, the method for manufacturing the semiconductor device substrate 100 according to the first embodiment allows brazing without using flux. This prevents the effectiveness of the second nickel-containing layer 17 as a barrier layer from being reduced.

[0065] Generally, 5000 series aluminum alloys and 6000 series aluminum alloys specified in JIS (Japanese Industrial Standards) H 4000:2017 cannot be brazed using flux. However, according to the manufacturing method of the semiconductor device substrate 100 according to the first embodiment, brazing can be performed without using flux. Therefore, the 5000 series aluminum alloy or the 6000 series aluminum alloy can be selected as the material for the cooler 2.

[0066] If the weight content of silicon and magnesium in each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is excessively high, each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 becomes hard. This makes it difficult to process each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 by rolling or the like. According to the manufacturing method for the semiconductor device substrate 100 according to the first embodiment, the weight content of silicon in each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is 12% by weight or less. The weight content of magnesium in each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is 5% by weight or less. This prevents the weight content of silicon and magnesium in each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 from becoming excessively high. This makes it easier to process each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43.

[0067] If the silicon weight content of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is excessively low, the melting points of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 will be high. According to the manufacturing method for the semiconductor device substrate 100 according to the first embodiment, the silicon weight content of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is 5 wt % or more. This prevents the silicon weight content of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 from becoming excessively low. This allows each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 to melt easily.

[0068] If the magnesium weight content of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is excessively low, the effect of removing the aluminum oxide film in the first brazing filler metal layer 41 and the second brazing filler metal layer 43 will be reduced. According to the manufacturing method for the semiconductor device substrate 100 according to the first embodiment, the magnesium weight content of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is 0.2 wt % or more. This prevents the magnesium weight content of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 from becoming excessively low. This prevents a reduction in the effect of removing the aluminum oxide film in each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43.

[0069] According to the substrate 100 for a semiconductor device according to the first embodiment, the thickness of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is 20 μm or more. This prevents the thickness of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 from becoming excessively small. This increases the bonding strength between the cooler 2, the stress relaxation layer 6, and the copper substrate 1. This further increases the reliability of the substrate 100 for a semiconductor device.

[0070] If the thickness of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is excessively large, there is a risk of leakage when each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 melts. According to the semiconductor device substrate 100 of embodiment 1, the thickness of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 is 0.2 mm or less. Therefore, it is possible to prevent each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 from becoming excessively large. This makes it possible to prevent each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 from leaking.

[0071] The material constituting the stress relaxation layer 6 is not limited to a material containing aluminum. The stress relaxation layer 6 may be, for example, a nickel plate. The nickel content in the stress relaxation layer 6 is, for example, 90% or more. The linear expansion coefficient of nickel is greater than that of the insulating plate 4 of the copper substrate 1 and less than that of the cooler 2. Therefore, the thermal stress generated in the copper substrate 1 and the cooler 2 is smaller than when the substrate 100 for a semiconductor device does not have the stress relaxation layer 6. Therefore, similar to the substrate 100 for a semiconductor device according to the first embodiment, the reliability of the substrate 100 for a semiconductor device can be improved.

[0072] Furthermore, when the stress relaxation layer 6 is a nickel plate, bonding between the material containing nickel and the stress relaxation layer 6 is facilitated. Specifically, bonding between the third compound layer 11 and the stress relaxation layer 6 is facilitated. This further increases the reliability of the substrate 100 for a semiconductor device.

[0073] The method for manufacturing the substrate 100 for a semiconductor device is not limited to the above-described method. The method for manufacturing the substrate 100 for a semiconductor device does not have to include the step (S30) of forming a plating layer on the second brazing material layer. The bonding material 200 does not have the second layer 44. In this case, the substrate 100 for a semiconductor device does not have the second alloy layer 14 and the first compound layer 13. Even in the above-described case, the same effects as those of the substrate 100 for a semiconductor device according to the first embodiment can be obtained.

[0074] In the manufacturing method of the semiconductor device substrate 100, the order in which the step (S20) of forming a plating layer on the copper substrate and the step (S30) of forming a plating layer on the second brazing filler metal layer are performed is not particularly limited. For example, the step (S20) of forming a plating layer on the copper substrate may be performed after the step (S30) of forming a plating layer on the second brazing filler metal layer. The step (S20) of forming a plating layer on the copper substrate and the step (S30) of forming a plating layer on the second brazing filler metal layer may be performed simultaneously in parallel.

[0075] The remainder of each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43, excluding silicon and magnesium, may contain at least one of bismuth and lithium, in which case each of the first brazing filler metal layer 41 and the second brazing filler metal layer 43 has high wettability when melted.

[0076] The method for forming each of the first layer 45, the second layer 44, and the fourth nickel-containing layer 42 is not limited to electrolytic plating. For example, each of the first layer 45, the second layer 44, and the fourth nickel-containing layer 42 may be formed by electroless plating. In this case, too, the same effects as those of the semiconductor device substrate 100 according to the first embodiment can be obtained.

[0077] The shape of the stress relaxation layer 6 is not limited to a plate shape. The stress relaxation layer 6 may have a slit that opens in a direction perpendicular to the up-down direction, for example. A plurality of slits may be provided. The stress relaxation layer 6 may have a hollow structure, for example. In any of the above cases, the same effects as those of the semiconductor device substrate 100 according to the first embodiment can be obtained.

[0078] The second plate portion 5 of the copper substrate 1 may have a nickel plating layer formed on the eighth main surface 38. The nickel plating layer can improve the reliability of the joint during soldering. Therefore, when a semiconductor chip is soldered to the second plate portion 5 on the eighth main surface 38, the reliability of the joint is improved.

[0079] The application of the manufacturing method for the substrate 100 for a semiconductor device in the first embodiment is not limited to the bonding between the copper substrate 1 and the cooler 2. The manufacturing method for the substrate 100 for a semiconductor device in the first embodiment can be applied to the bonding between aluminum and copper.

[0080] Embodiment 2 Next, a description will be given of the configuration of the substrate 100 for a semiconductor device according to embodiment 2. The configuration of the substrate 100 for a semiconductor device according to embodiment 2 differs from the configuration of the substrate 100 for a semiconductor device according to embodiment 1 mainly in that the substrate 100 for a semiconductor device according to embodiment 2 does not have the third compound layer 11. The following description will focus on the differences from the configuration of the substrate 100 for a semiconductor device according to embodiment 1.

[0081] Fig. 8 is a schematic vertical cross-sectional view showing the configuration of a substrate 100 for a semiconductor device according to embodiment 2. The schematic vertical cross-sectional view shown in Fig. 8 corresponds to the schematic vertical cross-sectional view shown in Fig. 1. The first alloy layer 12 of the second bonding layer 7 is in contact with the stress relaxation layer 6.

[0082] Next, a method for manufacturing the substrate 100 for a semiconductor device according to the second embodiment will be described.

[0083] Fig. 9 is a flow diagram that schematically shows a method for manufacturing the substrate 100 for a semiconductor device according to embodiment 2. As shown in Fig. 9, the method for manufacturing the substrate 100 for a semiconductor device according to embodiment 2 differs from the method for manufacturing the substrate 100 for a semiconductor device according to embodiment 1 in that it does not include the step (S30) of forming a plating layer on the second brazing material layer.

[0084] Before the step (S40) of heating the bonding material while the bonding material is disposed between the first main surface and the second main surface, bonding material 200 is prepared. Fig. 10 is a schematic vertical cross-sectional view showing the configuration of bonding material 200 according to embodiment 2. The schematic vertical cross-sectional view shown in Fig. 10 corresponds to the schematic vertical cross-sectional view shown in Fig. 6.

[0085] 10 , the bonding material 200 mainly includes a first brazing filler metal layer 41, a stress relaxation layer 6, a second brazing filler metal layer 43, and a third nickel-containing layer 46. The bonding material 200 is configured by stacking the first brazing filler metal layer 41, the stress relaxation layer 6, the second brazing filler metal layer 43, and the third nickel-containing layer 46 in this order. The bonding material 200 is configured by integrating the first brazing filler metal layer 41, the stress relaxation layer 6, the second brazing filler metal layer 43, and the third nickel-containing layer 46. A bonded material made of a material containing aluminum and a bonded material made of a material containing copper may be bonded.

[0086] Specifically, the stress relief layer 6 is located on the first brazing filler metal layer 41. The stress relief layer 6 is joined to the first brazing filler metal layer 41 by, for example, rolling. The second brazing filler metal layer 43 is located on the stress relief layer 6. The second brazing filler metal layer 43 is joined to the stress relief layer 6 by, for example, rolling. The third nickel-containing layer 46 is located on the second brazing filler metal layer 43. The third nickel-containing layer 46 is joined to the second brazing filler metal layer 43 by, for example, rolling. The third nickel-containing layer 46 is, for example, a nickel foil. The weight content of nickel in the third nickel-containing layer 46 is, for example, 85 wt % or more. The thickness of the third nickel-containing layer 46 in the direction from the first brazing filler metal layer 41 to the third nickel-containing layer 46 is, for example, 1 μm or more and 3 μm or less.

[0087] 11 is a schematic vertical cross-sectional view showing a state in which a bonding material is disposed between the first main surface and the second main surface in the manufacturing method of the semiconductor device substrate 100 according to the second embodiment. The schematic vertical cross-sectional view shown in FIG. 11 corresponds to the schematic vertical cross-sectional view shown in FIG. 5. As shown in FIG. 11, the third nickel-containing layer 46 of the bonding material 200 is in contact with the first layer 45. By performing the step (S40) of heating the bonding material in a state in which the bonding material is disposed between the first main surface and the second main surface, the semiconductor device substrate 100 shown in FIG. 8 is manufactured.

[0088] According to the manufacturing method of the substrate 100 for a semiconductor device according to the second embodiment, the bonding material 200 is formed by integrating the first brazing filler metal layer 41, the stress relaxation layer 6, the second brazing filler metal layer 43, and the third nickel-containing layer 46. This makes it easy to arrange the bonding material 200 in the manufacturing process of the substrate 100 for a semiconductor device. This improves the productivity of the substrate 100 for a semiconductor device.

[0089] The third nickel-containing layer 46 of the bonding material 200 is not limited to nickel foil. The third nickel-containing layer 46 may be, for example, a nickel-plated layer. In this case, the first brazing filler metal layer 41, the stress relief layer 6, and the second brazing filler metal layer 43 may be integrally formed by rolling or the like, and then the third nickel-containing layer 46 may be formed by plating.

[0090] The configuration of the bonding material 200 is not limited to the above configuration. FIG. 12 is a schematic vertical cross-sectional view showing the configuration of a bonding material 200 according to a modification of the second embodiment. The schematic vertical cross-sectional view shown in FIG. 12 corresponds to the schematic vertical cross-sectional view shown in FIG. 10. As shown in FIG. 12, the bonding material 200 may further include a fifth nickel-containing layer 47. The fifth nickel-containing layer 47 is located below the first brazing filler metal layer 41. The fifth nickel-containing layer 47 is bonded to the first brazing filler metal layer 41. The fifth nickel-containing layer 47 may be formed simultaneously with the third nickel-containing layer 46, for example, by plating. The bonding material 200 according to the modification of the second embodiment can also achieve the same effects as the bonding material 200 according to the second embodiment.

[0091] In the substrate 100 for a semiconductor device fabricated using the bonding material 200 according to the modification of the second embodiment, the first bonding layer 8 has a fourth compound layer and a third alloy layer. The fourth compound layer is in contact with the cooler 2 at the first main surface 21. The third alloy layer is located between the fourth compound layer and the stress relaxation layer 6. The third alloy layer is in contact with the stress relaxation layer 6. The substrate 100 for a semiconductor device according to the modification of the second embodiment can also achieve the same effects as the substrate 100 for a semiconductor device according to the first embodiment.

[0092] The embodiments disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present disclosure is defined by the claims rather than the above-described embodiments, and it is intended to include any modifications within the scope of the claims and meanings equivalent to the claims. [Explanation of symbols]

[0093] REFERENCE SIGNS LIST 1 copper substrate, 2 cooler, 3 first plate portion, 4 insulating plate, 5 second plate portion, 6 stress relaxation layer, 7 second bonding layer, 8 first bonding layer, 11 third compound layer, 12 first alloy layer, 13 first compound layer, 14 second alloy layer, 15 second compound layer, 16 first nickel-containing layer, 17 second nickel-containing layer, 20 main body portion, 21 first main surface, 23 third main surface, 24 protrusion portion, 32 second main surface, 33 outer peripheral side surface, 34 fourth main surface, 35 fifth main surface, 36 sixth main surface, 37 seventh main surface, 38 eighth main surface, 41 first brazing filler metal layer, 42 fourth nickel-containing layer, 43 second brazing filler metal layer, 44 second layer, 45 first layer, 46 third nickel-containing layer, 47 fifth nickel-containing layer, 51 third nickel-enriched layer, 52 second molten brazing filler metal layer, 53 First nickel-enriched layer, 54 third molten brazing material layer, 55 second nickel-enriched layer, 57 first molten brazing material layer, 100 substrate for semiconductor device, 200 bonding material.

Claims

1. a cooler including a first major surface; a plate portion including a second main surface facing the first main surface; a stress relief layer located between the first main surface and the second main surface; a first bonding layer bonding the cooler and the stress relaxation layer; a second bonding layer bonding the stress relaxation layer and the plate portion, the second bonding layer includes a first alloy layer and a nickel-containing layer located between the first alloy layer and the plate portion in a direction from the first main surface toward the second main surface, the nickel-containing layer is in contact with the plate portion at the second main surface, the cooler is made of a material containing aluminum, The substrate for a semiconductor device, wherein the plate portion is made of a material containing copper.

2. 2. The substrate for a semiconductor device according to claim 1, wherein said first alloy layer is made of a material containing aluminum, silicon and magnesium.

3. the second bonding layer further includes, between the first alloy layer and the nickel-containing layer, a first compound layer positioned on the first alloy layer, a second alloy layer positioned on the first compound layer, and a second compound layer positioned on the second alloy layer; the first compound layer is made of a material containing aluminum and nickel, 3. The substrate for a semiconductor device according to claim 1, wherein the second compound layer is made of a material containing aluminum and nickel.

4. 4. The substrate for a semiconductor device according to claim 3, wherein said second alloy layer is made of a material containing aluminum, silicon and magnesium.

5. the second bonding layer further includes a third compound layer located between the stress relaxation layer and the first alloy layer in a direction from the first main surface toward the second main surface, 5. The substrate for a semiconductor device according to claim 1, wherein the third compound layer is made of a material containing aluminum and nickel.

6. 6. The substrate for a semiconductor device according to claim 1, wherein the first bonding layer is made of a material containing aluminum, silicon, and magnesium.

7. 7. The substrate for a semiconductor device according to claim 1, wherein the aluminum content by weight in said stress relaxation layer is greater than the aluminum content by weight in said cooler.

8. 7. The substrate for a semiconductor device according to claim 1, wherein the stress relaxation layer is a nickel plate.

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